Digital Logic Families

 In Digital Designs, our primary aim is to create an Integrated Circuit (IC).

 A Circuit configuration or arrangement of the circuit elements in a special manner will result in
a particular Logic Family
 Logic Families: group of compatible ICs with same logic levels and supply voltages but
perform different logic functions.
 NOTE: 1) Chips from same family can be interconnected.
2) Chips from different family may not be compatible, means they may use
different power supply voltages and input, output conditions.
 Integrated circuit: A collection of one or more gates fabricated on a single silicon chip is
called an Integrated Circuit(IC)
 or it can be defined as an Integrated Circuit(IC) is a silicon wafer or a Die that contains
two or more number of active such as diodes, transistors and some of passive
components such as resistors, capacitors.
 NOTE: The passive element Inductor can’t be fabricated using ICs, Because they have
magnetic flux
Classification of Logic Families:

a. Bipolar ICs: which uses diodes and transistors (BJT)

b. Unipolar ICs: which uses MOSFETs

 Out of the logic families mentioned above, DL, RTL and DTL are not very useful due to
some inherent disadvantages
 while TTL, ECL and CMOS are widely used in many digital circuit design applications.
 TTL has an extensive list of digital functions and is currently the most popular logic
family.
 ECL is used in systems requiring high-speed operations.
 MOS is used in circuits requiring a high component density,
 whereas CMOS is used in systems requiring low power consumption.
 These three families, TTL, ECL and CMOS have LSI devices and also a large number of
MSI and SSI devices.
 TTL ICs are usually distinguished by numerical designations such as the 5400 and 7400
series.
 The most common ECL types are designated as the 10000 series.
 The 10102 provides four two input NOR gates.
 Note that the ECL gate may have two outputs, one for the NOR function and the other
for the OR function.
 ECL gates have three terminals for power supply. VCC1 and VCC2 are usually connected
to ground and VEE to a -5.2 Volt supply.
 CMOS circuits are designated by the 4000 series
 Positive and Negative logic:
 Every logic gate accepts inputs and produces output in terms of logic and voltage levels.
 It is possible to interpret logic and voltage levels in terms of two types of logic
configurations: positive logic and negative logic.
 Table-1 shows the two assignments that define positive and negative logic systems.
Characteristics of logic families:

the different parameters which are used to characterize different logic families:

High Level Output Voltage (VOH):

 It is the minimum voltage required for a logic ‘1’ at an Output under defined load conditions.

High Level Input Voltage (VIH):

 It is the minimum voltage required for a logic ‘1’ at an input.

 Any voltage below this level will not be accepted as HIGH by logic Circuit.

Low Level Input Voltage (VIL):

 It is the maximum voltage required for a logic ‘0’ at an input.

 Any voltage above this level will not be accepted as LOW by logic Circuit.

Low Level Output Voltage (VOL):

 It is the maximum voltage required for a logic ‘0’ at an Output under defined load conditions.

High Level Input Current (IIH):

 It is the current that flows into input when a specified high level voltage is applied to input.

High Level Output Current (IOH):

 It is the current that flows from an Output under specified load conditions.

Low Level Input Current (IIL):

 It is the current that flows into input when a specified low level voltage is applied to input.
Low Level Output Current (IOL):

 It is the current that flows from an Output under specified load conditions.

Supply current, ICC:

 The supply current when the output is HIGH, LOW and in the high-impedance state is
respectively designated as ICCH, ICCL and ICCZ

Fan out:

 It specifies the number of standard loads that the output of the gate can drive without affecting
its normal operation
 Sometimes, the term’ loading’ is also used instead of ‘fan out’.
 This term is derived from the fact that the output of the gate can supply a limited amount of
current above which it ceases to operate properly and is said to be overloaded.

Fan in:

 This is the number of inputs of a logic gate. It is decided by the input current sinking capability
of a logic gate.

Power Dissipation:

 This is the power supplied required to operate the gate.

 It is expressed in milli-watt (mW) and represents actual power dissipated in the gate.
 The power dissipation parameter for a logic family is specified in terms of power consumption
per gate and is the product of supply voltage VCC and supply current ICC.
  The supply current is taken as the average of the HIGH-level supply current ICCH and the LOW-
level supply current ICCL.

Rise time, tr:

 This is the time that elapses between 10% and 90 % of the final signal level when the signal
makes a transition from logic LOW to logic HIGH.

Fall time, tf:

 This is the time that elapses between 90 and 10 % of the signal level when the signal makes a
transition from logic LOW to logic HIGH

Propagation delay tp:

 The propagation delay is the time delay between the occurrence of change in the logical level at
the input and before it is reflected at the output.

a. Propagation delay tpLH:

This is the time delay between the specified voltage points on the input and output waveforms with the
output changing from LOW to HIGH.

b. Propagation delay tpHL:

This is the time delay between the specified voltage points on the input and output waveforms with the
output changing from HIGH to LOW.
  The signal through gate takes a certain amount of time to propagate from the inputs to the
output. This interval of time is defined as the propagation delay of the gate.
 Propagation delay is expressed in nanoseconds(ns)(1ns = 10-9 s).

Speed–power product(figure-of-merit):

 It is expressed in picojoules, which is the product of the propagation delay (measured in

nanoseconds) and the power dissipation per gate (measured in milliwatts).

Noise margin:

 This is the maximum noise voltage added to the input signal of digital circuit that does not cause
an undesirable change in the circuit output.
 This is a quantitative measure of noise immunity offered by the logic family

There are two types of noise to be considered here

a. DC noise :This is caused by a drift in the voltage levels of a signal

b. AC noise: This is caused by random pulse that may be created by other switching signals.

The noise margin in HIGH state is NMH= VOH – VIH

The noise margin in LOW state is NML = VIL – VOL

The noise margin = min(NMH, NML )

SEE REST PART OF LOGIC FAMILY FROM PANACEA NOTES PAGE N0. 231- 256

SEE ECL FROM MADE EASY NOTES