ECE 5121: Advanced Digital VLSI Design

Assignment Sheet – 1
Last Date for Completion: 20-10-2018
Max. Marks: 10
Purpose:
 To get familiarize a layout editor tool
 To get a feel of DRC, area, circuit parasitic etc., related to the VLSI circuits.

Task:
Draw the circuit, stick diagram and layout for the following.
1. Half adder and full adder circuits using XOR and AOI logics

2. 2:1 MUX using a) TG and b) gate logic

3. Half adder using 2:1 Mux

4. 2:4 Decoder

5. F(ABCD) = ((C.(A+B))+A.B)’

6. F(ABCD) = ((A.(B+C))+D)’

7. F(ABCD) = ((A+(B.C))+D.E)’

8. F(ABCD) = ∑m( 0,1,4,5,9,13)

9. F(ABCD) = ∑ m( 0,3,5,6,9,10,12,15)

10. F(ABCD) = ∑ m( 0,4,5,7,8,10,13,15)

Note:
1. Draw stick diagram with and without applying Euler path method and then
draw the layout.
1. Layout to be developed using microwind / Cadence and simulate for
functional verification
2. Calculate the area required and output node parasitic values
3. Try alternate methods and see the impact on area and node capacitance.
4. This is an individual assignment
5. Evaluation will be done in the lab.

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S.N.Bhat, Department of Electronics & Communication Engineering

M.I.T Manipal 1