ST5-06

GATE OXIDE THINNING EFFECTS AT THE EDGE OF SHALLOW

TRENCH ISOLATION IN THE DUAL GATE OXIDE PROCESS
Seok-Woo Lee, Ihl Hyun ChoySang Hyuk Park, Hong Goo Choi, Nam Gawk Kim,
Jong-Kwan Kim, Sang Beom Han and KyungHo Lee
Advanced Process Development 2 team, Hyundai MicroElectronics Co. Ltd.,
1 Hyangjeong-dong, Cheongju-si 361-380, Korea
Phone: +82-43 1-270-4586 Fax: +82-43 1-270-4882 e-mail: ardorsu@hmec.co.kr

Abstract modifying the DGO process flow. Qbd degradation of the

We have investigated the degradation of thick gate
oxide in conventional dual gate oxide process. To meet
the requirement of integrating 3 and 6 nm dual gate
oxide operated under the bias of 1.8 and 2.5V
respectively on a single chip, a novel dual gate oxide
process flow, without gate oxide thinning at STI comer,
is presented. Our new integration of dual gate oxide
shows an improved gate oxide reliability compared to
conventional dual gate oxide process.
1. Introduction
As CMOS logic scales down, it needs ultra thin
gate oxides and reduced operating voltage for high
performance. At the same time, an increasing number of
applications require dual voltage or dual gate oxide on a
chip to interface to a higher external voltage. This
requirement is met through dual gate oxide (DGO)
process integration. The conventional approach for
integrating DGO process flow requires photoresists to
come in contact directly on gate oxide layers, which
make this approach susceptible to contamination of gate
oxide layers in the wet clean and etching process [I].
The thick oxide layer formed by DGO process is issued
for its inferior property in charge-to-breakdown (Qbd)to
single-step-grown gate oxide with same thickness [2]-
131.
In this paper, we investigated oxide reliability with
thick oxide layer grown by DGO process was examined
and the issue of photoresists contamination on gate
oxide formed by DGO process was also studied. New
novel DGO process showed improved GO1 reliability
without gate oxide thinning at STI comer.
2.Experimental
Test devices having 0.18 design rule were
manufactured for evaluation of oxide reliability grown
by DGO process. 300 nm-deep shallow trenchs were
formed for device isolation. The trenchs were filled with
high-density plasma (HDP) oxide and annealed at high
temperature prior to planarization using chemical-
mechanical polishing (CMP). After shallow trench
isolation (STI), the well was formed and V, was
adjusted by implantation. For integrating 1.8V core
transistor and 2.5V 110 transistor, the two different gate
oxide thickness formed at thin and thick region were 3
and 6 nm, respectively. Fig. 1 (a), (b) shows DGO
process flow of conventional dual gate oxide (CDGO)
and our modified dual gate oxide (MDGO), respectively.
At first step, 10- and 6 nm-thick initial oxide was grown
for CDGO and MDGO, respectively. Buffered oxide
etchant (BOE) was used to remove the initially grown
oxide at thin oxide region, at second step. For the case
of CDGO, the thickness of residual oxide after BOE
etch was 2 nm. However, for the case of MDGO, the

0-7803-5727-2/99/$10.00 0 1999 IEEE - 249 -

initially grown oxide was thoroughly etched. After the
etch of initial oxide grown at thin oxide region, the
residual thickness of thick oxide was controlled by wet
etch in diluted HF solution at third step. The thickness
of residue oxide, after the wet etch at the thick oxide
region, was determined to meet the final thickness to be
6 nm after 2”doxidation. As a control oxide, 6 nm-thick
single-step-grown gate oxide was grown at the same
condition. To fabricate the MOS capacitors,
phosphorous doped polysilicon was deposited and gate
patterning was performed. The constant current TDDB
and breakdown voltage for thick gate oxide were
measured on both STI-flat and STI-edge intensive
pattern to examine the STI comer effect.
PR
2)
Thin
Thick Thin Thick Thin
(a)CDGO (b)MDGO
Fig. 1 Fabrication procedure of (a) conventional dual gate oxide
(CDGO) and (b) modified dual gate oxide (MDGO). The thick
oxide was grown by two-step oxidation. The initial oxides were
10 nm-and 6 nm-thick for CDGO and MDGO, respectively.
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3.Results and Discussion
To examine the STI comer effect on GO1 reliability,
we measured Qbd characteristics of STI-edge intensive
pattern, which sensitively detects the STI effect such as
gate oxide thinning. Fig. 2 shows Qbddistributions of
thick oxides formed by CDGO and MDGO, and single-
step-grown oxide as a control at STI-edge intensive
pattern. An inlet represents the shape of STI-edge
intensive pattern.
99
I edge i~ensive(l18750pm”andSOrr;AlCm‘> I
95 -
80 -
60 -
40-
20 -
5.
I S -
Charge-to-breakdown (Clan*)
Fig. 2 Cumulative distribution of QM of single- and two-step-
grown gate oxide for STIedge intensive pattern. An inlet shows
the shape of STI-edge intensive pattern, which sensitively detects
the STI comer effect such as gate oxide thinning.
Comparing it with control or MDGO, Qbdof two-step-
grown CDGO oxide was greatly degraded. We also
examined breakdown voltage characteristics of gate
oxides grown by CDGO and MDGO on STI-edge
intensive pattern, and Fig. 3 shows the results. A lot of
initial fails were observed for the case of CDGO, which
was thought to be associated with STI geometry with
wet etching process. To clarify the degradation of Qbd
and breakdown voltage characteristics of gate oxide
formed by CDGO process, we analyzed STI comer by
using TEM. Fig. 4 shows TEM image of thick gate
oxide after step 3 (PR strip f oxide etch) of CDGO flow
in Fig. ](a). It is interesting to notice that gate oxide
thinning at STI top comer is observed from CDGO flow.
We also analyzed STI top comer formed by MDGO
process and formed with control oxide, respectively
shown in Fig. 5 and Fig. 6 .

99, . , . , . . . . 1

edge intensive( 18750pd)

95 -
initial 10 nm
80 - CDGO
60 -
40 - Fig. 5 TEM image of thick gate oxide after step 4 (2""oxidation)

20 - in Fig. l(b) MDGO. Severe thinning is not observed.

5- 0
d
I - . ' . ' A

Fig. 3 Breakdown voltage distribution of thick gate oxide for STI-

edge intensive pattern. Many initial fails are observed for the case

of CDGO.

Fig. 6 TEM image with control oxide. No thinning is observed.

In comparison with the TEM image of CDGO process,

Fig. 4 E M image of thick gate oxide after step 3 (PR strip +
oxide etch) in Fig. I(a) CDGO. Severe thinning and grooving at
STI edge are observed for CDGE.Which is supposed to be caused
by wet etch process.
severe thinning was not observed for the case of MDGO
process and no thinning was observed for the case of
with control oxide. The severe thinning shown in Fig. 4
was caused by wet etch and enhanced by its structure
itself at STI comer, i.e., the oxide etch rate at STI comer
is faster than that at active center considering three
dimensional structure. In addition, severe grooving was
observed for the case of CDGO process shown in Fig. 4,
which was also caused by wet etch process. From these

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results, GO1 reliability of CDGO, which was examined
here as Qbd and voltage breakdown, was degraded by
wet etch. A decrease of the initially grown oxide
thickness in DGO process reduces the etch amount for
thick oxide and it results in improved Qbd and
breakdown voltage characteristics by reducing STI
comer oxide thinning and grooving. It is well known
that gate oxide thinning and enhanced grooving can
affect the GO1 reliability [4]. Fig. 7 shows
distributions of thick gate oxides, on STI-flat pattern,
grown by CDGO and MDGO, and single-step-grown
oxide as a control. An inlet shows the shape of STI-flat
pattern.
99
I Flat ( 1 O4 pm2a d 80 mA/cm2) ' 1
1 10 100
Charge-tebreakdown (C/cm2)
Fig. 7 Qbddistribution of thick gate oxides grown by CDGO and
MDGO,and single-step-grown oxide as a control. An inlet shows
the shape of STI-flat pattern, which excludes STI comer effect.
Although STI comer effect is excluded for the case of
STI-flat pattern, Qbd degradation of gate oxide grown by
CDGO process is still observed in Fig. 7, and this means
that there is another effect that affect GO1 reliability in
DGO process. To explain this, we analyzed oxide
surface morphology using AFM at step 3 in Fig. 1. The
rms data obtained fiom AFM were 8.1 and 4.2 A for
CDGO and MDGO, respectively (not shown here). It
reveals that the thick oxide surface micro-roughness
increases with increasing etch amount [ 5 ] . So, MDGO,
which reduces the etch amount for thick oxide, has
higher surface morphology and better reliability. We
also examined the metal contamination effect, induced
by photoresists contact, on gate oxide and silicon active
by SIMS analysis. No drastic difference was found from
the SIMS analysis data (not shown here) on both thin
Qbd and thick oxide grown by CDGO and MDGO.
From the results mentioned above, the degradation
of thick gate oxide in DGO process is caused by two
effects : excessive thinning and grooving at STI comer,
and roughened surface micro-roughness. Our MDGO
process, which decreases the thickness of the initially
grown oxide and thus reduces the etched amount in wet
etching step, drastically improved thick oxide reliability.
4. Conclusions
We have investigated the reliability of thick gate
oxide grown by DGO process with STI. It has been
found that the degradation of thick gate oxide is due to
the combined effect of enhanced thinning and grooving
at STI comer, and roughened oxide surface micro-
roughness, which is come fiom wet etching in DGO
process. A decrease of etched thickness of thick gate
oxide significantly improves the gate oxide reliability,
especially in Qbd and breakdown voltage. Our MDGO
process shows sub-quarter micron CMOS transistor
without gate oxide thinning at STI comer.
References
[ 11 Kenneth K. 0. et al., IEEE Trans. Electron Devices,
vol. 42, pp. 190, 1995.
[2] Hideo Oi, et al., SSDM98, Hiroshima, pp. 108, 1998.
[3] N. Bhat, et al., ZEDM98, pp. 93 1, 1998.
[4] M. Nandakumar, et al., ZEDM98, pp. 133, 1998.
[5] T. Ohmi et al., ZEEE Trans. Electron Devices, vol.
39, pp. 537, 1992.
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