Embedded Processing

Portfolio for Ultrasound

High performance, programmable platform
 Processor performance
speeds image analysis –
faster, clearer results
 Power/size efficient
processors enable portability
– point of care imaging
 Programmable DSPs
enable software upgrades –
extend product life
 Complete line of Code
compatible devices –
provides scalable platform to
address portable through
high-end cart-based systems
TI’s Medical Imaging Processors
Mission: to enable performance imaging every doctor demands
TI DSP Enables
Advances in medical
processing
 Latest algorithms
Improved image quality
More accurate diagnosis
Emerging Features
 Innovative applications
safer, non-invasive
 Real-time diagnosis
 Product differentiation
Portable medical
applications
• Longer battery life
• Smaller form factor
TI Confidential – NDA Restrictions
TI DSP Solutions
Complete product line of
high performance DSPs
 Software programmable
 Flexible
 Adaptable
 Upgradeable C66x™
 Real-time performance
 1.25GHz single core
 320GMACs/160GFlops multi-core C64x™
 Medical driven roadmap
Sitara™
™
C6-Integra™
Integra
Low power processors Davinci™
and SOCs
• Highly integrated
• Power efficient
• C64x+ & C66x core DSP
• OS, GUI, MMI, display
• High connectivity
3
Ultrasound system – Where DSP fits

DSP
RF Demodulation
B-Mode
Color Flow
Spectral Doppler
Scan Control

SOC (DSP+MPU)
Scan Conversion
Speckle Reduction
System Control
O/S
Display
Storage
Multi-core DSP
Console Ultrasound Solution
Decimation B-Mode Color Doppler System Ctrl
 RF Demod  Detection  Wall Filter  FFT  MMI
 Compression  Velocity Est  Peak/Mean Est
.  Scan Conv  Power Est .  PACs i/f
 Mode Switch
 Speckle Red  Scan Conv  Cineloop Mgmt

Probe

C6657 (~3.5w)

McBSP
DAC

66x (x2) MSMC

1GHz PC
L1P: 32KB Shared
AFE L2: 4MB
L1D: 32KB
L2: 512KB
SRIOx4

1 to 4
DDR3

Beam-former Multicore Navigator DDR3

lanes
64-bit
1.33GHz
SPI HL50 PCIe

control
data

• FPGA beam forms and routes data to DSP via SRIO

• C6657 (2-core) for scan control & back end image processing algorithms.
• PC performs system control, MMI, interface to PACs
• Lower power & system cost solution
5
Multi-core DSP
Portable Ultrasound Solution
Decimation B-Mode Color Doppler System Ctrl O/S
 RF Demod  Detection  Wall Filter  FFT  MMI  Linux
 Compression  Velocity Est  Peak/Mean Est
.  Scan Conv  Power Est .  PACs /fi .  Android
 Mode Switch  QT
 Speckle Red  Scan Conv  Cineloop Mgmt

Probe
DM814x

C6657 (~3.5w) AM3874 (~1w)

McBSP
DAC ARM®
Cortex™-A8 DISPLAY

DSS
MSMC 800 MHz
66x (x2) L1P: 32KB LCD
1GHz L1D: 32KB
L1P: 32KB Shared

SATA
AFE L2: 4MB 32-bit L2 : 256KB
L1D: 32KB 333/666MHz Storage

DDR
L2: 512KB
DDR2/3 Graphics Image
SRIOx4

Engine Engine

USB
1 to 4
DDR3

Printer
Beam-former Multicore Navigator DDR3
lanes Switch Fabric

GEmac
64-bit
1.33GHz PACs
SPI HL50 PCIe PCIe GPMC
16-bit200MHz
Flash control
data

• FPGA beam forms and routes data to DSP via SRIO

• C6657 (2-core) implements mid-back end image processing algorithms
• AM3874 performs system control, MMI, interface to PACs
• C6657 + AM3874 = ~4w total
6
SOC Based
Ultra-Portable Ultrasound Solution

Front End B-Mode Color Doppler System Ctrl

 Beamforming  Speckle Red  Wall Filter  FFT  O/S MMI
 Detection  Scan Conv  Velocity Est.  Peak/Mean Est.  PACs i/f
 Compounding  Power Est  Mode Switch
 Scan Conv  Cineloop Mgmt
AM387x
Probe
DM8148

McASP
DAC
ARM®
674x+ Cortex™-A8 DISPLAY

DSS
750MHz 1GHz
L1P: 32KB L1P: 32KB
L1D: 32KB LCD
L1D: 32KB
L2 : 256KB

SATA
32-bit L2 : 256KB
333/666 MHz Storage

DDR
AFE DDR 2/3 Graphics Image
Engine Engine

USB
Printer
Switch Fabric

GEmac
FPGA
PACs
Beam-former
RF Demod PCIe GPMC
16-bit 200 MHz
Flash control
data

• FPGA beam-former + RF demod and routes data to SOC via PCIe

• ARM Cortex A8 performs system control, MMI, interface to PACs
• DSP performs back end image processing
• Video & Graphics h/w accelerator
TI Confidential – NDA Restrictions 7
Multi-core DSP Based Performance Ultrasound Solution

B-Mode Color Doppler System Ctrl O/S

 RF Demod  Detection  Wall Filter  FFT  MMI  Linux
 Compression  Velocity Est  Peak/Mean Est
.  3D/4D  Scan Conv  Power Est .  PACs i/f .  Android
 Elastography  Mode Switch  QT
 Speckle Red  Scan Conv  Cineloop Mgmt

Probe

DM814x
AM 3874

McBSP
C66x DAC ARM®
Cortex™-A8 DISPLAY

DSS
66x (x8) MSMC 800 MHz
1GHz L1P: 32KB LCD
L1P: 32 KB Shared L1D: 32KB

SATA
AFE L1D: 32KB L2: 4MB 32-bit L2 : 256KB
333/666MHz Storage
L2: 512KB

DDR
DDR2/3 Graphics Image
SRIOx 4

Engine Engine

USB
DDR3
1 to 4 Printer
Beam-former Multicore Navigator DDR3
lanes Switch Fabric

GEmac
64-bit
1.33GHz PACs
SPI HL 50 PCIe x2 PCIe GPMC
16-bit 200MHz
Flash control
data

• FPGA beam forms and routes data to DSP via SRIO

• C6678 standard mid processing + 3D/4D, Elastography, & Speckle Reduction
• AM3874 performs system control, MMI, interface to PACs

TI Confidential – NDA Restrictions 8

C6655/ C6657 (Sample Now!)
 New C66x Core
– 2 C66x Cores @ 1.0GHz nominal (1.4GHz max)
– C6657 (2 Core), C6655 (1 core)
– High Performance Fixed & Floating Point DSP Cores
Multicore Navigator
 Power Optimized Design
– Target 3.5W for 2 Core, 2.5W for 1 Core implementation
(85c case @ 1Ghz) Communications
CoProcessors
 Keystone Multi-Core Architecture C66X
C66X
– Multicore Navigator, TeraNet, Hyperlink DSP 2x VCP2
DSP

TeraNet
 Memory Architecture
TCP3d
– 1MB Local L2 per Core L1 L2 L1 L2
– 1MB Multicore Shared Memory (MSM)
– Boot ROM,DDR3-1600MHz (32-bit)
– Address Translation & ECC
Memory Subsystem Peripherals & IO
 Interfaces Multicore Shared Memory Controller
– 4x RapidIO rev 2.1 (1x4, 2x2, 1x2+2x1) DDR3- (MSMC)
32b SGMII McBSP
– 2 lanes PCIe Gen II Shared Memory 1MB
– 10/100/1000 Mbps Ethernet SGMII ports

HyperLink
SRIO PCIe EMIF
– Universal Parallel Port (16-bit) Muxed with EMIF -16 System Elements x4 x2 16
– I2C, SPI, 2x McBSP (Mux), 32 GPIO, 2 x UART, 4x
Timers64, Semaphore Power Management SysMon I2C
uPP UART
Debug EDMA SPI
 Other
– 2x VCP2, 1x TCP3d
– Multicore debugging (embedded trace per core / chip)
– 0.8 mm pitch flip chip package
– 21x21 package
– Ext Temp Range: -55C to 105C
– 40nm High Performance Node
– Smart reflex

TI Confidential – NDA Restrictions

TI Confidential – NDA Restrictions 9 9
Shannon (TMS320C6678) – Block Diagram
• Multi-Core KeyStone SoC Multicore Navigator
• Fixed/Floating CorePac 8 x CorePac
• 8 CorePac @ 1.25 GHz Network
• 4.0 MB Shared L2 C66x C66x C66x C66x CoProcessors
DSP DSP DSP DSP
• 320G MAC, 160GFLOP, 60G DFLOPS Crypto
• ~10W L1 L2 L1 L2 L1 L2 L1 L2
Packet
Accelerator
• Navigator C66x C66x C66x C66x

TeraNet
• Queue Manager, Packet DMA DSP DSP DSP DSP IP Interfaces
• Multicore Shared Memory L1 L2 L1 L2 L1 L2 L1 L2 GbE
Switch
Controller
Memory Subsystem SGMII SGMII
• Low latency, high bandwidth memory access
Multicore Shared Memory Controller
• 3-port GigE Switch (Layer 2) DDR3- (MSMC)
64b
• PCIe gen-2, 2-lanes Shared Memory 4MB Peripherals & IO
SRIO PCIe EMIF
• SRIO gen-2, 4-lanes System Elements x4 x2 16
• HyperLink Power Management SysMon TSIP I2 C
Hyper UART
• 50G Baud Expansion Port Debug EDMA Link
2x SPI
• Transparent to Software 50

10
DM8148 Processor
Cores
 ARM Cortex A8™ (MPU) up to 1 GHz
 C674x™ Floating Point DSP Core up to 750 MHz
Memory
 ARM: 32KB L1I-Cache, 32KB L1 D-Cache, 256K L2 DM8148
 DSP: 32KB L1I-Cache, 32KB L1 D-Cache, 256K L2 Fixed/ ARM
HD Video Display
 Two DDR-800 Controllers Floating micro- Coprocessor
Coprocessors/Subsystem point DSP processor (x1)
On-Screen
 HD VICP 2.0 Accelerator at 320 MHz Display
– Real-Time HD Encode /Decode C674x ARM 3D Graphics Resizer

 3D Graphics engine DSP Cortex Engine

Video I/O
 Display Subsystem Core A8 TM
SD DAC (x2)
Peripherals
HDMI PHY
 Gigabit EMAC Switch
 USB 2.0 Ctlr/PHY x 2 HD Video I/O (x2)
 PCIe 2.0
 SATA 3.0Gbps
 DDR3 – 800 x2 Switched Central Resource (SCR)
 SD/SDIO x3
 McASP x6, McBSP Peripherals
 SPI, GPIO, I2C, UART, DCAN PCIe McASP USB
I2C/ UART GMAC
Power x6
SPDIF SPI x6
DCAN 2.0 GPIO
Switch
 Total Power – Typical <4 W McBSP x4
x2 x2

Package
 23x23, 0.8mm pitch, 684 ball BGA Memory Interfaces
• Via Channels enable low cost design rules -- 4 mil traces DDR3 SDIO
Async
SATA2
EMIF/
and 10/20 mil escape vias x2 /SD NAND
x3

Back to: DM roadmap | product positioning

Using DSPs & SOCs in Ultrasound Systems
• TI’s C6678 DSP with new C66x floating point core provides high
performance signal processing capabilities at low power
– C6657 dual core DSP can perform processing for mid-range system
– Upgrade to 4 or 8 core C6674/C6678 for more advanced algorithms

• C66x DSPs are well suited for processing such as:

– B-Mode (Detection, Compression)
– Color (Wall Filter, Velocity & Power estimation)
– Doppler (FFT, Peak Mean estimation)
– Scan Conversion
– 3D/4D, Elasto-graphy, Speckle Reduction

• Combining an FPGA for beam formation/routing and Sitara ARM SOC

C66x DSPs can provide a flexible, low-power solution for digital
ultrasound systems.
– High Level Language “Eclipse” development environment
– On-Chip DMA & Multicore Navigator for data movement.
– McBSP ports address I/O needs for CW Doppler & audio
Using DSPs & SOCs in Portable Ultrasound Systems

• TI’s low-power Davinci SoCs allow flexibility on the back-end SoC for
various display options, image filtering and target identification on a
single chip:
– C674x DSP (fixed-/floating-point DSPs)
– Cortex-A8 for peripheral and communications control
– 3D graphics engine for rich UIs
– Rich display sub-system for multiple HD displays
– HD video encode/decode accelerators (Davinci devices only)

• High system connectivity with peripherals such as:

– Gigabit ethernet
– PCIe
– USB
– SATA
– SPI/GPIOs/more…
Complete DSP & ARM MPU Software
Solutions by TI
Scalable BSP/SDK
Releases
LINUX Periph Libraries
and Stacks

SITARA™ Middleware/
Frameworks
ARM® MPU
Multimedia
Codecs
C6-INTEGRA™
Common IDE/
ARM® MPU + DSP Tools

Example SW
DAVINCI™ & Demos

ARM® MPU + DSP

+ Video Accelerator Engine “Instant Expert” SW
Development Kits

FREE Development license to use our Linux, Android, or WinCE Board FREE
Support Packages (BSP) / Software Development Kits (SDK)
* For use on our ARM, ARM+DSP, and ARM+DSP+Multimedia Processors
* Each release seamlessly and scalable works across all products
 Medical Software Toolkit 2.0

 Optimized implementations of commonly

used C64x+/C66x DSP processing blocks
 Source Code:
 Ultrasound:
• B-mode (Envelop Detection &
Compression)
• DAS Receive Beam-forming
• Doppler Processing
• RF Demodulation and Decimation
• Scan Conversion
 Optical Coherence Tomography
• Cubic Spline Interpolation
• Optimized FFT
 3D Rendering
• Affine Warp

Request download at: http://focus.ti.com/docs/toolsw/folders/print/s2meddus.html

Medical Ultrasound Demo (MIDAS) Rev. 2
All B-Mode, Color Flow, and Scan Conversion Processing on OMAP3530!

ARM Cortex A-8 • Runs Linux O/S

600MHz • User Interface , Control, Display TI OMAP3530 Mistral EVM

C64x+ DSP • Runs Ultrasound Algorithms

430MHz
Envelope Scan
Compression
Detection Conversion

B-mode Estimation Tissue Flow

DDR & Blending
Ensemble Wall Flow Scan
Aggregation Filter Estimation Conversion Display 640x480 @20fps
Color Flow

Input Data Size (Post RF Demod) Scan Samples/ Bytes/ Ensemble kB/ Loading DSP ARM ms/fm
Lines Scan Line Sample frame

B-mode + Scan Conversion B-Mode 19% 6% 15

128 416 4 - 208

Color Flow + Scan Conversion B-Mode+ 46% 21% 28

64 256 4 8 512
Color Flow

https://gstreamer.ti.com/gf/project/med_ultrasound/
Medical Imaging DSP
Value Proposition
 New & innovative algorithms in software
Improved image quality & emerging features
Field upgrades, Flexibility, Adaptive coding
C64x+™
 Deterministic signal processing architecture
Supports latest real-time O/S for predictable & reliable performance
Sitara™
C6-Integra™
 Portable imaging applications
Davinci™
Low power SOC’s replace PC. (DSP+ARM, Graphics, Video accl…)
Longer battery life. Smaller form factor.
C66x™
 Scalable platforms: PortableValuePremium
Code compatible family of products

 R&D Savings
Reuse (code, hardware, development environment)
No hardware spins, eco’s, & timing closure bottlenecks

 Time to Market
State of the art development tools: (Compilers, trace, emulation)
Develop & debug in high level language
Imaglib & Medical Software toolkit, 3d parties

 Roadmap & Product continuity

Long term supplier, Full product line: Analog, DSP, Power, etc…
10GHz-320GMACs/160GFlop DSP’s today,
Application support (Field, Factory, domain white papers & app notes)

TI Confidential – NDA Restrictions 17