Implementing the Low Power and High Speed Full Adder Using GDI Multiplexer

ABSTRACT:
This project proposes a new method for implementing a low power full adder by
means of a set of Gate Diffusion Input (GDI) multiplexers. Full adder is a very common
example of combinational circuits and is used widely in Application Specific Integrated
Circuits (ASICs). It is always advantageous to have low power action for the sub
components used in VLSI chips. The explored technique of realization achieves a low power
high speed design for a widely used subcomponent- full adder. With the help of CMOS
technology to implementing the full adder require more number of transistor and dissipate
more power having more delay and overcome this properly by explore technique of
realization of GDI multiplexer for designing full adder to achieve low power, high speed
design. Power speed and area comparision between conventional and proposed full adder is
also be dervied.

Software tools: Tanner tool crack version, micro wind