ECE 2300

Digital Logic & Computer Organization

Spring 2018

More Finite State Machines

Lecture 9: 1
 Announcements
• Prelab 3(B) due tomorrow

• Lab 4 to be released tonight

– You’re not required to change partner(s) from this lab
onwards

Lecture 9: 2
Example: Procedural Assignments

reg Y, Z; reg Y, Z;
always @ (posedge clk) always @ (posedge clk)
begin begin
Y = ~Z; = Y <= ~Z;
Z = A & B; Z <= A & B;
end end
Blocking assignments Nonblocking assignments

A A
B B

Z Y Z Y

Lecture 9: 3
 FSM Design Procedure
(1) Understand the problem statement and
determine inputs and outputs

(2) Identify states and create a state diagram

(3) Determine the number of required D FFs

This
(4) Implement combinational logic for outputs lecture
and next state

(5) Simulate the circuit to test its operation

Lecture 9: 4
 Example FSM: Pattern Detector
• Monitors the input, and outputs a 1 whenever a
specified input pattern is detected

• Example: Output a 1 whenever 111 is detected

on the input over 3 consecutive clock cycles
– Overlapping patterns also detected (1111...)

• Input In
• Output Out
• Reset causes FSM to start in initial state
• Clock input not shown (always present)
Lecture 9: 5
 State Diagrams
Reset
In = 1 In = 1 In = 1

Moore Init Got1 Got11 Got111

Out = 0 Out = 0 Out = 0 Out = 1
In = 0

In = 0 In = 0 In = 1
In = 0

In = 1 In = 1
Reset Out = 0 Out = 0

Init Got1 Got11

Mealy In = 0
Out = 0 In = 1
Out = 1
In = 0 In = 0
Out = 0 Out = 0
Lecture 9: 6
 Transition/Output Table
• Shows the next state (S*) and output values for
each combination of current state (S) and inputs

• Used to derive the minimized state transition (S*)

and output Boolean equations

Lecture 9: 7
 Moore Transition/Output Table 1
Reset
In = 1 In = 1 In = 1

Init Got1 Got11 Got111

Out = 0 Out = 0 Out = 0 Out = 1
In = 0

In = 0 In = 0 In = 1
In = 0

Current Next State (S*) Out

State (S) In = 0 In = 1
Init Init Got1 0
Got1 Init Got11 0
Got11 Init Got111 0
Got111 Init Got111 1
• Version 1: uses descriptive state names
Lecture 9: 8
 Moore Transition/Output Table 2
Reset
In = 1 In = 1 In = 1

Init Got1 Got11 Got111

Out = 0 Out = 0 Out = 0 Out = 1
In = 0 [01] [10] [11]
[00]

In = 0 In = 0 In = 1
In = 0

S 1* S 0* Out
S1 S0 In = 0 In = 1
00 00 01 0
01 00 10 0
10 00 11 0
11 00 11 1
• Version 2: uses state binary encodings
Lecture 9: 9
Minimized Equations for S* and Out

S 1* S 0* Out
S1 S0 In = 0 In = 1
00 00 01 0
01 00 10 0
10 00 11 0
11 00 11 1
Lecture 9: 10
 Mealy Transition/Output Table 1
In = 1 In = 1
Reset Out = 0 Out = 0

Init Got1 Got11

In = 0
Out = 0 In = 1
Out = 1
In = 0 In = 0
Out = 0 Out = 0

Current Next State (S*), Out

State (S)
In = 0 In = 1
Init Init, 0 Got1, 0
Got1 Init, 0 Got11, 0
Got11 Init, 0 Got11, 1

• Version 1: uses descriptive state names

Lecture 9: 11
 Mealy Transition/Output Table 2
In = 1 In = 1
Reset Out = 0 Out = 0

Init Got1 Got11

In = 0
[00] Out = 0 [01] [10] In = 1
Out = 1
In = 0 In = 0
Out = 0 Out = 0

S1* S0*, Out

S1 S0
In = 0 In = 1
00 0 0, 0 0 1, 0
01 0 0, 0 1 0, 0
10 0 0, 0 1 0, 1

• Version 2: uses state binary encodings

Lecture 9: 12
Minimized Equations for S* and Out

S1* S0*, Out

S1 S0 In = 0 In = 1
00 0 0, 0 0 1, 0
01 0 0, 0 1 0, 0
10 0 0, 0 1 0, 1
Lecture 9: 13
 FSMs in Verilog
<module statement>
<input and output declarations>

<reg declarations>

<parameter or typedef statement> Suggested

coding style
<always block for next state> for FSM
<always block for output>

<always block for state FFs>

endmodule

Lecture 9: 14
 Moore FSM in Verilog
Reset
In = 1 In = 1 In = 1

Init Got1 Got11 Got111

Out = 0 Out = 0 Out = 0 Out = 1
In = 0 [01] [10] [11]
[00]

In = 0 In = 0 In = 1
In = 0

module PatDetectMoore (Clk, In, Reset, Out);

input Clk, In, Reset;
output Out;

reg Out;
reg [1:0] Scurr, Snext;

parameter [1:0] Init = 2'b00,

Got1 = 2'b01,
Got11 = 2'b10,
Got111 = 2'b11;
Lecture 9: 15
 Moore FSM in Verilog
Reset
In = 1 In = 1 In = 1

Init Got1 Got11 Got111

Out = 0 Out = 0 Out = 0 Out = 1
In = 0 [01] [10] [11]
[00]

In = 0 In = 0 In = 1
In = 0
always @ (In, Scurr)
begin
case (Scurr)
Init: if (In == 1) Snext = Got1; else Snext = Init;
Got1: if (In == 1) Snext = Got11; else Snext = Init; next state
Got11: if (In == 1) Snext = Got111; else Snext = Init; comb logic
Got111: if (In == 1) Snext = Got111; else Snext = Init;
default: Snext = Init;
endcase
end

Lecture 9: 16
 Moore FSM in Verilog
Reset
In = 1 In = 1 In = 1

Init Got1 Got11 Got111

Out = 0 Out = 0 Out = 0 Out = 1
In = 0 [01] [10] [11]
[00]

In = 0 In = 0 In = 1
In = 0
always @ (Scurr)
if (Scurr == Got111) Out = 1; else Out = 0; output comb logic

always @ (posedge Clk) clock

if (Reset == 1) Scurr <= Init; state FFs
else Scurr <= Snext; (synchronous reset)

endmodule

Lecture 9: 17
 Mealy FSM in Verilog
In = 1 In = 1
Reset Out = 0 Out = 0

Init Got1 Got11

In = 0
[00] Out = 0 [01] [10] In = 1
Out = 1
In = 0 In = 0
Out = 0 Out = 0
module PatDetectMealy (Clk, In, Reset, Out);
input Clk, In, Reset;
output Out;

reg Out;
reg [1:0] Scurr, Snext;

parameter [1:0] Init = 2'b00,

Got1 = 2'b01,
Got11 = 2'b10;

Lecture 9: 18
 Mealy FSM in Verilog
In = 1 In = 1
Reset Out = 0 Out = 0

Init Got1 Got11

In = 0
[00] Out = 0 [01] [10] In = 1
Out = 1
In = 0 In = 0
Out = 0 Out = 0
always @ (In, Scurr)
begin
case (Scurr)
Init: if (In == 1) Snext = Got1; else Snext = Init;
Got1: if (In == 1) Snext = Got11; else Snext = Init; next state
Got11: if (In == 1) Snext = Got11; else Snext = Init; comb logic
default: Snext = Init;
endcase
end

Lecture 9: 19
 Mealy FSM in Verilog
In = 1 In = 1
Reset Out = 0 Out = 0

Init Got1 Got11

In = 0
[00] Out = 0 [01] [10] In = 1
Out = 1
In = 0 In = 0
Out = 0 Out = 0
always @ (Scurr, In) output comb logic
if ((Scurr == Got11) && (In == 1)) Out = 1; else Out = 0;

always @ (posedge Clk) clock

if (Reset == 1) Scurr <= Init; state FFs
else Scurr <= Snext; (synchronous reset)

endmodule

Lecture 9: 20
 Example FSM: Pushbutton Lock
• Two pushbutton inputs, X1 and X2
• One output, UL (“Unlock”)

• UL = 1 when X1 is pushed, followed by X2 being

pushed twice (X1, X2, X2)

• Represent X1 and X2 as two bit input

– 00: neither button pushed
– 10: X1 pushed
– 01: X2 pushed
– 11: both pushed, reset the lock

Lecture 9: 21
 Pushbutton Lock: Moore State Diagram
• Output: UL=1 with sequence X1, X2, X2
• Input: 00 (neither), 10 (X1), 01 (X2), 11 (reset)
01
X1 X1-X2 00
00 UL = 0 UL = 0
[01] [10]

11
10 11 10 01
10

00
01 Init X1-X2-X2 00
11 UL = 0 UL = 1 01
[00] 11 [11] 10

Lecture 9: 22
Moore Transition/Output Table 1
Current Next State (S*) UL
State (S)
Input Input Input Input
00 01 10 11
(neither) (X2) (X1) (reset)
Init Init Init X1 Init 0

X1 X1 X1-X2 Init Init 0

X1-X2 X1,X2 X1-X2-X2 Init Init 0

X1-X2-X2 X1-X2-X2 X1-X2-X2 X1-X2-X2 Init 1

• Version 1: uses descriptive state names

Lecture 9: 23
Moore Transition/Output Table 2

S1* S0* UL
S1 S0
Input Input Input Input
00 01 10 11
00 00 00 01 00 0
01 01 10 00 00 0
10 10 11 00 00 0
11 11 11 11 00 1

• Version 2: uses state binary encodings

Lecture 9: 24
 Pushbutton Lock: Mealy State Diagram
• Output: UL=1 with sequence X1, X2, X2
• Input: 00 (neither), 10 (X1), 01 (X2), 11 (reset)

X1 01/
00/ UL=0 X1-X2 00/
UL=0 UL=0
[01] [10]
11
10/
10/ 11 UL=0 01/
UL=0 10/ UL=0
UL=0

00 00
01 Init X1-X2-X2 01
11/ 11/ 10/
UL=0 [00] UL=0 [11] UL=1

Lecture 9: 25
Mealy Transition/Output Table

S1* S0* , UL
S1 S0
Input Input Input Input
00 01 10 11
00 0 0, 0 0 0, 0 0 1, 0 0 0, 0
01 0 1, 0 1 0, 0 0 0, 0 0 0, 0
10 1 0, 0 1 1, 0 0 0, 0 0 0, 0
11 1 1, 1 1 1, 1 1 1, 1 0 0, 0

• uses state binary encodings

Lecture 9: 26
 FSM for D Flip-Flop
D=0

State0 State1
D Q
Q=0 Q=1
[0] [1]
CLK
D=0 D=1 D=1
Moore state diagram
• Input: D
• Output: Q
• Clock is implicit in
the state diagram

Lecture 9: 27
Analyzing the FSM

S 0*

S 1*

What does this FSM do?

Lecture 9: 28
Transition and Output Equations
S0* =

S1* =

Out =

S0*

S1*

Lecture 9: 29
 Exercise: State Diagram
In = 0
In = 1
1. Complete the [00] [01] In = 0

transition/output
Out = 0 Out = 0
table and state
diagram
In = 1
2. Identify the [11] [10]
functionality of the
Out = 1 Out = 0
FSM (Hint: Pattern
detector?) S1* S0* 
Out
S1 S0 In = 0 In = 1
S0* = In’ 00 01 00 0
S1* = In’•S1•S0’+In•S0 01 01 10 0
Out = S1•S0 10 0
11 1

Lecture 9: 30
 Next Time
• H&H 2.9, 4.6, 4.9

More FSMs
Timing, Clocking

Lecture 9: 31