EL2095 Digital System

Number Representation
 Unsigned Integers

• From chapter 1.
B  bn 1bn  2 ...b1b0
n 1 n2
V ( B)  bn 1  2  bn  2  2  ...  b1  2  b0  2
1 0

n 1
  bi  2i
i 0
 Unsigned Integers
• Hexadecimal and
Octal Numbers
K  kn 1kn  2 ...k1k0
n 1
V ( K )   ki  r i
i 0

• In General
V ( K )   ki  r i

i
 Examples
• What is decimal value of
110.012
1 22  1 21  0  20  0  21  1 22  4  2  0.25  6.2510

177.48
1 82  7  81  7  80  4  81  64  56  7  0.5  127.510

1F16

1161  F 160  16  15  3110

Converting between binary,
hex, octal
• A group of bits corresponds to a digit
• Binary  Octal 1 octal digit = 3 binary digit
101.112 = 101.1102 = 5.68 0…7 = 000,…,111

• Binary  Hex
110.1012 = 0110.10102 = 6.A16
1 hexa digit = 4 binary digit
• Octal  Hex 0…F = 0000,…,1111

3778 = 011 111 1112

= 0 1111 11112 = FF16
 Do it Yourself
• Binary to Octal
– 1111
– 101101
– 11001.101
• Binary to Hexadecimal
– 1111
– 101101
– 11001.101
• Octal to Hexa
– 642
– 273
 Converting from Decimal
to Base r
• We are given a decimal number D
• We want to find digits k3,k2,k1,k0 such that
D = k3 r3 + k2 r2 + k1 r + k0

• Divide repeatedly by r:
Quotient Q0 = D/r = k3 r2 + k2 r + k1 remainder = k0
Quotient Q1 = Q0/r = k3 r + k2 remainder = k1
Quotient Q2 = Q1/r = k3 remainder = k2
Quotient Q3 = Q2/r = 0 remainder = k3

• The unknown digits are the remainders k3,k2,k1,k0

Example
Unsigned Binary Numbers
• Range of N bit number? 2n-1
• Addition x
+y
0
+0
0
+1
1
+0
1
+1
– Identical to normal addition c s 0 0 0 1 0 1 1 0

– Keep track of carries Carry Sum

• Examples (a) The four possible cases

Carry Sum
1100 1 1 1x 1y c s

+1101 + 0 0 00 10 0 0
0 1 0 1
------------- -------------
1 0 0 1
1 1 1 0

(b) Truth table

 x 0 0 1 1

Half Adder
+y +0 +1 +0 +1
c s 0 0 0 1 0 1 1 0

Carry Sum

(a) The four possible cases

Carry Sum
x y c s

0 0 0 0
0 1 0 1
1 0 0 1
1 1 1 0

(b) Truth table

x
s
y
x s
HA
y c
c

(c) Circuit (d) Graphical symbol

 Looking at a Single
Column
carry-in from
previous column Truth table
carry-out to
next column
ci+1 ci
xi ci xi yi s ci+1
the two bits to be
+ yi added
0 0 0 0 0
----- 0 0 1 1 0
si 0 1 0 1 0
sum bit for this
column
0 1 1 0 1
1 0 0 1 0
1 0 1 0 1
1 1 0 0 1
1 1 1 1 1
 Full Adder
xi yi
ci xi
00 01 11 10

0 1 1 yi si

1 1 1 ci

si = xi yi ci

xi yi
ci 00 01 11 10
ci + 1
0 1

1 1 1 1

ci + 1 = xi yi + xi ci + yi ci
 Ripple Adder
• Adding n-bit numbers
• Carry signals “ripple” through from LSB to
MSB
x n –1 yn – 1 x1 y1 x0 y0

c1
cn FA cn ” 1 c2 FA FA c0

sn – 1 s1 s0

MSB position LSB position

Delay is nDt, where Dt = delay for single FA

 Addition Examples
(unsigned)
• Binary 110011 100111
+ 11010 + 101010

• Octal 1776 57734

+ 1432 + 1066

• Hex 1776 4F1A5

+ 1432 + B8D5
 Overflow in Unsigned
Numbers
• Overflow: the sum doesn’t fit in the range of
numbers
• When adding two N-bit unsigned numbers, you
have a carry out of the most significant bit
(MSB) position
• Examples (5 bit unsigned numbers):
( 15) 01111 ( 17) 10001
+( 2) +00010 + ( 17) +10001
( 17) 10001 ( 2) 00010
 Representation of Signed
Numbers
• Positive number representation same in
most systems
– Standard positional binary notation
– MSB is the sign bit; 0 = plus, 1 = minus
• Major differences are in how negative
numbers are represented
• Three major schemes:
– sign and magnitude
– ones complement
– twos complement
 Signed Number Format
b n – 1 b 1 b 0

Magnitude
MSB

(a) Unsigned number

b n – 1 b n – 2 b 1 b 0

Magnitude
Sign
0 denotes +
1 denotes – MSB

(b) Signed number

 Negative Number
Representation
• Assumptions:
– we'll assume a 4 bit machine word
– 16 different values can be
represented
– roughly half are positive, half are
negative
– sign bit is the MSB; 0 = plus, 1 =
minus
 Sign-Magnitude
Representation
+0 High order bit is sign: 0 = positive
-7 +1
0000 (or zero), 1 = negative
-6 1111 0001 +2
1110 0010 Three low order bits is the
-5 +3
1101 0011 magnitude: 0 (000) thru 7 (111)
-4 1100 0100 +4 Number range for n bits = ±2n-1 - 1
-3 1011 0101
+5 Two representations for 0
-2 1010 0110
1001 0111 +6
-1 1000 The major disadvantage is that
+7
-0 we need separate circuits to
both add and subtract
0 100 = +4
1 100 = - 4 Number magnitudes need to be
compared to get the right result
Ones Complement Representation
Ones Complement
N is positive number, then N is its negative 1's complement

n
N = (2 - 1) - N 2 4 = 10000

-1 = 00001
Example: 1's complement of 7
1111

-7 = 0111

Shortcut method: 1000 = -7 in 1's comp.

simply compute bit wise complement

0111 -> 1000

Ones Complement Representation
like 2's comp except shifted
one position counter-clockwise
+0
-0 +1
0000
-1 1111 0001 +2
1110 0010
-2 +3
1101 0011 • Subtraction implemented by
addition & 1's complement
-3 1100 0100 +4
1011 0101
-4 +5 • Still two representations of
-5
1010 0110 0! This causes some
1001
1000
0111 +6 problems
-6 +7
-7
• Some complexities in
addition
 Twos Complement
Representation
+0
• Only one representation for
-1 +1 0
0000
-2 1111 0001 +2
1110 0010
3 +3 • One more negative number
1101 0011
than positive number
-4 1100 0100 +4

-5
1011 0101
+5 • Generation of the 2’s
-6
1010 0110 complement as 2r - N
1001
1000
0111 +6 implies r + 1 bits available in
-7
-8
+7 system
Twos Complement Operations
Example: Twos complement of 7 24 = 10000

sub 7 = 0111

1001 = repr. of -7

Example: Twos complement of -7 24 = 10000

sub -7 = 1001

0111 = repr. of 7

Shortcut method:
Twos complement = bitwise complement + 1
N* = 2r - N
0111 -> 1000 + 1 -> 1001 (representation of -7)

1001 -> 0110 + 1 -> 0111 (representation of 7)

 Value Sign-Mag 2’s comp 1’s comp
-8
-7
-6
Comparison of
Signed Number -5
Representations -4
(4-Bits) -3
-2
-1
0
1
2
3
4
5
6
7
 Value Sign-Mag 2’s comp 1’s comp
-8 - 1000 -
-7 1111 1001 1000
-6 1110 1010 1001
Comparison of
Signed Number -5 1101 1011 1010
Representations -4 1100 1100 1011
(4-Bits) -3 1011 1101 1100
-2 1010 1110 1101
-1 1001 1111 1110
0 0000, 1000 0000 0000, 1111
1 0001 0001 0001
2 0010 0010 0010
3 0011 0011 0011
4 0100 0100 0100
5 0101 0101 0101
6 0110 0110 0110
7 0111 0111 0111
Addition of Signed Numbers
• Difficult in signed-mag and 1’s comp
• Example – in signed-mag
– If signs are same, can add the
magnitudes
– If signs are different, subtract the
smaller from the larger

• Requires more circuitry, takes

longer

• But addition is easy in 2’s comp!

 Addition in 2’s comp
• Just add, and ignore carry out of most
significant bit
• Examples:
( + 5) 0101 (–5) 1011
+ ( + 2) + 0010 + (+ 2) + 0010
( + 7) 0111 (–3) 1101

( + 5) 0101 (–5) 1011

+ (–2) + 1110 + (–2) + 1110
( + 3) 10011 (–7) 11 0 0 1

ignore ignore
 Overflow in 2’s comp
• Overflow: result doesn’t fit in range of numbers

• Effectively we cross boundary between + and –

• Easy test for overflow:

– If signs of addends same, but sign of sum is different

• Examples (5 bit)
( + 15) 01111 (–15) 10001
+ ( + 2) + 00010 + (+ 2 ) + 00010
( -15) 10001 (–13 ) 10011
 Examples
• Add these 4-bit 2’s comp numbers. Does overflow
occur?
( + 7) 0111 ( –7) 1001
+ ( + 2) + 0010 + ( + 2) + 0010
( + 9) 1001 ( –5) 1011
c4 = 0 c4 = 0
c3 = 1 c3 = 0

( + 7) 0111 ( –7) 1001

+ (– 2) + 1110 + (–2) + 1110
( + 5) 10101 ( –9) 10 1 1 1
c4 = 1 c4 = 1
c3 = 1 c3 = 0
 Subtraction in 2’s comp
• Easiest way is to negate one number and then
add (then all we need are adders)
• Examples: Do the following using 4-bit two’s
complement arithmetic:
510 - 710 -510 - 510
31
Adder/Subtractor Unit
Recall that we negate by flipping all
the bits and adding 1

y y y
n–1 1 0
Add Sub
control

x x x
n–1 1 0

c n-bit adder c
0
n

sn–1 s1 s0
 Fast Adders
• Ripple adder is slow (NDt for N bits)
– The carry bits must propagate from one full adder
to the next
xn –1 yn – 1 x1 y1 x0 y0

c1
cn FA cn ” 1 c2 FA FA c0

sn – 1 s1 s0
MSB position LSB position

• With a little bit of extra circuitry we can

greatly speed up the adder
– We will compute the carry bits directly from the
input numbers
 Fast Adder Equations

• Recall equations for a full

xi yi

adder
si = xi xor yi xor ci (sum) c i+1 FA ci

ci+1 = xi yi + xi ci + yi ci (carry out)

• Let si
gi = xi yi
pi = xi + yi

• Then 1 OR gate
ci+1 = gi + pi ci 2 AND, 2 OR

1 AND 1 AND
1 OR
gate gate
gate
 Fast Adder Equations
(continued)
• Express ci in terms of x’s, y’s, and ci-1
ci+1 = gi + pi ci
= gi + pi (gi-1 + pi-1 ci-1 )
= gi + pi gi-1 + pi pi-1 ci-1

• If we have a 2-bit adder

c2 = g 1 + p 1 g 0 + p 1 p 0 c 0

• So c2 can be computed directly from the

inputs (we don’t need to wait for c1) … this
is a “carry-lookahead” adder
Two-bit x1 y1 x0 y0

Carry-
Lookahead
x0 y0

Adder
g1 p1 g0 p0

c0
c2
c1

Critical path (c2):

3 gate delays

s1 s0
 3-bit Fast Adder
• We have
• Note that
s0 = x0 $ y0 $ c0
– The p’s and g’s take one
c1 = g0 + p0 c0 gate delay
s1 = x1 $ y1 $ c1 – Each carry is produced
c2 = g1 + p1 g0 + p1 p0 c0 by a two-level AND-OR
• Find !! circuit (two additional
s2 = x2 $ y2 $ c2 gate delays)
c3 = g2 + p2 c2 – The sum bits take
another gate delay
= g2 + p2 (g1 + p1 g0 + p1 p0 c0 )
=> total is 4 gate delays
= g2 + p2 g1 + p2 p1 g0 + p2 p1 p0 c0
Note: $ = XOR
• In general
ci+1 = gi + pi gi-1 + pi pi-1 gi-2 + … + pi pi-1 ··· p2 p1 g0 + pi pi-1 ···
p1 p0 c0
 Combination CLA-RCA

x31– 24 y31– 24 x15– 8 y15– 8 x7 – 0 y7 – 0

c8
c32 Block c24 c16 Block Block c0
3 1 0

s31– 24 s15– 8 s7 – 0
 Hierarchical CLA Adder
x31– 24 y31– 24 x15– 8 y15– 8 x7 – 0 y7 – 0

Block Block Block c0

3 c24 1 0

G3 P3 G1 P1 G0 P0

s31– 24 s15– 8 s7 – 0

c32 c16 c8

Second-level lookahead
 Floating Point Number
32 bits

S E M

Sign
0 denotes+ 8-bit 23 bits of mantissa
1 denotes– excess-127
exponent
(a) Single precision

64 bits

S E M

Sign
11-bit excess-1023 52 bits of mantissa
exponent
(c) Double precision
Binary Coded Decimal
Addition of BCD digits
X 0111 7
+ Y + 0101 + 5

Z 1100 12
+ 0110

carry 10010

S=2

X 1000 8
+ Y + 1001 + 9

Z 10001 17
+ 0110

carry 10111

S=7