DESIGN AND IMPLEMENTATION OF FAULT TOLERANT PARALLEL FFT

USING PARTIAL SUMMATION

Abstract:

The increasing demand of low complexity and error-tolerant design in signal processing
systems is a reliability issue at ground level. Complex circuit is consistently affected by soft
errors in modern electronic circuits. Fast Fourier transforms (FFTs) plays a key role in many
communication and signal processing systems. Different algorithms have been used in earlier
techniques for achieving fault tolerant coverage design. In real time application systems,
numbers of blocks operating in parallel are frequently used. The proposed work exploits a
technique to implement fault tolerance parallel FFT with reduced low complexity of circuit
area and power. In Partial summation along with error detection and correction hamming
code is used for designing soft error tolerant parallel FFT shelter. This new method achieves
lower complexity proportional to that of FFT design size. Based on these two schemes, two
modified preserve techniques that combine the use of error correction codes and Partial
summation are proposed and evaluated. First method, the Parity-Partial Summation and ECC
uses one FFT with minimum Partial Sum blocks for reducing hardware area. Secondly,
Parallel Partial Summation ECC used for correcting errors in multiple FFTs protective
methods. The result for 4-paralle1 and 6- paralle1 FFT shows that the proposed technique
effectively reduces area and power of fault tolerant design along with improved fault
coverage.

Keywords: Fast Fourier transforms (FFT), EIC, Partial Summation, and ABFT.

I. INTRODUCTION memories, data bits are written in data bit

arrays, and check bits are concurrently
Error correction code (ECC) techniques
produced using the data bits and stored in
have been widely used to correct transient
check bit arrays. The check bit arrays, just
errors and improve the reliability of
like the data bit arrays, should be tested
memories. ECC words in memories
prudently for the same fault models if
consist of data bits and additional check
reliable error correction is to be insured[1].
bits because the ECCs used in memories
Fast Fourier transform is used to convert a
are typically from a class of linear block
signal from time domain to frequency &
codes. During the write operations of
this is needed so that we can view the
frequency components present in a signal.
If you know the frequency components
present in signals you can play with the
signals. Let’s say, we want to design a low
pass filter and want to decide on the cut off
frequency of the filter. If we have the
frequency domain details for a signals u
can clearly identify the frequency
components which we want to retain & the
ones which we want to take out.
Simultaneous testing of data bit and check
bit arrays has been proposed in order to
reduce the test time and hardware
overheads required for separate check bit
array tests. Simultaneous testing of a data
bit and check bit arrays using the
conventional SEC code brings decreases of
about 23.8%, 15.8%, and 9.9% in the time
required for memory array tests for 16, 32,
and 64 data bits per word. Although SEC
codes and SECDED codes are capable of
correcting single bit errors and are widely
used in memories, they cannot correct a
double or more bit error in an ECC word.
In this brief, the protection of parallel
FFTs is studied. In particular, it is assumed
that there can only be a single error on the
system at any given point in time.
Fast Fourier Transform
Fast Fourier Transform (FFT) algorithm
converts a signal from time domain into a
sequence in the frequency domain [13].
Fast Fourier transforms are widely used for
many applications which include
engineering, science, and mathematics. It
computes transformations through DFT
matrix. The FFT operation starts with
decomposing N-point time domain signal
and calculating N frequency spectra and
finally forming a single spectrum.
The Discrete Fourier Transform (DFT)
Discrete Fourier Transform (DFT) is an
important unit in many communication
applications like OFDM, etc. DFT is also
measured as one of the tools to act upon
frequency analysis of discrete time signals.
The Discrete Fourier Transform is a
continuous Fourier transform for the use of
discrete functions. Given a real sequence
as the input, the DFT outputs them as a
sequence of complex numbers. The
mathematical representation of the
transform is
If an N – point DFT is implemented
directly, the necessity of arithmetic units is
of the order of O(N2) that is N2
multiplications and N (N-1) additions.
Thus FFT is used for designing the DFT.
Depending on inputs being real or check bits for the SEC-DED-DAEC codes
complex, the design of adders and is the same as that for the SEC-DED
multipliers are formed. codes.

II. LITERATURE SURVEY In addition, the area and timing overheads

for encoder and decoder of the SEC-DED-
Different error coding schemes are chosen
DAEC codes are similar to those of the
depending on the types of errors expected,
SEC-DED codes. Consequently, adjacent
the communication medium's expected
double bit errors can be remedied with
error rate, and whether or not data
very little additional cost using the
retransmission is possible. Faster
SECDED-DAEC codes. The SEC-DED-
processors and better communications
DAEC codes may be an attractive
technology make more complex coding
alternative to bit interleaving in providing
schemes, with better error detecting and
greater flexibility for optimizing the
correcting capabilities, possible for smaller
memory layout. Furthermore, the SEC-
embedded systems, allowing for more
DED-DAEC code can be used in
robust communications. However,
conjunction with bit interleaving and this
tradeoffs between bandwidth and coding
method can efficiently deal with adjacent
overhead, coding complexity and
multi-bit errors [1]. The main purpose of a
allowable coding delay between
fault-tolerant system is to produce correct
transmissions, must be considered for each
results in the presence of faulty units. Two
application. Transient errors can often
fundamentally di
upset more than one-bit producing multi-
Trent approaches have been used to
bit errors with a very high probability of
achieve fault tolerance [AL81, SS82,
error occurrence in neighboring memory
LA94, Jal94]. They are based on
cells. Bit interleaving is one technique to
redundancy by replication of data and
remedy multi-bit errors in neighboring
computation and on checkpointing and
memory cells as physically adjacent bits in
rollback recovery. In the first approach, the
memory array are assigned to different
system is designed to perform correctly by
logical words [5],[6]. The single error-
hiding the of a faulty unit. This approach
correction, double-error-detection, and
can be applied either in space or in time.
double adjacent-error-correction (SEC-
The most popular redundancy-based
DED-DAEC) codes have previously been
technique for fault tolerance is NMR (N-
presented to correct adjacent double bit
Modular Redundancy), which employs a
errors [4]-[7]. The required number of
majority voting scheme. NMR systems can Checkpointing can be embedded in the
be designed with or without spare operating system and hence provide fault
processors. When spare processors are tolerance for parallel applications
used, upon detection of a faulty processor, transparently without any change to
the system is reconjured using a spare one. applications. Unfortunately, although
An NMR system detects permanent as conceptually simple, checkpointing is
well as transient faults. The disadvantage quite costly in terms of performance
of the NMR technique is its enormous overhead. The performance overhead
overhead in hardware, especially for large results mainly from saving the checkpoints
values of N. Conventional time on stable storage and communicating
redundancy involves computing the same between processes to build a globally
problem more than once, at carefully consistent state.
designed time intervals, until successive
An Error-Checking Device in Linear
results match. Such a system can detect
Computations In 1951, Dwyer [Dwy51]
intermittent and transient error conditions.
used to row and column checksums as a
However, errors due to permanent faults
checking device to eliminate computation
will not be detected. Once an error has
of \mistakes" and to study the
been detected, the unit must be replaced by
accumulation of errors in matrix
a spare unit that is known to be fault-free.
computations. The underlying idea of his
While the hardware overhead in a
checksum encoding scheme is that the
temporally redundant system is minimal,
checksum property is preserved throughout
the performance penalty can be very large.
some matrix computations. For example,
Checkpointing and rollback recovery, also
in Gaussian elimination, the sum of the
known as backward error recovery, is an
cosecants of a row (i.e., the row checksum)
attractive software approach to providing
always holds throughout the elimination of
fault tolerance [BBG83, KT87, EJZ92]. In
columns of the matrix. In solving a system
this approach, every process periodically
with Gaussian elimination, this checking
saves its own state on stable storage as a
method is continued through the forward
checkpoint during normal operation. If a
solution and can be carried through the
failure occurs, the processes will use the
back solution. Also, the basic nal check
latest checkpoints on stable storage to
can be used to verify that the computed
restore a globally consistent state and
solutions do actually satisfy all the original
restart execution from that state, instead of
equations.
restarting the computation from scratch.
Algorithm-Based Fault Tolerance: and correction of many errors virtually
impossible. Luk's scheme also introduces
Algorithm-based fault tolerance (ABFT) is
complications: it requires more time to
a new approach to fault tolerance, which
multiply and can introduce numerical
was rst proposed by Huang and Abraham
error. In contrast, the exponentially
for detecting transient errors on systolic
weighted checksums are easily computed
arrays. In this approach, fault tolerance is
in an outing-point system without loss of
achieved by tailoring the fault tolerance
precision because multiplication by a
scheme to the algorithm that is to be
power of 2 can be performed simply by
performed on the parallel machine. The
changing exponents. Moreover, the smaller
fundamental idea of ABFT techniques is
spacing of Luk's weights makes fault
characterized by three steps: (1) encoding
location more difficult. As a result of the
data at a higher-level using checksum
accumulation of round
schemes; (2) redesigning algorithms to
error and error in checksum division (the
operate on the encoded data; and (3)
checksum division becomes faulty
distributing the computation steps of the
element), an error can lead to erroneous
redesigned algorithm among
fault location. An alternative approach,
computational processors such that failure
called general linear codes, is introduced
of any processor a
in the paper. Although these codes
as little data as possible. One of the most
improve the numerical properties of ABFT
important issues of ABFT is the scient
schemes, the techniques are still extremely
encoding of data in terms of error
sensitive to round
detection and correction. A good scheme
errors, particularly in computations
of encoding data should be able to detect
involving large matrices. Fault-tolerant
all errors and locate and correct as many
algorithms must not only handle error
errors as possible including multiple,
detection, location, and correction, but
especially grouped, errors. Furthermore, an
must also tolerate certain inaccuracies due
ABFT scheme must address the possibility
to round
of over ow. In particular, the weighted
errors in trig point arithmetic. In, the
checksums may be extremely large if the
authors consider possible ways to scale
number of elements whose checksum is
linear code for algorithm-based error
required is large. Also, for a large matrix,
detection, correction, and fault location
the size of the larger weights can obliterate
techniques to trig point matrix operations
smaller weights, thus making the detection
in massively parallel systems. They
suggest incorporating general linear codes
into a partitioning scheme, thereby
enhancing the numerical properties of
ABFT encoding methods. According to Z.
Gao[1], adaptation to non-critical failure
construct framework based with respect to
Error Correction Codes (ECCs) utilizing
Verilog is composed, actualized, and tried.
It recommends that with the assistance of
ECCs. The channel they have utilized for
mistake location and revision are
fundamentally limited impulse reaction
(FIR) channels. They have been utilized
Hamming Codes[2] for blame adjustment
in which they take a piece of k bits and
produces a square of n bits by including
n−k equality check bits. The equality
check bits are XOR mixes of the k
information bits. By E. P. Kim and N. R.
Shanbhag[3], Triple Modular Redundancy
(TMR) and Hamming Codes have been
utilized to secure distinctive circuits
against Single Event Upsets (SEUs). In
this paper, the utilization of a Novel
Hamming[2] approach on FIR Filters is
examined and actualized to give low
many-sided quality, decrease deferral and
region productive security methods for
higher bits information. A novel Hamming
code[2] is proposed to build the
effectiveness of higher information bits. In
the view of T.Hitana and A.K.Deb[4], the
outline of an FIR channel with self-
checking abilities in view of the buildup
checking is dissected. This investigation is
regularly hard to perform and to acquire
adequate blame scope the arrangement of
picked buildups is overestimated.
Acquired outcome and thusly requires that
Instead, in this paper they have
demonstrated how utilizing a thorough
blame infusion crusades permits to
proficiently choose the best arrangement
of buildups.
III. PROPOSED SYSTEM
3.1 Error Correction based on
Hamming Codes
The aim of the error-tolerant design
is to protect parallel FFTs from errors.
Various schemes have been proposed for
error detection and correction in FFTs.
One of the basic and simple methods is
error correction using hamming codes.
Unlike parity code which can detect only
odd bit error, the Hamming code can
detect two-bit errors and correct one error.
Similar to other error correction codes,
Hamming codes also utilizes the parity bit
which is generated for the corresponding
input sequence for detecting errors. It
achieves higher code rate with a minimum
distance of three. The number of parity bits
depends on the total number of data bits.
The aim of the error-tolerant design
is to protect parallel FFTs from errors.
Various schemes have been proposed for
error detection and correction in FFTs. can be used to identify errors with
One of the basic and simple methods is minimum overhead. For parallel FFTs, the
error correction using hamming codes. Parseval’s check can be combined with the
Unlike parity code which can detect only error correction codes to minimize the area
odd bit error, the hamming code can detect overhead.
two-bit errors and correct one error.
Multiple error detection and
Similar to other error correction codes,
correction is achieved through this
hamming codes also utilizes the parity bit
combination. One of the easy ways is to
which is generated for the corresponding
generate the redundant input for single
input sequence for detecting errors. It
FFT with all the four FFT inputs. To
achieves a higher code rate with a
correct error the parity FFT output is XOR
minimum distance of three. The number of
with fault free outputs of the FFTs.
parity bits depends on the total number of
Compared to the previous schemes
data bits.
presented in the Fault Tolerant Parallel
FFTs Using Error Correction Codes and
Parseval Checks, this technique reduced
the total number of Sum of Squares used.
Another existing work done is by
The limitations of is that, during the combining SOS checks with hamming
multiple error scenario hamming code will codes instead of using Parseval’s check
not be able to exactly identify the individually as shown in Figure 2.
individual FFTs with error.

3.2 Fault tolerant FFT based on

Parseval’s check

Parseval’s method is one of the

techniques to detect errors parallel in
multiple FFT. This is achieved with Sum
of Squares (SOSs) check based on
Parseval’s theorem. The error free FFT
should have its Sum of Squares of the
input equalling the Sum of Squares of its
frequency domain output. This correlation
Figure 2. Parity-SOS-ECC fault-tolerant Technique 1 also uses 3 parallel redundant
parallel FFTs FFT in the case of 4-parallel FFT design
for correcting multiple errors in fault
This method combines the feature
tolerant for soft error.
of parity calculation of hamming codes
and error detection process of Sum of
Squares. Concurrent Error Detection
(CED) schemes for the FFT are the Sum of
Squares (SOS) check based on Pa theorem.
The use of parseval check is exponentially
reduced to the direct comparisons of FFTs
inputs and outputs used to protect parallel
FFTs Figure 3. Parallel-PS-ECC fault-tolerant
parallel FFTs
3.3 Proposed Error Indicator and
Corrector Techniques

The proposed work focuses on two

new techniques for reducing the hardware
overhead and increasing the error
correction capability. The Figure 3
describes the new technique which focuses
on the existing systems limitations. The
technique analyzed in the previous work
has certain limitation due to the
complexity of handling larger number of
FFTs and Sum of Squares block. Instead
of using Sum of Squares, Partial Figure 4. Parity-PS-ECC fault-tolerant

summation is used for calculating its parity parallel FFTs

at the input and the output side of the FFT.
It sums all possible node values of 4-point
FFT along with the twiddle factors.
Multiplication operation which leads to the
complexity in Sum of Squares is thus
eliminated using only the adder blocks.
Figure 4 illustrates the Parity Partial
Summation block for less error-prone
applications. For example when the error
occurs in A1 and A2 then it can be
detected by the partial summation used
individually for FFT blocks. The first
check equation is selected in such a way
that the both error block signals are not
present

The error in first FFT is corrected by using

equation
Figure 5. Implementation of Partial
Summation

Once the error is detected using in the first Figure 5 shows implementation

FFT is corrected then equation (7) can be architecture of partial summation block.

used for correcting error in the second one The sequential input and output of the 4-

which is given as, point FFT is fed to the magnitude sum

block. The magnitude comparator
compares the input and output for
verifying the FFT output. If both are equal
The combination of parity PS-ECC fault-
then the FFT is soft error-free.
tolerant parallel FFT reduces the number
of additional FFTs to just one and also For the less error-prone applications
reduces the shelter overhead. In our technique, two can be used with Partial
implementation those blocks are protected summation block replacing the Parseval
with adders used to compute the inputs and check. Both the new techniques proposed
the outputs to the redundant FFTs in the uses minimum hardware resources
existing technique with a small impact on compared to the existing design by the
circuit complexity as they are much modification of Partial summation block
simpler than the FFT computation. for Sum of Squares.

IV. RESULTS AND DISCUSSION

Fig: Existing method

Fig: Proposed Screen shot

V. CONCLUSION applications. Compared to the existing

counter methods, the result of proposed
The fault secure design of parallel FFTs
four-parallel and six parallel shows the
against multiple errors is analyzed and two
area optimization by 59% and 65% along
new techniques based on Partial
with the 99.97 fault coverage criteria. In
Summation is implemented. The
the future work, a self adaptive system to
evaluation result shows that both the
overcome hard errors can also be taken
approaches results in low complexity and
into consideration.
low power consumption. The parallel
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