ASYNCHRONOUS COUNTER UP

module asyncnt4(rst,clk,en,q);
input rst,clk,en;
output [3:0]q;
reg [3:0]q;
always @ (posedge clk, rst,posedge en)
begin
if(rst==1)
q<=4'b0000;
else if(en==1)
q<=q+1;
else
q<=4'b0000;
end
endmodule