Microelectronics Journal 75 (2018) 87–96

Contents lists available at ScienceDirect

Microelectronics Journal
journal homepage: www.elsevier.com/locate/mejo

Systematic design and optimization of operational transconductance

amplifier using gm/ID design methodology
Mostafa N. Sabry a , Hesham Omran b,* , Mohamed Dessouky b
a
Si-Vision LLC, Cairo, Egypt
b
Integrated Circuits Lab, Faculty of Engineering, Ain Shams University, Cairo, Egypt

A R T I C L E I N F O A B S T R A C T

Keywords: The simple square-law MOSFET model fails to describe the behavior of short channel and moderate/weak inver-
OTA design sion devices. The gm/ID methodology is a promising technique that addresses the square-law shortcomings and
Systematic analog design
bridges the gap between hand analysis and simulation. This paper describes a systematic procedure for the design
gm/ID methodology
of a single-stage operational-transconductance amplifier (OTA) using the gm/ID methodology. Both small signal
Analog design automation
Analog design optimization
and large signal specifications are used to constrain the design process, which is graphically illustrated using
CMOS trade-off charts. The presented design procedure is automated using MATLAB, and an iterative procedure is used
to take the OTA self-loading into consideration. Moreover, an automated optimization procedure is presented
to maximize the speed of a unity-gain buffer under current consumption, DC gain, and input capacitance con-
straints. The designed circuits are verified using Cadence Spectre and the 180 nm Predictive Technology Model
(PTM), where the simulation results are in close agreement with hand analysis and automation results.

1. Introduction design trade-offs, the development of valuable designer intuition, and

Analog IC design will always be there because we live in an analog
world. Analog-to-digital converters (ADCs) and digital-to-analog con-
verter (DACs) will always be needed (together with their associated cir-
cuits such as amplifiers, filters, references, and regulators) to interface
between our analog world and our digital electronic devices. It may be
thought that CMOS analog design is an art that depends on lots of expe-
rience and intuition. One reason that may support this claim is that the
simple square-law MOSFET model common to most textbooks and uni-
versity courses fails to describe the behavior of short channel devices,
as well as devices operated in moderate and weak inversion (which
are becoming increasingly popular in energy-efficient designs [1–3])
regardless of their channel length. On the other hand, more accurate
device models are too complicated, and are not amenable to hand anal-
ysis. In addition, there is no definite systematic recipe that the designer
can follow to design an analog block, even if it is a fundamental block
like an operational transconductance amplifier (OTA). As a result, the
analog designer has to rely on lengthy multi-variable sweeps on sim-
ulation tools, experience, and intuition to make his design work. In
addition to requiring significant design time and expensive simulation
tools licenses, this design methodology hinders the understanding of
the systematic porting of designs from one technology node to another.
A promising methodology that addresses the previous limitations,
and bridges the gap between hand analysis and simulation is the gm ∕ID
design methodology [4–9]. The basic idea of this methodology is to
describe the transistor behavior using a dataset generated from simula-
tion sweeps (or measurements) rather than inaccurate simple models.
This dataset characterizes different normalized transistor parameters
and figures-of-merit vs the transconductance-to-current ratio (gm ∕ID ).
The gm ∕ID is used as a primary design variable instead of the overdrive
voltage which is common in square-law based design flow. The gm ∕ID
can be thought as a normalized measure of the channel inversion level
for all operating regions, and it directly captures the relation between
the basic function of the transistor (the transconductance) and the most
valuable resource (the power consumption). The gm ∕ID dataset is one-
time generated for a given technology, and can be reused in the form of
trade-off charts or lookup tables. The design process becomes a system-
atic procedure, where hand analysis expectations are in close agreement
with simulation results.

* Corresponding author.
E-mail addresses: mostafa.nashaat@si-vision.com (M.N. Sabry), hesham.omran@eng.asu.edu.eg (H. Omran), mohamed.dessouky@eng.asu.edu.eg (M. Dessouky).

https://doi.org/10.1016/j.mejo.2018.02.002
Received 9 October 2017; Received in revised form 24 January 2018; Accepted 11 February 2018
Available online 30 March 2018
0026-2692/© 2018 Elsevier Ltd. All rights reserved.
M.N. Sabry et al. Microelectronics Journal 75 (2018) 87–96

One of the early works that discussed the gm ∕ID methodology was Table 1
proposed by Silveira et al. in Ref. [4]. This pioneering work proposed OTA specifications.
using the gm ∕ID methodology for OTA design; however, several design Technology 0.18 μm CMOS
variables were assumed without being constrained by clear circuit spec- Supply Voltage 1.8 V
ifications. In addition, the details of the optimization procedure used to Reference Current 10 μA
Current Consumption 20 μA
select the gm ∕ID values and the transistor sizing were not explained.
Capacitive Load 5 pF
Moreover, important circuit specifications such as input range, noise, Gain-Bandwidth Product 5 MHz
and common-mode rejection were not considered. Finally, it did not Phase Margin 70o
consider the variation of the gm ∕ID characteristics with channel length, Open-Loop DC gain 32 dB
since this variation was negligible for the 3 μm technology used in the Total Integrated Thermal Noise 50 μVrms
Input Range 0.2 V − 1.1 V
design. The gm ∕ID methodology was used to optimize a gain boosted Common Mode Rejection Ratio (CMRR) @ DC 70 dB
cascode in Ref. [5]. However, similar to [4], it suffered from the same
previously mentioned drawbacks. The optimization of a three-stage
nested-Miller OTA using gm ∕ID methodology was proposed in Ref. [8].
The design procedure aimed at optimizing both noise and settling time
specifications. However, it neglected other circuit specifications, and
assumed that the gm ∕ID values and channel lengths of all transistors are
known a priori. A common shortcoming in the aforementioned works is
that they do not demonstrate a fully-constrained complete design exam-
ple. Lastly, it is difficult for the interested designer to replicate or apply
the proposed design procedures due to the lack of details and the use of
proprietary device models.
As a result, there is a need for a complete and detailed design exam-
ple that clearly demonstrates the gm ∕ID methodology for a simple but
Fig. 1. Schematic of the five-transistor (5 T) OTA. IREF and CL are external elements used
real-life analog block, starting from a complete set of specifications and
in the testbench. The feedback connection for unity-gain buffer operation is not shown.
up to verification. This paper aims at providing such a design example
to promote the gm ∕ID methodology among experienced designers who
are not used to this powerful methodology, as well as novice designers
ing that relatively large W is typically used for analog circuits. A finger
who are embarking their analog IC design journey. A key merit that dif-
width of 2 μm is assumed; thus, all widths are selected to be multiples
ferentiates this work is that it clearly explains the design and optimiza-
of 2 μm. Since three transistors are stacked in the targeted OTA archi-
tion procedure for a complete design example using publicly available
tecture, VDS is set at VDD ∕3. The previous simulations are performed
device models. Consequently, the interested reader can replicate the
only once, and the results can be saved in the form of charts or lookup
results, or apply the presented techniques to his own design problems.
tables for further reuse.
A simple single-stage OTA (also known as five-transistor OTA [10]) is
used as a design example, which despite its simplicity still finds use in
complex mixed-signal systems (e.g. [11]). The OTA design process is 2.3. Design of the input pair
constrained by both small-signal and large-signal specifications, and is
graphically illustrated using trade-off charts. The presented procedure The first step is to choose the type of the OTA input pair. Since the
is automated using MATLAB, and the automation program is applied required input range (0.2 V − 1.1 V) is close to the ground rail, a PMOS
to solve more sophisticated design problems. Analytical expressions for input stage is necessary. The schematic of the OTA is shown in Fig. 1.
the OTA self-loading and input capacitance are derived, verified, and From the GBW and CL specifications the transconductance of the input
used in the automation program. The proposed design examples are pair can be determined [10].
verified using Cadence Spectre and the publicly available 180 nm Pre- gm1,2
dictive Technology Model (PTM) [12]. GBW = (1)
2𝜋 CL

2. Systematic design procedure using gm ∕ID trade-off charts where the OTA internal capacitors were neglected compared to the
large output load (more about this point in Section 2.6 and Section
2.1. OTA specifications 3). Substituting in (1) yields gm1,2 ≈ 160 μS. Since the 20 μA OTA bias
current is split equally between M1 and M2, the gm ∕ID of the input pair
The target design example is a single-ended output five-transistor is
OTA to be used as a unity-gain buffer to drive a large capacitive load.
(gm ∕ID )1,2 ≈ 16 S∕A (2)
The design specifications are shown in Table 1. The available current
consumption for the OTA is 20 μA. In addition, a 10 μA reference cur- The channel length can selected from the gain spec. The differential
rent is externally provided. The OTA gain-bandwidth product (GBW) DC gain of the OTA is given by Ref. [10].
is roughly equal to the buffer closed-loop bandwidth (BWCL ), and the
gm1,2
OTA common-mode input range (CMIR) is itself the buffer input range. Avdc = (3)
gds2 + gds4

2.2. Trade-off charts generation From (2) and Table 1, the requirement on the output conductance of
M2 and M4 is
DC simulation is used to generate the operating point parameters,
and AC noise simulation is used to extract the value of the noise gds2 + gds4 < 4 μS (4)
coefficient (𝛾 ). DC sweep is used for VGS from ≈ VTH − 100 mV to It is fair to assume that this requirement is split equally between M2 and
≈ VTH + 500 mV. Parametric sweep is used for the channel length (L). M4, i.e., M2 and M4 have the same output conductance (gds2 = gds4 <
The channel width (W) is kept constant since the transistor parameters 2 μS). Thus, the intrinsic gain of the input pair is constrained by
are approximately proportional to W regardless of the operating region.
A channel width of 10 μm is selected to avoid narrow width effects, not- (gm ∕gds )1,2 ≥ 80 (5)

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M.N. Sabry et al. Microelectronics Journal 75 (2018) 87–96

The channel length can be selected using the intrinsic gain vs gm ∕ID
chart shown in Fig. 2a. This chart shows a fundamental trade-off
between gain and speed, where higher gain requires long channel
length and large gm ∕ID , which both come at the expense of speed.
Selecting L1,2 ≈ 0.8 μm yields (gm ∕gds )1,2 ≈ 87, which satisfies (5).
The channel width can be specified using the current density (ID ∕W )
vs gm ∕ID chart shown in Fig. 2b. Using the previously calculated values
for (gm ∕ID )1,2 and L1,2 yields a current density ≈ 0.44 μA∕μm; thus the
width is given by
ID
W1,2 = ≈ 24 μm (6)
(ID ∕ W )

2.4. Design of the current mirror load

From Section 2.3, the condition on the output conductance of the

NMOS current mirror load (M3 and M4) is given by

gds3,4 ≤ 2 μS (7)

Thus, the gds ∕ID ratio of the current mirror load is equal to 0.2V− 1 .
This ratio is equivalent to the channel length modulation coefficient (𝜆)
in the long-channel model. gds ∕ID strongly decreases with increasing
L, and slightly increases with increasing gm ∕ID . Since the dependence
of gds ∕ID on gm ∕ID is rather weak, it can be initially ignored in order
to obtain an estimate for the channel length of M3 and M4. In order
to use the intrinsic gain vs gm ∕ID chart, we assume an arbitrary but
relatively large value for gm ∕ID , such that the actual gain is higher than
the required specification, which is usually desirable. Assuming gm ∕ID =
15 yields gm = 150 μS and gm ∕gds ≥ 75. From the chart in Fig. 3a, the
channel length that satisfies this requirement is L3,4 = 0.6 μm.
The choice of the gm ∕ID of the current mirror load is constrained
by the input range and the RMS noise specifications. Starting with the
input range, the minimum input signal that can be tolerated before
driving the input pair out of saturation is given and constrained by

Vin,min = 0.2 V ≥ −|VGS1,2 | + |Vdsat1,2 | + VGS3,4 (8)

where Vdsat is the minimum drain-source voltage required to keep the

transistor in saturation, and is equivalent to the overdrive voltage for
a square-law device. |VGS1,2 | and |Vdsat1,2 | can be extracted from the
PMOS input pair VGS and Vdsat charts shown in Fig. 2c and d, and are
approximately equal to 570 mV and 100 mV, respectively. Substituting
in (8), the constraint on M3 and M4 can be written as

VGS3,4 ≤ 0.67 V (9)

By using the NMOS VGS chart in Fig. 3b, the constraint on the NMOS
current mirror load due to the input range specification can be written
as
( )
gm
≥ 8.3 S∕A (10)
ID 3,4

The closed loop gain of the buffer is ≈ 1; thus, the total output-
referred mean-square integrated noise is given and constrained by
𝜋
V2n,rms ≈ V2n,in (f ) · BWCL (11)
2
gm1,2
= V2n,in (f ) · < (50 μVrms)2 (12)
4CL

where V2n,in (f ) is the input-referred thermal noise density, which is

given by
4kT 𝛾eff √
V2n,in (f ) = < (17.7 nV∕ Hz)2 (13)
gm1,2
where k is Boltzmann constant, T is the temperature in Kelvin, and 𝛾eff Fig. 2. PMOS input stage (M1 and M2) design charts vs gm ∕ID with length as a parameter
is the effective noise coefficient of the OTA, which is given by (L = 0.4 μm ∶ 0.2 μm ∶ 2 μm): (a) intrinsic gain (gm ∕gds ), (b) current density (ID ∕W ), (c)
( ) VGS , (d) Vdsat (variation with L is negligible), and (e) noise coefficient (𝛾P ).
g
𝛾eff = 2 × 𝛾P + 𝛾N · m3,4 (14)
gm1,2

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M.N. Sabry et al. Microelectronics Journal 75 (2018) 87–96

Fig. 3. NMOS current mirror load (M3 and M4) design charts vs gm ∕ID with length as
a parameter (L = 0.4 μm ∶ 0.2 μm ∶ 2 μm): (a) intrinsic gain (gm ∕gds ), (b) VGS , and (c)
current density (ID ∕W ).
Fig. 4. PMOS tail current source (M5) design charts vs gm ∕ID with length as a parameter
(L = 0.4 μm ∶ 0.2 μm ∶ 2 μm): (a) intrinsic gain (gm ∕gds ), (b) Vdsat (variation with L is
negligible), and (c) current density (ID ∕W ).

where 𝛾N and 𝛾P are the noise coefficients of NMOS and PMOS devices,
respectively [10]. Substituting from (13) in (12), the RMS noise con- value (gm ∕ID = 15) used to obtain L. The width of M3 and M4 can be
straint can be written as selected from the NMOS current density chart shown in Fig. 3c, where
kT 𝛾eff (ID ∕W )3,4 ≈ 6.7 μA∕μm; thus, W3,4 ≈ 2 μm.
V2n,rms = < (50 μVrms)2 (15)
CL
2.5. Design of the tail current source
𝛾eff < 3.02 (16)
The last step towards the design of the OTA is the design of the
From the PMOS noise chart in Fig. 2e, 𝛾P ≈ 0.86. Thus, by substitut- PMOS tail current source. The sizing of the tail current source is con-
ing in (14) the constraint on M3 and M4 can be written as strained by the CMRR and the input range specifications. The CMRR is
𝛾N gm3,4 ≤ 103 μS (17) given by Ref. [10].
CMRR (dB) = Avdc (dB) − Avdc,CM (dB) (19)
In general, the value of 𝛾N is a function of gm ∕ID ; thus, (17) should be
plotted on the NMOS noise chart to find the gm ∕ID that satisfies the where Avdc,CM is the common-mode DC gain. Substituting with data
constraint. However, the dependence of 𝛾N on gm ∕ID is fairly weak, from Table 1, the constraint can be written as [10].
and for L = 0.6 μm it is roughly constant at 𝛾N ≈ 0.89. Therefore, the 2gm1,2 1
constraint on the NMOS current mirror load can be directly written as Avdc,CM ≈ 2gm1,2
· (20)
1+ 2gm3,4
( ) gds5,6
gm
≤ 11.6 S∕A (18)
ID 3,4 < −38 dB ≈ 0.013 (21)

The constraints in (10) and (18) shows the trade-off between head-
room and noise, where lower gm ∕ID for the current mirror load cor-
responds to lower total noise but smaller signal swing. As a compro-
mise, we will proceed with (gm ∕ID )3,4 = 10 S∕A which satisfies both
requirements with adequate margin, and is lower than the assumed
Therefore, the output conductance of the tail current source must satisfy
gds5,6 < 2.6 μS (22)
Similar to Section 2.4, an arbitrary but relatively large value for
gm ∕ID can be assumed to obtain L. Assuming gm ∕ID = 15 S∕A results in

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Table 2
Summary of the OTA transistors sizing.
Transistor gm ∕ID Length Width Function
M1 and M2 16 0.8 μm 24 μm Input pair
M3 and M4 10 0.6 μm 2 μm Current mirror load
M5 and M6 14 1.2 μm 52 μm and 26 μm Bias current mirror

Fig. 5. Simulation results of (a) loop gain and (b) phase vs frequency in unity gain buffer
configuration. Open-loop DC gain, unity-gain frequency (𝜔u ), and phase at 𝜔u are anno-
tated.
gm = 300 μS and gm ∕gds ≳ 115 (note that ID = 20 μA for the tail current
source). From the PMOS intrinsic gain chart shown in Fig. 4a, choosing
L5,6 = 1.2 μm satisfies this requirement.
In order to keep the tail current source in saturation, the maximum
allowable input voltage is given by
Vin,max = 1.1V < VDD − |VGS1,2 | − |Vdsat5,6 | (23)
Since VGS1,2 ≈ 570 mV as calculated in Section 2.4, the CMIR constraint
can be written as
|Vdsat5,6 | < 130 mV (24)
From the PMOS Vdsat chart in Fig. 4b, the range of gm ∕ID that satisfies
this requirement is
( )
gm
≳ 11.84 (25)
ID 5,6
To keep some margin from operating the tail current source at the edge
of saturation, (gm ∕ID )5,6 = 14 is used, which is lower than the assumed
value (gm ∕ID = 15) used to obtain L. The selected gm ∕ID yields a current
density ≈ 0.4 μA∕μm as shown in the PMOS current density chart in
Fig. 4c. Consequently, the channel widths of the bias circuit are given
by W5 ≈ 52 μm and W6 ≈ 26 μm.
2.6. Results and discussion
Table 2 shows a summary of the OTA transistors sizing. The OTA
was verified using Cadence Spectre and 180 nm PTM model [12]. A
testbench similar to the one described in Ref. [13] is used. Fig. 5a shows
the simulated loop gain in unity-gain buffer configuration using Spec-
tre stability (stb) analysis. The DC gain is ≈ 33.5 dB and the GBW is
Fig. 6. Simulation results of (a) operating region of input pair (M1,2) and tail current
source (M5) vs buffer input voltage, and (b) variation of GBW vs buffer input voltage.
The region parameter is “1” for triode, “2” for saturation, and “3” for subthreshold. The
CMIR is annotated.
≈ 5 MHz, where both meet the requirements. As expected in Section 2.3
the OTA intrinsic capacitance has minor impact as it is much smaller
than the large capacitive load. However, if the effect of self-loading is
to be considered, the OTA internal capacitance can be estimated from
the MOSFET capacitance vs gm ∕ID charts. Next, another design itera-
tion is performed which takes both intrinsic and extrinsic capacitances
into consideration as will be shown in Section 3. Since the OTA has a
single dominant output pole, the phase margin specification is satisfied
without extra design effort as shown in Fig. 5b.
The buffer input range can be verified by plotting the operating
region of the input pair (M1,2) and the tail current source (M5) vs the
input voltage. The meaning of the “region” small signal parameter is
as follows: “1” for triode, “2” for saturation, and “3” for subthreshold
operation. The valid input range over which all transistors operate in
saturation is 0.14 V − 1.12 V as shown in Fig. 6a. The drawback of the
previous method is that the “region” parameter does not have a clear
quantitative relation to circuit specifications, and cannot be experimen-
tally measured in a lab environment. A more meaningful indication of
the CMIR can be obtained by using a parametric sweep to plot the GBW
vs the input signal level as shown in Fig. 6b, which shows that the GBW
quickly degrades when the input signal is outside the target range.
The output voltage noise density and the RMS total integrated noise
√
vs frequency are shown in Fig. 7. The noise density is ≈ 17nV∕ Hz
which meets the constraint in (13), and the total integrated RMS ther-
mal noise is 48.6 μVrms which meets the spec in Table 1. The CMRR
is verified using Spectre transfer function (xf) analysis. The achieved
CMRR is ≈ 73.6 dB as shown in Fig. 8.
The key simulation results are summarized in Table 3 and compared
with the required specifications. The comparison shows that all target

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M.N. Sabry et al. Microelectronics Journal 75 (2018) 87–96

Fig. 9. Simplified schematic for the analysis of the effective load capacitance.

problem that has no closed-form solution.

Fig. 7. Simulation result of OTA output noise: (a) voltage noise density vs frequency and
(b) integrated RMS noise vs frequency. Noise density and total output RMS noise are
annotated.
The aforementioned drawbacks can be alleviated by noting that
since the design flow is systematic, it lends itself well to automation.
First, the design procedure will be performed by a computer program
in a fraction of second. Second, the dataset can be much larger, and
interpolation can be used to improve the design step. Third, the design
procedure can be applied iteratively to solve sophisticated design and
optimization problems that do not have direct solutions.
As an example, in Section 2.3, the self-loading capacitance of the
OTA (COTA ) was neglected compared to the large load capacitance (CL ).
This approximation may be justified for CL ≫ COTA ; however, the error
significantly increases when this assumption is not valid. In general, (1)
should be modified to be
g
GBW = m1,2 (26)
2𝜋 CLeff

where CLeff = CL + COTA . However, in order to calculate COTA the siz-

ing of the transistors must be known. Contrastingly, the sizing is itself
the desired outcome of the design procedure. Such a dilemma can be
resolved by solving the problem iteratively as will be shown in the fol-
lowing subsections.

3.1. Analysis of the effective load capacitance

Fig. 8. Simulation result of OTA CMRR vs frequency.
Before delving into automation, an analytical expression must be
derived for the effective load capacitance (CLeff ). The equivalent circuit
for calculating CLeff of the OTA in unity gain buffer configuration is
specifications are successfully satisfied, which demonstrates the robust-
shown in Fig. 9. The output resistance and the drain capacitance of the
ness of the gm ∕ID design methodology.
tail current source (M5) are ignored to simplify the analysis. The drain-
bulk capacitance of M2 and M4 (CDB2 and CDB4 ) directly add to CL .
3. Automated design procedure using MATLAB The gate-drain capacitance of M4 (CGD4 ) has its gate terminal at a low
impedance node (diode-connected M3); thus, approximately, it directly
Section 2 showed a systematic design flow using gm ∕ID trade-off adds to CL as well. However, the gate-source capacitance of M2 (CGS2 )
charts. Despite the merits of this graphical flow, it suffers from several is floating between Vout and Vx ; thus, its contribution at Vout must be
drawbacks. First, it is time-consuming, and can be tedious if repeated analyzed. Assuming a test source Vt is applied at Vout , the gain from Vt
several times due to the frequent changes in specifications during the to Vx can be calculated as follows
initial phases of an IC design project. Second, in order to keep it
[( ‖ )‖ ( ‖ )]
tractable, the dataset was limited by choosing a relatively coarse step ( )
Vx 1 ‖‖ 1
‖
‖ 1 ‖
‖ 1 1
= Gm Zout ≈ gm2 + sCgs2 · ≈
gm1 ‖ ‖ ‖
for channel length and ignoring second order effects, e.g., VDS depen-
Vt ‖ sCgs1 ‖ gm2 ‖ sCgs2 2
dence. Third, it cannot be directly applied to a sophisticated design ‖ ‖ ‖
(27)

where M1 has a low impedance at its drain terminal. Thus, the contri-
Table 3 bution of CGS2 at Vout can be calculated using Miller’s theorem
Comparison of required specifications and achieved results. ( )
V C
Specification Required Achieved CGS2@Vout = CGS2 1 − x ≈ GS2 (28)
Vt 2
OTA Current Consumption 20 μA 20 μA
GBW 5 MHz 5 MHz Alternatively, (28) can be derived by looking from Vout while Vin is
Phase Margin 70o 90o
deactivated. It can be noted that CGS2 and CGS1 appear in series; thus,
Open Loop DC gain 32 dB 33.5 dB
Total Integrated Thermal Noise 50 μVrms 48.6 μVrms they are equivalent to a capacitance ≈ CGS2
2
at Vout . The effective load
Input Range 0.2 V − 1.1 V 0.14 V − 1.12 V capacitance can now be written as
CMRR 70 dB 73.6 dB
CLeff = CL + COTA (29)

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M.N. Sabry et al.
Fig. 10. Simplified flow chart for the iterative design procedure to take the effective load
capacitance into account. As an example, maximum no. of iterations is set to 10 and the
relative tolerance is set to 0.1%.
CGS2
≈ CL + + CDB2 + CGD4 + CDB4
2
The above analysis was verified using AC simulations, where the
GBW is measured from simulations, then CLeff is calculated using (26).
Simulations show that (30) slightly underestimates CLeff , especially for
large CL , as will be shown in Section 3.3. It is worth noting that the
feedback connection in Fig. 9 forms a short-circuit across CGD2 ; thus, it
does not contribute to CLeff . However, if the feedback loop is broken by
a current probe or a zero voltage source in order to perform stability
analysis, the simulator may erroneously add the effect of CGD2 to CLeff .
The solution to this simulator artifact is to substitute in (26) with GBW
measured from closed loop AC simulation rather than stability analysis.
3.2. Iterative design procedure
A MATLAB program was written to automate the design procedure
explained in Section 2. The NMOS and PMOS operating point and noise
parameters are stored as lookup tables (LUTs) in the form of MATLAB
matrices. A lookup function is used to extract the data from the LUTs
[14]. The systematic design procedure is embedded in an iterative loop
to take the effect of OTA capacitances into account. The flowchart of
the program is shown in Fig. 10. The program starts by assuming that
COTA = 0; thus, CL is assigned to CLeff . Two variables are used to con-
trol the iterative loop: ’MaxNoIter’ defines the maximum number of
iterations to avoid going into an infinite loop, and ’reltol’ defines the
required relative tolerance. The loop performs the sizing procedure,
then calculates COTA from the LUTs based on the sizing results. The rel-
Microelectronics Journal 75 (2018) 87–96
Fig. 11. Normalized progress of COTA vs the iteration index for different values of CL .
Fig. 12. Percent error in achieved GBW as extracted from AC simulations vs CL .
ative error is then calculated to compare the new CLeff with the value
of CLeff used in the current iteration as follows
|C + C |
|
Error = | L OTA
− 1|| (31)
| CLeff |
| |
Convergence is achieved if the error is less than the required relative
tolerance (0.1% in Fig. 10). The sizing results are then displayed to the
user.
(30) 3.3. Results and discussion
The automated iterative procedure was used to design the OTA for
different values of CL . Fig. 11 shows the variation of COTA vs the index
of iteration at different loading conditions. It is clear that the value of
COTA converges very quickly, and the required tolerance is achieved in
few iterations. The designed OTAs were simulated at different values
of CL in order to verify the automated procedure. For each value of
CL two OTA versions were simulated. The first version used transistor
sizing from single design iteration (i.e., COTA = 0), while the second ver-
sion used the iterative procedure to obtain a better estimate for COTA .
Fig. 12 shows that for single iteration the percent error at CL = 0.5 pF
is ≈ 10%. On the contrary, the iterative procedure gives a less than
1% error. The residual error for the iterative case is due to the approx-
imate nature of the analytical expression in (30) which was used to
estimate COTA in the program. The negative error shows that CLeff is
slightly underestimated (especially at relatively large CL ). A more elab-
orate expression, or an expression fitted from simulations, can be used
to reduce the error. Fig. 12 also shows that as CL increases, the con-
tribution of COTA becomes negligible, and the two curves will slowly
approach each other. It is worth noting that the OTA specifications in
Table 1 targets a low-power implementation (IOTA = 20 μA) that has
relatively small self-loading capacitance. If both current consumption
and speed are upscaled, the transistors widths and capacitances will
upscale as well, resulting in a significant COTA that can be comparable
to CL . Neglecting COTA in such a case can result in more than 50% error,
and the iterative procedure becomes indispensable.
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M.N. Sabry et al. Microelectronics Journal 75 (2018) 87–96

Table 4
Modified OTA specifications for optimizing GBW.
Specifications that are not shown are similar to Table 1.
Current Consumption 20 μA
Capacitive Load 5 pF
Input Capacitance at Low Frequency < 10 fF
Open-Loop DC gain 32 dB
Gain-Bandwidth Product Maximize

4. Automated optimization procedure using MATLAB

The design procedure explained in Section 2 then automated in Fig. 13. Simplified schematic for the analysis of the buffer input capacitance.
Section 3 assumed a complete and well-defined set of specifications
(constraints). However, optimizing real-life designs usually involve one
or more variables that need to be maximized or minimized given a Due to the unity-gain feedback action Vout is related to Vin through the
set of constraints. In this section we will give an example of such an relation
( )
optimization scenario within the framework presented in the previous Avdc 1
sections. Vout = Vin · ≈ Vin 1 − (34)
1 + Avdc Avdc
Substituting from (32) and (34) in (33), Vx can be written as
4.1. Optimization problem ( )
g 1
Vx = − m3 Vy + Vin 1 − (35)
The design example presented in this paper deals with a unity-gain gm2 Avdc
buffer that drives a large capacitive load, e.g., probing a sensitive sig- Writing KCL equation at Vy yields
nal in a mixed-signal design to an external test-pad. Consequently, the ( )
buffer should introduce minimum capacitive loading on the input sig- gm3 Vy + gds1 Vy − Vx + gm1 (Vin − Vx ) = 0 (36)
nal. Consider the modified set of specifications shown in Table 4, where where M1 has Vgs = Vin − Vx . Substituting from (35) in (36) and noting
the maximum input capacitance at low frequency is required to be that Avdc = 2ggm1 , it can be shown that Vy is approximately given by
ds1
less than 10 fF. The set of specifications is similar to the one given
in Table 1 except for the GBW. The optimization scenario presented in Vy g
≈ − ds1 (37)
this section considers the case of maximizing the OTA GBW under a Vin 2gm3
given current consumption, input capacitance, and DC gain specifica-
Substituting from (37) in (35) yields
tions. Maximizing the GBW for a given current means that gm ∕ID must
be maximized. However, increasing gm ∕ID means that the transistors are Vx 3
≈1− (38)
biased towards subthreshold operation, where they will have low cur- Vin 4Avdc
rent driving capability, i.e., low current density (ID ∕W ). Consequently, Using Miller’s Theorem and substituting with (37) and (38), Cin can
for a given bias current, W will increase, which will result in increased now be written as
capacitive loading on the stage preceding the buffer. On the other hand, ( ) ( )
V Vy
increasing gm ∕ID increases the intrinsic gain of the transistors. Since the Cin = CGS1 1 − x + CGD1 1 − (39)
gain spec is fixed, this means that a lower L can be used to satisfy the Vin Vin
gain spec, which may lead to a lower W and lower Cin . The overall vari- 3
≈ CGS1 · + CGD1 (40)
ation of Cin depends on how these two opposite effects interact together. 4Avdc
These constraints will limit the maximum gm ∕ID that can be used, and
The above analysis was verified using AC simulations showing good
consequently the maximum GBW that can be achieved.
match. It is worth noting that Cin is dominated by CGD1 rather than
CGS1 , since the effect of CGS1 is mitigated by the OTA gain as given by
4.2. Analysis of the buffer input capacitance (40).

An analytical expression for the buffer input capacitance (Cin ) has to
be derived in order to be used in the optimization program. A simplified
schematic for calculating Cin at low frequency is shown in Fig. 13. The
output resistance and the drain capacitance of the tail current source
(M5) are ignored for simplicity. M2 and M3 are both diode connected
transistors (due to the feedback and current mirror connections, respec-
tively); thus, they are equivalent to a low impedance ≈ 1∕gm . The input
signal is loaded by two floating capacitors: CGS1 and CGD1 . Thus, in
order to calculate the equivalent input capacitance, the gain from Vin
to Vx and Vy must be derived, then Miller’s theorem can be applied.
The current flowing through M3 is given by
iy = gm3 Vy (32)
Considering M1 as a super node, it is clear that the current flowing
through M2 is also equal to iy . Therefore, Vx can be written as
iy
Vx = − + Vout (33)
gm2
4.3. Optimization procedure
The flowchart of the optimization procedure is shown in Fig. 14.
The optimization procedure makes use of MATLAB power in handling
matrix operations. A gm ∕ID vector is created from 5 to 20 with 0.1
step resulting in 151 total design points. This vector reasonably cov-
ers the expected design space, and can be thought as equivalent to the
x-axis in the graphical procedure presented in Section 2. The previous
section described an automated iterative procedure where each itera-
tion depends on the result of the previous one. On the other hand, the
optimization procedure described in this section is applied to all design
points simultaneously using element-wise vector operations. For every
gm ∕ID value, the program searches for the minimum channel length of
M1 and M2 that satisfies the DC gain requirement. This step involves
multiple sub-steps because the current is constant; thus, every gm ∕ID
will yield a different gm and a different gds . A plot of the selected
channel length vs gm ∕ID is shown in Fig. 15a. It is worth noting that
automation facilitates using interpolation to yield a continuous channel

94
M.N. Sabry et al.
Fig. 14. Simplified flow chart for the GBW optimization procedure.
Fig. 15. Intermediate results of the MATLAB optimization program: (a) Channel length
and current density selected based on DC gain spec vs gm ∕ID and (b) input capacitance vs
gm ∕ID . The input capacitance meeting the design specification is annotated.
length curve, rather than the 0.2 μm step that was used in the graphical
procedure. The decrease in L vs gm ∕ID may misleadingly indicate that
the capacitance will decrease. However, the decay in current density is
faster as shown in Fig. 15a, leading to an overall increase in channel
width and input capacitance.
At every combination of gm ∕ID and L the program calculates the
corresponding ID ∕W and W, extracts the capacitances from the LUTs,
then Cin is calculated using (40). The plot of Cin vs gm ∕ID is shown in
95
Microelectronics Journal 75 (2018) 87–96
Fig. 16. Simulation results of (a) buffer input capacitance vs frequency and (b) loop-gain
vs frequency. Cin at low frequency, open-loop DC gain, and unity-gain frequency (𝜔u ) are
annotated.
Table 5
Comparison of required specifications and achieved results.
Specification Required Achieved
OTA Current Consumption 20 μA 20 μA
Input Capacitance 10 fF 9.9 fF
Open Loop DC gain 32 dB 32.6 dB
GBW Maximize 3.95 MHz
Fig. 15b. The program takes 10% margin below the Cin design spec
to account for the approximations done in (40). For the specifications
given in this example, a (gm ∕ID )1,2 = 12.8 is chosen. The selected gm ∕ID
is then used to complete the design procedure similar to the previous
sections.
4.4. Results and discussion
The buffer input capacitance was simulated using AC analysis. The
simulation results are shown in Fig. 16a, where Cin ≈ 9.9 fF achieving
the required spec. The input capacitance increases with frequency as the
OTA gain falls. The loop-gain simulation is also shown in Fig. 16b. The
DC gain meets the required spec, and the achieved GBW is 3.95 MHz. A
higher GBW can be obtained by revisiting the assumption made after (4)
and selecting a higer output conductance (smaller L) for the input pair
compared to the load. The achieved results are summarized in Table 5.
5. Conclusion
A complete OTA systematic design example considering gain, band-
width, noise, CMIR, and CMRR specifications was graphically illus-
trated using the gm ∕ID design methodology. The proposed systematic
procedure was automated using MATLAB, which enabled tackling iter-
ative and optimization problems. Analytical expressions were derived
for the OTA self-loading and input capacitances. The derived expres-
sions were further verified and employed in the automation programs.
The performance of the designed OTAs was verified using Cadence
Spectre, and simulation results meet all the design requirements with
M.N. Sabry et al.
acceptable accuracy. The proposed procedure can be similarly applied
to other OTA topologies. It is worth noting that the work presented in
this paper assumes that the circuit architecture is known beforehand. A
promising future extension to this work is to build a more sophisticated
automation procedure that selects (or synthesizes) the circuit architec-
ture based on the given specifications, possibly with the help of circuit
synthesis and symbolic analysis techniques [15–17].
Acknowledgments
The authors would like to thank Omar A. Abu-El-ela for useful hints
and discussions.
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