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Laboratory Exercise #2 4-Bit BCD Decoder: Submitted To Professor in EE 538/L
Laboratory Exercise #2 4-Bit BCD Decoder: Submitted To Professor in EE 538/L
Submitted to
ENGR. RODRIGO S. PANGANTIHON, JR., MIT
Professor in EE 538/L
Submitted by:
GLORY MAE M. FLORES
Student
November 2018
I – INTRODUCTION
II – OBJECTIVES
A B
1 0 1 1 1 1 1 1
0 1 1 1 1 0 1 0 A = B’D’ + C + B’D’ + A
x x x x x x x x B = B’ + C’D’ + CD
1 1 x x 1 1 x x
C = C’ + D + B
E F G
1 0 0 1 1 0 0 0 0 0 1 1
0 0 0 1 1 1 0 1 1 1 0 1
x x x x x x x x x x x x
1 0 x x 1 1 x x 1 1 x x
V – LOGIC CIRCUIT / DIAGRAM
VI – CONCLUSION
In light of this laboratory activity, the following conclusions were drawn about 4-
bit BCD decoder:
1. The usage of basic logic gates in decoding BCD for 7 segment display has
taught me how larger scale ICs work.
2. The painstakingly crucial process of the implementation in the breadboard also
taught me to be more thorough and careful with the circuitry.
VII – RECOMMENDATION