12-bit SAR ADC Design in 180 nm for Sensor Signal
Conditioning Applications
Abstract—Aim of this work is to create an analog to digital
converter (ADC) for the application of sensor signal conditioning
circuit. Successive approximation register (SAR) ADC was
chosen due to the requirements of implementation of this circuit
in 180nm technology, which leaves less room for complex and
high-resolution circuits. Hence, low frequency of operation with
low complexity is needed with moderate resolution, making SAR
ADC a best suitable choice. All the blocks of ADC such as Digital
to Analog converter (DAC), Comparator, Successive
Approximation Register (SAR) logic and sample and hold circuit
are implemented using Cadence Analog design tool with 180nm
PDK from Semiconductors laboratory, Chandigarh. The
proposed design achieves 1.1MS/s for 12 bits resolution
surpassing [1] and [2] while providing better SNDR (73.54dB)
and ENOB of (11.92 bits).
Keywords— Analog to digital converters (ADC),
Successive Approximation Register (SAR), Differential
charge scaling DAC, Boot-strapped switch, Auto-zeroing
technique.
I. INTRODUCTION
All the modern systems are digital in nature and require
analog to digital and digital to analog conversion to measure
response of all natural signals through sensors.
Depending on applications, there are various types of
ADCs. Higher sampling speed and higher resolution are not
achievable simultaneously, which creates a trade-off for
design. For IC design applications generally three type of
ADCs are used which are delta-sigma ADC, SAR-ADC and
Pipeline ADC. For high resolution and low speed application
delta sigma ADC is used, and for low resolution and high-
speed applications pipeline ADC is preferred while SAR-ADC
achieves moderate speed (10K- 1M samples per second) at
moderate resolution of 8-16 bits. A Delta sigma ADC consists
of simple analog block such as integrator, difference amplifier
and comparator but it requires complex digital filter, which
requires larger area for its implement. The simplest deign
among these three ADC is SAR ADC which consists of
sample and hold, comparator, DAC and SAR logic block.
Pipeline ADC can be thought of as combination of SAR ADC
and flash ADC but the size of this ADC is largest making it
least suitable for low cost applications.
XXX-X-XXXX-XXXX-X/XX/$XX.00 ©20XX IEEE
II. DESIGN AND INTEGRATION
Architecture of SAR ADC can be mainly divided into four
blocks [1, 2] as Digital to Analog converter (DAC),
Comparator, Successive Approximation Register (SAR) logic
and Sample and Hold circuit
A. Digital-to-analog converter (DAC)
In this design 12-bit differential charge scaling DAC [3] is
used which have dual input and dual output. This architecture
has 3 main advantages (a) Input voltage range will double with
increase of core power supply, (b) Cancellation of even order
harmonics, (c) Common mode rejection.
𝑉𝑂𝑈𝑇𝑝 − 𝑉𝑂𝑈𝑇𝑛 = (𝑉𝐼𝑁𝑃 − 𝑉𝐼𝑁𝑁 ) − 𝑉𝐷𝐷 + 2 {𝐵(𝑁 −
𝑉𝑟𝑒𝑓 𝑉𝑟𝑒𝑓
1) + 𝐵(𝑁 − 2) …+
2 4
𝑉𝑟𝑒𝑓
𝐵0 } (1)
2𝑁−1
B. Comparator
Comparators used in SAR ADC are discrete time, which
can be divided in 3 parts: preamplifier, regenerative latch and S
R flip flop. The pre amplifier block consists of a fully
differential amplifier in cascade with another differential
amplifier.
Since the pre amplifier block is active for only half clock
cycle, a regenerative latch is required to hold the comparison
result and hence regenerative latch is connected to SR flip-flop.
This is also known as auto-zeroing technique [4]. The inverted
clock, which is connected to SR flip flop, gives logic output at
positive edge of clock signal.
C. Switch
To overcome the drawbacks of transmission gate switches
and to suppress higher order harmonics, a switch, whose ON
resistance is constant, is needed. Bootstrapped switches have
emerged very useful in those applications [5].
When gate voltage of NMOS is changed from VDD to
ground then NMOS will not be instantly OFF. This causes
charge leakage from capacitor and input is shorted to ground
resulting in short-circuit. To turn off NMOS switch, its gate
voltage has to change from high to low instantly. To avoid
this, a two phase clock circuit is used as shown in figure
below
 Table I. COMPARISON OF RESULTS
Specifications [2] [3] This
work
Technology 180nm 180nm 180nm
Resolution (bits) 10 12 12
Power supply (V) 0.6 1.8 1.8
Sampling frequency 0.2 0.2 1.1
(M samples/s)
Maximum DNL/INL 0.29/ NA 0.8/3
-0.8
Fig. 1. Two phase clock circuit used for bootstrapped switch
SNDR (dB) 69.55 71.55 73.54
ENOB (bits) 9.3 11.59 11.92
D. SAR logic
Power (µW) 2 336 188
The components used in SAR logic are (a) 14 Bits Ring FOM (fJ/conversion 15.51 … 44
Counter, (b) Array of D Flip-Flop, (c) 12 Bits Array of NOR step)
and OR gates, and (d) Parallel In Parallel Out (PIPO) Register
[1, 2]. This consists of a N+2-bit ring counter for N bit SAR
ADC, and remaining two bits are required for sampling and IV. CONCLUSION
hold purposes.
A 12 bit SAR ADC design is completed and simulated
At sampling phase analog input voltage is sampled on the
using cadence with virtuoso and calibre tools with 180 nm
capacitors of DAC. At hold phase neither analog switch nor
PDK. Designed ADC exhibited better sampling frequency due
digital switch are connected to capacitor of DAC. After the
to bootstrapped switching and auto-zeroing technique for fast
hold, in conversion phase SAR operation starts and digital
comparison. Also the differential charge scaling DAC used in
switch are connected to capacitor of DAC. Except for two
design kept the capacitor sizes low which reduced the size of
MSBs of ring counter all the outputs is connected to clock
entire circuit.
input of an array of D-FF and simultaneously array of 2-input
OR gate array. Other pair of 2-input OR is connected through V. ACKNOWLEDGMENT
output of this array of D-FF. All the input array of D-FF is
connected through output of comparator. The main purpose of The authors would like to thank SCL Chandigarh, for
array of D-FF is that it holds results of previous comparison. providing the PDK of 180 nm, which was used in the design
Output of OR gate array with inverter is used for controlling of all the circuits. This work was sponsored by Special
digital inputs of DACs. Array of D-FF should be cleared Manpower Development Program for Chip to System Design
before starting of conversion phase. Output from OR gate (SMDP-C2SD) Project, an initiative of Ministry of Electronics
array is also connected to input of parallel in parallel out and Information Technology (MeITY).
(PIPO) register. The output of this PIPO register is updated at
end of the conversion phase. These outputs of PIPO are final
digital outputs for external interface. REFERENCES
[1] Y. Song, Z. Xue, Y. Xie, S. Fan, and L. Geng, "A 0.6-V 10-bit 200-kS/s
III. RESULTS AND DISCUSSION Fully Differential SAR ADC With Incremental Converting Algorithm
for Energy Efficient Applications," IEEE Trans. on Circuits and
The maximum sampling frequency, without affecting the Systems, vol. 63, pp. 449-458, 2016.
performance of SAR ADC is found to be 1.1-MS/s which is [2] X. Zhang, M. Wang, L. Guo, and X. Wang, "A 12-bit 200KS/s SAR ADC
about 5.5 times higher than as compared to Ref [1]. Maximum with Digital Self-Calibration," 2017 IEEE 2nd Advanced Information
value of DNL and INL error is calculated for this design is 0.8 Technology, Electronic and Automation Control Conference (IAEAC),
pp. 2531 – 2535.
LSB and 3 LSB respectively. Since magnitude of DNL is less [3] Y.-H. Chung, C.-W. Yen, P.-K. Tsai, and B.-W. Chen, "A 12-bit 40-MS/s
than 1 LSB, it can be concluded that there are not any SAR ADC With a Fast-Binary-Window DAC Switching Scheme," IEEE
intermediate missing digital counts. Split capacitor 𝐶𝑆 Transactions on Very Large Scale Integration (VLSI) Systems, pp. 1-10,
reduces the effective capacitance seen by input source. Due to 2018.
[4] Y. Zhu, C.-H. Chan, U.-F. Chio, S.-W. Sin, U. Seng-Pan, R. P. Martins, et
split capacitor 𝐶𝑆 , higher sampling rate was achieved in this al., "Split-SAR ADCs: Improved linearity with power and speed
design. Since this split capacitor increase the parasitic optimization," IEEE Transactions on Very Large Scale Integration
capacitance so DNL and INL error is more as compare to Ref (VLSI) Systems, vol. 22, pp. 372-383, 2014.
[1]. SNDR achieved this design is 73.54dB. The average [5] L. Wang, W. Yin, J. Xu, and J. Ren, "Dual-channel bootstrapped switch
for high-speed high-resolution sampling," Electronics Letters, vol. 42,
power consumption of this SAR ADC is 188µW, which is pp. 1275-1276, 2006.
about half as compare to Ref [2]. Using this SNDR value, the
ENOB of this ADC is calculated to be 11.92 bits. FOM of this
SAR ADC is calculated to be 44fJ/conversion step.