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CH 02B Inverter
CH 02B Inverter
Lecture 02:
CMOS Inverter
By Beyene Jember 1
Outlines
Static CMOS Logic Circuit
Scaling
2
Review: The MOS Transistor
3
MOS inverter
4
CMOS Logic Structures
5
Introduction to digital circuits: The inverter
In digital circuits, digitally-encoded information is represented by means of two distinct
voltage ranges:
7
Ideal inverter…
Define switching point or logic threshold :
VM input voltage for which VOUT = VIN
Ideal inverter returns well defined logical outputs (0 or V+) even in the presence of
considerable noise in VIN (from voltage spikes, crosstalk, etc.)
signal is regenerated!
8
Real inverter
VOUT
VMAX
V ----------
OH slope=-1
VOL
VMIN
0
0 V+ VIN
9
Real inverter…
Logic 0:
– VMIN output voltage for which VIN = V+
– VOL smallest output voltage where slope = -1
Logic 1:
– VOH largest output voltage where slope = -1
– VMAX output voltage for which VIN = 0
10
Real inverter…
If range of output values VOL to VOH is wider than the range of input values VIL
to VIH, then the inverter exhibits some noise immunity. (|Voltage gain| > 1)
12
Chain of two inverters
VOUT VIN
inverter M inverter N
output input
13
Noise Margins
V V(y)
"1" OH
Slope = -1
V V
IH OH
Undefined
Region
Slope = -1
V
IL VOL
"0"
V
OL V V V(x)
IL IH
14
Noise Margins
Noise margin is a parameter closely related to the input-output voltage
characteristics
The noise margins represent the levels of noise that can be sustained when gates
are cascaded.
This parameter allows us to determine the allowable noise voltage on the input
of a gate so that the output will not be affected.
The specification most commonly used to specify noise margin (or noise
immunity) is in terms of two parameters- The LOW noise margin, NML, and the
HIGH noised margin, NMH
15
Noise Margins…
NML is defined as the difference in magnitude between the maximum LOW
output voltage of the driving gate and the maximum input LOW voltage
recognized by the driven gate.
NML = |VIL-VOL|
The value of NMH is difference in magnitude between the minimum HIHG
output voltage of the driving gate and the minimum input HIGH voltage
recognized by the receiving gate.
NMH = |VOH-VIH|
16
General circuit structure of an NMOS inverter
The driver transistor
The input voltage Vin=VGS
The output voltage Vout=VDS
The source and the substrate are ground VSB=0
The load device
Terminal current IL,
Terminal voltage VL
17
Voltage transfer characteristic (VTC)
The VTC describing Vout as a function of Vin under DC condition
18
Voltage transfer characteristic (VTC)…
As Vin increases
⁃ The driver transistor starts conducting, the output voltage starts to decrease
⁃ The critical voltage point, dVout/dVin =-1
• The input low voltage VIL
• The input high voltage VIH
• Determining the noise margins
Further increase Vin
• Output low voltage VOL, when the input voltage is equal to VIH
⁃ The inverter threshold voltage Vm
• Define as the point where Vin=Vout 19
NMOS inverter
20
NMOS inverter with Pull-Up resistor
Essential features:
• VBS = 0 (typically not shown)
• CL summarizes capacitive loading of the
following stages (other logic gates,
interconnect lines, etc.)
Basic Operation:
• If VIN < VTN, MOSFET is OFF
VOUT = VDD
If VIN > VTN, MOSFET is ON
VOUT - small
22
NMOS inverter with Pull-Up resistor
Transfer function and Logic levels:
23
NMOS inverter with pull-up resistor
For VOH, transistor is cut-off, ID = 0: VOH = VDD
For VIL, transistor is in linear regime;
24
Current-Voltage Relationship
25
NMOS inverter with Pull-Up resistor
Strong HIGH output
VOH=VDD Disadvantage
Weak LOW output Unsuitable for VLSI fabrication
VOL= VDDRN/(RN+RD) Large chip area
How low is it? Asymmetric switching characteristics
Low level voltage Charging time will be greater than
Should be such that it will not make the discharging time
next stage transistor on Large static power dissipation
i.e. VOL<VT of the next transistor
26
Active Loads
VDD VDD
Depletion PMOS
Load VT < 0 Load
VSS
F F
In1 In1
In2 PDN In2 PDN
In3 In3
VSS VSS
27
CMOS Device Structure
28
CMOS Inverter
In CMOS, we use two transistors PMOS ( as PUN) and NMOS (as PDN).
PULL UP is something that pulls the output up from ground or “output has been pulled up to
source voltage"
PULL DOWN is that pulls the output down to ground or “output is pulled down to ground"
In CMOS, when the input is high, NMOS gets ON and pulls down the output to ground(i.e.,
output becomes low).
Whereas, when the input voltage is low, PMOS gets ON and pulls the output up from the ground
(i.e., output becomes high).
⁃ Vout=VDSP+VDD
30
CMOS Inverter: Analysis
31
No power consumption while idle in any logic state!
CMOS Inverter
A Y
0 1
1 0
Pull Up
32
CMOS Inverter
A Y
1 0
Pull Down
33
Why NMOS as PUN
With the output load initially at GND. VT drop cannot pass full VDD
PMOS can pass VDD without VT drop : Good for pass logic “ 1” or “HIGH”
A PMOS switch succeeds in charging the output all the way to VDD, while the NMOS
device fails to raise the output above VDD-VTn.
PMOS Transistors pass a 1 better than a 0.
PMOS transistor produce a strong 1 and a weak 0. 34
Why NMOS as PDN
NMOS can pass GND without VT drop : Good for pass logic “ 0 ”or “ LOW”
An NMOS device pulls the output all the way down to GND, while a PMOS lowers the
output no further than |VTp|
The PMOS turns off at that point, and stops contributing discharge current
NMOS Transistors pass a 0 better than a 1
35
37
NMOS Operation
VDD
Vgsn= Vin
Idsp
Vdsn = Vout Vin Vout
Idsn
38
NMOS Operation
Cutoff Linear Saturated
VDD
Vgsn = Vin Idsp
Vin Vout
Vdsn = Vout Idsn 39
PMOS Operation
Vin0
Idsn, |Idsp|
Vin0
VDD
Vout
42
Load Line Analysis
Vin = 0.2VDD
Vin1
Idsn, |Idsp|
Vin1
VDD
Vout
43
Load Line Analysis
Vin = 0.4VDD
Idsn, |Idsp|
Vin2
Vin2
VDD
Vout
44
Load Line Analysis
Vin = 0.8VDD
Vin4
Idsn, |Idsp|
Vin4
VDD
Vout 45
Load Line Analysis
Vin = VDD
Vin0 Vin5
Vin1
Idsn, |Idsp|
Vin2
Vin3
Vin4
VDD
Vout
46
Load Line Summary
47
DC Transfer Curve
48
CMOS Inverter: Transfer Plot
Region A: Vin<VTN
– NMOS OFF, PMOS ON IDN = I =0, DP
A
B
– Vout = VOH = VDD
Region B: Vin>VTN
– NMOS saturation, the Vout decreases
– The critical voltage VIL, (dVout/dVin)=-1
is located within this region
– As the output further decreases PMOS
enter saturation, boundary of region C
49
CMOS Inverter: Transfer Plot
Region C:
– If NMOS saturation VDSn VGSn - VTn
A
V B
out Vin VTn
-
51
Properties of CMOS
Full rail-to-rail swing high noise margins
Logic levels not dependent upon the relative device sizes transistors can be minimum
size ratioless
Always a path to Vdd or GND in steady state low output impedance (output resistance
in k range) large fan-out (albeit with degraded performance)
Extremely high input resistance (gate of MOS transistor is near perfect insulator) nearly
zero steady-state input current
Since : I Dn = -IDp
Usually, VTn and VTp fixed and VTn = - VTp VM engineered through kp/kn ratio. 53
CMOS Inverter: Transfer Plot
54
CMOS Inverter: Transfer Plot
55
CMOS Inverter: TRANSIENT RESPONSE
(a) Low-to-high
b) High-to-low
56
CMOS Propagation Delay
The CMOS model can likewise be used to estimate the propagation delay of a CMOS inverter.
To see how, consider a CMOS inverter with its output at low level Vo=0.0 (i.e., its input is vI
=5.0). The voltage across the output capacitance C is likewise zero:
Q: Output
capacitance?!
What is that?
57
CMOS Propagation Delay…
A: The output capacitance of a CMOS inverter is simply a value that represents the total
capacitance associated with the inverter output.
This includes the internal capacitances of the MOSFET devices, the wiring capacitance, and the
capacitance of the device that the output is connected to!
58
Review: RC Circuits
RC time-constant: dictates how rapidly the output voltage reacts to the voltage rise on input
(step function).
Larger RC, slower response
59
CMOS inverter: Propagation delay
Inverter propagation delay: time delay between input and output signals; figure of merit of
logic speed.
60
CMOS inverter: Propagation delay
Simplifications for hand calculations:
• Consider input waveform is an ideal square wave
• Propagation delay times = delay times to 50% point
61
Switch-level model
Delay estimation using switch-level model (for general RC circuit):
Switch-level model
For fall delay
Power and Energy Consumption
• The power consumption of a design determines how much energy is consumed per operation, and
much heat the circuit dissipates.
• These factors influence a great number of critical design decisions, such as the power supply
capacity, the battery lifetime, supply-line sizing, packaging and cooling requirements.
• Therefore, power dissipation is an important property of a design that affects feasibility, cost, and
reliability.
• In the world of high-performance computing, power consumption limits, dictated by the chip
package and the heat removal system, determine the number of circuits that can be integrated
onto a single chip, and how fast they are allowed to switch.
64
Power dissipation
Power dissipation in CMOS circuits comes from two components:
Static Dissipation
When input is not switching
▪ Subtreshold conduction
▪ Leakage through reverse biased diodes
Dynamic Dissipation
Dynamic capacitive power
Due to charging and discharging (switching) of load capacitance
Dynamic short-circuit power
Direct current from VDD to GND when both transistors are on 65
Power Dissipation
Instantaneous power dissipation
66
Dynamic Power Dissipation
Energy delivered to capacitor
Stored energy
Energy dissipation
68
Supply voltage scaling in CMOS inverters
The static characteristics of the CMOS inverter allow significant variation of supply voltage
without affecting the functionality of the basic inverter
The CMOS inverter will continue to operate correctly with a supply voltage limit value
Correct inverter operation will be sustained if at least one of the transistors remains in
conduction, for any given voltage
The exact shape of the VTC near the limit value is essentially determined by subthreshold
conduction properties.
69
Supply voltage scaling in CMOS inverters
If the power supply voltage is reduced below the sum of the two threshold
The VTC will contain a region in which none of the transistors is conducting
The output voltage level is determine by the previous state of the output
The VTC exhibits a hysteresis behavior
70
If we want to make relatively minor changes
in our lives,
we can focus on our attitudes and behaviors.
But if we want to make significant
quantum changes,
we need to work on our basic paradigms
( the way we view ourselves and the world around us).