IEEE - ICSCN 2007, MIT Campus, Anna University, Chennai, India. Feb. 22-24, 2007. pp.90-93.

Design of CDMA MAC for Microsatellite

S. Shobanal, S. Uma Priyadharshinil, S. Amrithal, G. Revadhi, Remya Manickavasagaml, B. Revathil,
V. Vaidehil and S. Vasuhil

Abstract: Code Division Multiple Access (CDMA) is a assumed to be 256 and the number of users who have parallel
digital wireless transmission technology that allows for a accessibility to the satellite is 16 i.e. at most 16 users are
large amount of users to share access to a single radio visible to the satellite at a time. The FPGA architecture has
channel. This technology is being widely used in cellular equal number of 'send' and 'receive' buffers for the 16 users,
communication and can be extended to store and forward as described in Figure 1. Each buffer pair has a unique
(S&F) payload that provides message relay service for spreading/despreading code.
several users with ground terminals, simultaneously. In The earlier work reported in [5] used 80186 processor in
this paper, the three layered model for the store and the satellite and it can access only limited memory due to the
forward payload using CDMA Medium Access Control limited number of address lines(16 address lines) and can
(MAC) is considered. Their design methodologies are support only low data rates due to the low processor speed of
discussed assuming static code assignment. 6 MHz. But to have greater processing speeds, efficient
memory management and rugged timers, and to support high
I. INTRODUCTION data rate applications such as multi media traffic and to
handle multiple users effectively, ARM processor which is a
CDMA is the use of spread spectrum by multiple 32 bit Reduced Instruction Set Computer (RISC) machine, is
transmitters to send data to the same receiver on the same used.
frequency channel at the same time without harmful
interference [6].In this paper we give the design of a three
layered model for the S&F payload that effectively utilizes
CDMA technology to improve the throughput efficiency.
The paper cited in [1] discusses the software design of
CDMA MAC scheme assuming static and dynamic code
assignment. The performance of the CDMA MAC is
compared with the existing slotted Aloha MAC and
concluded that channel is more effectively utilized in the
CDMA MAC scheme.
A user who wishes to communicate with another user
spreads his message in his unique code and sends it to the
satellite. The message is retrieved in the satellite by
despreading the received data and is stored in the on- board
memory. When the destination user becomes visible, the
message is retrieved from the memory, spread in the
receiver's code and sent in the downlink. A real time
operating system (RTOS) in the satellite is required to handle
multiple users simultaneously and schedule send and receive
operations, to transfer mails from buffer and memory, to
manage timers and to perform fail save operations. Fig. 1. System Model
The proposed design has the following three layers -
II. SYSTEM DESIGN application layer, data link layer and physical layer.
For the proposed model, the total number of users is A. Application layer
Department of Electronics, Madras Institute of Technology This layer handles memory management, scheduling
Campus, Anna University, Chennai 600 044, India operations and other house keeping functions.

1-4244-0997-7/07/$25.00 ©2007 IEEE 90

 IEEE-ICSCN, Feb. 2007
The on board memory is partitioned into three regions
namely file table area, free block manager and message
storage area.
File table area stores the mail details of every user like
the starting block address of every mail and day to live
parameters.
Free block manager uses 'bit vector technique' to keep
track of the free and used blocks in memory.
The message storage area is divided into equal-sized
blocks of 256 bytes to store the actual mails of the users.
Threads are created for every user using the RTOS to
service users simultaneously. The threads keep track of send
and receive buffers in the FPGA architecture to fully exploit
the advantages of CDMA MAC scheme [8].
The data transmission consists of various phases like
Directory broadcast phase,
Poll/request phase, and Allocation/data transfer phase. [1]
B. Data link layer
HDLC [High-level Data Link Control] is a group of
protocols for transmitting data between nodes. In HDLC, data
is organized into a frame. Flow control is achieved using
'stop and wait' protocol. Since the round trip propagation
time is more in satellite communication, stop and wait
protocol will prove to be advantageous if there are a large
number of retransmissions. Other protocols like 'Selective
Reject' may also be used.
III. PHYSICAL LAYER
The physical layer works as the back end tool which is
responsible for the transmission and reception of the data
frames. At the transmitter side, the physical layer gets the
data frame from the data link layer, encodes it for achieving
better bit error rate performance and spreads it by multiplying
the data with the unique pseudo random noise (PN) code
allotted to each user [3]. The spread data is modulated and
translated to higher frequency and transmitted through the air
medium by the RF up conversion block [7].
At the receiver side, the physical layer receives the frames
and achieves coarse and fine synchronization. The data is
then despread and decoded. The decoded data is stored in a
buffer from where it is sent up to the data link layer for
Spreading code
Convolutional
DataFn-fr
Fig. 2. Block Diagram of Transmitter (Single Ground Station)
91
further processing and storing.
We have considered an Additive White Gaussian Noise
(AWGN) channel to model the ground station- satellite link,
through which the data is transmitted [7].
A. Transmitter
The data bits from the data link layer are divided into 8 bit
blocks before encoding. The transmitter uses a Convolutional
Encoder with a code rate of V2, constraint length 4 and coding
window length 8. The PN code is generated as a Maximum
Length Sequence using 4 shift registers and an Ex or gate.
Maximum length sequences are spectrally flat, with the
exception of a near-zero DC term, and are used instead of
impulse responses because, being longer, they inject more
energy into a system; extracted impulse responses thus have a
higher signal to noise ratio. The codes are assigned to the
users in a static manner, i.e., each user is assigned a unique
code a priori which is permanent for them [9]
The 22 bit encoded data is multiplied with the 10 bit PN
sequence to generate the spread data.
s(t) = c(t) p(t) (1)
where c(t) is encoded data, p(t) is the PN code for the user
and s(t) is the signal transmitted by the ground station.
The transmitter block diagram is given in figure 2.
B. Receiver
The satellite receiver has a RF down conversion block to
convert to IF frequency and demodulates the data. The
demodulated data is synchronized in the Acquisition block by
shift and match mechanism. Once synchronization is
achieved, it is maintained by the Tracking loop using an early
latch and a late latch. When the satellite receiver has locked
on to the incoming bit stream, it performs despreading of the
data. Each receiver architecture is supplied a PN code from
the Look Up Table in the on-board memory corresponding to
the ground users in the satellite's footprint.
d(t)= r(t). p(t) (2)
= [s(t) + n(t)] p(t)
= [c(t) p(t)] p(t) + n(t) p(t)
d(t)= c(t) + n(t). p(t) )
 Design of CDMA MACfor Microsatellite

R<F dowvn
conversion and
Acquisition and
-4 Tracking loop
\
9-
Mlatched fifter |,
1
Threshold
eetr4.o
Viterbi decoder .| Buffer
clemoclulation

Fig. 3. Block Diagram of Receiver in Satellite

where r(t) is the received signal, n(t) is the noise added in
the channel.
Once despreading is done, the data is decoded using a
Viterbi decoder and stored in a buffer from where it is
transferred to the on-board memory. The decoder has a
window length of 22 along with code rate 12 and constraint
length4. The block diagram of the receiver in satellite is
shown in figure 3.

IV. SIMULATION AND OUTPUTS

A. Physical layer
The blocks of the CDMA transmitter and receiver in the
physical layer were tested in FPGA Advantage product of Fig. 5. Simulation of Receiver for First User
Mentor Graphics Corporation. The design was implemented
using VHDL language. B. Upper layers
We have simulated the physical layer architecture for two The snap shot in figure 6 shows the file table area
users. The transmitter section has been replicated for two indicating the presence of mail for the first and the fifth user.
users while the receiver section has been simulated and tested
under condition of two users transmitting simultaneously. A
single ground station user's data frame after encoding and
spreading is shown in Figure 4. The product modulator
output 'outl' (220 bits) gives the transmitted bits of a single
user. It spreads the 'enc_out' data in the 'pnl'. Dry
fff fTf ff
ffT ff Q ff
fff ff Q ftf
fff ff 0 ff
ff ff 0 Tff
fff ff C ff
f fS ff 0 ff
fff ff 0 ff
fff ff 0 ff
f2f ff 0 ff
fff ff 0 ff
ff ff 0 ff
fff ff 0 ff
f fT ff a ff
ff ftf X ff
fff ff 0 ff
Fig. 4. Simulation Output for Single User 4
ff ff
1
0
0
ff
ff
fff ff 0 ff
fff ff X ff
In a similar way, a number of ground stations can f fT
ff
fSf
f fT 0
ff
ff

communicate to the satellite using their unique PN code.

When the symbols are transmitted in air medium, data frames
from other users may cause Multiple Access Interference
(MAI).
The receiver for first user at the satellite is simulated and
Figure 5 shows the output of the Viterbi decoder, 'dec out',
corresponding to first user's data 'enc in'. The second user's
data that causes interference is given by 'enc in2'. 'pno 1'
and 'pno2' correspond to the orthogonal codes of the two
transmitting users, while 'outl2' refers to the bit sequence
that reaches the receiver.
Fig. 6. Snap Shot of On-Board Memory
Each user has a file table entry corresponding to him. The
first slot is of 1 byte size which stores the user address. The
next 20 consecutive slots are of size 3 bytes each in which the
first 2 bytes is used to store the starting block number where
the mail is being stored in the memory and the last 1 byte is
used to indicate the day to live parameter used for deleting
the mail. If there is no mail for the user, then the
corresponding starting block number slot should store a null
block indicator. Oxffff is used as the null block indicator.

92
 IEEE-ICSCN, Feb. 2007
Each user has a separate file table entry which is 61 bytes in
size.
The file table area has been simulated in the Linux
environment using C language.
The integration of the hardware implementation of the
physical layer and the software of the upper layers is under
progress.
V. CONCLUSION
The design of a three layer model for an S&F payload
using CDMA MAC was proposed. The various blocks in the
physical layer were discussed in detail and the functions of
the application and data link layer were outlined.
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[2] Chai-Sheng Chang, "Medium access protocol design for
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[4] Christian del Rosso et al, "Dynamic memory management for
software product family architecture in embedded real time
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[5] S. Muthuselvam, "Development of Embedded software for
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[6] Theodore S. Rappaport, "Wireless Communications", Pearson
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[7] Jochen Schiller, "Mobile Communications", Pearson
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[9] Simon Haykin, "Digital Communications", John Wiley &
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