34 Atmel ATMEGA8,16,32 PDF

.
TW
.C OM
00Y .TW
W W.1 Y.COM W
W 00 .T
Features W W.1 Y.COM W
.TW W 100 OM
.T
• High Performance, Low Power AVR®.C8-Bit OMMicrocontroller WW. .C
• Advanced RISC Architecture .100Y M .TW W . 100
Y
M .TW
W O W O
– 125 Powerful Instructions WW –.1Most .CSingle Clock
00YRegisters .TW Cycle Execution WW .100Y.C M.TW
– 32 x 8 General Purpose Working W O M W O
– Fully Static.T W Operation WW .100Y.C M.TW WW .100Y.C M.TW
M16 MIPS Throughput W O W O
0
– .C
Y Up Oto
.T W WW at .16 0 0Y.C M.TW
MHz WW .100Y.C M.TW
0 1
W.•1 Non-volatile M Program and Data
.CO .TWBytes of In-System
Memories
W O WW 00Y.CO .TW
WW .100–Y8K/16K/32K WW .1Self-Programmable
0 0Y.C M.TW Flash W .1 M
W W – 512/512/1024
.C OM
WEEPROM WW 00Y.CO .TW W WW 00Y.CO .TW
W 00 Y .T W 1 M .1 M
W W.1– 512/512/1024
.C OM Internal SRAMWW. Y .CO W W WW 00Y.CO .TW8-bit
W 0 Y
– 0Write/Erase W W
Cycles: 10,000 Flash/ .100,000
.T 10 0 EEPROM .T .1 M
W.–1 Data OM
retention:
C 20 years at 85C/ WW100 0years .Cat OM 25C(1)W WW 00Y.CO .TW
W Y . W W 0 Y T W
M. Bits WW 00Y.CO .TMicrocontroller
W 00 M.TCode Section with .1 .1 M
W W–.1OptionalY . C OBoot
W
WIndependent
Won-chip 0 Y
Lock
.COProgram W W W
W 00 In-System Programming
.T W by
. 10 Boot
M .T hardware-activated .1 after M
. 1 M W O W O
W reset
WW .10True
O
0Y.CRead-While-Write .TW WW .100Y.C M.TW WW .100Y.C Mwith .TW
M Operation W O W C O
WW
W .CO Lock .TW
W Y.C .TW WW .100Y. .TW
. 1 00Y
– Programming
M
for Software WSecurity
W . 100 O M W C O M8/16/32K Bytes
• USB W2.0 Full-speed
W–WComplies 0 .CO Device
Yfully .T W Module withW
W
Interrupt Y
0 0
on.CTransfer .T
CompletionWW
W . 1 0 0Y. M .TW
0 1
W.Specification M O
W.1 Y.C Owith
M Universal SerialW Bus
0Y.C
O REV 2.0
W at 12 Mbit/s
W
WW .100Y.C of ISP
W Flash
W–W 48 MHz PLL
. 1 0 0 for Full-speed
M .T W Bus Operation W
W .:1data
0 transfer.T
O M rates
W O M.T
– Fully W independant C O 176 bytes USB DPRAMW for endpoint
.C memory allocation W Y.C W
W Y. W W 8 up.1to0064-bytes Y .TW W
W.1 Y.C
00
and
OM USB
.T
–WEndpoint
W .1000 for ControlO M.TTransfers: fromW W . COM W W
.C .TW
–W W
4 Programmable
. 1 00Y Endpoints: M .TW W
W . 100
Y
O M
W
W .100 O M.T
IN W .CO .TW WW .100YController .C
WW .100Y.C M.TW
or Out Directions W
WW Bulk, Interrupt
. 1 00Y andMIsochronousTransfers W O W O M.T
WW 00Y.Cmaximum O Y.C WW .100Y. C W
WProgrammable .TWpacket size WW from 8 to
. 1 0064 bytes .TW
M M.T
. 1 M W O W C O
W
Programmable
WW .100YInterrupts .C O or double buffer W
single
.TW Y.C .TW WW .100Y. M.T
W
– Suspend/Resume M
W
W . 100 O M W C O
WW .10reset
– Microcontroller W
0Y.Con USB
O
M .TBusW Reset without WW detach .100
Y.C
M .TW WW .100Y
W
ATmega8U2
.
O M.T
W
W O C
– USB Bus Disconnection
• Peripheral W
WW
Features.100Y
.CO .TW
on Microcontroller Request
WW .100Y.C M.TW WW .100Y. M.T
W
M W O W C O
.TW(two 8-bit W W.1ATmega16U2
WW 00Y.COwith .Separate Y.C Mode W . W
– One 8-bit WTimer/Counters TW WW and
Prescaler
.100
Compare
M 00Y M.T
PWM channels) . 1 O M W O W .C O
– One 16-bit
WW 00Y.Cwith
WTimer/Counter .TW Prescaler,
Separate WW Compare Y.C
100 andOCapture .TW Mode W W.100Y OM.TW
. 1 M W . M .C
(three 8-bitW PWMWWchannels) 0 Y.C
O
.T W WW .100Y.C M.TW WW ATmega32U2
. 1 00Y M.T
W
– USART with SPI master . 1 0 only M
mode and hardware flow W control O
(RTS/CTS) W .C O
WW 00Interface O WW .100Y
– Master/SlaveWSPI Serial Y.C .TW WW .100Y.C M.TW M.T
W
.1 O M W O W .C O
– Programmable Watchdog W
WW .100Timer Y.C with.TSeparate W WW Oscillator
On-chip Y.C .TW WW .100Y M.T
W
– On-chip Analog Comparator M W . 100 O M W C O
W O WW .100Y .
– Interrupt and Wake-up WW on 0Y.C
0Pin Change .TW WW .100Y.C M.TW M.T
W
. 1 O M W O W .C O
• On Chip Debug Interface W
WW (debugWIRE) .C .TW WW .100Y.C M.TW WW .100Y M.T
W
• Special Microcontroller Features . 1 00Y M W O W .C O
W O WW .100Y
– Power-On Reset and WWProgrammable 00Y
.C Brown-out .TW Detection WW .100Y.C M.TW M.T
W
W .1 O M W O W W .C O
– Internal Calibrated Oscillator
WW .100Sources Y.C .TW WW .100Y.C M.TW W .100
Y
M.T
W
– External and Internal Interrupt W O M W O W W .C O
WW Y.C .TW Standby, WW Y.C Standby W W .100
Y
M.T
W
– Five Sleep Modes: Idle, Power-save,
W . 100 Power-down,O M W .100
and Extended
O M.T W W .C O
• I/O and Packages
WW 0Y.C M.TW WW .100Y.C M.TW W .100
Y
M.T
W
– 22 Programmable I/O Lines W.10 O W O W W .C O
WW Y.C .TW WW .100Y.C M.TW W .100
Y .TW
– QFN32 (5x5mm) / TQFP32 packages
W .100 O M W C O W W .C OM
• Operating Voltages
W W .100
Y .TW
– 2.7 - 5.5V W O W C O W W .C OM
• Operating temperature WW .100Y.C M.TW WW .100Y. M.T
W W .100
Y .TW
W O W C O W W .C OM
– Industrial (-40°C to +85°C)
W W .100
Y
• Maximum Frequency W O W C O W W
– 8 MHz at 2.7V - Industrial range WW .100Y.C M.TW WW .100Y. M.T
W W
W O W C O
– 16 MHz at 4.5V - Industrial rangeW
W 00Y
.C W WW .100Y. M.T
W
Note: 1. See “Data Retention” on page 6 for W .1details. O M.T W C O
WW .100Y.C M.TW WW .100Y.
W O W
WW .100Y.C M.TW WW 7799E–AVR–09/2012
W W .C O
W 00Y .TW
W W.1 Y.COM
W 00
W W.1
W
.TWATmega8U2/16U2/32U2
.C OM
00Y .TW
W W.1 Y.COM W
W 00 .T
1. Pin Configurations W W.1 Y.COM W
.TW W 00
W.1 Y.COM W
.T
. C OM W
Y W W 00 .T
Figure 1-1. Pinout W .100 O M.T W W.1 Y.COM W
WW .100Y .C W W 00 .T
W O M.T W W.1 Y.COM W
W WW .100Y .C W W 00 .T
O M.T W O M.T W W.1 Y.COM W
Y.C W WW .100Y .C W W 00 .T
.100 M.T M.T W.1 Y.COM W
PC5 ( PCINT9/ OC.1B)

W O W .C O W
WW .100Y.C M.TW WW .100Y M.T
W W 00 .T
O W O W.1 Y.COM W
PC4 (PCINT10)
W .C W
W W 00 .T
W O W .C O W W.1 Y.COM W
W
WW .100Y.C M.TW W .100
Y
M.T
W W 00
W.1 Y.COM W
.T
UGND
UVCC
AVCC
O
UCAP
W O W W .C W
WW .100Y.C M.TW W .100
Y
M.T
W W 00
W.1 Y.COM W
.T
D+
D-
W O W W .C O W
WW .100Y.C M.TW32 31 30 29W 28 27 26 25 .100
Y
M.T
W W 00
W.1 Y.COM W
.T
W O W W .C O W
WW .10(PC0) 0Y.CXTAL1 24 0Y
.TW W 00 .T
1W Reset (PC1 / dW)
W
W XTAL2O M.T2 W 10 PC6 (OC.1A
.23
.C OM / PCINT8) W W.1 Y.COM W
C W .TW
WW .100Y. GND M3.TW W 22 Y
.100PC7 (INT4 / ICP1
M / CLKO) W 00
W.1 Y.COM W
.T
W C O W W .C O W
. 0Y .TW 00
PB7 (PCINT7 / OC.0A / OC.1C) W
W VCC
00Y) PC2 M
4
.TW QFN32W 20
21 .T
W(PCINT11 ./1AIN2
W O 5 W .10PB6 (PCINT6)
.C OM W W.1 Y.COM W
W / INT0) .C W Y .TW W 00 .T
PC5 ( PCINT9/ OC.1B)

YPD0 6 .TW W 19 .1PB5 00(PCINT5)
W(OC.0B
W 100 PD1
.INT1) O M W . C OM W W.1 Y.COM W
(AIN0 /
Y.C W 0Y .TW W 00 .T
WW .100PD2 18
7 PB4 (T1 / PCINT4)
.TW W .10(PDO OM/ PCINT3) W.1 Y.COM W
PC4 (PCINT10)
(RXD1 / AIN1 / INT2)
W 8OM 17 W PB3 / MISO
C W
C W . .TW
WW .100Y. W W
M 11 12 13 14 15 16 WW.10
9 10.T 0Y W 00
W.1 Y.COM W
.T
W C O .C OM W
WW .100Y. W W .100
Y .TW W 00 .T
UGND
M.T W.1 Y.COM W
UVCC
AVCC
UCAP
(CTS / HWB / AIN6 / T0 / INT7) PD7
(XCK / AIN4 / PCINT12) PD5
(PDI / MOSI / PCINT2) PB2

(RTS / AIN5 / INT6) PD6
(TXD1 / INT3) PD3
(SCLK / PCINT1) PB1

(SS / PCINT0) PB0
(INT5/ AIN3) PD4
W CO W W .C OM W
D+
WW .100Y. Y .TW W 00 .T
D-
W W .100
W O M.T W .C OM W W.1 Y.COM W
C W .TW
WW .100Y. M.T
W W .100
Y 32 31 W
30 29 28 27 00
W.1 Y24
26 25
M.T(PC1 / dW)
W O W COMXTAL1 1 W .C OReset
WW .100Y. C
.TW W W Y
100 (PC0)
.
M .TW 2 W .100 23 O .TW / PCINT8)
M(OC.1A
M W . O XTAL2
W C
PC6
W O
WW .100Y.C M WW .10022 Y. PC7 (INT4 .TW
WW .100Y.C M.TW
GND W3 / ICP1 / CLKO)
.T W O M
W O CPB7 (PCINT7 / OC.0A / OC.1C)
O 0Y. PB6 (PCINT6)
VCC 4 21
W
WW .100Y.C M.TW WW (PCINT11 .C
00Y/AIN2 ) PC2 .TW TQFP32WW .1020 M .TW
. 1 M 5
W O W .COPD0 .T6W WW .119
W .CO .TW
WW .100Y.C M.TW WW (OC.0B 0 0Y/ INT0)
00YPB5 (PCINT5)
.1 / INT1) O M WW 1800PB4 OM
W W Y .C O
W W WW/(AIN0 0 Y.C PD1 .7TW W Y.C(T1 / PCINT4)
1 PB3 (PDO .TW/ PCINT3)
W . 1 00 M .T (RXD1
W
AIN1
. 10 / INT2) PD2
O M 8 W .17
C O M/ MISO
W O 14 W .
WW .100Y.C M.TW WW .100Y.C M.T9W10 11 12 13 W 15 16
.100
Y
M.T
W
O W O W .C O
W
WW .100Y.C M.TW WW .100Y.C M.TW WW .100Y M.T
W
/ HWB / AIN6 / T0 / INT7) PD7
(XCK AIN4 / PCINT12) PD5
(RTS / AIN5 / INT6) PD6
(PDI / MOSI / PCINT2) PB2

(SCLK / PCINT1) PB1
(TXD1 / INT3) PD3
(INT5/ AIN3) PD4
(SS / PCINT0) PB0
O W O W .C O
W
W
O W O W .C O
W
W
O W O W .C O
W
W
W O W O W W .C O
WW .100Y.C M.TW WW .100Y.C M.TW W .100
Y
M.T
W
W O W O W W .C O
Y
M.T
W
W O W O W W .C O
Y
M.T
W
W O W O W W .C O
W .C Y .TW
WW The
Note: 0Y.Ccenter
.10large M.padTWunderneathWthe QFN.1package 00Y W W
M.T be soldered to ground
should W .10on0 the board OM to
W O W C O W .C
WW ensure Y.C W stability.WW .100Y. M.T
W W .100
Y .TW
W .100good mechanical O M.T W C O W W .C OM
W W .100
Y .TW
W O W C O W W .C OM
1.1 Disclaimer WW .100Y.C M.TW WW .100Y. M.T
W W .100
Y
W O W C O W W
Typical values
WW .100Y.C M.TW
contained in this datasheet WW are based Y.on simulations
.TW
and characterization
W of
other AVR microcontrollers
W O manufactured on the W .100 process
same O Mtechnology. Min and Max values
Y.C WW .100Y. C W
WW after
will be available .100 the device
W
M.T is characterized. M.T
W O W C O
W O W
WW .100Y.C M.TW WW
W O
WW .100Y.C M.TW
W O
WW .100Y.C 2
W W
7799E–AVR–09/2012 W
.C OM
00Y .TW
W W.1 Y.COM W
W 00 .T
2. Overview W W.1 Y.COM W
.TW W 00
W.1 Y.CO M.T
The ATmega8U2/16U2/32U2 is a low-power C OM CMOS 8-bit microcontroller W based on the AVR enhanced RISC architecture.
1 00Y
.
M
W
.Tclock W . 100 M .TW
By executing powerful instructions . in a single
O cycle, the W
ATmega8U2/16U2/32U2 O achieves throughputs approaching
WW 00Y.C
Wthe .T W WW consumption 10 0Y.C M .TW processing speed.
1 MIPS per MHz allowing system
W. 1 designer
OM to optimize power W . O versus
.T W WW .100Y.C M.TW WW .100Y.C M.TW
OM W O W O
2.10 Y.C Block .T W Diagram WW .100Y.C M.TW WW .100Y.C M.TW
0 O
W.1 OM W O W
WW .100Y.C M.TW
WW .100Y.C M.TW WW .100Y.C M.TW
WFigure 2-1.O Block Diagram WW O W O
WW .100Y.C M.TW W 0 0 Y.C .T W WW .100Y.C M.TW
W. 1 OM W O
W
WW .100Y.C M.TW
O
W O W O
W
WW .100Y.C M.TW
O
W O WW 00Y.CO .TW
W
WW .100Y .CO .TW
WW .100Y.C M.TW PD7 - PD0 W
RESET
XTAL2
XTAL1
. 1 M - PB0 M
WW 00Y.CO .TW
PC7 - PC0 PB7
W W Y . C O
W W WW 00Y.CO .TW W
W 00 .T .1 M .1 M
W W.1 Y.COM W WW 00Y.CO .TW W WW 00Y.CO .TW
W 00 .T W .1 .1 M
W.1 Y.COM PORTD WW 00Y.CPORTC OM WWPORTB0DRIVERS Y .CO .TW
W W W T W W 0
W 00 .T M. .1
DRIVERS DRIVERS
.1 M
W.1 Y.COM W WW 00Y.CO .TW
-
+
W W WW 00Y.CO .TW W
W 00 .1
COMPARATOR
.T
ANALOG
W.1 Y OM .1 M WW 00Y OM
.C WW Y .CO REG. W W .CDIR. W
W M.T
DATA REGISTER DATA DIR. DATA REGISTER DATA DIR. DATA REGISTER DATA
W 00 PORTD .T W REG. PORTD W 10
PORTC
. 0 M .T
PORTC PORTB .1 REG. PORTB
. 1 M W O W C O
W O
WW .100Y.C M.TW
W Y. W
WW .100Y.C M.TW 8-BIT DA TA BUS W
W .100 O M.T
W O C
VCC W
WW 00Y.CO .TW WW .100Y.C M.TW WW .100Y. M.T
W
. 1 M W O W CO
W
WW .100Y.C M.TW
O W
POR - BOD
Y.C .TW WW .100Y. M.T
W
W RESET
W . 100 O M
INTERNAL
CALIB. OSC W CO
W O
GND
W
WW .100Y.C M.TW
OSCILLATOR
W O W O M.T
W O WW .100Y. C
WW .100Y.C M.TW WW .100Y.CWATCHDOG M .TW OSCILLATOR
M.T
W
W O W C O
W WW 00Y.CPROGRAM
Debug-Wire
O
COUNTER .TW
STACK
POINTER WW .100Y.C M.TW
TIMER
WW .100Y. M.T
W
. 1 M W O W C O
W
WW .100Y.C M.TW
O
W
W O W .C O
W
WW .100Y.FLASH CO
PROGRAM SRAM
WW .100Y C
MCU .CONTROL
.TW CONTROL W W.100Y OM.TW
TIMING AND W
ON-CHIP DEBUG
M .TW W
REGISTER
O M
W
WW .100Y.C M.TW
O
W O
W INSTRUCTION O W TIMER/
WW .1COUNTERS .CO .TW WW .100Y.C M.TW
0Y.C M.TWPURPOSE
PROGRAMMING
WW .10REGISTER 00Y
GENERAL
LOGIC
M WW 00Y.CO .TUVcc
W W Y .C O REGISTERS
W W WW 00Y.CO .TW W W
W . 1 00 M .T X
W . 1 O M W .1 O M
W INSTRUCTION O Y INTERRUPT
.C WW .3.3V Y .C W
WW .1UNIT
ON-CHIP
WW .DECODER .C .TW 00Y .TW 100 M.T
1 00Y M
Z
W O M W
REGULATOR
.C O
W O WW .100Y
Y.C WW .100Y.C M.TW .TW UCap
WW CONTROL 1 0 0 .T W
W O M
.
WLINES OM ALU W O
WW .100Y.C M.TW
1uF

EEPROM
W O WW 00Y.CO PLL.TW WW 00Y.CO .TW

WW .100Y.C STATUS M. T W W W
W.1 Y.COM W
W .C OREGISTER W W.1 Y.COM W W
W W
.100
Y
M.T
W W
W .100 O USB.T
M
W
W .100 D+/SCK.T
O M
W O W .C D-/SDATA
WW SPI .100Y.C M.TW WW .100Y.C M.TW W . 1 0 0Y

M.T
W
W O W O W W .C O
WW .100Y.C M.TW
PS/2
.TW
USART1
Y
WW .100Y.C M.TW W
W .100 OM
W O W C O W .C
W W .100
Y .TW
W O W C O W W .C OM
W W .100
Y .TW
W O W C O W W .C OM
W W .100
Y
W O W C O W W
WW combines Y.C .TW WW .100Y. .TW W
The AVR core W .100 Oa Mrich instruction set with
W 32 general
. C O M purpose working registers. All the
32 registers WWare directly .C
00Y connected .TW to the Arithmetic WW .1Logic 00Y Unit M .TW allowing two independent
(ALU),
. 1 M
W .CO .TW W
WW executed .CO
registers W to Wbe accessed
. 1 00Y in one M single instruction .1 00Y in one clock cycle. The resulting
W O W
WW .100Y.C M.TW WW
W O
WW .100Y.C M.TW
W O
WW .100Y.C 3
W W
7799E–AVR–09/2012 W
.C OM
00Y .TW
W W.1 Y.COM W
architecture is more code efficient
W
W .100 achieving
while
.T
OM throughputs up to ten times faster than con-
W .C
ventional CISC M .TW
microcontrollers.
W . 100
Y
M .TW
W O
.CO .TW WW .100Y.C M.TW
The . 1 00Y
ATmega8U2/16U2/32U2 M provides W the following O features: 8K/16K/32K Bytes of In-System
W O
WW 0 0 Y.C Flash .T W WW .100Y.C capabilities, M .TW 512/512/1024 Bytes EEPROM,
Programmable
. 1 O M with Read-While-Write W O
WW 00Y.CSRAM, .TW 22 generalW
W .C
00Ylines, M 32.T
W
M .TW W512/512/1024 . 1 O M purpose.1I/O
W O general purpose working registers, two
.CO .TW WW Timer/Counters
flexible 00Y
.C .TW with compare WWmodes Y.C
100and PWM,
W USART, a programmable Watch-
.Tone
.100Y M
W .
W with 1 O M W . O M
W O dogW
W Timer .CInternal Oscillator,W an WSPI serial Y.Cport, debugWIRE.TW interface, also used for
WW .100Y.C M.TW . 1 00Y M .TW W . 100 O M
WW 00Y.C
accessing the On-chip O Debug system and programming and five software selectable power sav-
W
WW .100Y.C M.TW
O
W .T W WW .100Y.C M.TW
ing modes. 1
. The Idle mode M stops the CPUWwhile W allowing O the SRAM, Timer/Counters, SPI port,
W O WW 00Y.CO .TW 0Y.C M.Tmode W
WW .100Y.C M.TW andW interrupt.1system to M continue functioning. W The
W . 1 0Power-down
O saves the register contents
W C O W
W the0Oscillator, .C O W chip 0functions Y .C W
W Y. W but freezes
W 0 Y W
disabling
T all W
other 0 .
untilT the next interrupt or Hardware
W
W .100 O M.T W .1 O M. W W.1 Y.COM W
W .C
WW .100Y.C M.TW
Reset. In Standby mode, the Crystal/Resonator
.TW Oscillator is running while the rest of the device
W
W . 1 00Y
O M
W
W .100 O M.T
W O is sleeping.
WW .100Y.C M.TW StandbyWmode, the
WThis allows Y.C very .fast TW
start-up combined WW .10with 0Y.Clow M power
.TW
consumption. In Extended
W . 100main Oscillator O M continues to W
run. C O
W
WW .100Y.C M.TW
O
W
W O W C O
W
WW .100Y.C M.TW
O The device isWmanufactured Y.C using .TW
Atmel’s high-density WW .10nonvolatile 0Y. M.T
memory
W technology. The on-
chip ISP
W
Flash allows
W . 100the program O M memory to be W
reprogrammed C O in-system through an SPI serial
W O .C WWprogrammer, . W
WW .100Y.C M.Tinterface, W W
byWa conventional . 1 00Y nonvolatile M .TW memory . 1 00Y orM by.Tan on-chip Boot program
W W .C O
W W W Y .COboot.Tprogram W W WW 00Y.CO .TW
Y running on the W AVR core. 0 The can use any interface to download the application
W 00
W.1 Y.COM program
.T .10 M
.CO memory. W.1 Y.COM W
W W in the W WW 00Flash
application Y .T W Software W Win the Boot 00 FlashM .T
section will continue to run
W
W .100 O
.T
Mwhile the Application W .1
Flash C OM is updated, providing
section
. W W.1true Y .C O
Read-While-Write W operation. By
C W .TW
WW .100Y. M .TW W .10CPU0Y M
W
W .100 O M.Ton a monolithic chip,
combining an 8-bit RISC W O
with In-System Self-Programmable C Flash
W
WW .100Y.C the
O
TW ATmega8U2/16U2/32U2
.Atmel WW .100Y.C is W
.aTpowerful WW .100Y. M.T
W
M W O M microcontroller
W that
C O provides a highly flexible
W W Y .C O
W W W 0 Y .C .T W W W 0 0 Y. .T W
W 00 and cost .T effective solution 10many embedded
.to M control applications. .1 M
W 00 .T W .1 program
W.1 Y.The OM ATmega8U2/16U2/32U2 .1 are supported M with a full suiteWof OM and system develop-
C WW 00Y.CO .TW W W 0 Y.C W
W W
. 1 00 ment M W
.T including: C compilers,
tools W
W . 1 macro
O M assemblers, program W
0
O M.T
.1debugger/simulators, in-circuit
W W .C O Wkits. 00Y.C W W W 0 Y. C T W
W 00 emulators,
Y .T W
and evaluation W .T .1 0 M .
W.1 Y.COM W .1 M WW 00Y.CO .TW
W W WW 00Y.CO .TW W
W 00 .T .1 M .1 M
2.2 Pin Descriptions
W 00 .T W .1 M .1 M
2.2.1 VCC W 00 .T W .1 M . 1 M
W 00 supply voltage.
Digital .T W .1 M . 1 M
W 0 0 .T W .1 M . 1 M
2.2.2 GND W W.1 Y.COM W WW 00Y.CO .TW W WW 00Y.CO .TW
W 0 .T W 1
W.1
0
OM W.1 OM W. OM
Ground.
WW .100Y.C M.TW WW .100Y.C M.TW WW .100Y.C M.TW
W W .CO W WW 00Y.CO .TW W WW 00Y.CO .TW
2.2.3 AVCC W 0 Y . T W .1 M
0
W.1 Y.COM W W W.1 Y.COM W WW 00Y.CO .TW
W W
AVCC is10the 0 supply .voltage T W
pin (input) for 0 0
all analog .T
features W
(Analog Comparator,
1 PLL).
M It
Wbe . OMconnected to VCC W.1 Y.COM W W W. Y .CO .TW
W
should .
externallyC W through a low-pass filter. W 0
W 00Y .TW W 00
W.1 Y.COM W
.T .10 M
W W.1 Y.COM W W W WW 00Y.CO .TW
W 0 T W 0 0 .T 1
2.2.4 Port B (PB7..PB0) .10 M. .1 M W. OM
WW 00Y.CO .TW W WW 00Y.CO .TW WW .100Y.C M.TW
W .1 Mresistors (selected
Port B is W an.18-bit bi-directional
.CO have
M I/O port with internal
WW 00Y.CO .TW
pull-up
W WforW eachYbit).
0 .COThe.TW
PortW BW output 0 Y
buffers . T Wsymmetrical W drive characteristics with both high W.
sink 1 0
and M
source
W .10
.C OM W W.1 Y.COM W W 0 Y .CO
capability. W
W As .inputs, 0 Y Port B T W
pins that are W externally 0 0 pulled low .T will source W
current if
. 1 0
the pull-up
0
W 1 Y.COThe M. W W.1 Ywhen M
.CO a reset WW
resistors W
W are activated. 0 0 M.
Port
T W B pins are W tri-stated
.1 0 0 M .T W condition W becomes active,
even if the W W.1is not
clock O
running. W C O
Y.C W WW .100Y. M.T
W
W
W .100 O M.T W C O
Port B also W
W serves.1the .C
functions of
Wvarious special WW features Y. of the ATmega8U2/16U2/32U2 as
listed on pageW74. W
00Y
O M.T W .100
Y.C W WW
W
W .100 O M.T
WW .100Y.C M.TW
W O
WW .100Y.C 4
W W
7799E–AVR–09/2012 W
. C OM
00Y .TW
W W.1 Y.COM W
W 00 .T
2.2.5 Port C (PC7..PC0) W W.1 Y.COM W
W W 00 .T
Port C is an O M.Tbi-directional I/OWport
8-bit W.1withYinternal.C OM pull-up resistors (selected for each bit). The
.C .TW
Y
Port.1C00output M .TW have symmetrical
buffers W
W . 0
10drive characteristics
O M with both high sink and source
W W .C O W are 0externallyY .C W
capability. Y As inputs, WPort C pinsW that 0 T
pulled
. low will source current if the pull-up
W
W .100 O M.T W W.1are tri-stated.C OM
resistors
WW .100Y are . C
activated. The Port C pins Y whenW a reset condition becomes active,
M .TW M .TW W
W . 100 O M .T
evenW O
.CO .TW if the clock is not running.
100Y O
W . O M W O
Y.C the .T WW special 0Y.Cfeatures .TW
WW .100Y.C M.TW WWC also
Port
. 1 0
serves
0 M
functions
W of Wvarious
. 10 M
of the ATmega8U2/16U2/32U2 as
Wpage 77. O W O
W
WW .100Y.C M.TW
O listedW
W
on
00Y
.C .TW WW .100Y.C M.TW
W . 1 O M W O
W
WW2.2.6 0
O
Y.CPort D.T W
(PD7..PD0) WW .100Y.C M.TW WW .100Y.C M.TW
0 O
W.1 OM WW as O
Y.C inputs
W
WW comparator. 0Y.C M.TW
WW .100Y.C M.TW Port D Wserves . 1 0 0analog M .T Wto the analog . 1 0
W O WW 00Y.CO .TW WW
W .CO .TW
0ifYthe
WW .100Y.C M.TW Port DW also serves 1 as an 8-bit bi-directional I/O .
port,1 0 M comparator is not used (con-
analog
W C O WW pins).
.
.C OM WW 00Y.CO .TW
W Y . W cerns W
PD2/PD1 0 Y Port T
pins Wcan provide W internal pull-up resistors (selected for each bit). The
W
W .100 O M.T W .10 O M. W W.1 Y.COM W
C W .C
WW .100Y. WPort D output W buffers
M.T capability. AsWinputs, .100 Port D .TW
Yhave symmetrical drive
W characteristics 00
W.1pulled OM
with
.T both high sink and source
W C O W .C OM pins that are W
externally Y .C
low will source
W current if the pull-up
WW .100Y. M.TW W .
Y
100 TheOPort M .TW W
W
00
.1when O M.Tcondition becomes active,
resistors are activated.
W D pins are tri-stated a
C reset
W
WW .100Y.C M.Teven
O
W if the clock WW is not 0Y.C M.TW WW .100Y. M.T
W
W . 10running. O W C O
W
WW .100Y.C M.TW
O
W
W O W C O
2.2.7 WWD- W .CO .TW WW .100Y.C M.TW WW .100Y. M.T
W
. 1 00Y M W O W C O
W
WW .100Y.C M.TW
O USB Full Speed Negative
WW .10Data 0Y.CUpstream .TW Port WW .100Y. M.T
W
W O M W CO
WD+WW 00Y.CO .TW WW .100Y.C M.TW WW .100Y. M.T
W
2.2.8 . 1 M W O W C O
W
WW .100Y.C USB
O
TWSpeed Positive WW Data Y.C W WW .100Y. M.T
W
M .Full W . 100UpstreamO M .TPort W C O
W
WW .100Y.C M.TW
O
W
W O W CO
2.2.9 W
WW .100Y.C M.TW
UGND O
W
W O W C O
W
WW .100Y.C M.TW
USBOGround.
W
O W O W .C O
2.2.10 UVCC
W
W
O W O W .C O
W
WW .10USB 0Y.CPadsMInternal.TW Regulator WW Input 0Y.C voltage. .TW WW .100Y M.T
W
W . 10supply O M W C O
W O WW .100Y .
WW .100Y.C M.TW WW .100Y.C M.TW M.T
W
O W O W .C O
2.2.11 UCAP W
W
USB Pads O Internal Regulator W
Output supply O
voltage. Should be W
connected to an
.C Oexternal capac-
W
WW itor.1(1μF). .C W WW .100Y.C M.TW WW .100Y .TW
00Y .T W O M
W OM W O
WW .100Y.C M.TW
W O W O
2.2.12 RESET/PC1/dW W
WW .100Y.C M.TW
O
WW input. .CAOlow .level W longer
Wfor Y.C
O W
WW length .COgenerate
Ywill Wa
WReset . 1 0 0 Y
M T W on this W pin
. 1 0 0 than the
M .T Wminimum pulse
W . 1 0 0
O M.T
O W O W .C
W WW 00Y.C
reset, even if the clock
.T
is
W not running. The minimum
WW .100Y.C M.TW
pulse length is given
W in “System
. 1 00Y
Control
M .Tand
W
Reset”W 1
. page 47.
on O MShorter pulses areWnot W guaranteed O to generate a reset.
W WThis pin O
alternatively
.C
.C 0Y .TW
WW as.10debugWire
serves 0Y.C M.channel TW or asWgeneric 00YThe configuration
.1I/O. M.T
W W
dependsW on .10the fuses O MRST-
W O W O W .C
WW and.1DWEN.
DISBL 00Y
.C W WW .100Y.C M.TW W .100
Y .TW
W O M.T W C O W W .C OM
W W .100
Y .TW
2.2.13 XTAL1 W O W C O W W .C OM
WW .100Y.C M.TW WW .100Y. W
M.T clock operating
W .100
Y .TW
Input to theWinverting Oscillator
O amplifier and W
input to the C O
internal W W
circuit. .C OM
W W .100
Y
W O W C O W W
2.2.14 XTAL2/PC0 WW .100Y.C M.TW WW .100Y. M.T
W W
W O W C O
WWthe inverting Y.C Oscillator W amplifierWifW Y. .TW serves as a generic I/O.
Output from
W .100 O M.T
enabled
W .100by Fuse. O MAlso
WW .100Y. C
WW .100Y.C M.TW
W O W
WW .100Y.C M.TW WW
W O
WW .100Y.C M.TW
W O
WW .100Y.C 5
W W
7799E–AVR–09/2012 W
.C OM
00Y .TW
W W.1 Y.COM W
W 00 .T
3. Resources W W.1 Y.COM W
.TW W 00
W.1tools,Y.application
OM
.T
A comprehensiveC OM set of development W C notes and datasheets are available for
1
.
M .TW
00Y on http://www.atmel.com/avr. W . 100 M .TW
.
download
W O W O
W O W O
4. .Code OM ExamplesWW Y.C
O W
WW .100Y.C M.TW
O
00 YC .T W W 1 0 0 .T W
W.1 OM W.
ThisWdocumentation OM contains simple code W examples that O briefly show how to use various parts of
the device. 1
. Be aware OMthat not all C compiler
W O WW 0handling Y.C in.C WW vendors .COinclude
0YPlease
bit definitions in the header files
TW with the C compiler documen-
WW .100Y.C M.TW andWinterrupt 1 0 T W
is compiler Wdependent. . 1 0 M .
confirm
W. OM W O
W
WW .100Y.C M.TW
O
WW
tation for more 0 Y.C
details.
0 .T W WW .100Y.C M.TW
. 1 M
W O WW 00Y.CO .TW WW 00Y.CO .TW
WW .100Y.C M.TW TheseWcode examples . 1 assume
M that the Wpart .1 header
specific Mfile is included before compilation.
W . C O WW 00located Y.CO in .extended
W W WW "IN", 0 Y.CO "SBIS", W "SBIC", "CBI", and "SBI"
WW
. 1 00 Y
M.TW For I/O W registers
W . 1 O M T I/O map,
W .1 0 "OUT",
O M.T
W O
WW must C
be .replaced WW that Y.C access Wto extended I/O. Typically
WW .100Y.C M.TW
instructions .TWwith instructions allow
W . 1 00Y
O M W .100 O M.T
W O "LDS" and "STS" combined with "SBRS", "SBRC", WW "SBR", C
Y.and "CBR".
WW .100Y.C M.TW WW .100Y.C M.TW .100 M.T
W
W O W CO
W
WW .100Y.C M.TW
O
W
5. W DataW Retention W O W C O
.CO .TW WW .100Y.C M.TW WW .100Y. M.T
W
W . 1 00Y M W O W .C O
W O Reliability Qualification WW .data
WW .100Y.C M.than TW 1 PPM over WW .10results 0Y.C show M .TW
that the projected
100
Yretention
M.T
failure
W rate is much less
20W years at O
85°C or 100 years at 25°C.W C O
W
WW .100Y.C M.TW
O
W
W O W C O
W
WW .100Y.C M.TW
O
W
W O W C O
W
WW .100Y.C M.TW
O
W
W O W C O
W
WW .100Y.C M.TW
O
W
W O W C O
W
WW .100Y.C M.TW
O
W
W O W C O
W
WW .100Y.C M.TW
O
W
W O W C O
W
WW .100Y.C M.TW
O
W
O W O W .C O
W
W
O W O W .C O
W
W
O W O W .C O
W
W
O W O W .C O
W
W
O W O W .C O
W
W
O W O W .C O
W
W
O W O W .C O
W
W
W O W O W W .C O
Y
M.T
W
W O W O W W .C O
Y
M.T
W
W O W O W W .C O
Y
M.T
W
W O W O W W .C O
Y .TW
W O W C O W W .C OM
W W .100
Y .TW
W O W C O W W .C OM
W W .100
Y .TW
W O W C O W W .C OM
W W .100
Y
W O W C O W W
W W
W O W C O
W
W O W C O
W O W
WW .100Y.C M.TW WW
W O
WW .100Y.C M.TW
W O
WW .100Y.C 6
W W
7799E–AVR–09/2012 W
.C OM
00Y .TW
W W.1 Y.COM W
W 00 .T
6. AVR CPU Core W W.1 Y.COM W
.TW W 00
W.1 Y.COM W
.T
.C OM W
0Y TW W 00 .T
6.1 Introduction WW.10 .COM. W W.1 Y.COM W
Y W W 00 .T
W .100 discusses
W This section
O M.T the AVR coreWarchitecture W.1 Y.CO inM general. The main function of the CPU core
WisWto ensure .C TW W
M .TW . 1 00Ycorrect M .program W
execution. W .
The 100CPU must O M .Ttherefore be able to access memories,
C O W W .C O W and0handle Y .C W
Y. W W 0 Y W W 0 .T
00
W.1 Y.COM W
.T perform calculations,
.10 M.T control peripherals, .1
WW 00Y.CO .TW
interrupts.
M
W W WW 00Y.CO .TW W
W .100 Architectural.T .1 M .1 M
W W6.2 .C OM
W WW 00Y.CO .TW
Overview W WW 00Y.CO .TW
W 00 Y .T W .1 M .1 M
W 00 .T W .1 M
W.1 Y.COM W Figure W 6-1.W.1 Block Y
M
Diagram
.CO .TW
of the AVR Architecture
WW 00Y.CO .TW
W W 0 W .1
W 00
W.1 Y.COM W
.T .10 M WW 00Y.CO .TW
M
W W WW 00Y.CO .TW W
W 00 .T .1 M .1 M
W.1 Y.COM W WW 00Y.CO .TW W WW 00YData .COBus 8-bit W
W W
. 1 00 M .T W
W . 1 O M W .1 O M.T
W O WW .100Y. C
W
W O W C O
W
WW .100Y.C M.TW
O
WW Flash 00Y
.C Program
.T W WW .10Status 0Y. M.T
W
W . 1 O M Counter W and ControlC O
W
WW .100Y.C M.TW
O
WW
Program
W
Memory
W . 100 O M W C O
W
WW .100Y.C M.TW
O
W
W O W O Interrupt
W W .C O W Y .C W W W 32 x080Y. C T W
Y W W 0 .T . Unit
W
W .100 OM.T Instruction W .10
.C OM W W.1 Y.COM W
General
C W .TW
WW .100Y. M.T
W W
Register
.100
Y W Purpose 00
W.1 Y.COM W Unit
.T SPI
W C O W W .C OM Registrers
W
W Y . W W 0 Y .T W W .1 0 0 .T
W 00
W.1 Y.COM W
M
W W WW 00Y.CO .TW W
W 00 .T Instruction 1 .1 M Watchdog
W W.1 Y.COM W DecoderWW. 0Y.COM W W WW 00Y.CO .TW Timer
W .T
Indirect Addressing
W 1 00 .T .10 M W .1 O M
Direct Addressing
. M W O C
W
WW .100Y.C M.TW
O
WW .100Y.C M.TW W W
ALU W.10
0Y. W
M.T Analog
W O C O
W O
WW .100Y.C M.TWControl Lines WW .100Y.C M.TW WW .100Y. .TW
MComparator
O W O W .C O
W
W
O W O W . C O
W
WW .100Y.C M.TW WW .100Y.C M.TW WW .100Y .TW
MModule1
O W O W .C O
I/O
W
W
W O W O W W .C O
WW .100Y.C M.TW WW .100Y.C M.TW Data W .100
Y
M.T
W
W O W O W W .C
I/OOModule 2
WW .100Y.C M.TW WW .100Y.C M.TW SRAM W . 100Y M .TW
W O W O
W
WW .100Y.C M.TW
O
W O W O
W O
WW .100Y.C M.TW WW .100I/O Y.CModule n.TW
WW .100Y.C M.TW W OM
W O
W
WW .100Y.C M.TW
O
WW .100Y.C MEEPROM .TW WW .100Y.C M.TW
W O W O
W
WW .100Y.C M.TW
O
W O W O WW 00Y.CO .TW
WW .100Y.C M.TW WW .100Y.C I/O .T W W
W O W .C OM Lines W W.1 Y.COM W
.C W W
W W
.100
Y
M.T
W W
W .100
Y
O M.T
W
W .100 OM
.T
W O C W .C
W W .100
Y .TW
W O W C O W W .C OM
Y.C performance W Y. .TW a Harvard Y W
WWto maximize
In order .100 M.T
W and W parallelism,
W .100the AVR O Muses
W .100 – O
architecture
W M.T
with
W O Y. C W .C
Y are
WWmemories
separate Y.C and buses Wfor program WWand .data. 100 Instructions
W
M.T in the program
W .100
memory
W .100 O M.T W C O W W
executed WW with a single .Clevel pipelining.
.TW WWone instruction
While Y. W executed,
is being W the next instruc-
W .1 00Y
O M W .100 O M.T
tion is pre-fetched from the program memory. WW This concept C
Y. enables Winstructions to be executed
WW .100Y.C M.TW .100 Reprogrammable
M.T
in every clock W cycle. TheCprogram O memory is In-System W C O Flash memory.
WW .100Y. .TW WW .100Y.
W O M W
WW .100Y.C M.TW WW
W O
WW .100Y.C M.TW
W O
WW .100Y.C 7
W W
7799D–AVR–11/10 W
.C OM
00Y .TW
W W.1 Y.COM W
W 00 .T
The fast-access Register File contains W W.1 32 Y x .8-bit
C OMgeneral purpose working registers with a single
clock cycle access M .TW time. This
W
allows . 100
single-cycle M .TW
Arithmetic Logic Unit (ALU) operation. In a typ-
C O W W .C O
Y . W W 0 Y .T W
100 operation,
ical ALU
W.the OM
.T two operands areWoutput .10 from Mthe Register File, the operation is executed,
Wand Y
result. C is stored W back in the
W WRegister 0 Y
File.CO – in .TW
one clock cycle.
W . 1 00 M .T W . 10 O M
W C O W . C
.TW WSix W of the0032
1
.
Y registers
M .TW can be used W as three .
Y
100 16-bitOindirect M .TW address register pointers for Data
M . O W
.CO .TW WW addressing
Space 00Y
.C – enabling .TW efficient WWaddress Y.C
100 calculations. .TWOne of these address pointers can
.100Y M
W .
Wused Y1 O M W . O M
W O alsoWbe as.Can address pointer W forWlook up0tables Y.C in Flash .TW program memory. These added
WW .100Y.C M.TW W . 1 00 M .TW W . 10 O M
function W registers O
are the 16-bit X-, Y-, and Z-register, described later in this section.
W
WW .100Y.C M.TW
O
W O WW 00between O registers or between a constant and
W O The ALU
WW supports Y.Carithmetic Wand logic W operations Y.C .TW
WW .100Y.C M.TW . 1 0 0 M .T
W . 1 O M
a register. W Single registerO operations can also be executed in the ALU. After an arithmetic opera-
W O
WW .100Y.C M.TW tion, the WWStatus 0 0 Y.C .T W WW .100Y.C M.TW
1
W. Register OM is updated to reflect information W about
O the result of the operation.
W
WW .100Y.C M.TW
O
O by conditional andWunconditional W Ojump and call instructions, able to
W O Program flow WWis provided Y.C 0Y.C M.TW
WW .100Y.C M.TW directly W 1 0 0 M .T W W . 1 0
O address W.the whole Oaddress space. Most AVR instructions
W Y.C
O have a single 16-bit word for-
W
WW .100Y.C M.TWmat. Every WW program 0 0 Y.C
memory .T
address W contains WW a 16- . 1
or0 032-bit M .TW
instruction.
W . 1 O M W C O
W
WW .100Y.C M.TW
O
WW memory Y.C TW WW .100Y. W
M.T Program section and the
Program Flash W . 100 space O M .is divided in two sections,
W the
C O Boot
W O W 0Y.C Both WWdedicated Y. .TWfor write and read/write
WW .100Y.C M.TApplication W WProgram.10 section. M .TW sections have W .100 Lock O Mbits
O W O Y. C
W
WW .100Y.C M.protection. TW TheWWSPM.1instruction 00Y
.C .TWwrites into
that WW .100
the Application W
M.T memory section must
Flash
W O M W C O
W O
WW .100Y.C Mreside .TW
in the Boot WWProgram .C
Ysection. .TW WW .100Y. M.T
W
W . 100 O M W C O
W O W Y.C calls,.Tthe WW Program Y. W
WW .100Y.C During M .TW interruptsWand subroutine .100 M
W return address
W .100 Counter O M.T (PC) is stored on the
O W O C
Y. and consequently
W
WW .100Y.C Stack. .TW
The StackW isW effectively .C
Yallocated .TinWthe general WW data SRAM,
.100 M.T
W the Stack
M W . 100 O M W C O
W Osize is only limited byWthe total Y SRAM size and the usage
0 .C M.TW WW of the Y.
SRAM. All T
. user
W programs must
WW .100Y.C initialize M .TWthe SP inW the Reset . 10routine (before subroutines or W .100
interrupts O
areMexecuted). The Stack
W O C
W
WW .100Y.CPointer
O
.T W is read/write WW accessible 0 0Y.C inMthe .TW WW .100Y. M TW
.easily
(SP) .1 I/O space. The data SRAM can be accessed
W W .C OM
W
W
Waddressing Y
O
.Cmodes W W WW 00Y.CO .TW
W 00 Y through the
.T five different W .10 0 M .T supported in the AVR .1 architecture. M
W
W 00 The memory
W.1 Y.COM W
.T spaces in the AVR .1 architecture M are all linear andWregular W.1 memory OM maps.
W W WW 00Y.CO .TW W 0 0 Y.C .TW
W . 1 00A flexible M .T
interrupt module has . 1its control O Mregisters in the I/O W
space .1 with an O M
additional
W O W W
0Y.C All WW .100Y .C W Global
WW .10Interrupt0Y.C Enable .T W bit in theWStatus . 10
Register. M .TW
interrupts have a separate Interrupt M .TVector in the
W W .C OM
W WW 0have Y .CO .TW W WW 00Y.CO .TW
Y W 0 1
W
W .100
Interrupt Vector
O M.T table. The interrupts
W W.1 Y.COM W
priority in accordance with
W W. their Interrupt
Y .C OM Vector
W
posi-
WW tion. The . C
Y lower.Tthe W InterruptW Vector address, 00 the higher.T the priority.W 00 .T
W .100 O M W.1 Y.COM W W W.1 Y.COM W
.C W W functions 0 .T Regis-
WW The 0Y memory
.10I/O
W
M.Tspace containsW64
W 00
addresses for.T CPU peripheral 0
W.1 Yas Control
OM
W O W.1 Y.COM W W .C
WW ters,.10SPI, .C
0Y and M other
.TWI/O functions. W The W 0 M.theTWData
W .10I/O0 Memory
O M .Tcan be accessed W
directly,
.10
C
or as
O
W O C
.Register WW .
Y addition, Wthe
Space
WW .100Y.C M.TW
locations following those WW of.1the 00Y M .TWFile, 0x20 - 0x5F.00In
.1 M.T
ATmega8U2/16U2/32U2 O has Extended W I/O space O from 0x60 - 0xFF in
W W SRAM C
where
. O only the
WW 00Y.C
WST/STS/STD . T W WW .100Y.C M.TW W . 100Y M .TW
W. 1 andOM LD/LDS/LDD instructions W can be O used. W O
W W .CO W WW 00Y.CO .TW W WW 00Y.CO .TW
6.3 ALU – Arithmetic Logic W 0 Unit
0 Y .T W .1 M
The W
W high-performance 0 AVR
T ALU W
operates in 0
direct
0 connection . T with all W
the 32 general
1 purpose
0
W.1 Y.CWithin
.
OM a single clock W W.1 Y.COM W WWgeneral
. OM
W 0 Y.C W
WW registers.
working
. 1 0 0 M .T W W cycle,
W .1
arithmetic
0 0
O M
operations
.T between
W . 1 0
O M.T
purpose
W O C W .C
Y divided.TW
registers or between a register and an immediate
WW .100Y.C M.TW WW .10are 0Y.executed. W The ALU operations
M.T See the “Instruction
W are
.100 Set” sec-
W O W OM
into three main
W W categories
Y .C O – arithmetic,
W
logical,
W W and
0
bit-functions.
Y .C
.T W W W 0 0 Y.C
W 0 .T 0 . 1
tion for a detailed 0
W.1 description. OM W.1 OM W
WW .100Y.C M.TW WW .100Y.C M.TW WW
W O W O
6.4 Status Register WW .100Y.C M.TW WW .100Y.C M.TW
WW 0contains O
WW
W .CO
The Status WRegister . 1 0Y.C M .TW
information about the result. 1 00Yof the most recently executed arithme-
W information .CO .Tcan W
tic instruction. WW This 00Y W be used WW for altering program flow in order to perform
W . 1 O M
WW .100Y.C M.TW
W O
WW .100Y.C 8
W W
7799D–AVR–11/10 W
.C OM
00Y .TW
W W.1 Y.COM W
W 0
.10Status M.T is updated after all ALU operations, as
conditional operations. Note that W Wthe .C ORegister
.TW Y W
specified in the M Instruction Set
WReference.
W . 100 This O M
will .Tmany
in cases remove the need for using the
.C O W Y .C W
dedicated Y
00 compare W
.Tinstructions, resulting W 0
.10in faster M .T
and more compact code.
W W.1 Y.COM W WW 00Y.CO .TW
W The Status 00 .T W .1stored when M entering an interrupt routine and restored
W W.1 YRegister .C OM is not automatically
W WW 00Y.CO .TW
.T W Wwhen returning 00 from .an T interrupt. This must W .1 be handled M by software.
.C OM W W.1 Y.COM W WW 00Y.CO .TW
Y W W 0 W
100
W.6.4.1 M.T – Status Register .10 M.T .1
WW 00Y.CO .TW
M
W Y .C OSREG
W W WW 00Y.CO .TW W
W 00 .T .1 M .1 M
W 00 .T W .1 M .1 M
W.1 Y.COM W Bit WW 070Y.CO 6 .TW 5 W 4W 3 .CO
Y 2 W 1 0
W W W 0 0 M.NT
W .1 00 M .T 0x3F (0x5F) W.1 I O M T H S W.1 V O Z C SREG
W
WW .100Y.C M.TW
O
WW .1R/W
Read/Write 00Y
.C R/W .TW R/W WR/W W
. 1 0 0Y.C M
R/W R/W.TW R/W R/W
W O W OM 0 W
W .CO 0 .TW 0
WW .100Y.C M.TW Initial Value WW 0.100Y.C 0 M.TW 0 W 1 000Y 0
W O W C O W W .
.C OM
W . Y W
WW .100Y.C M.TW • Bit 7 W Y
.100Interrupt .TW W 00
W.1 Y.COM W
.T
W C O – I: W Global
W .C OMEnable W
WW .100Y. W Y W W .100 .T
W O
W
M.T The Global Interrupt W .100EnableObit M.T must be set for the W W interrupts .C OM
to be enabled. The individual inter-
C W .C Y W
WW .100Y. M .TWrupt enableWcontrol.1is00 Y performed
then M .TW in separate W control
W .100registers. O MIf.Tthe Global Interrupt Enable
W O C
W O
WW .100Y.C M.TRegister W is W W
cleared, .C
00Y of the .TW areW
W 0Y.
.10independent
W
M.Tof the individual interrupt
W . 1none O M interrupts enabled
W C O
W O
WWThe .I-bit Yis.Ccleared W an0interrupt Y. has W
WW .100Y.C M.enable TW settings. 100 M .Tby
W hardware Wafter
W .1 0 O M.T
occurred, and is set by
O the RETI instruction W O
to enable subsequent interrupts. C
Y. can also
W
WW .100Y.C Mthe .TW WW .100Y.C M.TW WW The I-bit
.100 in the M .TW be set and cleared by
application with the
W SEI and O CLI instructions, as W
described C O instruction set reference.
W
WW .100Y.C M.TW
O
WW .100Y.C M.TW WW .100Y. M .TW
W O
W O
WW Storage
W .CO .TW WW .100Y.C M.TW
WW .100Y.C • M Bit.TW 6 – T: Bit Copy . 1 00Y M W O
W O
WW BLD
W .CO .Tand WW 0Y.C W
WW .100Y.C TheMBit .TW Copy instructions
. 1 00Y(Bit LoaD)M
W BST (Bit STore)
W . 1 0use the T-bit
O M.Tas source or desti-
W O
nation for the operated W O
.C a register W C
. be copied
WW .100Y.C M.TW WWbit. A.10bit 0Yfrom M .TW
in the W Register FileYcan
.100 in the .TW into T by the
MRegister
BST instruction, and a bit W in T can beO copied into a bit in a Wregister C O File by the
W
WW .100Y.BLD CO
.T W WW .100Y.C M.TW WW .100Y. M .TW
OM instruction. W O W O
W
W O
W .CO5 – H: WW 00Y.CO .TW WW .100Y.C M.TW
WW .100• YBit .T WHalf CarryW Flag
.1 M
W The Half OMCarry Flag H indicates W .CO W
WW operations. .CO .TW Is useful
WW .100Y.C M.TW WW a.1Half 00Y CarryMin.Tsome W arithmetic . 1 00Y HalfMCarry
W in BCD O arithmetic. See the “Instruction W SetODescription” for detailed W
WW information. .CO .TW
WW .100Y.C M.TW WW .100Y.C M.TW . 1 00Y M
W W .C O WW 00Y.CO .TW W WW 00Y.CO .TW
W Y
00 4 – S: Sign
• Bit .T Bit, S = N V W.1
W W M . 1 M
W W.1 Y.COM W W or between Y .COthe Negative W W WW 00Y.CO .TW
The S-bit is always an exclusive W 0 .T Flag N and the Two’s
W
W .10 0
O M.T 0
W.1Set Description”
C OM W W. 1
.C OComplement
M
. C W Y . W W 0 Y W
W W Overflow
. 1 0 0 Y Flag V.
M
See
.T W the “Instruction
W
W .1 0 0
O M .T for detailed information.
W . 1 0
O M.T
W O WW .100Y .C
WW• Bit.1300–YV: .C W
.TComplement WW .100Y.C M.TW M.T
W
Two’s
O M Overflow
W Flag O W W .C O
WW 00Y.C
WThe .TW Overflow WWFlag.1V00supports Y.C .TW complement W .100
Y
M .TW
Two’s
. 1 Complement
O M W O M two’s
W Warithmetics. .C O See the
WW 00Y .C W for detailed WW information. Y.C W W .100
Y
M.T
W
W“Instruction
W .1 Set Description”
O M.T W .100 O M.T W W .C O
Y
M.T
W
W O W O W W .C O
• Bit 2 – N: Negative Flag
Y .TW
The Negative W Flag ON indicates a negative W result in C O
an arithmetic or logic W W
operation. .C OMthe
See
WW .Set Y.C W WW .100Y. M.T
W W .100
Y .TW
“Instruction W 100 Description” O M.T for detailed information. W C O W W .C OM
W W .100
Y .TW
W O W C O W W .C OM
• Bit W 1– WZ: Zero .C
Flag
Y W WW .100Y. M.T
W W .100
Y
The Zero WW Flag Z indicates .C a .zero TW result inWan arithmetic
W Y. or logic.Toperation.
W See
W the “Instruction
W
00Y
.1for O Minformation. W .100 O M
Set Description” detailed
WW .100Y. C
WW .100Y.C M.TW M.T
W
W O W C O
W O W
WW .100Y.C M.TW WW
W O
WW .100Y.C M.TW
W O
WW .100Y.C 9
W W
7799D–AVR–11/10 W
.C OM
00Y .TW
W W.1 Y.COM W
W 00 .T
• Bit 0 – C: Carry Flag W W.1 Y.COM W
.TW W
in.1an00arithmetic .T
OM or logic operation. See the “Instruction Set
The Carry Flag
C OMC indicates a carry W W .C
00Y forM
Description”
1
. .TW information.
detailed W . 100
Y
M .TW
W . O W O
W O W O
6.5 General
.T W PurposeWW Register 0 0 Y.C File.TW WW .100Y.C M.TW
. 1 M W O
OM WW CO is optimized
Y.File WWAVR.1Enhanced 0Y.C M .TWinstruction set. In order to achieve
00 Y.C .T W The
W Register
. 1 0 0 M .T W for the 0 RISC
.1 M W O W O
W O the Wrequired performance
.C WWthe following
and flexibility, Y.C input/output .TW schemes are supported by the
WW .100Y.C M.TW W
Register . 1
File:00Y M .TW W . 100 O M
W O
W
WW .100Y.C M.TW
O
W O • One 8-bit O
W output operand and one 8-bitWresult W input .CO .TW
WW .100Y.C M.TW WW .100Y.C M.TW W . 1 00Y M
W W .C O • TwoW W output
8-bit Y .C O
operands W and one 8-bit W
W input
Wresult 0 Y .CO .TW
Y W W 0 M. T 0
W 00 .T
W.1 Y.COM W • Two 8-bit .10 operands
.CO .Tand W.1 input OM
WWoutput Y W one 16-bit W Wresult 0 Y.C W
W W
. 1 00 M .T W
W . 10 0
O M W .1 0
O M.T
W O
WW .100Y.C M.TW
• One 16-bit output operand and one 16-bit WW result input Y.C W
WW .100Y.C M.TW W .100 O M.T
O W O .C
W
WW .100Y.C M.TW
Figure 6-2 shows
WW .100Y.C M.TW
the structure of the 32 general WW purpose .100
Yworking
M.T
registers
W in the CPU.
W O W C O
W O
WWAVR.1CPU .C WW Registers Y. W
WW .100Y.C M.TW Figure 6-2. 00Y General M
W
.TPurpose WorkingW .100 O M.T
W O C
W
WW .100Y.C M.TW
O
W
W O W C O
W
WW .100Y.C M.TW
O
WW .100Y.C7 M.TW 0
WW .10Addr. 0Y. M.T
W
O W O W .C O
W
WW .100Y.C M.TW WW .100Y.R1 C
R0
.TW WW .10x00 00Y M.T
W
W O M W 0x01 C O
W O
WW .100YR2 .C WW 0x02 Y. W
WW .100Y.C M.TW M .TW W .100 O M.T
W O C
W
WW .100Y.C M.TW
O
WW .100…Y.C M.TW WW .100Y. M.T
W
W O W C O
W
WW .100Y.C General
O
.TW WW .100Y.C M.TW
R13
WW 0x0D.100Y. M.T
W
M W R14 O W
0x0E C O
W O
WW .100Y.C Purpose .TW WW .1R15 00Y
.C .TW WW0x0F .100Y. M.T
W
M W O M W C O
W O
WW R16 Y.C WW Y. W
WW .100Y.CWorking M .TW . 100 M .TW 0x10
W .100 O M.T
W O W O W Y. C
WW .100Y.C M.TW WW .100Y.C M.TW W
Registers R17
W0x11 .100 M.T
O W… O W .C O
W
WW .100Y.C M.TW WW R26.100Y.C M.TW WW X-register
0x1A
Y
.100 LowOByte M.T
W
O W O W .C
W
WW .100Y.C M.TW WWR27 .100Y.C M.TW WW X-register
0x1B Y
.100 High Byte M.T
W
W O W O W
0x1C W Y-register .C O
WW .C Y W
WW .100Y.C M.TW
R28 Low Byte
R29 W.1
00Y M .TW W
W .100 High Byte O M.T
O O 0x1D Y-register .C
W
WW .100Y.C M.TW
W Y.C .TW WWZ-register .10Low0Y Byte M.TW
WR30 . 100 M 0x1E
W W .C O W W Y .C O
W W W W
0 .CO .TW
YByte
W 0 0 Y .T W WR31
.1 0 0 M .T 0x1F Z-register
. 1 0
High
M
W 0 .T W 1
0
W.1 of the OM W.the1 Register M WW to
. OM
Most instructions
Y.C are single
operatingWon
Y .CO File W
have direct access
W 0
all
Y.Cregisters, .TW
and
WWmost.1of00them .T W cycle W
instructions. . 1 0 0 M .T
W . 1 0
O M
W OM W O
WW .100Y.C M.TW
O a data memoryW W O them
As shown
WW 00Y.CO .TW
in Figure 6-2, each register
W WW is also assigned
0 0 Y.C .T W W
address,
1 0 0
mapping
Y.C .TW
W
directly .1 into the first M32 locations of the .1 Data Space.
user M Although not W beingW . physically O Mimple-
W O W O .C
WW as 0Y.C locations, W this memory WW organization Y.C provides W great W Y
00access of.T
W
mented
W .10SRAM O M.T W .100 O M.T flexibility
W W .1in
.C O M the
Y.C W .C W any register 00Yfile. M.TW
WW as
registers,
.100
the X-, Y- and
M.T
WZ-pointerW registers 00Ybe setMto.Tindex
.1can
W
W
in.1the
O
W O W C O W Y.C
WW .100Y.C M.TW WW .100Y. .T W W 1 0 0 .TW
6.5.1 The X-register, Y-register, W and Z-registerO W C O M W W .
.C OM
.C WW .100Y. .TW purpose W 0Y W
The W
W
registers 00Y
.1R26..R31 M .TWsome added
have functions
W to C their
O Mgeneral W
usage. .10These O M.T
reg-
W O Y. of the W Y .C
isters W
W 0Y.C M .TW for indirect WW addressing .100
W
M.T data space. The
W .100 indirect
are 16-bit
W .10address O
pointers W C O W W three
W .C and Z.Tare W defined W asW Y. W W
address Wregisters
W .100
X,YY,
O M
described
W .100 in Figure O M.T6-3.
WW .100Y. C
WW .100Y.C M.TW M.T
W
W O W C O
W O W
WW .100Y.C M.TW WW
W O
WW .100Y.C M.TW
W O
WW .100Y.C 10
W W
7799D–AVR–11/10 W
.C OM
00Y .TW
W W.1 Y.COM W
W 00 .T
W W.1 Y.COM W
.TW W 00
W.1 Y.COM W
.T
.C OM W
Y W W 00 .T
W .100 O M.T W W.1 Y.COM W
WW .
0Y TheC TWY-, and Z-registers W 00 .T
Figure
W .106-3. O M.X-, W W.1 Y.COM W
W WW .100Y .C W W 00 .T
O M.T W O M.T15 W W.1 Y.COM W
.C W .C XH XL 0
100Y M .TW WX-register . 1 00Y M .7TW W
W . 100 O M .T
. W O 0 7 0
W O
WW .100Y.C M.TW WW .100Y.C MR27 .TW (0x1B)
WW .100Y.C M.R26 TW(0x1A)
W O W O
W
WW .100Y.C M.TW
O
W O W O
W
WW .100Y.C M.TW
O
WW .100Y.C 15M.TW YHWW .100Y.C M.TW YL 0
W O W C O W W .C O7
W . Y W
WW .100Y.C M.TW
Y-register 7 0 0
W .100
Y
M .TW W 00
W.1 Y.COR28
.T
M(0x1C)
W O W W .C O
R29 (0x1D)
W W
WW .100Y.C M.TW W . 100
Y
M .TW W
W .100 O M.T
W O
W
WW .100Y.C M.TW
O
WW .100Y.15 C
.TW ZH WW .100Y.C M.TW ZL 0
W O M W C O
W O .C WW .100Y.
Z-register 7 0 7 W 0
WW .100Y.C M.TW WW .100YR31 M .TW R30 O M.T
W (0x1F)
O W C (0x1E)
W
WW .100Y.C M.TW
O
W
In the different addressing
W O
modes these address W
registers haveC Ofunctions as fixed displacement,
W O
WW .100Y.C M.Tautomatic W WW .1and .C
00Y automatic .TW WW .100Y. M .TW
increment, M decrement (see the
WW 00Y.CO .TW
instruction set reference for details).
W W Y .C O
W W WW 00Y.CO .TW W
W 00 .T W.1 Y.COM W .1 M
6.6 WStack.10Pointer W 0 M. T
0
OM
.T .10
CO temporary W.1 Y.COM W
W W Y.C The W
Stack is W
mainly WW used 0
forY .storing .T W W
data,
Wfor 00 local variables
storing .T and for storing
W
W .100 O M.T W .10
.C
M
Oand W W.1 Y.COM W
C return addresses W
after interrupts subroutine
.TW calls. Note that the Stack is implemented as
WW .100Y. M .TW W . 100
Y
M
W
W .100 O M.T
O W O .C
W growing from higher W
WW .100Y.C topMof.Tthe W W
to lower memory
0Y.C M.TW
locations. The Stack WW Pointer 00Y
.1Stack
Register
.Talways
W points to the
Stack. The StackW . 10Pointer Opoints to the data SRAM W O
area
C
Mwhere the Subroutine
W
WW .100Y.Cand M
O
.TW StacksWare located.
W .C
00YA Stack TW command
.PUSH WW .100Y. M .T W
Interrupt W .1 O M will
W decrease O the Stack Pointer.
W
WW .100Y.The CO
W .CO .TW
M in the data SRAM
Stack
WW must beO defined by the program WWbefore CO subroutine
.any W calls are
WW .100Y executed or interrupts Ware 1
enabled.
. 0 0Y.CInitial M .TW PointerWvalue equals
Stack . 1 00Y the last M .Taddress of the
W W .C OM
W WWPointer Y.CO .TW W WW 00Y.CO .TW
W 00 Y
internal SRAM and the W
Stack .10 0 must be set to point above .1
start of the SRAM, see Figure
W.1 7-2Y.on M.T
Opage WW 00Y.CO .TW
M WW 00Y.CO .TW
M
W C 18.W W W
W 00 .T .1 M .1 M
W W.1 Y.COM W WWdetails. Y .CO .TW W WW 00Y.CO .TW
W 00
See Table 6-1.T for Stack W
Pointer .10 0 M . 1 M
W 1
W .100 6-1.OM.Stack
WTable
T Pointer instructions .1
WW 00Y.CO .TW
M .
WW 00Y.CO .TW
M
W W 0 Y . C W W W 1
.10 .T W.1 Y.COM W . M
W WInstruction .C OMStack pointer
W WDescription W WW 00Y.CO .TW
W 0 Y .T W 0 0 .T 1
.10 OM W.1is pushed OM W. OM
W
PUSH
WW .100Y.C M.TW
Decremented by 1 W
W
Data
0 0 Y.C onto the .T W stack WW .100Y.C M.TW
.1 M W a subroutine O
W
CALL O WW address
Return .CisOpushed onto the stack Wwith Y.C call.TorW
WWICALL.100Y.C Decremented M. T W W 0 0 Y .T W W
W. 10 0
OM
by 2 interrupt W.1 OM
WW 00Y.CO .TW
WRCALL WW .100Y.C M.TW WW .100Y.C M.TW
.1
WW 00Y.Incremented CO
M
W WW 00Y.CO .TW W WW 00Y.CO .TW
WPOP .T by 1 W
Data is popped from the stack .1 M
W W 0 T W 0 0 .T W 1
RET
W.1
0 Incremented
OM
. by 2 Return address W.1 is Y popped
.C OMfrom the stack withW W. fromY.COM W
return
WW .100Y.C M.TW
RETI WW or.return
subroutine 0 0 from interrupt
.T W W .100 .T
W O W 1
C O M W W .C OM
M.Tin the I/O space.
W .100
Y .TW
The AVR Stack
W Pointer O is implemented as W
two 8-bit O
registers
C W W
The .
numberC OM of
WW used Y.C W WW .100Y. TW
M.data
W .100
Y
bits actually W .100 is implementation
O M.T dependent. W Note that C Othe space in some W W implementa-
W .C
isW WW Y. W W
tions ofW
W
00Y
the AVR.1architecture
O M.T so small that onlyW .100 is needed.
SPL O M.TIn this case, the SPH Register
WW .100Y. C
will not be WW present.00Y.C W M.T
W
W .1 O M.T W C O
W O W
WW .100Y.C M.TW WW
W O
WW .100Y.C M.TW
W O
WW .100Y.C 11
W W
7799D–AVR–11/10 W
.C OM
00Y .TW
W W.1 Y.COM W
W 00 .T
6.6.1 SPH and SPL – Stack Pointer High and Low Register W W.1 Y.COM W
.TW W 00
W.1 Y.COM W
.T
.C OM W
Y W W 10012 .T
Bit
W .100 O M.T
15 14 13 W.
W .C OM11 10 9 8
WW0x3E (0x5E) 0 .C
Y SP15 .TW SP14 W 0 0Y .TW SP10
1 0 SP13 . 1 SP12 M
SP11 SP9 SP8 SPH
W
.
W(0x5D) .C OM WW SP4 Y .COSP3 .TW SP2
W Y W W 0 0
W .100 M.T 6
0x3D SP7 SP6 SP5 SP1 SP0 SPL
O M.T W .C O W W.14 Y .C O M
W
Y.C W 7
W 5 3 2 1 0
.100 M.T
W WRead/Write
W
Y
.100 R/WOM.T R/W R/W
W
WR/W.100 OM
R/W
.T
R/W R/W R/W
W O C W .C
WW .100Y.C M.TW WW .100YR/W M.TR/W . W R/W
W R/W . 1 00 R/W M.TW
Y
R/W R/W R/W
WW O
W W Y .C O
W W
InitialW W
Value 0 Y
0 .CO 0.TW 1 W 0 0 0 Y.0C .T 0W 0 0
W 00 .T .10 M .1 OM 1
W.1 Y.COM W WW 010Y.CO 1 .TW 1 W W1 W 00Y 1 .C W 1 1
W W
.1 00 M .T W
W . 1 O M W .1 O M.T
WW
W Y.C
O
.TWExecution WW .100Y.C M.TW WW .100Y.C M.TW
6.7W.100Instruction M Timing
W O W O
O
WW .100Y.C M.TW This section WW describes 0 0 Y.C .T W WW .100Y.C M.TW
W. 1 theMgeneral access timing W concepts Ofor instruction execution. The AVR
W O
WW by.1the .CO .TW WW generated 0Y.CfromMthe .TW
WW .100Y.C M.TW CPU is driven 00YCPU clock M clk CPU , directly W . 1 0
O selected clock source for the
W C O W
W clock .C O W Y .C W
W Y. W chip. No internal
W 0 Y division is
.T W
used. W .1 0 0 .T
W . 1 00 M .T W . 10 O M W C O M
W O W Y.C instruction WWand instruction Y. W
WW .100Y.C M.TW Figure 6-4W shows the . 100parallelOM .TW fetches W .100 O M.T
executions enabled by the Har-
W .C O W
W and 0the Y C
.fast-access W Wconcept. 0 Y .C W
W Y W
vard architecture W 0 .T Register WFile 0 This is .T
the basic pipelining concept
W
W .100 O M.T W .1
.C OM with the corresponding W W.1 Y.COM W
C to obtain up to W1 MIPS per MHz .TW unique results for functions per cost,
WW .100Y. M .TW W . 100
Y
M
W
W .100 O M.T
W O C
W
WW .100Y.C M.TW
O functions per clocks, and functions per power-unit.
W
W O W C O
W O
WWParallel Y.C W Y. W
WW .100Y.C Figure M .TW 6-4. The .100Instruction M
W
.TFetches andW Instruction
W .100Executions O M.T
W O W O W Y. C
WW .100Y.C M.TW WW .100Y.C M T1.T
W W T2 .100 T3OM.T
W
T4
W O W .C O W W Y. C W
W Y.C W W W 0 Y .T W W 0 0 .T
W 00 .T .10 M .1 M
W 00 .T W clk CPU .1 M .1 M
W 00 1st
.T Instruction W
Fetch .1 M .1 M
W W.1 Y.COM 1st W
Instruction Execute WW 00Y.CO .TW W WW 00Y.CO .TW
W 00 .T W .1 M
W.1 Y.COM 2nd Instruction Fetch WW.1 .CO .TW
M WW 00Y.CO .TW
W W W 0 Y W .1
W 00
W.1 Y.COM
.T
2nd Instruction Execute .10 M WW 00Y.CO .TW
M
W 3rd Instruction
W Fetch WW
W 0 Y .CO .TW W
W 00 3rd Instruction
M.T .10 M .1 M
W W.1 Y.C O4th
W
Execute
WW 00Y.CO .TW W WW 00Y.CO .TW
W 00 Instruction
.T Fetch W .1 M . 1 M
W 00 .T W .1 M . 1 M
W Figure 0 W
.T the internal timingWconcept . 1 M an ALU
W .10 6-5 shows OM W
.1 for the
.CO .and
M Register File. InW aW single clockOcycle
Y.Cto the.Tdestina- W
W W operation 0 Y .Cusing two W register W
operands is0 0 Y
executed, T W the result W is stored 1 0 0
back
. 1 0 M .T W .1 O M W .
C O M
W O WW .100Y .
WWtion register.00Y
.C .TW WW .100Y.C M.TW M.T
W
.1 O M W O W W .C O
WW 00Y.C
WFigure W
.TCycle WW .100Y.C M.TW W .100
Y
M.T
W
W . 16-5. Single
O M ALU Operation W O W W .C O
WW .100Y.C M.TW WWT1 .100Y.C T2 M.T
W W Y
.100 T4 OM.T
W
W O W O T3
W W .C
Y
M.T
W
W O W O W W .C O
WW .100Y.C clk .TW WW .100Y.C M.TW W .100
Y .TW
W O MCPU W C O W W .C OM
WW Total 0Y.C Time W WW .100Y. M.T
W W .100
Y .TW
W .10Execution O M.T W C O W W .C OM
W Y.C W WW .100Y. M.T
W W .100
Y .TW
WRegister W 100
.Operands M.T
Fetch
O W C O W W .C OM
W W .100
Y
W O W C O W W
WW .100Y.
ALUW Operation Execute
Y.C W M.T
W W
W
W .100 O M.T W C O
WW Result Write .C
YBack W WW .100Y. M.T
W
W .100 O M.T W C O
W O W
WW .100Y.C M.TW WW
W O
WW .100Y.C M.TW
W O
WW .100Y.C 12
W W
7799D–AVR–11/10 W
.C OM
00Y .TW
W W.1 Y.COM W
W 00 .T
6.8 Reset and Interrupt HandlingW W W.1 Y.COM W
The AVR provides
.T
OM several different
W
W .100 sources.
interrupt
.T
OM These interrupts and the separate Reset
.C W .C TW
Vector . 1
Y have.TaW
00each M separate
W
program . 00Y in the
1vector M .program memory space. All interrupts are
W C O W W .C O
W Y . W W 0 Y .T W
0be written logic one together with the Global Interrupt
W assigned 00individual .T
enable bits which must
W.1 Y.COM W
W W.1 bit Y .C OM
W Worder
W W Enable
.100
in the Status
M.T
Register W in 00enableM
to the.T interrupt. Depending on the Program
O M.T Counter W value, .C O
interrupts may be W W.1 Ydisabled
automatically .C O when
W Boot Lock bits BLB02 or BLB12
00Y
.C .TW WW .100Y M .TW W . 100 M .T
.1 M are programmed. OThis feature improves Wsoftware O
security. See the section “Memory Program-
W O WW 00Y.C WW .100Y.C M.TW
WW .100Y.C M.TW W 1 .T
Mdetails.
W
ming” on W.page 246Ofor W O
W
WW .100Y.C M.TW
O
O in the program memory W space are O by default defined as the Reset and
W O The lowest WW addresses Y.C WW .100Y.C M.TW
WW .100Y.C M.TW W 1 0 0 M .T W
O Interrupt Vectors.W. TheOcomplete list of vectors Wis shown Oin “Interrupts” on page 64. The list also
0Y.CTheMlower
W
WW .100Y.C M.TW determines WW the 0 0 Y.C levels
priority .T W of the differentWW interrupts. . 1 0 .TW the address the higher is the
W . 1 O M W O
W O Y.C the.Thighest WWand.1next .C W
WW .100Y.C M.TW priorityW
W RESET
level.
. 100 has M
W priority, 00Yis INT0 M.–T the External Interrupt Request
O W O W O
.C Flash
W
WW .100Y.C M.TW WW Vectors
0. The Interrupt
00Y
.C can be .Tmoved
W to the WW start of the
.100
YBoot
M.T
Wsection by setting the IVSEL
W . 1 O M W C O
W O bit in the MCU Control Register (MCUCR). Refer
WW .100Y.C M.TW WW to “Interrupts” Y. on page W 64 for more information.
WW .100Y.C M.TWThe Reset Vector can also be moved to the start W
of 100Boot Flash
.the O M.Tsection by programming the
W O C
W
WW .100Y.C M.TW
O W Y.C .TW Won W 0Y.
.10246. M.T
W
BOOTRSTW Fuse,Wsee . 100“Memory O M Programming” page
W C O
W O
WW .100Y.C M.TWhen W WW .100Y.C M.TW WW .100Y. W
M.Tand all interrupts are dis-
an interrupt W occurs, the O Global Interrupt Enable W I-bit is O
cleared
C
W O
WW .100Y.C M.abled. TW The user WWsoftware Y.C W WW .to 0Y.
10enable
W
M.T interrupts. All enabled
W . 100 can write O M .T
logic one to the I-bit W C Onested
W O Y.C W . .TW
WW .100Y.C Minterrupts .TW can W then W interrupt
. 100 theOcurrent M .TW interruptW routine..1The 00YI-bit isMautomatically set when a
W O W C W W .C O
C W . .TW Y W
WW .100Y. Return
M.T
W from Interrupt W instruction .100
Y – RETI – is executed. W 00
W.1 Y.COM W
.T
W C O W W .C OM W
WW .100Y. There M.T
Ware basically W two types Y
.100 of interrupts. .TW The firstWtype W is.1 00
triggered Oby
T event that sets the
M.an
W O W C OM W .C
C
WW .100Y. Interrupt .TWFlag. ForW
W
these interrupts, .
Y the Program .TW Counter W is vectored Y
.100 toOthe TW Interrupt Vec-
M.actual
M W . 100 O M W C
W O in order to executeWthe interrupt
tor 0Y.C handling routine,W and W hardware Y. clears.T theW corresponding
WW .100Y.C M.TW W .10can M .TW W .100 one to O M
Interrupt Flag. Interrupt W
Flags also O be cleared by writing a logic C the flag bit position(s)
W
WW .100Y.to CO
.T W If an interrupt WW .1condition 0 0Y.C occurs .TW while the WW .100Y. M .TW
be
OM cleared. M corresponding
WW 00Y.CO .TWenable bit is
interrupt
W W Y .C W W WW 00Y.CO .TW W
W 00 cleared, .T Interrupt Flag will
the be
.1 set andOremembered M until the W .1
interrupt OM
is enabled, or the flag is
W W.1 cleared
Y .C OMby software. Similarly,
W WWif one 0 Y .Cmore interrupt
or W W
conditions
W occur 00 Y.C the .Global
while T W Interrupt
W .T
W 00
W.1 Enable M.T .10 M W.1 Y.COM W
.C Obit is cleared, WW 00Y.CO
theWcorresponding Interrupt W Flag(s) will Wbe set and remembered until the
W W
. 1 0 Y
0Global M .T W
W . 1 will then O M .T W
W .100 O M.T
W O
Interrupt Enable bit is set, and be executed by order
WW .100Y of .C
priority.
W
O W O W .C O
W
WW The .C
second typeWof interrupts WWwill trigger Y.Cas long.Tas W the interrupt WW condition .100
Y is present.
M.T
W These
. 1 00Y M .T W . 100 O M W C O
W interrupts O
do not necessarily have Interrupt Flags. If the interrupt condition
WW .100Y .
disappears
.TW the
before
WW interrupt 0 0 Y.C .T W WW .100Y.C M.TW M
W. 1 OM
is enabled, the interrupt will Wnot be triggered. O W O
W theYAVR
When .CO exits from an interrupt, WW it will .CO return
always
Y W to the main W
W
Wprogram 0 Y .COexecute
and
.TWone
WWmore.1instruction
0 0 .T W W . 1 0 0 M .T
W . 1 0
O M
W OM before any pending interrupt W is served.
O
WW .100Y.C M.TW
O anWinterrupt O
WWthat0the
Note
Y.C
O Register is not automatically
Status
W W WW 00Y.Cstored .T
when
W entering W W
1 0 0 Y.Croutine,.TnorW
W restored
0
.1when returning T
M. from an interrupt .1
routine. This Mmust be handled by W .
software. O M
W O W O W .C
Y
M.T
W
W O W O W W .C O
WW .100Y.C M.TW
When using the CLI instruction to disable interrupts, the interrupts will be immediately Y disabled..TW
WW .10will
No interrupt
0Y.C be O M.T
executed
W
after the CLI instruction,
W
W .100 OMthe
W W C Oeven if it occurs simultaneously
W .Cwith
W W .100
Y .TW
W O W C O W W .C OM
W W .100
Y .TW
W O W C O W W .C OM
W W .100
Y
W O W C O W W
W W
W O W C O
W
W O W C O
W O W
WW .100Y.C M.TW WW
W O
WW .100Y.C M.TW
W O
WW .100Y.C 13
W W
7799D–AVR–11/10 W
.C OM
00Y .TW
W W.1 Y.COM W
W 00 .T
CLI instruction. The following example W W.1 shows . C OM this can be used to avoid interrupts during the
how
timed EEPROM M TW sequence..
.write W . 100
Y
M .TW
W O
. 1 00Y Code M W O
Assembly
W O Example
Win r16, OSREG W
WW .value .CO .TW
WW .100Y.C M.TW
; store SREG
.T W 1 00Y M
.C OM W W cli
Y . O
;Cdisable
W
interruptsWduring
W
W
0 Y .CO sequence
timed
W
.100 Y
M .TW W sbi.1EECR, 0 0 M
EEMPE .T ; start EEPROM W . 1write OM.T
0
W O
W
WW .100Y.C M.TW
O
WWsbi .EECR, .C
00Y EEPEM.TW WW .100Y.C M.TW
1
W O W C
Y.r16
O WW 00Y.CO .TW
WW .100Y.C M.TW WW out SREG,. 1 0 0 M .T ; Wrestore W SREG .1
value (I-bit)M
W W .C O
W 00 Y .T W
C Code Example .1 M .1 M
W 00 .T W .1 M .1 M
char W cSREG;
W W W 0 Y .CO .TW W
W 00 .T 0
W 1 Y.COM W
cSREG = .SREG; /* store SREG value */ .1 M
W 0 T
M. during timedWsequence
W 00 .T .10interrupts W.1 Y.COM W
/* disable */
W W.1 Y.COM W WW 00Y.CO .TW W 0 0 .T
W
__disable_interrupt();
W
W .100 O M.T W .1
. C O M W W.1 Y.COM W
C W W
WW .100Y. M.T
W EECRW|= (1<<EEMPE); .100
Y /*.Tstart EEPROM W write 00*/
W.1 Y.COM W
.T
W C O EECR |= W W
(1<<EEPE); .C OM W
WW .100Y. M.T
W W .10/* 0Y .TW W 00
W.1 */ OM
.T
W C O SREG = cSREG; W W .C OM SREG value (I-bit)
restore W Y .C W
WW .100Y. M .TW W . 100
Y
M .TW W
W .100 O M.T
O W O .C
W
WW .100Y.C MWhen .TW using the WW Y.C to enable .TW interrupts, WW the.1instruction
00Y .TW
W . 100
SEI instruction
O M W C O Mfollowing SEI will be exe-
W C O cuted before any W
pending .C
interrupts, as shown in this Wexample. Y . W
WW .100Y. M.T
W W .100
Y .TW W 00
W.1 Y.COM W
.T
W C O W W .C OM W
WW .100Y. M.T
W W .100
Y .TW W 00
W.1 Y.COM W
.T
W CO W W .C OM W
WW .100Y. M.T
W W .100
Y .TW W 00
W.1 Y.COM W
.T
W C O W W .C OM W
WW .100Y. M.T
W W .100
Y .TW W 00
W.1 Y.COM W
.T
W C O W W .C OM W
WW .100Y. M.T
W W .100
Y .TW W 00
W.1 Y.COM W
.T
W C O W W .C OM W
WW .100Y. M.T
W W 00Y .TW W 00
W.1 Y.COM W
.T
W .C O W W.1 Y.COM W W
WW .100Y W W 00 .T W 00 .T
W O M.T W.1 Y.COM W W W.1 Y.COM W
.C W W 00 .T
WW .100Y M.T
W W 00 .T W.1 Y.COM W
WW .100Y W W 00 .T W 00 .T
.C W W 00 .T
WW .100Y M.T
W .C O W W.1 Y.COM W W 0
WW .100Y W W 00 .T W 0 .T
.C W W 0 .T
WW .100Y M.T
W W 00 .T 0
W.1 Y.COM W
WW .100Y .TW W .10 M.T
M
W
W . 100 O M .T W C O
W O W .
Y
M.T
W
W O W O W W .C O
Y
M.T
W
W O W O W W .C O
Y
M.T
W
W O W O W W .C O
Y .TW
W O W C O W W .C OM
W W .100
Y .TW
W O W C O W W .C OM
W W .100
Y .TW
W O W C O W W .C OM
W W .100
Y
W O W CO W W
W W
W O W C O
W
W O W CO
W O W
WW .100Y.C M.TW WW
W O
WW .100Y.C M.TW
W O
WW .100Y.C 14
W W
7799D–AVR–11/10 W
.C OM
00Y .TW
W W.1 Y.COM W
W 00 .T
W W.1 Y.COM W
Assembly Code.TExample W W 00 .T
.C OM W W.1 Y.COM W
seiY ; set.T W
Global W
Interrupt 00
Enable .T
W .100 O M W W.1for interrupt
.C OM
WW .100Y .C Y .TW
sleep; enter
M .TW sleep, waiting
W
W . 100 O M
O
W; note: will enter sleep W Y.Cpending
WW .100Y.C M.TW W before .TW
any
M .TW W . 100 O M
W O
; interrupt(s)
00Y WW .100Y.C M.TW
.1 M W Example O W O
W O
WW .100Y.C M.TW
C Code
W O W O
W O
WW Y.C WWGlobal Y.C .TW
WW .100Y.C M.TW
__enable_interrupt(); W /* set 0Interrupt Enable */
. 1 0 0 M .T . 1 0 M
O W O W C O
.interrupt
W
__sleep(); /* enter sleep, waiting
WW .1for 00Y TW */
M.interrupt(s)
W O W O
WW .100Y.C M.TW
W O /* note: will enter sleep before any pending */
W O W O
WW 00Y
W6.8.1 .CO .T
Interrupt W
Response WW .100Y.C M.TW
Time
WW .100Y.C M.TW
W.1 OM W O
Y.Cresponse WW 00Y.CO .TW
WW .100Y.C M.TW The interrupt WW execution . 1 0 0 M .T Wfor all theW enabled .1AVR interruptsM is five clock cycles minimum.
W .C O WWcycles Y .CO W W WWfor the 0 Y .CO interruptW handling routine is exe-
W W
. 1 00 Y
M .TW After five Wclock
W . 10 0 the program
O M .T vector address
W .1 0 actual
O M.T
W O cuted. During C cycle
.clock WW Y. C W
WW .100Y.C M.TW WWthese.1five 00Y M .TW
period, the Program00Counter
.1this jump
is pushed
M.T
onto the Stack. The
vector is normally W a jump to O the interrupt routine, W
and C O takes three clock cycles. If an
W O
WW .100Y.C M.Tinterrupt W W W 0 0 Y.C .T W WW .100Y. M .TW
occurs during . 1 M
execution of a multi-cycle instruction, W thisOinstruction is completed before
W O WW 00Y.CO .TW WW Y.C W
WW .100Y.C M.the TWinterrupt is Wserved. . 1 If an interrupt M occurs when theW .
MCU 100 is in sleep
O M.Tmode, the interrupt exe-
O W O Y. C
W
WW .100Y.C Mcution .TW response WW 0Y.C Mby
time is10increased .TWfive clock cycles. WW This .100increase TW in addition to the
M.comes
W . O W C O
W O
WW .100Y.C start-up .TW
time from WW the selected Y.Csleep mode.
.TW WW .100Y. M.T
W
M W . 100 O M W C O
W O
WW .handling Y.C routine W Y. .TW five clock cycles,
WW .100Y.C AM .TW from an interrupt
return 100 M .TWtakes fiveW .100 During
clock cycles.
W O Mthese
O W O .C
W
WW .100Y.C theMProgram .TW
Counter WW(three Y.C is popped
bytes) .TW back from WW the .1Stack,
00Y the M .TW Pointer is incre-
Stack
W . 100 O M W CO
W
WW .100Y.C M.TW
O
mented by three, and W the I-bit inYSREG .C is.T set.
W WW .100Y. M.T
W
W
W .100 O M W C O
W
WW .100Y.C M.TW
O
W
W O W C O
W
WW .100Y.C M.TW
O
W
O W O W .C O
W
W
O W O W .C O
W
W
O W O W .C O
W
W
O W O W .C O
W
W
O W O W .C O
W
W
O W O W .C O
W
W
O W O W .C O
W
W
W O W O W W .C O
Y
M.T
W
W O W O W W .C O
Y
M.T
W
W O W O W W .C O
Y
M.T
W
W O W O W W .C O
Y .TW
W O W C O W W .C OM
W W .100
Y .TW
W O W C O W W .C OM
W W .100
Y .TW
W O W C O W W .C OM
W W .100
Y
W O W C O W W
W W
W O W C O
W
W O W C O
W O W
WW .100Y.C M.TW WW
W O
WW .100Y.C M.TW
W O
WW .100Y.C 15
W W
7799D–AVR–11/10 W
.C OM
00Y .TW
W W.1 Y.COM W
W 00 .T
7. AVR Memories W W.1 Y.COM W
W W .100 M.T
This section M.T
Odescribes the different
W W memories .C O
in the T ATmega8U2/16U2/32U2. The AVR archi-
.C 00Y . W
.
tecture1
Y
00has two M .TW memoryW
main spaces,W . 1the Data O M
Memory and the Program Memory space. In
W O
WW 0 0 Y.CATmega8U2/16U2/32U2
.T W WW features . 1 0 0Y.Can EEPROM M .TW Memory for data storage. All three
addition,
. 1 the OM W O
W WW 0spaces
Wmemory 0 Y.C are .linear TW and regular. WW .100Y.C M.TW
.T 1 OM
OM W. W O
0 Y.C .T W WW .100Y.C M.TW WW .100Y.C M.TW
0
W.1 Y.CIn-System
OM W O WW 00Y.CO .TW
WW 7.1 0 T WW .100Y.C Flash
W Reprogrammable .T WProgram WMemory .1
0
W.1 Y.COM W
. M WW 00Y.C OM
W TheW WW 00Y.CO .TW contains
ATmega8U2/16U2/32U2 W 8K/16K/32K
1 .TW In-System Reprogrammable
bytes On-chip
W .1 00 M .T W . 1 O M W . O M
W O Flash W memory for.C program storage. SinceWall AVR0instructions Y.C .TW
are 16 or 32 bits wide, the Flash
WW .100Y.C M.TW is
W
organized . 00Y
1as 4K x M
16,
TW
.8K x 16. For
W
software W .10security,OM the Flash Program memory space is
W O W O W .C
WW .100Y.C M.TW divided WW into two 0 0 Y.C
sections, .T
Boot
WProgram W section . 1
and 0 0Y ApplicationM .TW Program section.
. 1 M
W W . C O
Y W
W 00 .T
W.1 Y.COM W The Flash .1
memory hasMan endurance W of W at.1least.C100,000 OM
W W WW 00Y.CO .TW W 0 0 Y . Wwrite/erase cycles. The
Twide,
W 00 .T ATmega8U2/16U2/32U2 1 MProgram Counter (PC). 1 is 16 M
bits thus addressing the
W.1 Y.COM W W.
Wprogram Y .CO locations. W WW 00Y.CO .TW
W 8K/16K/32K W 0 memory T The W operation of Boot Program section and associated
W
W .100 O M.T W .10 O M. W W.1 Y.COM W
C W .C
WW .100Y. WBoot Lock W
M.T 246. “MemoryW
bits for software
.100
Y protection .TW are described W in detail
00 in “Memory
Wa.1detailed M.T Programming” on page
W C O W
Programming” .C OMon page 246 contains W Y .C Odescription
W on Flash data serial
WW .100Y. M
W
.Tdownloading W .
Y
100SPI pins M .TW W
W .100 O M.T
using W the O or the debugWIRE interface. C
W
WW .100Y.C M.TW
O
W
W O W C O
W O Constant tables can
WW be.1allocated .C within the entire W W
program Y. address
memory W space (see the LPM
WW .100Y.C M–.T W 00Y M .TW W .100- ExtendedO M.TLoad Program Memory
Load Program MemoryW O
instruction description and ELPM C
W O
WW .100Y.C instruction .TW WW .100Y.C M.TW WW .100Y. M.T
W
M description). W O W C O
W
WW .100Y.C M.TW
O
W
Timing diagrams for W
instruction O
fetch and execution are W
presented inC O
“Instruction Execution Tim-
W
WW .100Y.C ing”Mon
O
.TW WW .100Y.C M.TW WW .100Y. M .TW
page 12. W O W O
W
WW .100Y.C M.TW
O
W O W O
W
WW .100Y.C M.TW
O
W O W O
W
WW .100Y.C M.TW
O
W O W O
W
WW .100Y.C M.TW
O
W O W O
W
WW .100Y.C M.TW
O
W O W O
W
WW .100Y.C M.TW
O
W W .C O
Y W
W
W .100 O M.T W.1 Y.COM W W W.1 Y.COM W
.C W
WW .100Y M .TW W
W . 100 O M .T W
W .100 OM
.T
W .C O W Y .C W W W 0 Y .C W
WW .100Y M .TW W
W .100 O M .T W .10 O M.T
W O WW .100Y .C
W
W O W O W W .C O
Y
M.T
W
W O W O W W .C O
Y
M.T
W
W O W O W W .C O
Y
M.T
W
W O W O W W .C O
Y .TW
W O W C O W W .C OM
W W .100
Y .TW
W O W C O W W .C OM
W W .100
Y .TW
W O W C O W W .C OM
W W .100
Y
W O W C O W W
W W
W O W C O
W
W O W C O
W O W
WW .100Y.C M.TW WW
W O
WW .100Y.C M.TW
W O
WW .100Y.C 16
W W
7799D–AVR–11/10 W
.C OM
00Y .TW
W W.1 Y.COM W
W 00 .T
Figure 7-1. Program MemoryW W.1 Y.COM W
Map
.TW W .100 OM
.T
C OM Program W WMemory .C
1 00Y
.
M .TW W . 100
Y
M .TW
W . O W O
WW .100Y.C M.TW WW .100Y.C M.TW0x00000
W O W O
OM W O W O
0 O
W.1 OM W O W
WW .100Y.C M.TW
W O W O
W
WW .100Y.C M.TW
O
W O W O Application FlashW W
W Section .CO .TW
W W .C O
W 00 Y .T W .1 M .1 M
W 00 .T W .1 M .1 M
W 00 .T W .1 M .1 M
W 00 .T W .1 M .1 M
W 00 .T W .1 M .1 M
W 00 .T W .1 M .1 M
W 00 .T W .1 M .1 M
W 00 .T W .1 M .1 M
W 00 .T W .1 M .1 M
W 00 .T W .1 M .1 M
W 00 .T W .1 M .1 M
W
W 00
W.1 Y.COM W
.T Boot
.1 Flash Section M W.1 Y.COM W
0x7FFF 0
0(32KBytes) .T
W
W .100 O M.T W .1
.C OM 0x3FFF
W W.1 (16KBytes)
Y .C OM
W
C W .TW
WW .100Y. M .TW W .100
Y
M
W
0x1FFF W
00
.1(8KBytes) O M.T
O W O .C
W
W
W O W .C O
WWMemory .CO .TW WW .100Y.C M.TW WW .100Y M.T
W
7.2 SRAM W Data . 1 00Y M W O W .C O
W
WW .Figure .CO shows .TW how the W
W Y.C .TWSRAM Memory WW is.1organized.
00Y M.T
W
1 00Y 7-2 M W 100
ATmega8U2/16U2/32U2
. O M W C O
W O Y.C microcontroller WW peripheral Y . W
WW The Y.C .TW
00ATmega8U2/16U2/32U2 WW . 100
is aWcomplex M .TW with more .100 M.T than can
units
. 1 O M O W .C O
W
WW be.1supported .C within .TW the 64 location WW reserved Y.C in the.T W WW 0Y instructions.
.10OUT M.T
W For
00Y M W . 100 O M Opcode for the IN and
W C O
W O
.C I/O.Tspace W - $0FF C SRAM,
Y.in WW .100Yand LD/LDS/LDD . W
WW the .Extended
1 00Y M
W from W $060
.100 M .TW only the ST/STS/STD
W O M.T
O W O .C
W
instructions
WW .100Y.C M.TW
can be used.
W
O W O W W .C O
WTheWWfirst00768 Y.CData Memory .TW WW address
locations
100
C Register
Y.the .TW File, theWI/O Memory, Y
.100 Extended M.T I/O
W
. 1 O M
W and the internal data SRAM. W . O M W W .C O
Memory,
WW The.1first C locations
.32 W addressWthe Register Y file, the.T next
W
WW .100Y.C M.TW 00Y M.Tof Extended I/OWmemory, W .100 andOthe M 512
64 location
W the Cstandard
O I/O Memory,W thenW 160 locations O .C
WW .1of00internal Y. .TW Y.C W W 0Y
.10memory M.T
W
locations
W O data
M
W
SRAM.The five different W .100 addressing O M.T modes for the W data
W .C O cover:
WW Indirect Y.C W WW Indirect Y.C .TW Wand Indirect Y
.100 withOPost- M.T
W
Direct,
W .100 withODisplacement,
M.T Indirect,
W .100 with O MPre-decrement,
W W .C
Y.CRegister WWR26.1to C
. feature W Y .TW
WW .In
increment.
100
the
M .TWfile, registers W
00Y R31
O
W
M.T the indirect addressing W .100 pointer OM
W O C W .C
WW .100Y.C M.TW
registers. WW .100Y. M.T
W W .100
Y .TW
W O W C O W W .C OM
WW addressing Y.C reaches Wthe entireW W space. Y. W W .100
Y
The direct
W .100 O M.T
data
W .100 O M.T W W
WW63 address Y. C
The Indirect WW with 0Y.C M.TW
.10Displacement mode reaches .100 locations
W W
M.T from the base address given
W O W C O
by the Y-WorWZ-register. Y.C W WW .100Y. M.T
W
W .100 O M.T W .C O
WW Y.C addressing W WWwith.1automatic00Y
When using register
W .100indirect O M.T modes
W W pre-decrement and post-incre-
W . C W Z are decremented
ment, the address W 00Y X, Y,.Tand
registers W or incremented.
W W.1 Y.COM W
W 00 .T
W W.1 Y.COM
W 00
W W.1 17
7799D–AVR–11/10 W
. C OM
00Y .TW
W W.1 Y.COM W
W 00 T
M.registers,
The 32 general purpose workingWregisters, W.1 Y64 . C OI/O and the 512/512/1024bytes of inter-
nal data SRAM .
inT W
the
W
ATmega8U2/16U2/32U2 . 1 0 0 M
are .TallWaccessible through all these addressing
OM W O
modes. 0 0 Y.C Register
The .T WW in
WFile is described . 1 0 0Y.C M
“General .TW Register File” on page 10.
Purpose
W . 1 O M W O
W 7-2. Data Memory Map WW
Figure O .CO .TW
.T W WW .100Y.C M.TW W . 1 00Y M
.COM
W W W Y.C O
W W WW 00Y.CO .TW
00 Y .T W .10 0 M.TData Memory WW.1
W.1 Y.COM W OM
W W WW 00Y.CO .TW W 0 0 Y.C
1$0000 - $001F .TW
W .100 M .T W . 1 O M 32 Registers W . O M
W O
WW .100Y.C M WW $0020 Y.C .TW
WW .100Y.C M.TW 64.TI/OW Registers
W . 100 - $005F O M
O W O Y.C
W
WW .100Y.C M.TW WW .100Y.C 160 W I/O Reg.WW $0060
.TExt .100 - $00FF M.T
W
W O M W O
W O
WW .100Y.C M.TW WW $0100 Y.C W
WW .100Y.C M.TW W .100 O M.T
O W O Y.C
W
WW .100Y.C M.TW WW .100Y.C Internal .TW SRAM WW .100 M.T
W
W O M W O
W O
WW .100Y.C M.TW
(512/512/1024 x 8) WW Y.C W
WW .100Y.C M.TW W .100 O M.T
W O C
W
WW .100Y.C M.TW
O
W
W O W
$2FF/$2FF/$4FF C O (8U2/16U2/32U2)
W
WW .100Y.C M.TW
O
W
W O W C O
W
WW .100Y.C M.TW
O
W
W O W C O
W
7.2.1W Data. 1 MemoryM Access Times W O W C O
W O
WW .1the .C WW Y. W
WW .100Y.C MThis .TWsection describes 00Ygeneral M .T W
access timing concepts
W .100 for internal
O M.T memory access. The
W O W O W .C
WW .100Y.C internal .TW data SRAM WWaccess Y.C .TWin two clkW .10as0Ydescribed W
M.T in Figure 7-3.
M W .100is performed
O M CPU cycles
W C O
W
WW .100Y.C M.TW
O
W
W O W C O
W OFigure 7-3. On-chip Data SRAM Access Cycles WW
WW .100Y.C M.TW Y. W
WW .100Y.C M.TW W .100 O M.T
W O W CO T2 WW C
Y. T3 W
WW .100Y.C M.TW WW .100Y.T1 M .TW .100 M.T
W O W CO
W
WW .100Y.C M.TW
O
W
W O W C O
W O
WW .100Y.C M.TW clkCPU W
W Y.C .TW WW .100Y. M.T
W
W .100 O M W C O
W O Y.C WW .100Y . W
WW .100Y.C M.TAddress W WWCompute .
W
100AddressOM.T Address valid M.T
O W W .C O
W
W
O Data W O W .C O
W
W
Write
O W O W .C O
W
WW .100Y.C M.TW WR WW .100Y.C M.TW WW .100Y M.T
W
O W O W .C O
W
WW .100Y.C M.Data TW WW .100Y.C M.TW WW .100Y M.T
W
O W O W .C O
W
WW .100Y.C M.TW WW .100Y.C M.TW WW .100Y Read M.T
W
O W O W .C O
W
WW .100Y.C MRD .TW WW .100Y.C M.TW WW .100Y M.T
W
W O W O W W .C O
Y
M.T
W
W O W O W W .C O
Y
M.T
W
W O W O W W .C O
WW .100Y.C M.TW WW Access
Memory Y.C
Instruction W Next Instruction
W .100
Y
M.T
W
W O W .100 O M.T W W .C O
Y .TW
W O W C O W W .C OM
W W .100
Y .TW
7.3 EEPROM Data Memory W O W C O W W .C OM
WW .100Y.C M.TW WW .100Y. .TW W Y
.100It is orga- .TW
The ATmega8U2/16U2/32U2
W O contains 512/512/1024 W bytes
C O Mof data EEPROM memory.
W W .C OM
Y.C W . W 0Y
nized W
W
.100 data
as a separate .TW in which
Mspace,
Wsingle 00Y can M
.1bytes be.T
W
read and written. The W .10EEPROM
W O W C O W
W Y.C TW WW cycles. Y. W W
has an W endurance
W .100of at leastO M.100,000 write/erase
W .100 TheOaccess M.T between the EEPROM and
Yin.Cthe following, WW the.1EEPROM .C W Registers, the EEPROM
the CPUW isW described
. 100 M .TW specifying 00Y Address
M.T
W O W C O
Data Register,
WW .100Y.C M.TW
and the EEPROM Control Register. WW .100Y.
W O W
WW .100Y.C M.TW WW
W O
WW .100Y.C M.TW
W O
WW .100Y.C 18
W W
7799D–AVR–11/10 W
.C OM
00Y .TW
W W.1 Y.COM W
W 00 M.TParallel data downloading to the EEPROM,
For a detailed description of SPI, W W.1 Y.COand
debugWIRE
see page 259, M .TW244, andW
page page 250 . 0
10respectively. M .TW
W O
. 1 00Y M W O
W O
7.3.1 WW .1Access
EEPROM Read/Write
00Y
.C .T W WW .100Y.C M.TW
WWEEPROM OM W inOthe I/O
.T W WThe 0 0 Y.C Access .T Registers are
W WWaccessible . 1 0 0Y.C M .TW space.
M . 1
W access O M W O
.CO .TW Wwrite .C Wthe EEPROM WW is given Y.C W on page 22. A self-timing function,
.100Y M
WThe
. 1 00Y time M .Tfor W . 100 in Table O M .T7-2
O W O .C byte.Tcan
W
WW .100Y.C M.TW
however,
WW .lets 00Y
.C user .software
the
TW detect WW when the
. 100
Ynext
M
W be written. If the user code con-
1 O M W O
W O tains WW 00Y.C
instructions that write the EEPROM, some
WW .100Y.C M.TW
precautions must be taken. In heavily filtered
WW .100Y.C M.TW W 1 .T W
VCCOisMlikely to rise or fall slowly
W O power supplies, W. Y.C to run.TatWa voltageW WW 0on power-up/down.
Y.C
O This causes the device for
WW .100Y.C M.TW some WW period.1of 00time lower than
. 1 0specified M .TW
as minimum for the clock frequency
M WW .COfor details
W W Y.C O
W used. W See WW “Preventing 0 Y .COEEPROM T W Corruption” W on page0 0 Y 19. .T W on how to avoid problems in
W
W .100 O M.T W .10 O M. W W.1 Y.COM W
W . C
WW .100Y.C M.TW
these situations. Y W W 00 .T
W O
W
W .C
WW .100Y.C M.TW In orderW to prevent Y
.100unintentional
W
M.T EEPROM writes,
W 0
a 0specific
W.1 Y.COM W
write.T procedure must be followed.
W C O Refer to the W W
description .CofOthe EEPROM Control W Register for details on this.
WW .100Y. M .TW W . 100
Y
M .TW W
W .100 O M.T
W O W O
.C the .CPU W .C
WW .100Y.C M.TW When the EEPROM WW .10is0Y read, TW is haltedWfor four.1clock 00Y cycles TW the next instruction is
M.before
O W O M W C O
. two clock
W
WW .100Y.C M.Texecuted. W WW the.1EEPROM
When
00Y
.C is .written,TW the CPU WWis halted .100
Yfor
M.T
W cycles before the next
W O M W C O
W
WW .100Y.C M.TW
O instruction is executed.
W
W O W C O
W
7.3.2 WWPreventing
.CO .TW Corruption WW .100Y.C M.TW WW .100Y. M.T
W
. 1 00Y EEPROM
M W O W C O
W O
of W Y.C W Y. W
WW .100Y.C During M .TW periods W low V.CC, 100the EEPROM M .TWdata canWbe corrupted W .100 because O M.T the supply voltage is
O low for the CPUWand the Y W O .C
W
WW .100Y.C too .TW
.C
EEPROM Woperate properly.
.Tto WW .1These 00Y issues W
M.Tare the same as for
M
W
W . 100 O M W C O
W Oboard level systems W
Wusing .EEPROM, Y.C and the same design WW solutions Y. should.Tbe Wapplied.
WW .100Y.C M.TW 100 M .TW W .100 O M
O W O C
Y. voltage
W
WW .100Y.CAn EEPROM .TW data corruption WW .1can .C
00Y be caused .TWby two situations WW when .100 the O
W
M.T is too low. First,
M W O M W C
W O
a regular write sequence WWto the Y.C
EEPROM requires a minimumWW voltage Y. to operate Wcorrectly. Sec-
WW .100Y.C M.TW . 100 instructions M .TW W .100 voltage O M.T
ondly, the CPU itself can W
execute O incorrectly, if the supply C is too low.
W
WW .100Y.C M.TW
O
W EEPROM O data corruption W W .CO WW CO
WdesignY.recommendation: W
WW .100Y.C M.TW W can easily .1 00Y
be avoided
M .TW
by following this
. 1 00 M.T
O AVR RESET active W O W .C O
W
WW .10Keep0Y.Cthe M WW (low) 0Y.C periods .TWof insufficient WW power Y
.100supplyOvoltage.
W
M.T This can
.TW W . 10during O M W C
W be doneOby enabling the internal Y.C Detector W detection . W internal
WW .100Y.C M.TW WW Brown-out .100 M .TW (BOD). W If the
.100
Y level of.Tthe
M
BOD does O not match the needed W detection O
level, an external low V W reset C O
Protection
. circuit can
W
WW be 0 Y.C If a reset .T W WWa write 0 Y.C
0operation .TW WWCC .100Y M .TW
1 0
used. occurs while . 1 M is in progress, the write operation O will be com-
W W. .C OM
W WW 00Y.CO .TW W WW 00Y.C .T W
W pleted 0 Y
0 provided .that W
T the power supply.1voltage is Msufficient. . 1 M
WW.1 Y.COM W WW 00Y.CO .TW W WW 00Y.CO .TW
W 0 W 1
.10 M.T W.1 OM W. OM
7.4 I/O MemoryWWW 00Y.CO .TW WW .100Y.C M.TW WW .100Y.C M.TW
.1
WWI/O0space OM WW 00Y.CO .TWis shownWinW“Register
W CO
Y.Summary” W
WThe 0 Y.C definition . T W of the ATmega8U2/16U2/32U2
W . 1 M . 1 0 0 M.T on
W288.. 1 O M W O W W .C O
page
Y
M.T
W
W O W O W W .C O
WW
All ATmega8U2/16U2/32U2 .C .TW I/Os and WW peripherals Y.Care placed W in the I/O Wspace..1All 00Y M.T
I/O locations W
W . 1 00Y
O M W .100 O M.T W W . C O
mayW be accessed Y.C by the.TLD/LDS/LDDW WW and ST/STS/STD
.10the0Y.C Minstructions, .TW
transferring
W data
Y between
.100the address .TW
W
the 32 general W .100 purpose O M working registers Wand I/O
C O space. I/O Registers W W
within .C OM
WW 0Y.CareM .TW bit-accessible WW using Y. TWCBI instructions. W 0Y
10these .TW
range 0x00 W .1- 00x1F O directly W .100 the SBI O M.and W W .In
.C OM
regis-
Y.C bits WW by.1using .C W Y W
ters,W the Wvalue0of
.1 0 single
W
M.T can be checked W
00Y the SBIS
O M.T and SBIC instructions.
W
W .100 Refer OMto .T
W O Y. C W .C
0Y OUT,
WW .1set
the instruction 00Y
.C
section W details.
for more WW When 1using
. 00 theOI/O M.T
W
specific W
commands IN.10and
W O M.T W .C W W
the I/O addresses
WW .1000x00 Y.C - 0x3F .TW
must be used. WW When 00Y addressing W I/O Registers W as data space
Md.Tt o t h e s e a d d r e s s e s . T h e
u s i n g L DWaW n d S T i.C n sOtM ructions, 0x20 W mu Ws.1t b e Ya.CdO de W
W
ATmega8U2/16U2/32U2 .100
Y
isM TW
a .complex
W
microcontroller .100 with more O M.Tperipheral units than can be
W O W . C
W Y.C W WW .10for 0Ythe
supportedWwithin the
W .10064 location O M.T reserved in Opcode W IN and OUT instructions. For the
WW .100Y.C M.TW WW
W O
WW .100Y.C M.TW
W O
WW .100Y.C 19
W W
7799D–AVR–11/10 W
.C OM
00Y .TW
W W.1 Y.COM W
Extended I/O space from 0x60W-W
W .100 in SRAM,
0x1FF
.T
OM only the ST/STS/STD and LD/LDS/LDD
.C
instructions can M .TW
be used.
W . 100
Y
M .TW
W O
. 1 00Y M O bits should be written to zero if accessed.
ForW compatibility
.C O with future WW reserved
devices,
0Y.Cbe written. .TW
WW Reserved . 1 0 0 YI/O memoryM .T W
addresses
Wshould . 10
never M
W O W O
.TW WW .100Y.C M.TW WW .100Y.C M.TW
M Some of the StatusO Flags are cleared W writing
by aOlogical one to them. Note that, unlike most
Y.C
O
W W WW 00Y.C .T W WW will 1 0 0Y.C M.TW
00 .T other AVRs, 1 the CBI M and SBI instructions . only operate on the specified bit, and can therefore
W.1 Y.COM W W W. Y .CO W WW 00Y.CO .TW
W W
be used on 0
0registersM .T
containing W
such Status .Flags. 1 TheM CBI and SBI instructions work with reg-
W 00 .T W.1 to 0x1F
W W.1 Y.COM W isters W0x00 Y .COonly..TW W WW 00Y.CO .TW
W 00 .T W 0 0 .1 M
W W
The I/O and .peripherals 0 .T W
W 00
W.1 Y.COM W
.T 10 Mcontrol registers are explained .1
WW 00Y.CO .TW
in later
M sections.
W W WW 00Y.CO .TW W
W 00 .T .1 M .1 M
W W.1 Y
7.4.1 OM Purpose I/O Registers
General
.C W WW 00Y.CO .TW W WW 00Y.CO .TW
W
W 00 .T
W.1 Y.COM W The ATmega8U2/16U2/32U2 .1 M W.1 Y .CO .I/O
M
W W WW 00Y.CO .Tcontains W threeWGeneral
W 1 0 0
Purpose
TW
Registers. These registers
W 0 0 .T 1
. storing anyMinformation, and they . M
W.1 OM can be used for
WW 00Y.CO .TW WW
Ware particularly .CO .Tuseful
0Ywithin W
for storing global vari-
WW .100Y.C M.TWables andWStatus.1Flags. General Purpose I/O Registers . 1 0 Mthe address range 0x00 - 0x1F
W C O WW 00Y.Cusing OM WWand00SBIC Y .CO .TW
W Y. Ware directly W bit-accessible the
T W SBI, CBI, WSBIS, instructions.
W 00
W.1 Y.COM W
.T .1 M. .1
WW 00Y.CO .TW
M
W W WW 00Y.CO .TW W
W 00 .T .1 M .1 M
W.1 Y.CDescription
7.5 WRegister OM
W 00 .T W .1 M .1 M
7.5.1 W EEARH 00 W .1
W.1 and O M.T – The EEPROM
EEARL 1
.Address
WW 00Y.CO .TW
M
Register
WW 00Y.CO .TW
M
W Y . C W W W
W 00 Bit.T .1 13 M .110 O9 M
W.1 Y.COM0x22 (0x42) WW EEAR10
15 14 12 11 8
W W W WW –00Y.CO– .TW – W 0 0 Y.C EEAR9.TW EEAR8 EEARH
W 00 M.T(0x41)
–
W.1 OM EEAR4
EEAR11 .1 OM
W W.1 Y.CO0x21 W EEAR7 W EEAR6 Y.C
0 EEAR5 W EEAR3W WWEEAR2 0 0Y.CEEAR1 .TWEEAR0 EEARL
W 00 .T W .10 M . T .1 M
W W.1 Y.COM W 7
WW6 00Y.C5O .TW 4 3
W WW 2 00Y.CO1 .TW0
W 00 .T W R .1 M R .1 R/W M
Read/Write R R R/W R/W R/W
W W WR/WW
0 Y .CO .R/W T W W
W .100 Initial M.T .10 W.1 Y.COM W
R/W R/W R/W R/W R/W R/W
W C O W W .C OM 0 W
WW .100Y.
Value
M .TW X W X W.100Y
0 0 0
M .TW X W X
W .100 X OM.TX
X X
O O .C
W
WW .100Y.C M.TW WW .100Y
X X X X W
WW .100Y.C M.TW W O M.T
W O .C
W
WW .10• 0Y .CO15:12 .T–WRes: Reserved WW Bits Y.C .TW WW .100Y M.T
W
Bits
M W . 100 O M W C O
W .CO are Y.C WW .100Y . W
WW .These 00Y bits M W
.Treserved WW
and will always
.100 readOas M TW
.zero. M.T
1 O W W .C O
W
W
• Bits 11:0 O – EEAR[8:0]: EEPROM W Address O W .C O
WW The
W
0Y.C MAddress .TW WW .100Y.C M.TW WW .100Y W
M.T in the
. 1 0EEPROM Registers W– EEARH and
O EEARL specify the WEEPROM .C O
address
W O Y.C WW .100Y W
WW 512.1bytes .C
00Y EEPROM .TW space. The WWEEPROM .100 data M .TWare addressed
bytes linearly between M.T 0 and
W O M W O W W .C O
WW512. .The .C .TW
W Y.C TW must beWwritten.1before 00Y the M .TW
1 00Yinitial value M
of EEAR isWundefined.
W . 100 A proper O M .value W C O EEPROM
WWbe 0accessed. O W .
Wmay 0Y.C M.TW WW .100Y.C M.TW W .100
Y
M.T
W
W . 1 O W O W W .C O
WW .1Data .C
00Y Register W WW .100Y.C M.TW W .100
Y
M.T
W
7.5.2 EEDR – The EEPROM W O M.T W O W W .C O
W Y.C TW6 WW .100Y.C M.TW W .100 0
Y
M.T
W
WBit
W .100 7 M.
O 5 W 4 O3 2 1
W W .C O
WW (0x40) 00Y MSB
.C W WW .100Y.C M.TW W .100 EEDR
Y .TW
0x20
W .1 O M.T W C O W W LSB
.C OM
WW .100YR/W .C W R/W WW R/W Y.R/W W R/WW R/W 00Y .TW
.100 0 OM.T 0
Read/Write R/W R/W
M.T0 W W .1 OM
Initial ValueW 0.CO C W .C
WW .100Y W 0
WW .100Y.
0
M.T
W 0
W 0
.100
Y .TW
W Y.C EEPROM W W Y. W W .100
Y
• BitsW7:0 – EEDR[7:0]:
W .100 O M.T DataW W .100 O M.T W W
W Y.C operation, W the EEDR WW Register Y. C W W
For theWEEPROM
W .100write O M.T W .100 contains O M.T the data to be written to the
Y.C given WWRegister. YFor C
. the .EEPROM W
EEPROM WW in the address
. 100 M .TWby the EEAR
.100 MT
read operation, the
W O W C O
EEDR contains the data read out from the EEPROM
WW .100Y.C M.TW WW .at theY. address given by EEAR.
W 100
W O
WW .100Y.C M.TW WW
W O
WW .100Y.C M.TW
W O
WW .100Y.C 20
W W
7799D–AVR–11/10 W
.C OM
00Y .TW
W W.1 Y.COM W
W 00 .T
W W.1 Y.COM W
.TW W 00
W.1 Y.COM W
.T
.C OM W
7.5.3 EECR – The EEPROM Y
.100Control .TW
MRegister
W 00
W.1 Y.COM W
.T
W .C O W
WWBit .100Y M.T
7 W 6 W5 004 M3.T 2 1 0
W .C O W W.1EEPM0 .C OEERIE
W
.TW WW .100Y
0x1F (0x3F) –
M .TW R
– EEPM1
W . 00Y
1R/W M .T EEMPE EEPE EERE EECR
M O W O
.CO .TW WW 00Y.C
Read/Write R
W0
R/W
W W
1X00
Y.C R/W
.TW 0
R/W R/W R/W
.100Y M
WInitial Value . 1 0 M.T
O X
W . O 0M X 0
W W Y.C O
W W WW 00Y.C .T W W W 0 0 Y .C .T W
W 00 .T .1 OM .1 M
W W.1 Y.COM W • W Bits WW 7:6 – Res: Y .CReserved W Bits W WW 00Y.CO .TW
W 00 .T 10 0 T
M. and will always .1 M
W.1 Y.COM W TheseW bitsW.are .CO bits
reserved
Y W WW read as 0 Y .CO .TW
zero.
W W 0 T W 0
W 00
W.1 Y.COM W
.T .10 M. .1
WW 00Y.CO .TW
M
W W WW 00Y.CO .TW W
W 00 .T • Bits 5, 4 – .EEPM1
W 1 Y.Cand OMEEPM0: EEPROM .1
Programming MMode Bits
W W.1 Y.COM W W W W WW 00Y.CO .TW
W
The EEPROM .Programming 0 T
M. mode bit settingW defines
W 00 .T
W.1 Y.COM W gered when
10
.CO It is W.1 which Oprogramming
M action that will be trig-
W W WW writing 0 Y
EEPE. .T W
possible to Wprogram 1 data
0 0 Y .C
in one T W
atomic
. operation (erase the old
W
W .100 O M.T value and program W .10 OMvalue) or to splitW W.Erase . COM
C W the .C new the Y and Write W operations in two different
WW .100Y. M .TWoperations. W . 100
Y
M .TW W
W .100 areOshown M.T in Table 7-1. While EEPE
The W Programming O times for the different modes C
W
WW .100Y.C M.TW
O
W W .C
00Y will .TW WW .100Y. W
M.T bits will be reset to 0b00
is set, any write Wto . 1EEPMn O M be ignored. During Wreset, theC O
EEPMn
W O
WW .100Y.C M.Tunless W the EEPROMWW .1is Y.C programming.
00busy .TW WW .100Y. M.T
W
W O M W C O
W
WW .100Y.C M.TW
O
W
W O W C O
W
WW .100Y.C M.TW
O
W
W O W C O
W
WW .100Y.C M.TW
O Table 7-1.
WW .1Mode
EEPROM
00Y
.CBits .TW WW .100Y. M.T
W
W O M W C O
W
WW .100Y.C M.TW
O
WW Programming Y.C W WW .100Y. M.T
W
EEPM1 EEPM0 W . 100Time OM.T Operation W C O
W
WW .100Y.C M.TW
O
W
W O 0 0 W O Erase and WriteW W .C O
WW .100Y.C M.TW
3.4 ms
WW .100Y.C M.TW W in one.1operation
00Y
(Atomic
M.T
WOperation)
W O W C O
W O0 1
WW 1.8 msY.C Erase Only WW Y. W
WW .100Y.C M.TW . 100 M .TW W .100 O M.T
W O C
W
WW .100Y.C M.TW
O1 0
WW 1.8.1ms 00Y
.C Write
.TWOnly WW .100Y. M.T
W
O W O M W .C O
W
WW .100Y.C1 M.TW 1 WW –.100Y.C Reserved .TW for future WW use
.100
Y
M.T
W
W O M W .C O
W
WW .10• 0Y .CO .TW WW .100Y.C M.TW WW .100Y M.T
W
Bit 3 – MEERIE: EEPROM ReadyW Interrupt O Enable W .C O
W
WW .Writing .CO .TW WW the.1EEPROM 00Y
.C .TW InterruptWif theW
W Y
.100in SREG
W
Mis.Tset. Writing
1 00Y EERIE M to one enables W O M
Ready I bit .C O
W O WW generates
WW EERIE .C
00Y to zero .T W
disables the W
W
interrupt. . 0Y.C
10The EEPROM M .TWReady interrupt .100
Y
M.T
aOconstant
W
inter-
. 1
Wrupt when O M W O W W .C
W Y .C EEPE W
is cleared. W W 0 Y .C .T W W 0 0 Y .T W
W 0 0 .T .1 0 M . 1 M
W 0 W 1
.102 – EEMPE: M.T .1
WWProgramming OM Enable W. OM
•W Bit
WWThe EEMPE 0 Y .CO .TEEPROM W
Master
W 0 0 Y.C .T W WW .100Y.C M.TW
.10 bitM determines whether W .1 OMto one causes theWEEPROM W toObe written.
WW 00Y.CO .TW W setting EEPE
Y.C W W 0 Y.C W
WWhen .EEMPE
1 is M set, setting EEPE within W
W . 0 0
1four clock O M .T
cycles will write data to W 1 0
.the EEPROM O M.T at the
WW 0address O W .C
selected Y.C If EEMPE W is zero, WW setting .10EEPE 0Y.C willMhave .TW no effect. WWhen .EEMPE 100
Y has .been
MT
W
W
W .1 0 O M.T W O W W .C O
WW to.10one
written 0Y.C by software, .TW hardware WWclears Y.Cbit to .zero
the W after four W clock.1cycles. 00Y See M.T
W
the
W O M W .100 O MT W W . C O
description of the EEPE bit for an EEPROM WW write .C
Yprocedure. Y .TW
WW .100Y.C M.TW .100 M.T
W W
W .100 OM
W O W C O W .C
WW Y.C W WW .100Y. M.T
W W .100
Y .TW
• Bit 1 – EEPE:
W .100 EEPROM O M.T ProgrammingWEnable W C O W W .C OM
W 0Y.C Enable W W is the 0Y. strobe W
M.Tto the EEPROM.
W Y
.100 address .TW
The W EEPROM
W .10Write O M.T Signal EEPEW W .10write O W WWhen
.C OM
Y.C set up, C
0Y.written Y
and data WWare .correctly 100 M.T
Wthe EEPEWbit must .10be Mto.TW one to write Wthe value
W .100 into the
W O W C O W
EEPROM.WThe EEMPE Y.C bit must Wbe writtenWtoWone .before Y. a logical .TW one is written W to EEPE, other-
W .100write O M.Tplace. The following W 100 O Mshould
wise no EEPROM W takes procedure C be followed when writing
WW (the 0Y.C of steps
0order .TW WW .100Y. M .TW
the EEPROM W . 1 O M 3 and 4 is not essential):
W O
WW .100Y.C M.TW WW .100Y.C
W O W
WW .100Y.C M.TW WW
W O
WW .100Y.C M.TW
W O
WW .100Y.C 21
W W
7799D–AVR–11/10 W
. C OM
00Y .TW
W W.1 Y.COM W
W 00 .T
1. Wait until EEPE becomes W W.1 Y.COM W
zero.
.TW W 00
W.1 becomes OM zero.
.T
2. Wait until
C OMSELFPRGEN in SPMCSR W .C
1 00Y newM
. .TW W .
Y
100 (optional). M .TW
3.
W . Write O EEPROM address
W
to W EEAR
.C O
WW4. .Write .C .TW data to 00Y .TW
1 00Y new EEPROM M
WEEDR
W . 1(optional). O M
W O .C
.TW WW 5. Write
.C
00Ya logical TWto the EEMPE
.one WW bit.1while 00Y writing M .T W
a zero to EEPE in EECR.
M . 1 O M W O
.CO .TW WW 00Y
.C W after W W
100
Y.C .aTW
.1 00Y M
W6. Within
W . 1 four clock
O M .Tcycles settingWEEMPE, .
.C
write
O M logical one to EEPE.
W W .C O W Y .C W W W 0 Y .T W
W 00 Y .T W W
The EEPROM . 1 0
0 can not M T programmed during
.be . 0
1 a CPUOwrite M to the Flash memory. The software
W .1 O M W that O W
Wis completed .C before
W Y .C W mustW Wcheck 0 Y .C
the Flash .T W programming W 00 Y .T Winitiating a new EEPROM write.
W .1 00 M .T . 1 0 M W . 1 O M
W relevant O
W
WW .100Y.C M.TW
O Step 2W
W is only Y.C if the .TW
software contains WW .a10Boot 0Y.CLoader allowing
W the CPU to program the
M2.Tcan be omitted. See “Memory Pro-
Flash. If theW . 100 is never
Flash O M being updated by W
the CPU, O
step
W O
WW .100Y.C M.TW gramming” WW on.1page .C
00Y 246 M W
.Tdetails WW .100Y.C M.TW
W O for about BootW programming. O
W
WW .100Y.C M.TW
O
AnWinterrupt O W 6 will O
0Y.C M.TW
W O Caution: W between step 5 andWstep make the write cycle fail, since the
WW .100Y.C M.TW EEPROM W Master 0 0 Y.C .T W W . 1 0
1
W. Write OM will time-out. IfWan
Enable W interrupt Oroutine accessing the EEPROM is
W O
WW .100Y.C M.TWinterrupting WW another 0 0 Y.C
EEPROM .T W the EEAR
access, W or EEDR . 1 0 0Y.C Register
W
M.Twill be modified, causing the
W . 1 O M W C O
W O W Y.C WW .10to0Y . TW Interrupt Flag cleared
WW .100Y.C M.TW interruptedW EEPROM
. 100accessOto M .TWIt is recommended
fail.
W
have the
O M.Global
W C
W O
WW .100Y.C M.Tduring W all the W to 0avoid
Wsteps Y.C these.Tproblems. W WW .100Y. M.T
W
W . 1 0 O M W C O
W O
WW 0Y.ChasMelapsed, WW bit.1is00cleared Y. W
WW .100Y.C M.When TW the write access
. 10time .TW the EEPE W O
by.T
M hardware. The user soft-
W CO ware can poll this W W
bit and wait .C O
for a zero before writing W the next Y .C
byte. When W EEPE has been set,
WW .100Y. M .TW W . 100
Y
M .TW W
W .100 O M.T
O the CPU is halted W W O Y. C
W
WW .100Y.C M.TW
for two cycles Y.C before .TW
the next instruction WW .is 100
executed.
M.T
W
W
W .100 O M W C O
W
WW .100Y.C • M
O
.TW 0 – EERE: W
W 0Y.C Enable .TW WW .100Y. M.T
W
Bit EEPROM
W . 10Read O M W C O
W O
WW .100Y.C TheMEEPROM .TW Read WW Enable 0Y.C EERE .TW is the readW
W
.10the0Y.EEPROM. W
M.T When the correct
W . 10Signal O M strobe to
W C O
W O WEEAR0Register, Y.C WWbe written Y. W
WW .100Y.Caddress M .TW is set up in W the
.1 0 M
the .TW EERE bit must
W .100 to aOlogic M.T one to trigger the
W O W O W C
. the .requested
EEPROM
WW .100Y.C M.TW
read. TheW EEPROM
W Y.C access
read
.TW
takes oneW instruction, Yand
.100 forOfour
W
M Tcycles before the
data is
available immediately. When W . 100 EEPROM
the O M is read, the CPU W
is halted C
W
WW .100Y .CO .TW WW 0Y.C M.TW WW .100Y. M.T
W
next O instruction
M is executed. W.10 O W . C O
W
WW .100Y.C M.TW WW .100Y.C M.TW WW .100Y W
M.Toperation is in
The user
O should poll the EEPE W bit before O starting the read W
operation. If a
.C O
write
W
0Y.C M
WW .10progress, .isTW WW to .read Y.C .TW nor to change WW .100Y M.T
W
it neither possible W 100 the EEPROM, O M W the EEAR C O Register.
W O WW .100Y .
W
The calibratedO Oscillator is used W to time the OEEPROM accesses. W
Table 7-2 C O
lists
. the typical pro-
W
WW gramming 0 Y.C time.Tfor W W
Waccess 0 0Y.C .TW WW .100Y M .TW
1 0 EEPROM . 1from the M
CPU. W O
W. OM W O
WW .100Y.C M.TW
W W
Table 7-2. .C O EEPROM Programming
W WW Time Y .CO .TW W WW 00Y.CO .TW
Y W 0
W
W .10 0
O M.T W.1 Y
0
.C OM W W.1 Y.COM W
.C W W W 100 T
WW .100Y
Symbol
M .TW
Number of
W Calibrated
. 100
RC Oscillator
M .T Cycles Typ
W .Programming O M.Time
W O W O W .C
WWEEPROM .C WW 26,368 Y.C .TW W Y
.1003.3 ms OM.T
W
. 1 00Ywrite M.TW W . 100 O M W .C
W
(from CPU) O W
Y
M.T
W
W O W O W W .C O
.Ccode examples WWone.1assembly .C andWone C function Y TW
WWfollowing
The
. 1 00Y M .TW show
W
00Y
O M.T
W
W .100writingOto
for M.the
W O Y.Ccontrolled W .C
EEPROM.
WW .100Y.C M.TW
The examples assume that Winterrupts
W
100
are TW (e.g. by disabling
M.these
W interrupts
00Y
.1examples .TW
glob-
ally) so W that no interrupts O will occur during W .execution
C O of functions. W The W .C OM also
WW that C
0Y.Flash .TW Loader W
W Y. W W 0Y
.10present, .TW
assume W .10no O MBoot is present W .100in the O M.T
software. If such code W W is .C OMthe
Y.C must WW ongoing C
Y. SPM .command W Y .TW
EEPROM WW write .100function
W
M.T also wait for any .100 MT to W finish.W.100 OM
W O W C O W .C
W W .100
Y
W O W C O W W
W W
W O W C O
W
W O W C O
W O W
WW .100Y.C M.TW WW
W O
WW .100Y.C M.TW
W O
WW .100Y.C 22
W W
7799D–AVR–11/10 W
.C OM
00Y .TW
W W.1 Y.COM W
W 00 .T
W W.1 Y.COM W
.TW W 00
W.1 Y.COM W
.T
.C OM W
Y
.100 Code TW
M.Example
W 00 .T
Assembly
W .C O (1)
W W.1 Y.COM W
WW .100Y M.T
W W 00 .T
W EEPROM_write:.C O W W.1 Y.COM W
W WW .100Y TW
M.completion
W 00 .T
O M.T W ; Wait for
C O of W W.1 Y.write
previous C OM
00Y
.C .TW WW sbic 1
.
00YEECR,EEPE M .TW W . 100 M .TW
.1 M W . O W O
W O
WW .100Y.C M.TW WW rjmp Y.C
00EEPROM_write .TW WW .100Y.C M.TW
W . 1 O M W O
W
WW .100Y.C M.TW
O
WW ; Set 0 0 Y.Caddress
up .T W(r18:r17) WW in address
. 1 00Y.C register M .TW
W . 1 O M W O
W
WW .100Y.C M.TW
O
WWout .1EEARH, 00Y r18
W O M W O
W
WW .100Y.C M.TW
O
WoutW EEARL, 0 0 Y.Cr17 .TW WW .100Y.C M.TW
1
W. data OM to Data Register W O
W
WW .100Y.C M.TW
O
W ;W Write
0 0 Y.C (r16) .T W WW .100Y.C M.TW
W . 1 OM W O
W
WW .100Y.C M.TW
O
WW .100Y.C M.TW
out EEDR,r16
WW .100Y.C M.TW
Oone to EEMPE W O
W O ; Write
WW logical Y.C WW .100Y.C M.TW
WW .100Y.C M.TW W 1 0 0 .T W
W O sbi EECR,EEMPE W. OM WW 00Y.CO .TW
WW .100Y.C M.TW WW eeprom 0 0 Y.Cwrite .TbyW settingWEEPE .1 M
; Start
W. 1 M
W W .C O
W W Y .CO W W WW 00Y.CO .TW
W 00 Y .T W
sbi EECR,EEPE .10 0 M. T .1 M
W W.1 Y.COM W ret WW 00Y.CO .TW W WW 00Y.CO .TW
W 00 .T W .1 M
W.1 Y.COM W W(1)W.1 Y.COM W WW 00Y.CO .TW
W W 0 T W
W 00
W.1 Y.COM W
C
.T Code Example .10 M. .1
WW 00Y.CO .TW
M
W W WW 00Y.CO .TW W
W 00 .T void EEPROM_write(unsigned .1 M int uiAddress, .1
unsigned M ucData)
char
W
W 00 .T W.1 Y.COM W
{
W.1 Y.COM W W.1 Y.COM W
Wcompletion W*/
W /* Wait W
for 0 of T
previous
. W
write 00 .T
W
W .100 O M.T while(EECR &W(1<<EEPE)) W .10
.C OM W W.1 Y.COM W
WW .100Y. C W Y .TW W 00 .T
W O M.T ;
W
W .100 OM W W.1 Y.COM W
C W .C
WW .100Y. M/*.TWSet up address W Y
100 DataOM
.and .TW W 00
W.1 Y.COM W
.T
W C O W W .C Registers */ W
WW .100Y. .TW= uiAddress; W 00Y .TW W 00
W.1 Y.COM W
.T
W .C O MEEAR
W W.1 Y.COM W W
WW .100Y W W 0 .T W 00 .T
W O M.T = ucData; WW.10
EEDR
.C OM W W.1 Y.COM W
WW .100Y /*MWrite.C 00Y W W 00 .T
.TW logical W one .to
W 1 EEMPE O*/ M.T W.1 Y.COM W
W .C O W . C W W
WW .100Y EECR |=W(1<<EEMPE); W 00Y .T W 00 .T
.C W W 00 .T
WW .100Y /* Start M.T
Weeprom write W 0
by 0setting .T */
EEPE
W.1 Y.COM W
WW .100Y EECR |= (1<<EEPE);
W W 00 .T W 0 .T
} .C W W 0 .T
WW .100Y M.T
W W 00 .T 0
W.1 Y.COM W
WWNote:.1001.Y See “Code .TWExamples”W W .10 M.T
M on page .6.
W 100 O M .T W C O
W O W .
Y
M.T
W
W O W O W W .C O
Y
M.T
W
W O W O W W .C O
Y
M.T
W
W O W O W W .C O
Y .TW
W O W C O W W .C OM
W W .100
Y .TW
W O W C O W W .C OM
W W .100
Y .TW
W O W C O W W .C OM
W W .100
Y
W O W C O W W
W W
W O W C O
W
W O W C O
W O W
WW .100Y.C M.TW WW
W O
WW .100Y.C M.TW
W O
WW .100Y.C 23
W W
7799D–AVR–11/10 W
.C OM
00Y .TW
W W.1 Y.COM W
W 00 .T
The next code examples show assembly W W.1 and .C OCM functions for reading the EEPROM. The exam-
W W Y
.100 so that M.no TWinterrupts will occur during execution of
ples assumeOthat M.Tinterrupts are controlled W O
these 0Y.C M.TW
0functions. WW .100Y.C M.TW
W . 1 O W O
W O
W WW
W
Assembly 0 .CO Example
YCode .T W (1) WW .100Y.C M.TW
.T 1 0
OM W. OM W O
0 Y.C .T W WW EEPROM_read: 0 0 Y.C .T W WW .100Y.C M.TW
0 W. 1 M
W.1 OM .CO completion WW 00Y.CO .TW
WW .100Y.C M.TW WW ; .Wait 1 00Y for M .TW ofWprevious .1 write M
W W .C O
W WW Y .CO .TW W WW 00Y.CO .TW
W 00 Y .T W sbic 0 0
EECR,EEPE
.1 M
W.1 Y.COM W Wrjmp W.1 EEPROM_readY .CO .TW
M WW 00Y.CO .TW
W W 0 W
W 00
W.1 Y.COM W
.T .10 M
.CO .T(r18:r17) W.1 Yregister M
.CO .TW
W W WW
; Set up Yaddress
0 W WinWaddress
0 0
W 00 .T .10 OM .1 M
W W.1 Y.COM W outWWEEARH, Y .C r18
W W WW 00Y.CO .TW
W 00 .T W 0
.10 r17OM. T .1 M
W W.1 Y.COM W out W
W
EEARL,
Y .C W W WW 00Y.CO .TW
W 00 .T W 0 0
.1eeprom T
M. by writing EERE .1 M
W W.1 Y.COM W
; Start
WW 00Y.CO .TW
read
W WW 00Y.CO .TW
W 00 .T W .1 M
W.1 Y.COM W
sbi EECR,EERE
W W 0 T W
W 00
W.1 Y.COM W
.T ; Read data .10 from Data M. Register .1
WW 00Y.CO .TW
M
W in W WW 00Y.CO .TW
r16,EEDR W
W 00 .T .1 M .1 M
W 00 .T W .1 M
W.1 Y.COM C W W(1) W.1 Y.COM W WW 00Y.CO .TW
W Code Example W 0 T W
W 00
W.1 Y.COM W
.T .10 M. .1
WW 00Y.CO .TW
M
W W 0 .CO .TW
WWEEPROM_read(unsigned
Y W
W 00 .T unsigned char
.10 M int .1
uiAddress) M
W W.1 Y.COM {W WW 00Y.CO .TW W WW 00Y.CO .TW
W
W 00
W.1 Y.COM W
.T W.1 Y.COof M W*/ W.1 Y.COM W
W /* Wait for W Wcompletion 0 W
previous
.T write W 00 .T
W
W .100 O M.T while(EECR &W(1<<EEPE)) W .10
.C OM W W.1 Y.COM W
WW .100Y. C W Y .TW W 00 .T
W O M.T ;
W
C W .C
WW .100Y. .TWSet up address W 100
Y .TW W 00
W.1 Y.COM W
.T
W C O M/* W W .register
.C OM */ W
WW .100Y. .TW= uiAddress; W 00Y .TW W 00
W.1 Y.COM W
.T
W . C O M EEAR
W W.1 Y.COM W W
WW .100Y W eeprom W read.1by 00 writing .T W 00 .T
W O M.T
/* Start
W .C OM EERE */ W W.1 Y.COM W
.C W 00Y W W 00 .T
WW .100Y EECR M.T
W (1<<EERE);
|= W .T W.1 Y.COM W
WW .100Y /* M .TW data from
Return W Data 00Register.T*/ W 00 .T
W O W.1 Y.COM W W W.1 Y.COM W
.C W W 00 .T
WW .100Y return
M.T
EEDR;
W } .C O W W.1 Y.COM W W 0
WW .100Y W W 00 .T W 0 .T
.C W W 0 .T
WW Note: .100
Y1. See “Code W
M.T Examples” onW
W page.16. 00 .T 0
W.1 Y.COM W
W C O W .C OM W
WW .100Y . .TW Y W W .10 0 M.T
M
W
W . 100 O M .T W C O
W O W .
Y
M.T
W
7.5.4 GPIOR2 – General W Purpose.C I/O
O Register 2 W O W W .C O
WW .100Y .TW 6 WW .100Y.C M.TW W .1000
Y
M.T
W
Bit W O7M W O W W .C O
WW .100Y.C M.TW
5 4 3 2 1 W
W Y.C W W 00Y GPIOR2
.1LSB M.T
W
0x2B (0x4B)
W .100 MSB O M.T W O W W .C O
WW .100Y.C W WW R/W Y.C W W .100
Y .TW
Read/Write
W
R/W
O M .TR/W R/W
W .100 R/WOM.T R/W R/W
W W
R/W
.C OM
WW 0 .100Y. 0 M.TW C Y .TW
WW .100Y.C M.TW .100
Initial Value 0 0 0 0 0W 0
W O W C O W W .C OM
WW .1I/O .C
00YRegister W WW .100Y. M.T
W W .100
Y .TW
7.5.5 GPIOR1 – General Purpose W O M.T1 W C O W W .C OM
Bit WW .1007Y.C M6.TW 5 WW4 .100Y3 . M.2T
W
1
W
0 W.1
00Y
W O W C O W
WW .1MSB 00Y
.C W WW .100Y. M.T
W W LSB
M.T
0x2A (0x4A) GPIOR1
W R/W Y.C R/W O W W .C O
Read/Write W
.TW
R/W R/W R/W Y R/W W R/W R/W
W 00
W.10 Y.CO0 M W0
W
0 WW 0
.100 O0M
.T
Initial Value
W Y .C 0 0
W . 1 00 M .T W .1 00
W O W
WW .100Y.C M.TW WW
W O
WW .100Y.C M.TW
W O
WW .100Y.C 24
W W
7799D–AVR–11/10 W
.C OM
00Y .TW
W W.1 Y.COM W
W 00 .T
7.5.6 GPIOR0 – General Purpose I/O Register 0 WW.1 .C OM
.T7 W Y W
M
W
W . 100 4 OM.T3
.CO .TW
Bit 6 5 2 1 0
00Y
0x1E.1(0x3E) MSB WW .100Y.C M.TW LSB GPIOR0
W W .C OM WW 0R/W Y .CO R/W W
Y W W 0 .T
W .100 .T
Read/Write R/W R/W R/W R/W R/W R/W
OM .1 OM0
WValue C 0WW 0 Y.C
.T W W WInitial
1 00 Y . 0
M .TW 0
W . 1 0 0 M .TW 0 0 0
M W . O W O
.CO .TW WW .100Y.C M.TW WW .100Y.C M.TW
.100Y M W O W O
W O
W O W O
W
WW .100Y.C M.TW
O
W O W O
W
WW .100Y.C M.TW
O
W O W O
W
WW .100Y.C M.TW
O
W O W O
W
WW .100Y.C M.TW
O
W O W O
W
WW .100Y.C M.TW
O
W O W O
W
WW .100Y.C M.TW
O
W O W O
W
WW .100Y.C M.TW
O
W O W O
W
WW .100Y.C M.TW
O
W O W O
W
WW .100Y.C M.TW
O
W O W O
W
WW .100Y.C M.TW
O
W O W O
W
WW .100Y.C M.TW
O
W O W O
W
WW .100Y.C M.TW
O
W O W O
W
WW .100Y.C M.TW
O
W O W O
W O
W O W O
W
WW .100Y.C M.TW
O
W O W O
W
WW .100Y.C M.TW
O
W O W O
W
WW .100Y.C M.TW
O
W O W O
W
WW .100Y.C M.TW
O
W O W O
W
WW .100Y.C M.TW
O
W W .C O
Y W
W
.C W
WW .100Y M.TW W
W . 100 O M .T W
W .100 OM
.T
WW .100Y M .TW W
W .100 O M .T W .10 O M.T
W O WW .100Y .C
W
W O W O W W .C O
Y
M.T
W
W O W O W W .C O
Y
M.T
W
W O W O W W .C O
Y
M.T
W
W O W O W W .C O
Y .TW
W O W C O W W .C OM
W W .100
Y .TW
W O W C O W W .C OM
W W .100
Y .TW
W O W C O W W .C OM
W W .100
Y
W O W C O W W
W W
W O W CO
W
W O W CO
W O W
WW .100Y.C M.TW WW
W O
WW .100Y.C M.TW
W O
WW .100Y.C 25
W W
7799D–AVR–11/10 W
.C OM
00Y .TW
W W.1 Y.COM W
W 00 .T
8. System Clock and Clock Options W W.1 Y.COM W
.TW W 00
W.1 Y.COM W
.T
.C OM W
Y W W 00 .T
8.1 Clock Systems and
W .100their O M.T
Distribution W W.1 Y.COM W
WW . C W
FigureW
00Ypresents
.18-1 O M.Tthe principal clock
W .100 in O
systems
W the
.T
MAVR and their distribution. All of the clocks
W .C
Yactive at.TaW W
WIn order.1to Y .C
0reduce TW consumption, the clocks to modules
.T W Wneed not
1 0 0
be given time. 0 M .
power
OM W. OM W .CO .TW
0 Y.C T W notWbeing10used
W 0 Y.Ccan be.Thalted W by usingWWdifferent 1 0 0Ysleep modes, as described in “Power Manage-
W .10
O M . W .
C O M W W .
.C OM
WW .100Y.C M.TW WWand.1Sleep
ment .
00Y Modes” M .Ton W page 42.WThe clock .
Y
100systems M .TW
are detailed below.
W O W C O W W .C O
WW .100Y.C M.TW WW .100Y .
M .TW W . 100
Y
M .TW
Figure 8-1.
W Clock O Distribution W O
W
WW .100Y.C M.TW
O
WW .100Y.C M.TW WW .100Y.C M.TW General I/O W .1 OM
.CO .TW Modules WWW 00Y.CCPU Core.TW RAM
Flash and
O USB W
W W Y . C W W 0 Y EEPROM
W 00 .T W . 10 M .1 M
. 1 M W O W O
W
WW .100Y.C M.TW
O
W O W O
W
WW .100Y.C M.TW
O
W O W O
W
WW .100Y.C M.TW
O
W O W .CO .TW
clk AVR Clock W
WW
clk
.CO .TW
WW .100Y.C M.TW clkWW 00Y
I/O CPU
. 1 00Y
USB (48MHz)
M
Control Unit
. 1 M
W W .C O
W USB PLL W W Y .CO .TW W WW 0clk0Y.CO .TW
FLASH
W 00 Y .T X6 W .10 0 M .1 M
W
W
W .100 O M.T clk W .1
. C OM W W.1 Y.COMWatchdog
Reset Logic
W
Timer
C W .TW
WW .100Y. Y W 00 .T
Pllin (8MHz)
W W .100
W O M.T PLL Clock W .C OM W W.1 Y.COM W
C W .TW
WW .100Y. M.T
WPrescaler W .100
Y Wclock .100 Watchdog clock
Source
OM
.T
W CO W W .C OM W W Y .C W
WW .100Y. M .TW clk W . 100
Y
M .TWSystem Clock W
W .100 O M.T
Watchdog
W O Prescaler
C Oscillator
W
WW .100Y.C M.TW
O
WW .100Y.C M.TW
XTAL (2-16 MHz)
WW .100Y. M.T
W
W O W C O
W
WW .100Y.C M.TW
O
WW .100Y.C M.TWClock WW .100Y. M.T
W
W O W C O
O WW .100Y.
Multiplexer
W
W
O W O W .C O
W
W
O W O W .C O
W
W
O W O W .C O
W
WW .100Y.C M.TW
W Y.C External .TW WW .100Y .TW
WCrystal
W .100 O M W C O M Calibrated RC
W O WW .100Y .
Oscillator Clock Oscillator
W O W O M.T
W O WW .100Y .C
8.1.1 CPU Clock WW– clkCPU 00Y
.C .TW WW .100Y.C M.TW M.T
W
. 1 O M W O W .C O
W
WW The.1CPU .C .TW WW of the Y.C .TW WW Y
.100 of the .TWcore.
00Y clockMis routed to parts
W .100system O M concerned with operation
W C O MAVR
W .C O WGeneral Y.C W W Status Y . TWthe
WWExamples .1 00Yof such M TW
.modules areW the
W . 100 Purpose O M Register
.T File,Wthe
W .100 Register O M.and
O
W memory holding the Stack Pointer. Y.Cthe CPU W .C
Y performing W
WW .100Y.C M.TW
data WW Halting . 100 M .TW clock inhibits W the core .100
from
M.T
general
W operations O and calculations. W O W W .C O
Y
M.T
W
W O W O W W .C O
8.1.2 I/O Clock – clkI/O WW .100Y.C M.TW WW .100Y.C M.TW W .100
Y
M.T
W
W O W O W W .C O
WW
The I/O clock Y.C
is used by.Tthe W majorityW ofWthe I/O 0Y.C Mlike
.10modules, .TW W
Timer/Counters, SPI, Y
.100and USART. .TW
W
TheWI/O W clock00isYalso .C used .TW by the External WW Interrupt Y. module, W note that
but W some .1external 00Y inter- M.T
W . 1 O M W .100 O M.T W W .C O
rupts are detected by asynchronous logic,W
W allowing suchC
Y. interrupts W to be detected even Yif the I/O.TW
WW .100Y.C M.TW .100 M.T
W
W .100 OM
clock is halted. W O
W
WW .100Y.C M.TW
O
WW .100Y. C
.T W W W
. 1 00Y.C
M W
8.1.3 Flash Clock – clkFLASHWW
W Y .CO .TW W WW 00Y.CO .TW WW
0
.10
.CO
M W.1 Y.COM W
The Flash WW controls
Wclock 0 Y operation.T W of the Flash
W Winterface. 00 The Flash .T clock is usually active simul-
taneously with W .10
the CPU .C OM
clock. W W.1 Y.COM
W W 00Y .TW W 00
W.1 Y.COM W W W.1
W W 00 .T W
W W.1 Y.COM W
W 00 .T
W W.1 Y.COM
W 00
W W.1 26
7799D–AVR–11/10 W
.C OM
00Y .TW
W W.1 Y.COM W
W 00 .T
8.1.4 USB Clock – clkUSB W W.1 Y.COM W
.TW with a dedicated
W 100 domain.
W.clock
.T
OM This clock is generated with an on-chip PLL
The USB is provided
C OM W .C
running 00at
.
Y 48 MHz..TThe W PLL always W multiply .
Y
100 its input M TW
.frequency by 6. Thus the PLL clock register
W . 1 O M W O
W
should be Y .C
programmed W by W
software Wto generate 0 Y .Ca 8 MHz .T W clock on the PLL input.
W .100 M.T 0
W .C O W W.1 Y.COM W
W WW 0Y .TW W 00 .T
8.2 Y.CO M.T Switch WW.10
Clock .C OM W W.1 Y.COM W
W Y W W .100 .T
.100 O M.T
W
In the W .100 O
ATmega8U2/16U2/32U2 M.T product, W W
the Clock .C OM
Multiplexer
W
WW .100Y.C M.TW WW .100Y .C
M .TW W . 100
Y
M .TW and the System Clock Prescaler
can be modified
W by software.
O W O
W
WW .100Y.C M.TW
O
W O W O
W
WW8.2.1 0
O
Y.CExemple
.T Wof use WW .100Y.C M.TW WW .100Y.C M.TW
0 .CO Suspend
W.1 OM W O
Y.Coccur.T WWenters
W
0YUSB W mode. It then switches from
WW .100Y.C M.TW The modification WW .100can M
W the device
when . 1 0 in M.T
W O W O RC OscillatorWinWorder 0 W .C O
WW .100Y.C M.TW
External WW Y.C
Clock to 0Calibrated
.TW .1 0
to Y reduce W
consumption.
M.T
In such a configura-
W . 10Clock is O M W O
WW .100Y.C M.TW
W O tion, the External disabled.
W O W O
W
WW .100Y.C M.TW
O The firmware WW can.1use 00Y
.C watchdog
the
.T W timer toWbe Wwoken-up
. 1 0 0Y.C W
from power-down
M.T
in order to check if
there is an event W on the O M
application. W C O
W
WW .100Y.C M.TW
O
W
O W O W . CO
W
WW .100Y.C M.TW
If an event occurs WW on.1the 00Y
.C
application
.TWor if the USB WWcontroller .100
Ysignals
M.T
W
a non-idle state on the USB
line (Resume for W
example), O
the Mfirmware switches the W Clock C O
Multiplexer from the Calibrated RC
W O
WW .100Y.C M.Oscillator TW W W 0 0Y.C M.TW WW .100Y. M .TW
to the External
W . 1 Clock.O W O
W
WW .100Y.C M.TW
O
W O W O
W
WW .100Y.C Figure
O
.T W 8-2. Example WW .of 00Y.C switching
clock .TW with wake-up WW from . 1 0Y.CHost
0USB M.T
W
M W 1 O M W C O
W
WW .100Y.C M.TW
O
M.Tresume
W O W O W W .C O
WW .100Y.C M.TW WW .100Y.C M.TW ResumeWfrom Host.100Y M.T
W
W O 1 W C O
W
WW .100Y.C M.TW
O
W
W O W C O
W
WW .100Y.C M.TW
O
W
W O W C O
USB W
WW non-Idle .CO .TIdle W WW .100Y.C M(Suspend) .TW WW .100Y. M.T
W non-Idle
. 1 00Y M W O W .C O
WW 00Y.CO .TW WW .100Y.C M.TW WW .100Y1 M.T
W
CPU Clock W . 1 O Ext
M W O RC W .C O Ext
W
WW .100Y.C M.TW WW .100Y.C M.TW WW .100Y M .TW
W O W O
External
W
WW .100Y.C M.TW
O
Oscillator W W .C O
Y W
W
.C W
RC oscillator WW .100Y M .TW W
W . 100 O M .T W
W .100 OM
.T
WW .100Y 3ms M.TW W
W .100 O M .T W .10 O M.T
W O Y.C WW .100Y .C W
WW .100Y.C M.TW WW Watchdog . 100wake-upOM.T
W M.T
W O W W W .C O
WW .100Y.C M.TW WWfrom power-down Y.C .TW W .100
Y
M.T
W
W . 100 O M W C O
W O W .
Y
M.T
W
W O W O W W .C O
Y
M.T
W
W O W O W W .C O
Y .TW
W O W C O W W .C OM
W W .100
Y .TW
W O W C O W W .C OM
W W .100
Y .TW
W O W C O W W .C OM
W W .100
Y
W O W C O W W
W W
W O W C O
W
W O W C O
W O W
WW .100Y.C M.TW WW
W O
WW .100Y.C M.TW
W O
WW .100Y.C 27
W W
7799D–AVR–11/10 W
.C OM
00Y .TW
W W.1 Y.COM W
W 00 M.T
Figure 8-3. Example of clockW W.1 Y
switching with
.C Owake-up from Device
.T W W . 1 0 0 M .TW
OM W O
0 0 Y.C .T W WW .100Y.C M.TW upstream-resume
W .1 O M W W .C O
WW .100Y .C W W 00Y .T W
W O M.T W W.1 2YUpstream .C OM Resume from device
WW .100Y .C .TW
M .TW M .TW W
W . 100 O M
WW 00Y.C O
O
0Y.C M.TW non-IdleW .TW WW .100Y.C M.TW
.10USB W . 1 Idle O M W (Suspend) O non-Idle
W
WW .100Y.C M.TW
O
W CO W O
WW .1RC
W .CO .TW 2
WW .CPU 0 0 Y.Clock .T W WW Ext.100Y.C M.TW 00Y M Ext
W 1 O M W C O W W .C O
W . Y W
WW .100Y.C M.TW W .100
Y .TW W 00
W.1 Y.COM W
.T
WExternal CO W W .C OM W
WW Oscillator Y. W Y W W 00 .T
W .100 O M.T
W
W .C
WW .100Y.C M.TW W .100
Y
M.T
W W 00
W.1 Y.COM W
.T
RCW oscillator O W W .C O W
WW .100Y.C M.TW W .100
Y
M.T
W W 00
W.1 Y.COM W
.T
W C O W W .C O W
WW .100Y. M.T
W W3ms
.100
Y .TW WatchdogW 00
W.1 Y.COM W
.T
W CO W W .C OM wake-up
W
WW .100Y. M.T
W W .100
Y .TWfrom power-down W 00
W.1 Y.COM W
.T
W C O W W .C OM W
WW Clock Y. TW W .100
Y .TW W 00
W.1 Y.COM W
.T
8.2.2
W .100 switch OM.Algorythm W W .C OM W
WW Y.C Y .TW W 00 .T
100 M .TW W .100 OM W.1 Y.COM W
8.2.2.1 WW.SwithYfrom C O external clock to RCW W
clock .C W
. W W .100
Y .TW W .100 .T
W
W .100 OM.T if (Usb_suspend_detected()) W W .C OM // if W W
(UDINT.SUSPI
Y .C OM == 1)
W
WW .100Y. C .TW
M .T{W W
W .100
Y
O M
W
W .100 O M.T
W O W Y. C
WW .100Y.C M.TWUsb_ack_suspend(); WW .100Y.C M.TW // W UDINT.SUSPI .100 = 0; M.T
W
W O W C O
W
WW .100Y.C M.TW
O
Usb_freeze_clock(); WW .100Y.C M.TW // USBCON.FRZCLK WW .100Y. = 1;M.TW
W O W O W
WW .100=Y.0; CO
WW .100Y.C M.TDisable_pll(); W WW .100Y.C M.TW // PLLCSR.PLLE M.T
W
O W O W .C O
W
WW .100Y.C MEnable_RC_clock();
.TW WW .100Y.C M.TW // CLKSEL0.RCE WW .10=0Y1; M.T
W
W O W C O
W O while (!RC_clock_ready());
WW .100Y.C M.TW// whileW(CLKSTA.RCON
W Y. != 1); W
WW .100Y.C M.TW W .100 O M.T
O W O .C
W Select_RC_clock();
WW .100Y.C Disable_external_clock();
.TW WW .100Y.C M.TW
//
WW .100Y
CLKSEL0.CLKS = 0;
M.T
W
O M W O // CLKSEL0.EXTE W = 0; .C O
W
WW .100Y.}C M.TW WW .100Y.C M.TW WW .100Y M.T
W
O W O W .C O
W
W
O W O W .C O
8.2.2.2 Switch from
WW RC
W clock Y.C to external .TW
clock WW Y.C .TW WW .100Y M.T
W
. 1 00if M W . 100 O M W C O
W O
(Usb_wake_up_detected()) // if
WW .100Y
(UDINT.WAKEUPI == .
1)
WW .10{0Y.C M.TW WW .100Y.C M.TW M.T
W
O W O W .C O
W
WW .100Y .C .TW WW .100Y.C //MUDINT.WAKEUPI .TW WW .100Y M.T
W
W
Usb_ack_wake_up();
O M W O W
= W 0;
.C O
Y.C
WW .100Enable_external_clock(); .TW WW .100Y.C // M .TW
CKSEL0.EXTE W
= 1; W.10
0Y M.T
W
W O M W O W .C O
WW .1while .C .TW
00Y (!External_clock_ready()); WW .100Y.C// while M .TW (CLKSTA.EXTON W .!=
Y
1001); OM.T
W
W O M W O
C CLKSEL0.CLKS W W .C W
Y.C
WW .Select_external_clock(); W WW .100Y.// M.T
W =W 1; .100
Y
M.T
W 100 O M.T W O W W .C O
.C WW .100Y .C PLLCSR.PLLE W Y W
WW Enable_pll(); W .100 M.T
// = 1;
. 1 00Y M .TW W O M.T W C O
W O Y.CCLKSEL0.RCE W Y . .TW
WW .100Y.C M.TW
Disable_RC_clock();
WW .100// M.T
W = 0; W .100
W
while O
(!Pll_ready()); W // C O
while (PLLCSR.PLOCK W != W 1); .C OM
WWUsb_unfreeze_clock();Y.C W WW .100Y. M.T
W W .100
Y .TW
W .100 O M.T W O
// USBCON.FRZCLK
C = 0; W W .C OM
W W .100
Y .TW
}W
W .100 O M.T W C O W W .C OM
W W .100
Y
W O W C O W W
W W
W O W C O
W
W O W C O
W O W
WW .100Y.C M.TW WW
W O
WW .100Y.C M.TW
W O
WW .100Y.C 28
W W
7799D–AVR–11/10 W
.C OM
00Y .TW
W W.1 Y.COM W
W 00 .T
8.3 Clock Sources W W.1 Y.COM W
M.the TW W .100 options, .T
OM selectable by Flash Fuse bits as shown
The deviceCO has following clock W Wsource .C
.
0Y clock
0The .TW the selected W source .
Y
100is input M TWAVR clock generator, and routed to the
.the
below.
W . 1 O M from W O to
WW appropriate .C
00Y modules. .TW WW .100Y.C M.TW
. 1 M
W O
WW .100Y
W .CO .TW
T W WW .100Y.C M.TW
OM
. Table W8-1. Y.C Device
O Clocking Options WW Select .COM(1)
00 Y.C
.T W W W
1 0 0 M .T W W . 100
Y
M .TW
.1 M .
W Clocking Option O W O
WW .100Y.C M.TW
W O Device CKSEL3:0
W Crystal O W O
W
WW .100Y.C M.TW
O LowW
W
Power
00Y
.C Oscillator .TW WW .100Y.C M.TW 1111 - 1000
. 1
W Crystal Oscillator O M W O
W
WW .100Y.C M.TW
O
WW .100Y.C M.TW
Full Swing WW .100Y.C M.TW 0111 - 0110
W O W O
W
WW .100Y.C M.TW
O Reserved
WW .100Y.C M.TW WW .100Y.C M.TW 0101 - 0100
W O W O
W O
WW .100Y.C M.TW Reserved WW .100Y.C M.TW WW .100Y.C M.TW 0011
W O W C O W W .C O
W . Y W
WW .100Y.C M.TW Calibrated W Internal .100
RC Y Oscillator.TW W 00
W.1 Y.COM W
.T 0010
W C O W W .C OM W
WW .100Y. M.T
W External W Clock
.100
Y .TW W 00
W.1 Y.COM W
.T 0000
W C O W W .C OM W
WW .100Y. M.T
WReserved W .100
Y .TW W 00
W.1 Y.COM W
.T 0001
W CO W W .C OM W
WW .100Y. W
M.TNote: 1. For all
W fuses Y
.100“1” means .TW W 00
W.1meansY.programmed.
OM
.T
W C O W W .C OMunprogrammed while W
“0”
C W
WW .100Y. M .TW W . 100
Y
M .TW W
W .100 O M.T
W O C
W
8.3.1 WDefault .CO Source
Clock
.TW WW .100Y.C M.TW WW .100Y. M.T
W
W . 1 00Y M W O W C O
. with.Tthe
W O The device is shipped with internal RC oscillatorW atW8.0 MHz Yand W fuse CKDIV8 pro-
WW .100Y.C grammed, .TW WW .100Y.C M.TW 100 is setOto
.time M maximum and time-out
M resulting in W 1.0 MHz system
O clock. The startup W C
W
WW .100Y.C period
O
.TW WW .=10"0010", 0Y.C SUT .T=W"10", CKDIV8 WW .100Y. W
M.T setting ensures that
M enabled. (CKSEL W O M =W "0"). TheCdefault
O
W O Y.C source WW any.1available . W
WW .100Y.C all M .TWcan makeWtheir W
users W desired
. 100 clock M .TW setting using 00Y M.T
programming interface.
W O C O W W .C O
C W . .TW Y W
WW .100Y. M.T
W W .100
Y W 00
W.1 Y.COM W
.T
8.3.2 Clock W
Startup O
Sequence
C W W .C OM W
WW .100Y. W
M.T source needs W
W Y
.100 V OM .TW W 00
Wa.1minimum M.T of oscillating
Onumber
W AnyC O clock W
a sufficient .C CC to start oscillating and W Y .C W
WW .100Y .
cycles .TW it can beW
before
M considered .
Y
100 stable. M .TW W
W .100 O M.T
O W O .C
W
WW .100Y.C M.TW WW .100Y.C M.TW WW .100Y M.T (t
W
To ensure sufficient V , the Wdevice issues O an internal reset withW a time-out .C O delay ) after
W
WW .10the CO
0Y.device T W CC
WWby all 0 0Y.C reset . W
Tsources. WW .100Y .TWTOUT
. . 1 M M
W W .C OM reset
W
is released other
WW 00Y.CO .TW
“On-chip
W WW 00Y.CO .TW
Debug System” on page 45
Y W 1
W 100
describes
W.Oscillator OM
the.T start conditions for the .1 internalOreset. M The delay (tTOUT ) is. timed from
WWand 0CKSELx OMthe Watchdog
.C WW in00the Y .Cdelay is W W 0 Y.C fuse W
W W
. 1 00 Y and
M
the
.T W number W
of cycles
W . 1 O M .T set by the SUTx
W . 1 O M.T bits. The
W O
.C delays inW C frequency
Y.The W Y .C isW
WW selectable
. 1 00Y M .TW
are shownW Table 8-2.
. 100 M .TW of theWWatchdog W .100
Oscillator
O M.T
voltage
O W O .C
dependent
W
WW .100Y.C M.TW
as shown in “Typical Characteristics”
WW .100Y.C M.TW
on page 273. WW .100Y M.T
W
O W O W .C O
W
WWTable.108-2. 0Y.C Number .TW of Watchdog WW Oscillator Y.C .TW WW .100Y M.T
W
M W . 100 Cycles O M W C O
W O .C W Y . W
WW Typ 0Y.C M
0Time-out (V.CCTW = 5.0V) WW Typ.1Time-out 00Y (V
M .T=W 3.0V) W Number .100 of Cycles M.T
W . 1 O W O CC
W W .C O
WW .100Y.C0 msM.TW WW .100Y.0Cms M.TW W .1000
Y
M.T
W
W O W O W W .C O
WW .100Y4.1 .C
ms M.TW WW .1004.3 Y.Cms .TW W 00Y
.1512 M.T
W
W O W O M W W .C O
Y.Cms WW .1069 .C W Y .TW
WW .10065 M.T
W
W
0Yms
O M.T
W
8K
W .100
(8,192) OM
W O C W .C W
Mit.Tis supplied with W
W .100
Y
M.T
Main purpose W of the O
delay is to keep the AVR W in reset C O
until W
minimum .C
Vcc. OThe
.C W Y. W Y W
delay Wwill W
not 00Y the
.1monitor .TW voltageWand itWwill
Mactual .100be required O M.Tto select a delay
W
W .100 thanOthe
longer M.T
W O C
Y. Brown-Out W 0Y be.C
Vcc rise WW time. .If10this 0Y.is C
notM .TW an internal
possible, WW or.external 100 M.T
W W
Detection circuit .10should
W O W C O W W
W circuit .C ensure W WWbefore Y. .TWreset, andWthe time-out delay
used. AWBOD
W .100
Ywill
O M.T
sufficient Vcc
W .10it0releases O Mthe
can be disabled. .C the.Ttime-out WWwithout Y. C W
WW .1Disabling 00Y M
W delay
.100
utilizing a Brown-Out
M.T
Detection circuit is
not recommended. W O W C O
W O W
WW .100Y.C M.TW WW
W O
WW .100Y.C M.TW
W O
WW .100Y.C 29
W W
7799D–AVR–11/10 W
.C OM
00Y .TW
W W.1 Y.COM W
The oscillator is required to oscillate
W 100a minimum
W.for
.T
OM number of cycles before the clock is consid-
W .C
ered stable. O .TW ripple W
AnMinternal counter 100
Y
.monitors the .TW
Moscillator output clock, and keeps the internal
C W W .C O
Y . W W 0 Y .T W
0cycles. The reset is then released and the device will
00
reset.1active for M T
a .given number of clock
W.1 Y.COM W
W W to execute. .C O Woscillator
start Y The Wrecommended W 00 start-up M.T time is dependent on the clock type, and
W
W .100 O M.T W W.1 clock .C Oto
varies
WW .100Y from 6.C cycles for an externally applied Y 32K .TW cycles for a low frequency crystal.
M .TW M .TW W
W . 100 O M
W O
.CO .TW TheWstart-up .C
00Ysequence W the clockWincludes
.Tfor
W 0Y.Cthe time-out
10both .TW delay and the start-up time when
.100Y M
W
W . 1 O M W . O M
.C Power-save
W O the W .Cup from W
WW .100Y.C M.TW W device.1starts 00Y M .TW
reset. When Wstarting .
upYfrom
100 M .TW or Power-down mode, Vcc is
assumed W to be at aO sufficient level and only W the start-up O time is included.
W
WW .100Y.C M.TW
O
O W O
W .CO .TW WW 00Y.C W WW .100Y.C M.TW
WW8.4.100Y LowOPower W
Crystal Oscillator 1 .T
M W. OM W O
W
WW .100Y.C M.TW Pins XTAL1 WW and 0 0 Y.C are.Tinput
XTAL2
W and output, WW respectively,. 1 0 0Y.C ofMan .TW inverting amplifier which can be
W . 1 O M W O
W W .CO W for use Y .Can On-chip W W W 0 Y .C .T W
W 00 Y .T W W
configured . 10 0 as M .T Oscillator, as shown
.1 0 in Figure
M 8-4. Either a quartz crystal or a
. 1 M W O W O
W O
WW .100Y.C M.TW ceramicW
W
resonator mayY.Cbe used. .TW WW .100Y.C M.TW
W . 100 O M W O
W O
WW .100Y.C M.TWThis Crystal WWOscillator 0 0 Y.isCa low.T W oscillator,
power WW with.1reduced 0 0Y.C voltage W
M.T swing on the XTAL2 out-
W . 1 O M W C O
W O W lowest .C consumption, WW Y. of driving W
WW .100Y.C M.TW put. It gives Wthe . 100
Ypower
M .TW but is not 1capable
W . 00 O M.T other clock inputs, and
W O C
W
WW .100Y.C M.TW
O may be more susceptible
WW .100Y.to C noise TinWnoisy environments.
. WW .100Y. M.T
W
W O M W C O
W
WW .100Y.C M.C1
O
TWand C2 should WW always Y.beC equalTfor
. W both crystals WW and 0Y.
.10resonators.
W
M.TThe optimal value of the
W . 100 O M W C O
W O capacitors depends
WW on.1the .C
crystal or resonator inW W the amount
use, Y. of stray Wcapacitance, and the
WW .100Y.C Melectromagnetic
.TW 00Y M .TW W .100 O M.T
noise W of the O
environment. Some initial guidelines C for choosing capacitors for
W
WW .100Y.C use
O
.T W crystals Ware W 0 Y.C
0in . TWFor ceramic WW .100Y. M .TW
with .1
given Table M 8-3. resonators, the capacitor values given by
W W .C OM
W W W Y .CO .TW W WW 00Y.CO .TW
W 00 Y .T
the manufacturer W should be 0
.10used. M .1 M
W 00 .T W .1 M
W.1 Y.CFigure
OM 8-4. Crystal W W.1 Y
Oscillator .CO .TW
M
Connections WW 00Y.CO .TW
W W W 0 W .1
W 00
W.1 Y.COM W
.T .10 OM WW 00Y.CO .TW
M
W W WW 00Y.CC2 .T W W
W 00 .T .1 M .1 M
XTAL2
W 00 .T W .1 M .1 M
W W.1 Y.COM W WW 00YC1 .CO .TW W WW 00Y.CO .TW
W 00 .T W .1 M .1 M
XTAL1
W WW 00Y.CO .TW
W 00 .T W .1 M .1 M
W 00 .T W .1 M GND . 1 M
W 00 .T W .1 M . 1 M
W 0 0 .T W .1 M . 1 M
W 0 0 .T W .1 M . 1 M
W.1 Y.COM W WW in three Y .CO .TW W WW 00Y.CO .TW
WWThe Low 0 Power M. T
Oscillator can W
operate 0 0 different modes, each optimized
W. 1 for a specific
M fre-
W .10
.C O W W.1 Y.COM W W 0 Y .CO W
W
Wquency.10range. 0Y The operating
.TW mode W is selected 00 by the fuses .T CKSEL3..1 asWshown W .10 in Table T
M. 8-3.
W .C OM W W.1 Y.COM W W 0 Y .CO .TW
W .TW Crystal W 00 W 0
WTable 8-3. 00Y W.1 Operating OMModes
.T (3) W.1 Y.COM W
W W.1 Y.Low C OM Power
W
Oscillator
W Y .C W W W 00 .T
W
W .100 O M.T
W
W .100 O M.T
Recommended Range W W .1Capacitors
for .C O M C1
WWFrequency Y.C (1) W W Y.C W andW C2 (pF) .100
Y .TW
W .100 Range O M.T(MHz)
WCKSEL3..1
W .100 O M.T W W .C OM
Y.C WW Y. C W Y .TW
WW .1000.4 - 0.9 M.TW 100(2).100
W O M.T
W
– W .100 OM
W O C W .C
WW .100.9 0Y-.C 3.0 M.TW WW 101 .100
Y.
M.T
W W .100
Y .TW
W O W C O 12 - 22
W W .C OM
WW .3.0 Y.C W W Y. W W .100
Y
W 100- 8.0 OM.T
W110
W .100 O M.T 12 - 22
W W
Y.C WW .100Y. C W W
WW 8.0 .10- 016.0 OM.T
W
111 W M.T 12 - 22
W C O
W
Notes: 1. The W frequency O
ranges are preliminary W
values. Actual C O
values are TBD.
2. This W option shouldOnot be used with crystals, Wonly with ceramic resonators.
WW .100Y.C M.TW WW
W O
WW .100Y.C M.TW
W O
WW .100Y.C 30
W W
7799D–AVR–11/10 W
.C OM
00Y .TW
W W.1 Y.COM W
W 00 .T
3. If 8 MHz frequency exceeds
W W.1the specification.C OM of the device (depends on VCC), the CKDIV8
Fuse M TWbe programmed
.can W in order .
Y
100 to divide M .TW
the internal frequency by 8. It must be ensured
C O the resulting dividedW W .C O
Y . that W W clock meets 0 Y the frequency
.T W specification of the device.
. 1 00 M .T W . 10 O M
W CKSEL0
The O
.C Fuse .together withW theW SUT1..0 .C
YFuses select
WW 1 00Y M TW . 100 M .TW the start-up times as shown in Table
8-4. W . O W O
M W O W O
0 Y.C
O
0
W.1 OM W .CO .Times WW 00Y.CO .TW
WW .100Y.C M.TW WW 8-4..100YStart-up
Table M T W for theWLow Power.1 CrystalMOscillator Clock Selection
W W .C O
Y W
W 00
W.1 Y.COM W
.T .1 OM Start-up Time from W.1 Y.C OM
Additional Delay
W Oscillator
W WW Source 0 Y .C/ .T W Power-down W Wand 0 0 from .T W
Reset
W 00 .T 0
W.1 Y.COM W Power-save .1 OCC M = 5.0V)
W.1 Y.COM W PowerW Conditions
W WW 00Y.C(V W CKSEL0 SUT1..0
W W
.1 00 M .T W
W . 1 0 0
O M .T
W .1 O M.T
W O CeramicW resonator, fast
0Y.C M.TW 258 CKW
W Y.C 4.1.Tms W(1)
WW .100Y.C M.TW rising W power W.10 W .100 14CKO+M 0 00
W O W .C O W Y .C W
WW .100Y.C M.TW CeramicWresonator, 0Y
.10slowly .TW W
W.1 14CK
00 M.T (1)
W C O W W .C OM 258 CK W Y .C O65
+ ms W 0 01
WW .100Y. M .TW rising power W . 100
Y
M .TW W
W .100 O M.T
W O C
W O
WW .100Y.C M.TWCeramic resonator, WW .1BOD 00Y
.C .TW WW .100Y. (2)M.TW
W O M 1K CK W 14CKO 0 10
W
WW .100Y.C M.TW
O enabled WW
00Y
. 1 M
W O W .CO .TW WW 14CK
W .CO .TW
WW .100Y.C M.TCeramic W WW fast
resonator,
. 1 00Y M 1K CK . 1 00+Y4.1 msM (2)
0 11
W O rising power W C O W W .C O
W Y .C W W W 0 Y . .T W W 0 0 Y .T W
W 00
W.1 Y.COM Ceramic
.T
resonator,W
0
W.1 Y.COM W
slowly W14CK W.1 Y.CO M
W
W W W 0 1K .T CK W .1+0 0
65 ms (2)
M.T 1 00
W . 1 00 M .T power
rising W .10 O M W C O
W CO W .C W W Y . W
WW .100Y. W
M.T Oscillator, BOD
Crystal
W .100
Y
M.T
W .100
W14CK OM
.T
W C O W W .C O16K CK W Y .C W 1 01
WW .100Y. enabled M .TW W . 100
Y
M .TW W
W .100 O M.T
W O C
W
WW .100Y.C Crystal
O
W
.TOscillator, fastWW .100Y.C M.TW WW .100Y. M.T1
W
M W 16K O CK 14CK W
+ 4.1 ms C O 10
W
WW .100Y.CrisingMpower
O
W O
W CO Oscillator, WW .100Y
WW .100Y.Crystal .T W slowly
16K CK M 14CK + 65 ms 1 11
W W rising
.C OM power
W 00 Y .T W .1
W.1 Notes: OM .1 M WWto the OM
W .C 1. These options shouldWWonly0be Y .COwhen
used W
not operating W close 0 Y.C
maximum .TW
W . 1 00 Y
M .T W W
W . 0
1 stability O M .T
W .1 0
O Mfrequency of the
W .C O device, and only if frequency
W .C at start-up
W is not important
W for the
Y .Capplication. W These
WW .100Y .TW are not suitable W 00Y .T W 00 .T
W O Moptions W for.1crystals.
.C OM W W.1 Y.COM W
.C W Y with ceramic W W and will.1ensure 00 .T stability
WW .100Y 2. These W
M.T options are intended
W 00use
.1for .T resonators OM
frequency
W O Wbe C OM W W .C
WW .100Y .C at start-up.
.TW
They can W W
also used
100
Y .
with crystals
M .T W when not W
operating 0
closeY to
.10 for the
the .TW fre-
maximum
Mapplication.
O M
quency of the device, and W
if .
frequency O
stability at start-up is not W
important .C O
W
W
O W O W .C O
W
WWTable.108-5. 0Y.C Start-up .TW times forWthe internal
W .C
Ycalibrated .TRC W Oscillator WW 100
clock .selectionY
M.T
W
M W . 100 O M W C O
W O W .
WW .100Y.C M.TW WW Time
Start-up
. 0Y.CPower-
10from M .TW Additional W Delay.1from 00Y M.T
W
W Conditions O W O W W .C O
Power
WW .100Y.C M.TW
downW and Power-save Y.C W Reset W (VCC = 5.0V)0Y
.10
SUT1..0
M.T
W
W O
W
W .100 O M.T W W .C O
WW .100Y.C M.TW
BOD enabled
WW6 CK.100Y.C M.TW 14CK
W .100
Y 00 .TW
M
W O W O W W .C O
Fast .C W .C W Y 01 .TW
WWrising.1power 0 Y
M. T W W 6 CK
0 0 Y .T 14CK +W 4.1 ms
W. 10 0
OM
0 W.1 Y.COM W14CK + 65 ms
WWrising
Slowly W power
0 Y .CO .TW W 6WCK 0 0 .T WW(1) .100Y.C10 M.TW
W.1
0
OM W.1 OM W O
Reserved WW .100Y.C 11 M.TW
Note: WW 1. W The device .COis shipped W with this WW selected.
option Y .CO .TW W WW 00Y.CO
0 Y .T W 0 0 .1
0
W.1 Y.COM W W W.1 Y.COM W WW
W W 00 .T W
W 00 .T W.1 Y.COM W
W W.1 Y.COM W W
W 00 .T W 00 .T
W.1 Y.COM W W W.1 Y.COM
W W 00 .T W 00
W.1 Y.COM W W W.1
W W 00 .T W
W W.1 Y.COM W
W 00 .T
W W.1 Y.COM
W 00
W W.1 31
7799D–AVR–11/10 W
.C OM
00Y .TW
W W.1 Y.COM W
W 00 .T
8.5 Full Swing Crystal OscillatorW W W.1 Y.COM W
T
M.XTAL2
W 100
W.output, OM
.T
Pins XTAL1 C Oand are input W
and .Crespectively,
1
.
00Y for use M .TasW W .
Y
100 as shown M .TW of an inverting amplifier which can be
W .
configured O an On-chip W
Oscillator, O in Figure 8-4. Either a quartz crystal or a
WWceramic 0 0 Y.C
resonator .T
mayWbe used.WW .100Y.C M.TW
. 1 M W O
W WW 00Y.CO .TW
WThis WW .100Y.C M.TW
.T . 1
Crystal OM is a full swing oscillator,
Oscillator W with O rail-to-rail swing on the XTAL2 output. This is
OM WWfor 0driving Y.C other WW 0Y.C environments.
.TW
00 Y.C .T W W
useful . 1 0 M .T W
clock inputs and in
. 1 0noisy M The current consumption is
.1 M O W O
W W Y.C O
W W WWthan00the
higher Y .C“Low Power W CrystalW W
Oscillator” 0 0 Yon.C page .T W
30. Note that the Full Swing Crystal
W
W .100 O M.T Oscillator W O M.T for V = 2.7W
.1will only operate - W.1volts.Y.COM W
5.5
WW .100Y .C
WW .100Y.C M.TW W .100
CC W
M.T .T
W O C1 and W
C2 should C O
always be equal for W
both Wcrystals .C OMresonators. The optimal value of the
and
WW .100Y.C M.TW W W
100
Y .
M .TW W 0
10use,
.in
Y
M .TW
capacitors W .
depends on
O the crystal or resonator W O
the amount of stray capacitance, and the
W O
WW .100Y.C M.TW electromagnetic WW .100noise Y.C of the .T Wenvironment. WWSome . 1 0 0Y.C guidelines
initial M .TW for choosing capacitors for
W OM WW resonators, O
W O
WW .100Y.C M.TW use with WW crystals 0 Y.C
are
0 W 1. ForW
given in.TTable ceramic . 1 0 0Y.C Mthe .TWcapacitor values given by the
W . 1 O M W O
W
WW .100Y.C M.TW
O manufacturer WW should .C used..TW
Ybe WW .100Y.C M.TW
W . 100 O M W O
W
WW .100Y.C M.TW
O
W O W O
W
WW .100Y.C M.TW
O
W O W O
W
WW .100Y.C M.TW
O
W O W O
W
WW .100Y.C M.TW
O
W O W O
W
WW .100Y.C M.TW
O
W O W O
W
WW .100Y.C M.TW
O
W O W O
W
WW .100Y.C M.TW
O
W O W O
W
WW .100Y.C M.TW
O
W O W O
W O
W O W O
W
WW .100Y.C M.TW
O
W O W O
W O
W O W O
W
WW .100Y.C M.TW
O
W O W O
W
WW .100Y.C M.TW
O
W O W O
W
WW .100Y.C M.TW
O
W W .C O
Y W
W
.C W
WW .100Y M .TW W
W . 100 O M .T W
W .100 OM
.T
WW .100Y M .TW W
W .100 O M .T W .10 O M.T
W O WW .100Y .C
W
W O W O W W .C O
Y
M.T
W
W O W O W W .C O
Y
M.T
W
W O W O W W .C O
Y
M.T
W
W O W O W W .C O
Y .TW
W O W C O W W .C OM
W W .100
Y .TW
W O W C O W W .C OM
W W .100
Y .TW
W O W C O W W .C OM
W W .100
Y
W O W C O W W
W W
W O W C O
W
W O W C O
W O W
WW .100Y.C M.TW WW
W O
WW .100Y.C M.TW
W O
WW .100Y.C 32
W W
7799D–AVR–11/10 W
.C OM
00Y .TW
W W.1 Y.COM W
W 100
W.Swing
.T
OM Oscillator Clock Selection
Table 1. Start-up Times for the W Full C
Crystal
.
M .TW W . 100
Y
M .TW
W O
.CO .TW Start-up WWTime.from Y.C Additional .TWReset Delay
. 1
Oscillator00Y Source M / Power-down W 100
and O Mfrom
W O
WWPower 0Y.C M.TW
0Conditions WW .100Y.C (VMCC.T=W
Power-save 5.0V) CKSEL0 SUT1..0
. 1
W W W Y .C O
W W WW 00Y.CO .TW (1)
.T W Ceramic 0
.10resonator, .T
fast 258 CK .1 14CKM+ 4.1 ms 0 00
COM W
rising Wpower .C OM WW 00Y.CO .TW
Y. W W 0 Y W W
00
W.1 Y.COM W
.T .10 M.T .1
WW 00Y14CK
M
.CO + 65.Tms
W WW resonator,
Ceramic
W 0 Y .CO .TW 258 CK W W(1) 0 01
W .100 M .T . 1 0 M W . 1 O M
W O slowly W
rising power . C O W Y .C W
W W 00 .T
W O Ceramic Wresonator, .C O 1K CK W W.1 Y.14CK C OM(2)
W 0 10
W
WW .100Y.C M.TW BOD W enabled . 100
Y
M .TW W
W .100 O M.T
W O
W
WW .100Y.C M.TW
O
WWresonator, Y.C W WW .100Y.C M.(2) TW
Ceramic W . 100 fast OM.T 1K CK W 14CK + O
4.1 ms 0 11
W O
WW .100Y.C M.TW rising W
W
power 0 0 Y.C .T W WW .100Y.C M.TW
. 1 M
W O WW 00Y.CO .TW WW 14CK
W
0+Y65.CO (2) .TW
WW .100Y.C M.TW CeramicWresonator, 1 M 1K CK . 1 0 ms M 1 00
W .C O slowly rising W.
Wpower Y .CO .TW WW 00Y.CO .TW
W Y W W 0 W .1
W 00 .T
W.1 Y.COM WCrystal Oscillator, .10 M WW 14CK
M
.CO .TW
W W WW BOD 0 Y .CO 16K .T W CK W 0 0 Y 01
W
W .100 O M.T enabled W .10
.C OM W W.1 Y.COM W 1
C W .TW
WW .100Y. W
M.T Crystal Oscillator,
W .100
Y W 00
W.+1 4.1 Y OM
.T
W C O W W
fast .C OM 16K CK W
14CK ms.C W 10
WW .100Y. M
W power W
.Trising . 100
Y
M .TW W
W .100 O M.T1
W O C
W O
WW .100Y.C M.Crystal TW Oscillator, WW .100Y.C M.TW WW .100Y. M.T
W
W 16K
O CK 14CK W
+ 65 ms C O 11
W
WW .100Y.C Mslowly
O
.TW rising power WW .100Y.C M.TW WW .100Y. M
1.TW
W O
W O WW 00Y.CO .TW WW .100Y.C M.TW
WW .100Y.C Notes: . T W1. TheseW options . 1
should only M
be used when not operating close to the
O maximum frequency of the
W .C OM WonlyW Y .CO stability W W WisWnot important
0 Y.C for .the W
W W
. 1 00 Y
M .T W device, Wand
W . if
10 0
frequency
O M .T at start-up
W .1 0
O M T application. These
W O options are W not suitableYfor .C crystals. WW .100Y. C W
WW .100Y.C M.TW W .100 whenOnot M .TW W O M.T of the device, and
TheyO can also be used with W
crystals operating close to the maximum .Cfrequency
W
WW .100Y.ifCfrequency .TWstability at start-up WW is.1not 00Y
.C TW
.for WW 00Y M.T
W
M W importantO M the application. W.1 C O
W
WW .100Y.C M.TW
O
W
W O W .C O
W
WW Internal .CO .Oscillator TW WW .100Y.C M.TW WW .100Y M.T
W
8.6 Calibrated . 1 00Y RC M W O W .C O
W
WW .10By .CO the .TWInternal RC
W Y.C .TW WW 00Y Though W
M.T voltage and
0Ydefault, M
WOscillator
W . 100provides O M an approximate 8 MHz.1clock.
W C O
W .CO dependent, .C very accurately WW by .
0Y the user. W
WW .temperature00Y .TW WW
this clock can
.100
Ybe
M .TW calibrated
.10the M.T See Table
1
W 26-1 Y O M W O W
W CKDIV8 .C O
on .Cpage 266 for more details.
WW .The .C
Ydevice is shipped
.TW
withWthe YFuse programmed. W
WW See . 1 00“SystemMClock .TW Prescaler” on W page10035 forOmore M details. W .100 O M.T
W O WW .100Y .C
W
W O W O W
theWCKSEL0Fuses .C O
This clock may be selected as the
WW .100Y.C M.TW WWsystem Y.C by programming
0clock .TW W 0 Y
.1reset,
as .shownW in
M T loads
Table 8-6. If selected, it will operate W .
with10no externalO M components. During W O
hardware
C
W O WW .100Y .
WWthe pre-programmed
00Y
.C .TW calibrationW
W
valueW .
into 0Y.C
10the OSCCAL M .TW Register and thereby automatically M.T cal-
W
.1 O M O W W .C O
WW the
Wibrates .C
00YRC Oscillator. .TW The accuracy WW .1of 00thisY.C calibration .TW is shown W as Factory Y
.100 calibration M.T in
W
. 1 O M W O M W W .C O
WW26-1
Table Y.Cpage 266.
on W WW .100Y.C M.TW W .100
Y
M.T
W
W
W .100 O M.T W .C O W W Y .C O
W
WW Y.C W WW .1see 00Y“OSCCAL W W
M.T – Oscillator Calibration .100 Register” M.Ton
By changing
W .100 the OSCCAL O M.T register fromWSW, W O W W .C O
WW38, it.1is
page Y.C W a higherWcalibration Y.C W by using Wthe factory Y
.100 calibration. .TW
00possible M
to
.Tget W .100 accuracy O M.T than
W .C OM
W O Y. C W Y .TW
WW .100Y.C M.TW
The accuracy of this calibration is shown WW as User 0calibration
.10 M.T
inW Table 26-1 Won page .100
266.
W O W C O W W .C OM
When Wthis W Oscillator Y.C is used W as the chipWclock, W the Y. W W 00Y for the .TW
W . 100 O M.T W .100Watchdog O M.TOscillator will still W
be.1used
W .C OM
Watchdog Y.Cfor the.TReset WW For.1more .C Y cali-
WW Timer and
100 the section
.see
W Time-out.
M “Calibration Byte” 00Y information M.T
W on the pre-programmed
W
W .100
bration value, W O W on page C O
249. W
W W
W O W C O
WW Internal Y.C WRC Oscillator WWOperating Y. (3)W
Table 8-6.
W .100
Calibrated
O M.T W .100 Modes O M.T
Y.C Range W Y. C
WW Frequency .100 M.T
W (2)
(MHz) W .100 CKSEL3..0
W .C O W W
W Y 8.1.TW W 0010(1)
W
W .100 7.3O- M
WW .100Y.C M.TW
W O
WW .100Y.C 33
W W
7799D–AVR–11/10 W
.C OM
00Y .TW
W W.1 Y.COM W
Notes: 1. The device is shipped with
W .100option selected.
Wthis OM
.T
W Y .C W
2. The M .TW
frequency ranges
Ware preliminary
W . 100 values.
O M .TActual values are TBD.
O
0 0 Y.CIf 8 MHz
3. .T W
frequency WW the.1specification
exceeds 0 0Y.C Mof . W
Tthe device (depends on VCC), the CKDIV8
W W.1 Y.Fuse C OMcan be programmedW
W in
W
order 0
to Y .CO the .internal
divide W frequency by 8.
W 0 T
W
W .100 O M.T W W.1times .C OM
When
WW .100Y this .C
Oscillator is selected, start-up Y are W
determined by the SUT Fuses as shown in
M .TW M .TW W
W . 100 O M .T
TableW8-5 on page 31. O
100Y O
W . O M W .C O WW calibrated 0Y.C RC W
WW .100Y.C M.TW WW 8-7..100YStart-up
Table
M .T W for the W
times internal . 10 M .TOscillator clock selection
W O W C O W W .C O
WW .100Y . Y W
WW .100Y.C M.TW W
M.T Start-up Time
W from 0
0Power-
W.1 Y.COM W
.TAdditional Delay from
W O Power W W
Conditions . C O down and W Power-save Reset (VCC = 5.0V) SUT1..0
WW .100Y.C M.TW W . 100
Y
M .TW W
W .100 O M.T
W O W O W Y.C
WW .100Y.C M.TW
BODW W
enabled Y.C .TW 6 CK
W .100 M.T
W 14 CK 00
W . 100 O M W C O
W O W .C W Y. W
WW .100Y.C M.TW Fast rising W power .100
Y
M.T
W 6W CK 00
W.1 Y.COM W
.T14 CK + 4.1 ms 01
W O W W .C O W
WW .100Y.C M.TW Slowly W rising power00Y .TW W 00 .TCK + 65 ms (1)
6 CK 14 10
W O W .1
. C OM W W.1 Y.COM W
C W .TW Reserved
WW .100Y. M.T
W W .100
Y W 00
W.1 Y.COM W
.T 11
W CO W W .C OM W
WW .100Y. W W
M.T Note: 1. TheWdevice
Y
.100is shipped .TW W 00
W.1 Y.COM W
.T
W CO W .C OMwith this option selected. W
WW .100Y. M.T
W W .100
Y .TW W 00
W.1 Y.COM W
.T
W CO W W .C OM W
WW .100Y. M.T
W W .100
Y .TW W 00
W.1 Y.COM W
.T
W CO W W .C OM W
WW .100Y. M.T
W W .100
Y .TW W 00
W.1 Y.COM W
.T
W CO W W .C OM W
WW .100Y. M.T
W W .100
Y .TW W 00
W.1 Y.COM W
.T
W C O W W .C OM W
WW .100Y. M.T
W W .100
Y .TW W 00
W.1 Y.COM W
.T
W C O W W .C OM W
WW .100Y. M.T
W W .100
Y .TW W 00
W.1 Y.COM W
.T
W C O W W .C OM W
WW .100Y. M.T
W W .100
Y .TW W 00
W.1 Y.COM W
.T
W CO W W .C OM W
WW .100Y. M.T
W W .100
Y .TW W 00
W.1 Y.COM W
.T
W C O W W . C OM W
WW .100Y. M.T
W W 00Y .TW W 00
W.1 Y.COM W
.T
WW .100Y W W 00 .T W 00 .T
.C W W 00 .T
WW .100Y M.T
WW .100Y W W 00 .T W 00 .T
. C W W 00 .T
WW .100Y M.T
WW .100Y W W 00 .T W 0 .T
.C W W 0 .T
WW .100Y M.T
W W 00 .T 0
W.1 Y.COM W
WW .100Y .TW W .10 M.T
M
W
W . 100 O M .T W C O
W O W .
Y
M.T
W
W O W O W W .C O
Y
M.T
W
W O W O W W .C O
Y
M.T
W
W O W O W W .C O
Y .TW
W O W C O W W .C OM
W W .100
Y .TW
W O W C O W W .C OM
W W .100
Y .TW
W O W C O W W .C OM
W W .100
Y
W O W C O W W
W W
W O W C O
W
W O W C O
W O W
WW .100Y.C M.TW WW
W O
WW .100Y.C M.TW
W O
WW .100Y.C 34
W W
7799D–AVR–11/10 W
.C OM
00Y .TW
W W.1 Y.COM W
W 00 .T
8.7 External Clock W W.1 Y.COM W
.TW W 00
W.1source
.T
OMshown in Figure 8-5. To run the device on an
The deviceCcan OMutilize a external W clock .C as
external 1 00Y
.
clock, the
M
W
.TCKSEL Fuses
W must .be Y
100programmed M .TW as shown in Table 8-1.
W . O W W .C O
W Y .C W W 0 Y .T W
W . 1 00 M .T W . 10 O M
WW 8-5. O Y.C
.TW WFigure .C
00Y External .TW Clock Drive WW Configuration
. 100 M .TW
M W . 1 O M W O
00Y
W .1 OM W O WW 00Y.CO .TW
WW .100Y.C M.TW WW .100Y.C M.TW NC W .1 M
XTAL2
W W .C O
W 00 Y .T W .1 M .1 M
W W.1 Y.COM W WW 00Y.CO .EXTERNAL W W WW 00Y.CO .TW
W 00 .T W .1 T
M CLOCK .1 M
W.1 Y.COM W WW 00Y.CO .TW W WW 00Y.XTAL1 CO W
W W
.1 00 M .T W
W . 1 O M SIGNAL W .1 O M.T
W
WW .100Y.C M.TW
O
W O W O
W O
WW .100Y.C M.TW WW .100GND Y.C W
W O C
W
WW .100Y.C M.TW
O
W
W O W C O
W
WW .100Y.C M.TW
O
W
W O W C O
W
WW .100Y.C M.TWhen
O
W this clock WWsource Y.C W WW .100Y. M.theTW
W . 100is selected, O M .Tstart-up times are W determined C O by SUT Fuses as shown in
W
WW .100Y.C M.Table
O
TW 8-8. W
W 00Y
.C .TW WW .100Y. M .TW
W . 1 O M W O
W
WW .100Y.C M.TW
O
W O W CO WW 00Y.CO .TW
WW .100Y.C Table .T W8-8. WW Times
Start-up .1 0 0Y.for the M . TW
External Clock
WSelection .1 M
W W .C OM
W 00 Y .T W MTime from Power- WW.1Additional
W.1 Y.COM Power .1 Start-up OM Delay from
W W Conditions W WW 00Ydown .CO and.TPower-save W W 0 0
ResetY.C(V = .5.0V) TW SUT1..0
W . 1 00 M .T W . 1 O M W .1 OCCM
W C O W . C W Y .C W
WW .100Y. BOD W W .100
Y TW
6 .CK W 00 .T
W O M.T
enabled
W .C OM W W.1 Y14CK .C OM
W
00
C W .TW
WW .100Y. Fast M .TWpower
rising W .100
Y 6 CK W 00
W.114CKY+.C4.1 OM ms.T 01
W C O W W .C OM W W
W Y . W W 0 Y .T W W 0 0
.1 + 65 ms .T
W 00 Slowly rising
W.1 Y.COM W
.T power .10 6M CK 14CK
WW 00Y.CO .TW
M 10
W W WW 00Y.CO .TW W
W 00 .T .1 Reserved M .1 M 11
W
W 0
0When
W.1 Y.COM W
applying .T an external clock, .1it is required OM to avoid sudden W W.1 inYthe
changes M
.COapplied clock fre-
W quency to ensure stable W WW of
operation 0 Y
the
.CMCU. .TA W variation W
in frequency 1 0 0 of more .T
than
W2% from
W 100
W.one M.T .10 M W. CO
M
.C Ocycle WW Y .CO .TW behavior. W W 0 Y.of W 2% is
W W
. 1 00
clock
Y
M .T to
W the next Wcan lead
W . 10to0 unpredictable
O M
If changes
W . 1 0 more
O M.T than
O
Wrequired, ensure that the MCU W Y.C during WW .100Y .C W
WW .100Y.C M.TW Wis kept.1in00Reset M .TW
the changes.
M.T
O W O W . C O
W that
WW Note .C WW can Y.C W WW changes .100
Y of the.Tinternal W
. 1 00Y the System M .TWClock Prescaler W .100be used O M
to.Timplement run-time
W .C O M
clock O
W frequency while still ensuringWstable operation. Y.C ReferW to “System WWClock Prescaler”
Y onW
page
WW .100Y.C M.TW W .100 M.T W .100 O M.T
35W for details. O W O W .C
Y
M.T
W
O W O W W . C O
WW 00Y.C W WW .100Y.C M.TW W .100
Y
M.T
W
8.8 Clock Output W Buffer W .1 O M.T W O W W .C O
Y.C WW on.1the .C .TWTo enableWthe output, Y W
WWdevice
The .100can output
W
M.Tthe system clock W
00YCLKOMpin.
O W .100 the CKOUT O M.T
W O Y.C W .C
WWhas to .C W This mode WWis suitable .TW Wused to.1drive 00Y otherMcir- .TW
Fuse
W .100
beYprogrammed.
O M.T W .100 when O Mthe chip clock is
W W .C O
.C The.T WW .C Wand the normal Y of I/O.TW
cuitsWW on the system.
. 1 00Y M
clock
W also will be output
W .100
Y
during
O
reset,
M.T
W
W .100
operation
OM
pin willW W
be overridden
Y
O
.C when.Tthe W fuse is programmed.
W W 0 YAnyC
. clock .T source,
W W
including
W Y.C RC.TW
the 0internal
0
W 0
.10be selected 0
.1 on CLKO. 1
W. Prescaler OM
Oscillator, W can M is W OM If the System Clock
W W 0 Y .CO .when T W
the clock W
W
output
0 0 Y.C .T W WW .100Y.C
is
used, it is the .divided 1 0 systemM clock that is output. W .1 O M W
W O WW
W O W O
8.9 System Clock Prescaler WW .100Y.C M.TW WW .100Y.C M.TW
W O W
WW prescaler, .CO
WW .100Y.C M
The ATmega8U2/16U2/32U2 .TW
has a system clock .1 00Y and the system clock can be divided
W O W
by setting W theW“CLKPR
00Y
–.CClock Prescale Register”
.TW WW on page 39. This feature can be used to
W . 1 O M
WW .100Y.C M.TW
W O
WW .100Y.C 35
W W
7799D–AVR–11/10 W
.C OM
00Y .TW
W W.1 Y.COM W
W 00 M.T consumption when the requirement for pro-
decrease the system clock frequency W W.1and Y the.C O
power
cessing power M is
W
.Tlow. This can
Wbe used . 0 all clock
10with M .TW source options, and it will affect the clock
C O W W .C O
Y . W W 0 Y .T W
frequency
. 1 00 of theMCPU .T and all synchronous W . 10 peripherals. O M clkI/O, clkCPU, and clkFLASH are divided by
W W asYshown .C O W 40.00Y.C W
W a factor 00 in
.T W
Table 8-9 on W page
. 1 M .T
. 1 O M W O
WW switching 00Y
.C between .TW prescaler WW settings, Y.C
100 theOSystem .TW Clock Prescaler ensures that no
M .TW WWhen . 1 O M W . M
.CO .TW WW occurs
glitches .C
00Y in the TW system.WIt also ensures
.clock
W
100
Y.C that no W
.Tintermediate frequency is higher than
.100Y M
W
W . 1 O M W .
.C O M
W O neither the clock .C frequency corresponding W to the Yprevious setting,
W nor the clock frequency corre-
WW .100Y.C M.TW WW .100Y M .TW W . 100 M .T
sponding W to the new O setting. W O
W
WW .100Y.C M.TW
O
W O WW 00runs O
W O The ripple
WW counter Y.Cthat implements theWprescaler Y.C at the.Tfrequency
W of the undivided clock,
WW .100Y.C M.TW . 1 0 0 M .T W
W . 1 O M it is not possible to determine the
which may W be faster O
than the CPU's clock frequency. Hence,
W O
WW .100Y.C M.TW state W
W Y.C .TW WW .100Y.C M.TW
of the . 100
prescaler - M
even if it were readable, W and the exact time it takes to switch from one
W O W .C O
WW 0YFrom.CO W
WW .100Y.C M.TW clock division WW to.1the 00Yother cannot M .T W be exactly predicted.. 1 0 M.T
the time the CLKPS values are writ-
W O W O
W O
WWbetween Y.C Wbefore00the Y.Cnew clock W
WW .100Y.C M.TW ten, it takes . 100 T1 +OT2 M .TandW T1 + 2 *WT2
W .1 O M.T frequency is active. In this
W O W
W clock .C W T1 is C
Y. previous Wclock period, and T2 is the
WW .100Y.C M.TW
interval, 2Wactive
. 1 00YedgesMare .TW produced. W Here,
W .100
the
O M.T
W O C
W
WW .100Y.C M.TW
O period corresponding
WW .100Y.C M.TW
to the new prescaler setting. WW .100Y. M.T
W
W O W C O
W O
WW .100changes Y.C WW a special Y. write procedure
W
WW .100Y.C M.TTo W avoid unintentional M
of.Tclock
W frequency,
W .100 O M.T
must be followed
W O C
W
WW .100Y.C M.TW
O to change the CLKPS
WW .100Y.C M.TW
bits: WW .100Y. M.T
W
W O W C O
W
WW .100Y.C M.1.
O
TWWrite theWClock Prescaler
W Y.C Change .TWEnable (CLKPCE) WW .10bit 0Yto. oneM and.TW all other bits in
CLKPR to zero. W . 100 O M W C O
W
WW .100Y.C M.TW
O
Ma.Tzero to CLKPCE.
2. Within four cycles, W write the O desired value to CLKPS W while O
writing
C
W O
WW .100Y.C Interrupts .TW must be WW .100Y.C M.TW WW .100Y. M.T
W
M disabled
W when changing
O prescaler setting W to make C O
sure the write procedure is
W
WW .100Y.C notM
O
interrupted. W O W O
W
WW .100Y.C M.TW
O
W O W O
8.10 PLLWW
W
0 Y.C
O
0 O
W.1 M
.COPLL .is W
0Y.ChighM
O WWclock Y.CUSB interface, W
WW .100Y The T Wused to generate WW internal .1 0 TW
frequency
. (48 W MHz) . 1 00for M.T the PLL
W O M W C O W W .C O
input.C is generated from anW external .
low-frequency W (the crystal oscillatorY or external W clock input
WW .100Y M .TW W
W .100
Y
O M .T W
W .100 O M.T
W pin from O XTAL1). WW .100Y .C
W
O W O W .C O
8.10.1 WWfor 0USB
InternalWPLL 0Y.Cinterface .TW WW .100Y.C M.TW WW .100Y M.T
W
.1 O M W O W .C O
WW The
W Y.C .TWin ATmega8U2/16U2/32U2WW .100Y.C generates .TW a clock WW Y
.100 that O
W
.Tmultiplied
. 1 00internal M
PLL
W O M frequency
W .C
isM 6x
W O C 8 MHz
ofY.the W is the00outputY W
WW from 00Y
.C
nominally 8TMHz
. W input. The WWsource . 100 M .TW PLL input W clock
.1 M.T internal
of the
. 1 O M W O W .C O
W
PLL clock prescaler that generates
WW .100Y.C M.TW WW the.180MHz. 0Y.C M.TW WW .100Y M.T
W
O W O W .C O
W
W
W O W O W W .C O
Y
M.T
W
W O W O W W .C O
Y
M.T
W
W O W O W W .C O
Y
M.T
W
W O W O W W .C O
Y .TW
W O W C O W W .C OM
W W .100
Y .TW
W O W C O W W .C OM
W W .100
Y .TW
W O W C O W W .C OM
W W .100
Y
W O W C O W W
W W
W O W C O
W
W O W C O
W O W
WW .100Y.C M.TW WW
W O
WW .100Y.C M.TW
W O
WW .100Y.C 36
W W
7799D–AVR–11/10 W
.C OM
00Y .TW
W W.1 Y.COM W
W 00 .T
Figure 8-6. PLL Clocking System W W.1 Y.COM W
.TW W 00
W.1 Y.COM W
.T
.C OM W
Y W W 00 .T
WW .100Y .C W
M.T
W 100
W.PINDIV OM
.T PLLE
PLOCK PLLITM
W W .C O W Y .C W
.T W W 00 Y .T W CKSEL3:0
W .1 0 0 M .T
.COM W W.1 Y.COM W WW 00Y.CO .TW /48 1
Y W W 0 0 .T W 1
.100 M .T W . 1 O M W . O M TclkTimer1
W O
WW .100Y.C M.TW WW .100Y.C Detector .TW
Lock
WW .100Y.C M.TW W O M T1 0
W O
W
WW .100Y.C M.TW
O
WW .100XTAL
XTAL1 Y.C .T W WW .100Y.C M.TW
W O XTAL2 WW OSCILLATOR OM WW Y.C
O
WW .100Y.C M.TW W 0 0 Y.C .T W WPLL clock .100 M.T
W
W . 1 O M W O PLL /2 1
W
WW .100Y.C M.TW
O
WW RC OSCILLATOR 0 0 Y.C .T W WW .clk
Prescaler
1 0 0Y.C M.TW clk USB
8W
. 1 O M W 8MHz
C O
W O W MHz .C W Y . W
WW .100Y.C M.TW W 0
W .100
Y
M.T
W
To System W.1
00 .T
W O W C O W .C OM
W . Prescaler 00 PDIV3..0 .TW
Y
WW .100Y.C M.TW W . 100
Y
M .TW ClockW
.1 M
W W .C O
W W W Y .C O
W W WW 00Y.CO .TW PLLUSB
W 00 Y .T W . 10 0 M .T .1 M
. 1 M W O W C O
W
WW .100Y.C M.TW
O
W
W O W C O
W
WW Register .CO .TW WW .100Y.C M.TW WW .100Y. M.T
W
8.11 . 1 00Y Description
M W O W C O
W
WW .100Y.C M.TW
O
W
W O W C O
W
8.11.1WWCLKSEL0 .CO .TW W Y.C .TW WW .100Y. M.T
W
. 1 00Y – Clock
M
Selection W Register
W . 1000 O M W C O
W O
W7W .1060Y.C M WW Y. W 0
WW .100Y.C MBit.TW 5 .TW 4 3
W .1002 O M1.T
W O (0xD0) W O W EXTEY. C
WW .100Y.C Read/Write WW .100Y.C M.TW .TW CLKS CLKSEL0
RCSUT1 RCSUT0 EXSUT1 EXSUT0 RCE -
.TW W 00
.1R/W M
O M R/W W R/W O
R/W R/W R/W W .C O R R/W
W
WW .100Y.C Initial .T W 0W
W
0100
Y.C 0 .TW0 WW See . 1 0YDescription
0Bit M .TW
OM
Value
W . O M W O
W
W O
W • O Bit 7:6 – RCSUT[1:0]: W
WW SUT.10for 0YRC .COoscillator WW .100Y.C M.TW
WW .100Y.C M.TW M .TW
W .CO 2 bits
These are the SUTW W for Y
value the O RC Oscillator. If the WRC WW oscillator .CisOselected .TW by fuse bits,
WW .100Y .T W W .1 0 0 .C M.TW . 100Y M
the SUT
O M fuse are copied into Wthese bits. OA firmware change will Wnot have .any
C O effect because this
W Y.C
WW .100additionnal .T W WisWonly .used 0
.C
0Yafter .TW and not after WW .100Y M .TW
start-up time 1 aM reset aWclock switch. O
W OM W O
WW .100Y.C M.TW
W O – EXSUT[1:0]: SUT W O WW Oscillator .CO .TW
WW .•10Bit 0Y.C 5:4
T W WWfor .External 0 0Y.C Oscillator .TW / Low W Power 1 00Y
.
OMare the SUT value
1 M .
WW Oscillator. OM
W These .2Cbits Wfor W the External Y .CO Oscillator W / Low W Power 0 Y.C If the WExternal
W W
. 1 00 Y
M
W
.TPower Oscillator W W . 0 0 .T
1selectedObyMfuse bits, the SUT fuse W 1 0
. are copyed O M.Tinto these
Woscillator /
O Low is
Y.C WW .100Y .C
WW bits. 0Y.Cfirmware
0The .TWcan modify WtheseW
100 by writing M .TaWnew value. Mused.TW
W . 1 O M W .bits O This
W W value will .C O
be at the
W Y . C W W W 0 Y .C .T W W 00 Y .T W
W next.1start 0
0 of theMExternal .T Oscillator / Low 0 Power Oscillator. W. 1 OM
W.1 OM
W
WW .100Y.C M.TW
O
W O W O
• BitW 3 – RCE:
WW .100Y.C M.TW
O Enable RC Oscillator
TheWW RCE bit must .CO be.T written to logicW one W to enable O
Y.C the RC WOscillator.W TheWW RCE bit 0 .CO be.T
Ymust writ-
W
W 0 0 Y W W .1 0 0 M .T . 1 0 M
ten toW 1
. zero to
logic O M
disable the RC Oscillator. W O W W .C O
Y
M.T
W
W O W O W W .C O
•W BitW2 – EXTE: Y.CEnable.TExternal W WW .1/ 0Low
Oscillator 0Y.CPower W
M.TOscillator
W .100
Y .TW
W .100 O M W C O W W . C OM
W
TheWOSCE W bit 0must .C be written .TW to logicW
W to enable
one Y. External WOscillator /W Low Power Y
.100 Oscillator. M.T
W . 1 0 Y
O M W .100 O M.T W W .C O
The OSCE bit must be written to logic zero
WW to disable
Y. C the External Oscillator / Low Y Power.TW
WW 0Y.C M.TW .100 M.T
W W .100 OM
Oscillator. W.10 W O W
WW .100Y.C M.TW
O
WW .100Y. C
.T W W W
. 1 0 0Y.C
M WW
• Bit 0W –W
W
CLKS:10Clock
O
Y.C Selector W W WW 00Y.CO .TW W
. 0 M. T .1 M
bitW CO toTW
Y.written WW the00External Y .CO Oscillator W
The CLKS WW must0be
. 1 0 M . logic one to W select
.1 M.T / Low Power Oscillator
as CPU clock. W The CLKS C O bit must be written W
to W
logic zero .C O
to select the RC Oscillator as CPU
W . .TW 00 Y
W 00YCLKSMbit W .1the
clock. After a W W.1 the Y
reset, O is set by hardware W if External Oscillator / Low Power Oscil-
W 00
.C .TW WW
W . 1 O M
WW .100Y.C M.TW
W O
WW .100Y.C 37
W W
7799D–AVR–11/10 W
.C OM
00Y .TW
W W.1 Y.COM W
W 00 M.Tfirmware has to check if the clock is correctly
lator is selected by the fuse bits W W.1 Y.COThe
configuration.
started before M .TW it.
selected
W . 100 M .TW
W O
. 1 00Y M W O
W O
8.11.2 CLKSEL1 – Clock WW Selection 0 0 Y.C Register .T W1 WW .100Y.C M.TW
. 1 OM W 4 Y.CO 3 W 2
Bit W Y.C 7 5 W
.T W WW . 1 0 0 M .T W6 W . 100 M .T 1 0
M W O W O
O WW L0 0Y.C L3M.TW L2
(0xD1) RCCKSE RCCKSE RCCKSE RCCKSE EXCKSE EXCKSE EXCKSE EXCKSE CLKSEL1
00 Y.C .T W WW .100Y.C L3
M .T WL2 L1 . 1 0 L1 L0
W.1 OM W O
WW 00YR/W .CO .T R/WWW R/W 0Y.CR/W .TW
WW .100Y.C M.TW W
Read/Write R/W R/W R/W R/W
W . 1 M . 10 M
W O W O
W O WW .100Y.C M.TW
Initial Value 0 0 1 0 0 0 0 0
W O WW– RCCKSEL[3:0]: Y.C
O WW 00Y.CO .TW
WW .100Y.C M.TW • Bit W7:4 1 0 0 .T WCKSEL for WRC oscillator
.1 OM
W C O WW 00Y.C
. OM WWa reset, Y .Cthis W
W Y. W Clock W configuration for the RC
. T W Oscillator. W After .1 0 0 M.Tof the register is loaded with the
part
W .1 00 M .T W . 1 O M W .C O
W O W that00corresponds Y.C W Y W value by firmware before
WW .100Y.C M.TW
0010bW value .TWto the RCWoscillator. Modifying this
W . 1 O M W .100 O M.T
W O switching to RC oscillator is prohibited because WW the.1RC .C will.T
clock not
Wstart.
WW .100Y.C M.TW WW .100Y.C M.TW 00Y M
W O W C O
W O W Y.C CKSEL WW oscillator Y. W
WW .100Y.C M.TW• Bit 3:0W – EXCKSEL[3:0]: . 100 M .TW for External W .100 /O M.TPower Oscillator
Low
W O W .C O W Y. C W
WW .100Y.C M.TW Clock configuration WW .1for 00Ythe External M .TWOscillatorW / Low Power .100 Oscillator. M.T After a reset, if the Exter-
W O W C O
W
WW .100Y.C M.Tnal
O
W oscillator W/W Low Power Y.COscillator .TWis selected WW by fuse 0Y. thisM
.10bits, .TW
part of the register is loaded
W . 100 O M W C O
W C O with the fuse configuration.
W . C Firmware can modify W it to change Y . the start-up
W time after the clock
WW .100Y. M TW
.switch. W . 100
Y
M .TW W
W .100 O M.T
W O C
W
WW .100Y.C M.TW
O
W
W O W C O
8.11.3 WW
W .CO .StatusTW Register WW .100Y.C M.TW WW .100Y. M.T
W
CLKSTA
. 1 00Y– Clock
M W O W C O
W
WW .100Y.C Bit
O
.TW
W Y.C 5 .TW 4 W3W .1020Y. 1 .T
W 0
M
W7
W . 1600 O M W C O M
W O(0xD2) - W Y.C - .TW - - W - Y. RCON .TW
WW .100Y.C M.TW W .1R00
- EXTON CLKSTA
W
W . 100 O M W C O M
W O
WW 0 .100Y.C0 M.TW WW .100Y.
Read/Write R R R R R R R
W
WW .100Y.C InitialMValue .TW 0 0 W O
See Bit Description M.T
W O C
W
WW .100Y.C M.TW
O
W
W O W C O
W
WW .100Y • .CBitO 7:2 - Res: Reserved
.TW WW bits Y.C .TW WW .100Y. M.T
W
M W .100 O M W C O
W These O bits are reserved and .C read .as WW .100Y . W
WW .100Y.C M.TW WW will.1always 00Y M TW zero.
M.T
W O W .C O
W
WW .10• 0Y .CO .TW WW On Y.C .TW WW .100Y M.T
W
Bit 1 – M RCON: RC Oscillator W . 100 O M W C O
W .CO .T W .C WW .100Y . W
WW .This 1 00Ybit is set M byWhardwareW to one if.1the 00YRC Oscillator M .TW is running. W O M.T
O W O .C
W
WW This Y.Cis set by .TW
W if the Y.C .TW is stoped. WW .100Y M.T
W
. 1 00bit M
hardware to Wzero
W . 100 RC Oscillator O M W C O
W O WW .100Y .
W
•W Bit 0 –.C EXTON:
O External Oscillator W / Low O
Power Oscillator On W .C O
WW This.1bit .TW WW .100Y.C M.TW WW .100Y M.T
W
00Y is set byM hardware to one if the
W External OOscillator / Low Power W
Oscillator .C is O running.
W O Y.C WW .100Y W
WWThis .bit .C
00isYset byM .TW
hardware to zero WW if the . 100
External .TW / Low Power
Oscillator
M Oscillator isO M.T
stoped.
W 1 O W O W W .C
Y
M.T
W
W O W O W W .C O
8.11.4 OSCCAL – Oscillator
WW Calibration Y.C Register
.TW WW .100Y.C M.TW W .100
Y
M.T
W
W . 100 O M W O W W .C O
WW .100Y.C M.TW
Bit 7 6 5 W 4 Y.C 3 .TW 2 W1 100
0 Y
M.T
W
(0x66) W O
W
W .100 O M CAL2 W W .CAL0
.C O
Y.C
CAL7 CAL6 CAL5 CAL4 CAL3 CAL1 OSCCAL
WW .100Y.C W WW R/W W W .100
Y .TW
Read/Write
W
R/W M.TR/W
O R/W
W .100 R/WOM.T R/W R/W
W W R/W
.C OM
Y.C WW Specific 0Y. C W Y .TW
WValue
Initial W
.100 M.T
W Device
W .10Calibration O M.T
Value W
W .100 OM
W O C W .C
W W .100
Y .TW
• Bits 7:0 W – CAL[7:0]: O Oscillator Calibration W Value C O W W .C OM
WW .10Calibration 0Y.C M.T W WW .100Y. M.T
W W .100
Y
The Oscillator W O Register is used to
W trim the.C O
Calibrated Internal RC
W W Oscillator to
W
removeWprocess.1variations 00Y
.C .TWthe oscillator
from WWfrequency. . 1 00Y A pre-programmed
M .TW W
calibration value is
W O M W
Wreset, .CO .TW
automatically WW written 0 Yto .Cthis T
registerW during W
chip 0 0 Y
giving the Factory calibrated frequency as
0
W.1 26-1Y.on M. WW software
.1 M
.CO can write this register to change
specified W in W Table 0 COpageT266. W The application
W 0 0 Y
0 . W.1
W.1 OM
WW .100Y.C M.TW WW
W O
WW .100Y.C M.TW
W O
WW .100Y.C 38
W W
7799D–AVR–11/10 W
.C OM
00Y .TW
W W.1 Y.COM W
W 00 M.T
the oscillator frequency. The oscillator W W.1 canYbe .C O
calibrated
W to frequencies as specified in Table 26-
.T W W that.1range 0 0 M . T
1 on page 266. OM Calibration outside W isO not guaranteed.
0 0 Y.C .T W WW .100Y.C M.TW
W.1that Ythis
Note M
.COoscillator is used toWtime W EEPROM
0Y.C or
O and Flash write accesses, and these write
WW times 1 0
will 0 be affected
M .T W
accordingly.
W If the .EEPROM
1 0 M .TW are written, do not calibrate to more
Flash
. O W O
WW8.8 0MHz. 0Y.COtherwise, .TW the EEPROM WW or.1Flash .C
00Y writeMmay .TWfail.
M .TW Wthan . 1 O M W O
.CO .TW WW 00Y.C .TWthe rangeWof operation
W Y.C
100 for O TW
.oscillator.
.100Y M
WThe CAL7 W . 1 bit determines
O M W .
.C
the M Setting this bit to 0 gives the
W W .CO W Y .C W W W 0 Y .T W
W 00 Y .TW W
lowest frequency .10 0 M.T setting this bitWtoW1.1gives.C
range, 0 the highest frequency range. The two fre-
W.1 Y.COM W OM
W quency
W WW ranges 0 Y .COoverlapping,
are .T W in W
other words 0 0 Ya setting ofW
.T OSCCAL = 0x7F gives a higher
W .1 00 M.T . 1 0 M W . 1 O M
W O frequency W W than C
OSCCAL
. O = 0x80. W Y .C W
WW .100Y.C M.TW W . 100
Y
M .TW W
W .100 O M.T
W O
W O
WW .100Y.C M.TW The CAL[6:0] WW .1bits .C
00Yare used .TtoWtune the W W
frequency 0Y.C the
.10within TW
M.selected range. A setting of 0x00
W O W O M W W .C O
gives the Wlowest .
frequencyC in that range, and a setting Yof 0x7F W
gives the highest frequency in the
WW .100Y.C M.TW W . 100
Y
M .TW W
W .100 O M.T
W O
WW .100Y.C M.TW
W O range.
W O W O
W
WW .1CLKPR .CO – Clock
W Prescale W 0 Y.C W WW .100Y.C M.TW
8.11.5 00Y .T WRegister
W. 1 0
OM
.T
W OM WW 00Y.CO .TW
WW .100Y.C M.TWBit WW 7 .100Y.C6 M.TW5 4W
W.1 Y.COM W
3 2 1 0
W C O W W .C O W
WW .100Y. .TW
(0x61) CLKPCE Y – W
– – W CLKPS3
.100
CLKPS2
M.T
CLKPS1 CLKPS0 CLKPR
M
W
W . 100 R OM.TR W C O
W O
WW .100Y.C M.TInitial W Value WW0 .100Y0.C M.T
Read/Write R/W
W R
WW .100Y. R/W R/W
M.T
R/W
W R/W
O 0 0 W See BitO Description

W C
W
WW .100Y.C M.TW
O
W
W O W C O
W
WW .100Y.C M.TW
O
W
W O W C O
W
WW .100Y.C • M
O
Bit.TW 7 – CLKPCE: WWClock 0Y.C MChange .TW WW .100Y. M.T
W
W . 10Prescaler O
Enable
W C O
W O
WWbe written Y.C W Y. W
WW .100Y.C TheMCLKPCE .TW bit must
. 100 to logic M .ToneW to enable Wchange
W .10of0 the CLKPS
O M.T bits. The CLKPCE
W O C
W
WW .100Y.C M.TW
O is only updated when
bit WW the.1other 00Y
.Cbits in CLKPR
.TW are simultaneously WW .100Y.written M.T
to W zero. CLKPCE is
W O M W C O
W cleared
CO
WW .100Y.CLKPCE .
by
T W
hardware four cycles
WW .100Y.C M.TW
after it is written or when WW .100Y.
CLKPS bits are written.
M .TW
Rewriting the
M bit within this time-out W period O does neither extend W time-outOperiod, nor clear the
the
W
WW .100Y .CO .T
CLKPCE W
bit. WW .100Y.C M.TW WW .100Y.C M.TW
OM W O W O
W
W O
W • Bit 6:4 O - Reserved bits WW .CO .TW WW .100Y.C M.TW
WW .100Y.C M.TW W . 1 00Y M W O
W These bits O are reserved and W W
W will always CO as zero.
.read WW .100Y.C M.TW
WW .100Y.C M.TW .1 00Y M .TW
W W .C O
Y W
W
W
00 3:0 –MCLKPS[3:0]:
•.1Bits
O
.T Clock W .1
Prescaler
.C
Select
OM Bits 3 - 0 W W.1 Y.COM W
. C W Y the selected W clockW 100 the internal .T
WW These . 1 00Ybits define M .TW the divisionWfactor between . 100 M .T source W .and OM system
W O W C O W .C
WW clock. 00These
Y .C bits.Tcan W be written W
W run-time Y .
100 to vary M .the W
T clock frequency W .to 0 Y
10suit theOM .TW
application
. 1 O M W . O W .C
W
requirements.
WW .100Y.C M.TW
As the divider divides WW the .master Y.Cclock .input TW to the MCU, WW the.speed 100
Y of all synchro-
M.T
W
nous peripherals is reduced when a W 100 factor
division O M is used. The divisionW factors C O
are given in
WW 00Y.C O W .
WTable .T W WW .100Y.C M.TW W . 100Y M .TW
W. 1
8-9. OM W O W O
COCLKPS WW is unprogrammed, O
The CKDIV8
WW 00YFuse .CO determines the initialWW value of Y .the W bits. If CKDIV8
W 0 Y.C W
W
the CLKPS .1 bits will Mbe TW
. reset to “0000”. W W 1 0 0
If .CKDIV8 Ois M .T
programmed, CLKPS W 1 0
.bits are O M.Tto
reset
W O W .C
WW giving Y.C W WW up. 0Y.Cfeature
.10This
W
M.Tshould be usedW
W if the.1selected00Y M.T
W
“0011”,
W .100 a division O M.Tfactor of 8 at start W C O W .C Oclock
WWhas .a10higher 0Y.C frequency W than the W Y. W W the present Y
.100 operat- .TW
source
W O M.T
Wmaximum
W .100frequency O M.Tof the device at W W .C OM
Wwritten00toY.the CLKPS C Y .TW
ing conditions.
WW .10Note 0Y.C thatMany .TW
value canW be
.1 M.T
Wbits regardless W
W
of1the
. 00 CKDIV8 OMif
Fuse setting. W The O
Application software must W
ensure thatC O a sufficient division W
factor is .C
chosen
WW clock Y.C .TW WW .100Y. M.T
W W Y
.100device at
the selectedW .100 source O Mhas a higher frequency W than the
C Omaximum frequency W of W the
WW operating Y.C W WW shipped Y. W W
the present
W .100 conditions. O M.T The device is W .100 withOthe M.T CKDIV8 Fuse programmed.
WW .100Y. C
WW .100Y.C M.TW M.T
W
W O W C O
W O W
WW .100Y.C M.TW WW
W O
WW .100Y.C M.TW
W O
WW .100Y.C 39
W W
7799D–AVR–11/10 W
.C OM
00Y .TW
W W.1 Y.COM W
W 00 .T
W W.1 Y.COM W
W W 00 .T
O M.T W W.1 Y.COM W
Table 8-9. Y .C Clock WPrescaler W Select 00 .T
WW CLKPS3 Y .C W
CLKPS2 W CLKPS1 00 .T
CLKPS0 Clock Division Factor
W WW .0100Y .C W W 0 .100 0 .T
M.T
0 1
O M.T W .C O W W Y .C OM
W
Y.C W WW 0.100Y M.T0
W W 0 .100 1 .T 2
W .100 O M.T W
W 0 00Y .C O W W Y .C OM
W
W Y .C W W W W 0 0 .T
W 00
W.1 Y.COM W
.T .1 M0.T 1 .1
WW 00Y.CO .TW
0M 4
W W WW 00Y.CO .TW W
W 00 .T 0 .1 M0 1 .1 1 M 8
W 00 .T W 0 .1 1M 0 .1 0 M 16
W 00 .T W 0 W.1 1M 0 .1 1 M 32
W W.1 Y.COM W W Y.CO .TW W WW 00Y.CO .TW
W 00 .T W 1 0 0 1 OM . 1 M
W.1 OM 0 W. 1 W 0 O 64
0 W 1 O 1 W 1 O 128
W
WW .100Y.C M.TW
O
W 0 O W 0 O
WW .100Y.C M.TW
W O 1 0 256
W O W O
W
WW .100Y.C M.TW
O 1
WW .100Y.C M.TW
0 0
WW 1.100Y.C M.TW Reserved
W 0 O W O
W
WW .100Y.C M.TW
O 1
WW .100Y.C M.TW
1 WW 0 .100Y.C M.TW Reserved
W O W O
W
WW .100Y.C M.TW
O 1
WW .0100Y.C M.TW 1 WW1 .100Y.C M.TWReserved
W O W O
WW
W .CO .TW
WW .100Y.C M.TW
1 WW 1.100Y.C M.T 0W 0
. 1 00Y M
Reserved
W O W C O
W
WW .100Y.C M.TW1
O
WW 1 .100Y.C M0.TW W1W .100Y. W
M.TReserved
W O W C O
W O
WW1 .100Y.C M 0W Y. .TW
WW .100Y.C M.T1W 1 .TW W
W .100 O MReserved
W O W O W Y.C
WW .100Y.C M.T 1W WW Y.C 1 .TW 1W .100 .TW
1
W .100 O M W C O M Reserved
WW
W .CO .TW WW .100Y.C M.TW WW .100Y. M.T
W
00Y
PLLCSRW–.1PLL Control M W O W C O
8.11.6
WW .100Y.C M.TW
O and Status Register
WW .100Y.C M.TW WW .100Y. M.0T
W
W O W .C O
W
WW .100Y .CO .TW
Bit 7
WW
6 5
Y.C
4
.TW DIV3 W
3 W2 1
00Y M.T PLLCSR
W
M
0x29 (0x49) – –
W .100– O M
DIV5 PINDIVW.1 PLLE
C O PLOCK
W O WRW .1R/W .
Y.C
WW .100Read/Write .TW R WRW .1R00Y.C R/W M .TW R 00Y M.T
R
W
M W O W .C O
W CO
.Value 0 W 0 0Y.C 0
.TW 0 0 W 0 Y W
WW .1Initial W .100 M.T
0 0
00Y M .TW W
W .10 O M W C O
W .C O W Y.C WW .100Y . W
WW •.1Bit 00Y7:5 – Res: M .TW Reserved
WBits . 100 M .TW W O M.T
O W O .C
W
WW These .C .TW
W Y.C .TW WW .read Y
100 as zero. M.T
W
. 1 00Ybits areMreserved Wthe
bits in W . 100
ATmega8U2/16U2/32U2 O M and always W C O
W O WW .100Y .
W
O W O W .C O
W
WW• Bit.1400–YDIV5.C PLL WW (1:5)
Input Prescaler
.TW Y.C .TW WW .100Y M.T
W
M W . 100 O M W C O
W O Y.C W Y . W
W•WBit .310–0DIV3Y.C PLL.T W
Input Prescaler WW(1:3) . 100 M .TW W .100 M.T
W O M W O W W .C O
Y
M.T
W
W O W O W W .C O
•WBit
W 2 – PINDIV .C PLL.T Input
W Prescaler WW(1:1,.11:2) .C W Y W
. 1 00Y M W
00Y
O M.T
W
W .100 O M.T
W O Y.C to generate W .C
These bits allow to configure the PLL
WW .100Y.C M.TW Winput
W prescaler W the 8MHz
W input .100
clock
Y for the .TW
PLL from W either a C 8O or 16 MHz input. W .100 O M.T W W .C OM
WW .100Y. C W Y W
WW .100Y. M .TW M.T
W
W .100 OM.T
W O W C O W .C
When using a 8 MHz clock source, this W
WW .100Y.C M.TW
bitW must be0set Y. to 0 before
M.T
W enablingWPLL (1:1). .100
Y .TW
W O W .10 O W W .C OM
Y.C clock.Tsource, bitW C
Y. to 1 before W enablingWPLL (1:2). Y
WhenW W a 16
using
.100
MHz
M
W this W must be
W .100
set
O M.T W .100
W O C W
WW .10Reserved 0Y.C MBits .TW WW .100Y. M.T
W W
• Bit 3:2 – Res: W O W W .C O
WW Y.C .TW read asWzero.W.100Y OM.TW
These bits areW .100 and
reserved O Malways
W O W
WW .100Y.C M.TW WW
W O
WW .100Y.C M.TW
W O
WW .100Y.C 40
W W
7799D–AVR–11/10 W
.C OM
00Y .TW
W W.1 Y.COM W
W 00 .T
• Bit 1 – PLLE: PLL Enable WW.1 .C OM
When the PLLE M is
W
.Tset, the PLL
W
is started. .
Y
100Note that M .TWCalibrated 8 MHz Internal RC oscillator is
the
W O
.CO .TW W 0Yset.C .TWPINMUX (see PLLFRQ register) is set.
. 1 00Y enabled
automatically M when theWPLLE W bit
. 10is and
O M with
W O
WWThe PLL Y.C be disabled
00must .TW before
W
Wentering . 0Y.C down
10Power M
W in order to stop Internal RC Oscil-
.Tmode
. 1 O M W O
WWand0avoid
Wlator 0Y.C extra-consumption.
.TW WW .100Y.C M.TW
M .TW . 1 O M W O
Y.C
O
W W WW 00Y.C .T W WW .100Y.C M.TW
0 0 .T • Bit W 1
0 –. PLOCK:OPLL M Lock DetectorWW
W.1 OM .C .CO .TW
WW .100Y.C M.TW WW the.1PLOCK
When 00Y bitMis.Tset, W the PLLW is locked . 10to0Ythe M
reference clock. After the PLL is enabled, it
W W .C O W
Wabout Y .COms for W W WWTo clear 0 Y .CO .TW
Y W W
takes 0
several M. T the PLL to lock. 0 PLOCK, clear PLLE.
W
W .100 O M.T W .10
.C O W W.1 Y.COM W
W
WW .100Y.C M.TW W .100
Y
M.T
W W 00
W.1 Y.COM W
.T
W O W W .C O W
WW .100Y.C M.TW W .100
Y
M.T
W W 00
W.1 Y.COM W
.T
W O W W .C O W
WW .100Y.C M.TW W .100
Y
M.T
W W 00
W.1 Y.COM W
.T
W O W W . C O W
WW .100Y.C M.TW W .100
Y .TW W 00
W.1 Y.COM W
.T
W C O W W .C OM W
WW .100Y. M.T
W W .100
Y .TW W 00
W.1 Y.COM W
.T
W CO W W .C OM W
WW .100Y. M.T
W W .100
Y .TW W 00
W.1 Y.COM W
.T
W CO W W .C OM W
WW .100Y. M.T
W W .100
Y .TW W 00
W.1 Y.COM W
.T
W CO W W .C OM W
WW .100Y. M.T
W W .100
Y .TW W 00
W.1 Y.COM W
.T
W CO W W .C OM W
WW .100Y. M.T
W W .100
Y .TW W 00
W.1 Y.COM W
.T
W CO W W .C OM W
WW .100Y. M.T
W W .100
Y .TW W 00
W.1 Y.COM W
.T
W C O W W .C OM W
WW .100Y. M.T
W W .100
Y .TW W 00
W.1 Y.COM W
.T
W C O W W .C OM W
WW .100Y. M.T
W W .100
Y .TW W 00
W.1 Y.COM W
.T
W C O W W .C OM W
WW .100Y. M.T
W W .100
Y .TW W 00
W.1 Y.COM W
.T
W C O W W .C OM W
WW .100Y. M.T
W W .100
Y .TW W 00
W.1 Y.COM W
.T
W C O W W .C OM W
WW .100Y. M.T
W W 00Y .TW W 00
W.1 Y.COM W
.T
WW .100Y W W 00 .T W 00 .T
.C W W 00 .T
WW .100Y M.T
WW .100Y W W 00 .T W 00 .T
.C W W 00 .T
WW .100Y M.T
WW .100Y W W 00 .T W 0 .T
.C W W 0 .T
WW .100Y M.T
W W 00 .T 0
W.1 Y.COM W
WW .100Y .TW W .10 M.T
M
W
W . 100 O M .T W C O
W O W .
Y
M.T
W
W O W O W W .C O
Y
M.T
W
W O W O W W .C O
Y
M.T
W
W O W O W W .C O
Y .TW
W O W C O W W .C OM
W W .100
Y .TW
W O W C O W W .C OM
W W .100
Y .TW
W O W C O W W .C OM
W W .100
Y
W O W C O W W
W W
W O W CO
W
W O W C O
W O W
WW .100Y.C M.TW WW
W O
WW .100Y.C M.TW
W O
WW .100Y.C 41
W W
7799D–AVR–11/10 W
.C OM
00Y .TW
W W.1 Y.COM W
W 00 .T
9. Power Management and Sleep Modes W W.1 Y.COM W
.TW W 00
W.1 Y.COM W
.T
.C OM W
Y W W 00 .T
9.1 Overview W .100 O M.T W W.1 Y.COM W
WW .C W
Sleep W
00Y enable
.1modes O
W
M.T the applicationWtoWshut .100downOunused M.T modules in the MCU, thereby saving
C .C
.TW
W
Wpower. The
1
.
00YAVR provides M .TW variousWsleepWmodes .
Y
100 allowing M .TW the user to tailor the power consump-
O M W . O W .C O
Y.C W W W 0 Y .C W W 0 0 Y .T W
100 M .T tion to the
. 1 0 application’s
M .T requirements.
W . 1 O M
. W O
W
WW .100Y.C M.TW
O
W O W O
W9.2 O
Sleep
WW .100Y.C M.TW
Modes WW .100Y.C M.TW WW .100Y.C M.TW
W page O W O in the ATmega8U2/16U2/32U2, and
W O FigureW
W 8-1 on Y.C26 presents W the different WW clock Y.C
0systems W
WW .100Y.C M.TW . 1 0 0 M .T
W . 1 0
O M.T sleep mode. shows the differ-
their W
distribution. The O figure is helpful in selecting an appropriate
W O
WW .100Y.C M.TW ent sleep WWmodes Y.C .TW up sources. WW .100Y.C M.TW
W . 100and their O M wake W O
W
WW .100Y.C M.TW
O
W O the Different Sleep Modes.
W O Table 9-1. WW Active
W .CO Domains
YClock W and Wake-up WW .Sources 0Y.C inM .TW
WW .100Y.C M.TW . 1 0 0 M .T
W 1 0
O
W O C
W
WW .100Y.C M.TW
O
WW .100Active Y.C Clock .TW WW .100Y. TW
M.Wake-up
W O
Domains M Oscillators W C O Sources
W
WW .100Y.C M.TW
O
W O W O
W O WW .100Y.C M.TW
USB Asynchonous
WW .100Y.C M.TW
USB Synchronous
WW .100Y.C M.TW
EEPROM Ready
W O W O
W
WW .100Y.C M.TW
O
WDT Interrupt
INT[7:0] and
Interrupts(3)
W O W O
Main Clock
W O
PCINT12-0
WW .100Y.C M.TW
Interrupts
Other I/O
Enabled
clkFLASH
W O
Source
W O
W O
clkCPU
WW .100Y.C M.TW
SPM/
clkIO
W O W O
W
WW .100Y.C M.TW
O Sleep Mode
W O W O
WW
W .CO
WW .100Y.C Idle .T W WW .100Y.CX M.TW X X
. 100Y X M.TW
X X X X
C W . .TW Y W
WW .100Y. Power-down
(2)
W W .100
Y WX 00 X .T X
C W .TW
WW .100Y. Power-save Y XW 00 X .T
(2)
W W .100 X
C W .TXW
WW .100Y.Standby M.T
(1) W W 00Y XW(2) 00 X
W.1 Y.COM W
.T X
WW .100Y Extended .TW W 00 .T W 00 .T
W O M W.1 Y.COMX W X(2) W W.1 X Y.COM W X
.C
Standby W W 00 .T
WW .100Y .T W W . 1 0 0 M . T . 1 M
W .CO Only
M W .CO .or W
WW as.1clock .CO .TW
WW .Notes:
00Y 1. M .TW recommended WWwith external
.1 00Y crystal M TW resonator selected 00Y source. M
W W 1
.C O For INT[7:4], only level
W WW Y .CO .TW W WW 00Y.CO .TW
W 00 Y 2. W interrupt. 0 0 1
W.1 Y.3. M.T
OAsynchronous .1
WW is0WAKEUPI
M
.CO only.
.
WW 00Y.CO .TW
M
W W 0 C W USBW interrupt 0 Y .T W W 1
0 .T .1 M . M
W 0 W 1
0
W.1 Yany M.T WW the
.1 OM W. M
.CO one.Tand
WWTo enter 0 .COof the .T five
W sleep modes,
W 0 0 Y
SE .Cbit in SMCR
.T W must W
be Wwritten . 1 0 0
to Ylogic
M
W a
.1 0 M W . 1 O M W C O
O
W instruction must be executed. .CSM1, and W .
YRegister.T W
SLEEP
WW .100Y.C M.TW WW The.1SM2, 00Y M .TWSM0 bits W in the SMCR
.100 M
select
which sleep modeO (Idle, Power-down, W
Power-save, O Standby or Extended W W standby) .C O
will be acti-
W WW 00Y.C TW WW .100Y.C M.TW W .100
Y .TW
vatedW by .1the SLEEP O M.instruction. See Table W 9-2 forCaOsummary. W W .C OM
WW .100Y. Y W
WW .100Y.C M.TW W
M.Tmode, the MCUWwakes
W
W .100 O M.T
If an enabled
W interrupt
O occurs while the MCUW is in a O
sleep up. .CThe MCU
W Y.C .TW in addition WW .100Y.C M.TW W Y
.100routine, .TW
isWthen halted W .100 for four O Mcycles to W the start-up C O time, executes the interrupt W W .C OMand
W
WW execution Y.C from .the W WW .100SLEEP. Y. .TW W Y
.100 FileOand M.T
resumes
W .100 O M T instruction following W C O MThe contents of the Register
W W .C
SRAM WW are unaltered Y.C when.Tthe W device wakes WW up.1from .
00Ysleep.MIf.T aW reset occurs W during.1sleep 00Y mode, .TW
the MCU WWwakes upY.andC executes W from the W
WReset Vector.Y. W W .100
Y
W .100 O M.T W .100 O M.T W W
WW .100Y. C
WW .100Y.C M.TW M.T
W W
9.3 Idle Mode W O W C O
When the SM2:0 W bits are written
O to 000, the SLEEP W instruction CO makes the MCU enter Idle mode,
W .C
00Yallowing W WW .100Y.
stopping W the CPU W . 1but O M .Tthe USB, SPI, USART,
W Analog Comparator, Timer/Counters,
WW .100Y.C M.TW WW
W O
WW .100Y.C M.TW
W O
WW .100Y.C 42
W W
7799D–AVR–11/10 W
.C OM
00Y .TW
W W.1 Y.COM W
Watchdog, and the interrupt system
W
W.to100continue .T
OMoperating. This sleep mode basically halts clk-
W .C
W
.Twhile W the other .
Y
100clocksOto M .TW
CPU and clkFLASH M , allowing W run.
Idle . 1 00Y enables
mode M the MCU to wakeWup from.Cexternal O triggered interrupts as well as internal
W O
WW 0 0 Y .C .T W WW Transmit . 1 0 0Y Complete M .TW or some USB interrupts (like SOFI,
ones . 1
like the Timer M Overflow, USART
W WW 00Y.CIfOwake-up W from theW WW 00Y.CO .TW
.T WWAKEUPI...). 1 .T Analog .Comparator
1 Minterrupt is not required, the Analog Com-
COM W W. can Y .C OM WW the Y .CObit in.Tthe W Analog Comparator Control and
Y . W parator
W 0 0 be powered .T W down by W setting 1 0 0ACD
.100 M .T W . 1 O M W .
.C O M
W O Status .C WW power
WW .100Y.C M.TW WW Register . 1 00Y
– ACSR. W
M .T
This will reduce
. 100
consumption
Y
M .TWin Idle mode.
W O W O
W
WW 9.4 .CO .TW WW .100Y.C M.TW WW .100Y.C M.TW
.1 00YPower-down
M Mode W O W O
W
WW .100Y.C M.TW
O
When theW SM2:0 bits Oare written to 010, the W SLEEP instruction O makes the MCU enter Power-
W O W Y.C WW .1is00stopped, Y.C TW the external interrupts, the 2-
WW .100Y.C M.TW downW mode. In 1 0 0
this mode, .T
the
Wexternal Oscillator M .
while
W. OM W O
W O
WW .100Y.C M.TW wire Serial WWInterface, 0 0 Y.C and the .T W
Watchdog WW operating
continue . 1 0 0Y.C (ifMenabled). .TW Only an External Reset,
W . 1 O M W C O
W O W .C W Y . W
WW .100Y.C M.TW a Watchdog W Reset, aYBrown-out
.100 an external .TWReset, 2-wire W Serial 0Interface
W.1 a pin
0 address
.T match, an external level
OM interrupt or an asynchronous
W C O interrupt on W W
INT7:4, . C OM interrupt on INT3:0, W Y .Cchange W
WW .100Y. W
M.T USB interruptWsource
W Y
.100 (WAKEUPI .TW W 100 OM
.T
W O W C OM only), can wake W Wup. the MCU. .C This sleep mode basically halts
WW .100Y. C
.T W W clocks, 1 0 0 Y .
M .T W W . 1 0 0 Y
M .TW
OM all generated W. allowing O operation of asynchronous W modules O only.
W
WW .100Y.C M.TNote W WW .100Y.C M.TW WW .100Y.C M.TW
that if a level O W from Power-down O
W O WWtriggered .Cinterrupt is used for wake-up
WW .100Y.C M.TW
mode, the changed
WW .100Y.C M.level TW must beW held for . 1 00Y timeM
some to
W
.Twake up the MCU. Refer to “External Interrupts” on page 84
W W .C O
W 00 Y .Tdetails.
for W .10 0 M .1 M
W
W 00
W.1 Y.COWhen M.T waking up from .1
WPower-down .CO .TW
Mmode, there is a W W.1fromYthe
delay M
.COwake-up W
condition occurs
W W W W 0 Y W 0 0 .T
W 00
W.1 Y.CO M.Tthe wake-up becomes
until 0 effective. This allows the clock
W.1 Y.COM W W W.1to restart YCKSEL
and
M become stable after
.CO Fuses W that define the
WThe W 0
W W
. 1 00 having
M .T been
W stopped. W
W .
wake-up
10 0 period
O M .T is defined by the
W
same
.1 0
O M.T
W O Time-out period,Was described
Reset Y.C in “Clock W Y.C W
WW .100Y.C M.TW W .100 M .TW Sources”Won page W .100
29.
O M.T
W O C
W
WW .100Y.C M.TW
O
W
9.5 Power-save Mode W O W C O
W
WW .100Y .CO .TW WW .100Y.C M.TW WW .100Y. M .TW
When O M
the SM2:0 bits are written
W to 011, O the SLEEP instruction W makes .the
C O MCU enter Power-
W
WW .100save Y.C mode. .T W mode W W 0
C
0toY.Power-down. .TW This mode WW .100Y M .TWfor compati-
This is identical .1 M hasW been conserved
O
W OM W O
WW .100Y.C M.TW
WW .10bility 0Y.Cpurpose .T W
with higher-end WW products. . 10 0Y.C M.TW
OM W O W O
W
W O W O
9.6 Standby W WW 00Y.CO .TW
Mode WW .100Y.C M.TW WW .100Y.C M.TW
.1 M W O
WWhen the
. C OSM2:0 bits are 110 Wand W an external Y .CO crystal/resonator
W W Wclock option
0Y.Cis selected, W the
W W
. 1 0 0 Y
M .T W W
W . 1 0 0
O M .T
W . 10
O M.T
SLEEP
W O
instruction makes the MCU enter Standby mode. This modeWW .100Y
is identical .C to Power-down
WW with.1the .C
00Yexception W
.Tthat WW .100Y.C M.TW .TW
Mwakes
O M the Oscillator Wis kept running.
O From Standby W
mode, the device
.C O up
W
WWin six.1clock .C W WW .100Y.C M.TW WW .100Y .TW
00Y cycles. .T W O M
W OM W O
WW .100Y.C M.TW
W O
W .CO .TW WW 00Y.CO .TW WW .100Y.C M.TW
9.7 Extended Standby WW Mode 0 Y W
0
W.1 SM2:0 M
.CObits .are W.1 Y.COM W W Y.C
O
WW the
When 0 Y T W 111 and W an Wexternal 0 0 crystal/resonator
.T WW
clock option . 1is
0 0 selected, M.T
W
the
W . 10 O M W .1 O M W W .C O
WW .100Y.C M.TW
SLEEP instruction makes the MCU W enterW Extended 0Y.C Standby
.10Oscillator
W mode. This W mode
Mis.Tkept running. SoWExtended .100
is Yidentical .TtoW
Power-save W mode O
with the exception that Wthe C O W .C OM
Standby
WWis equivalent Y.C .TW Mode,Wbut isWalso
W Y. W W .100
Y .TW
Mode W .100 toM
O Standy .100 conserved O M.T for compatibility W W purpose. .C OM
From
Y.C WW up in .C Y .TW
WW Standby .TWdevice wakes 0Yclock
.10six .TW W .100
Extended
W .100 mode, O Mthe W C O cycle.
M W W .C OM
W W .100
Y
W O W C O W W
9.8 Power Reduction Register WW .100Y.C M.TW WW .100Y. M.T
W W
W O W C O
The Power WW Reduction C
Y.Registers .TW (PRR0 andWPRR1), W Y.
provides a method W to stop the clock to indi-
W . 100 O M W .100 O M.T
vidual peripherals to reduce power consumption. WWSee.1“PRR0 C
. – Power Reduction Register 0” and
WW .100Y.C M.TW 00Y
“PRR1 – PowerW Reduction Register
O 1” on page 46 W
for details. The current state of the peripheral
WW Y.C .TWnot be read WW
is frozen and theWI/O .100registers O M can or written. Resources used by the peripheral
WW .100Y.C M.TW
W O
WW .100Y.C 43
W W
7799D–AVR–11/10 W
. C OM
00Y .TW
W W.1 Y.COM W
when stopping the clock will remain
W .100
Woccupied, O M.T the peripheral should in most cases be dis-
hence
W W Y . C W
abled beforeOstopping M.T
W
the clock. Waking W .100up a module, O M.T which is done by clearing the bit in PRR,
.C W same state WWas before Y.C .TW
puts.1the 00Y module M in.Tthe
W . 100 shutdown. O M
W O W Y.C
WW Module . 1 0Y.C Mcan
0shutdown .TWbe used in WIdle mode . 100 and Active M .TW mode to significantly reduce the overall
W C O W W .C O
W W Y . W W 0 0 Y .T W
M .T . 1 00
Wpower consumption. M .T W . 1 O M
W O
.100Y M W O W O
W
WW 9.9 0
O
Y.CMinimizing
.T W Power WWConsumption 0 0 Y.C .T W WW .100Y.C M.TW
0 W. 1 OM CO
W.1 OM Y.Cissues.TtoWconsider when WW trying
W Y.minimize .TW
WW .100Y.C M.TW WWare several
There
. 1 0 0 M . 1 0 0to M
the power consumption in an AVR
controlled O
Wsystem. In general, sleep modes W O
.Cused as
W
WW .100Y.C M.TW
O
WW .100Y.C M.TW WW should be
Y
.100 of the .TW
Mdevice’s
much as possible, and the sleep
mode should W be selected O so that as few as W
possible O functions are operating. All
W O
WW .100Y.C M.TW functions WWnot .needed .C
00Y should .T W
be disabled. WIn W
. 1
particular,0 0Y.Cthe following
M .TW modules may need special
1 M W O
W O
WW when
W .CO to.T WW possible 0Y.Cpower W
WW .100Y.C M.TW consideration . 1 0 0 Ytrying
M
W
achieve the lowest
W . 1 0
O M.T consumption.
W O
W
WW .100Y.C M.TW
O
W O W O
9.9.1 W Analog OComparator
WW .100Y.C M.TWWhen entering WW .100Y.C M.TW WW .100Y.C M.TW
Idle mode, O Analog Comparator
the Wshould be disabled O if not used. In other sleep
W O WW Y.C WW .100Y.C M.TW
WW .100Y.C M.TW modes, theWAnalog 1 0 0 M .T W
W .C O W W. Comparator
Y .CO .TW
is automatically disabled.
WW 00Y.CO .TW
However, if the Analog Comparator is
W Y W W 0 W .1the Analog
W 00
W.1 Y.COM abled
.Tset up to use the W .10 Voltage
Internal M Reference as input, WW Voltage
MComparator should be dis-
.COReference
W modes. Y .CO W W 0 Y W will be enabled,
W W
. 1 00 M .T W in all Wsleep
W . 10 0 Otherwise,
O M .T the Internal
W .1 0
O M.T
W O independent of sleep Y.CRefer to WW .100on C
Y. page 223 Wfor details on how to
WW .100Y.C M.TW WW mode. . 100 M .TW “Analog Comparator”
M.T
configure the Analog W Comparator. O W C O
W
WW .100Y.C M.TW
O
W
W O W C O
9.9.2 WW 00Y.Detector
WBrown-out CO
W
. 1 M W O W C O
W O
WW is C
0Y.needed WW this Y. .TW be turned off. If
WW .100Y.C If the M .T W
Brown-out Detector . 10not M .TbyWthe application, W .100module O Mshould
O W O C
. be enabled
W
WW .100Y.Cthe Brown-out .TW
DetectorWW is .enabled Y.C by the .TW BODLEVEL WW Fuses,
.100
it Ywill
M.T
W in all sleep
M W 100 O M W C O
W CO WWsleep.1modes, . this .will
WW .100Y.C M.TW
modes, and hence, always consume power. In the deeper TWcontribute sig-
WW .100Y.nificantly .Tto W 00Y Mpage
M the total current W consumption. O Refer to “Brown-out W Detection” C Oon 50 for details
W
WW .100Y .CO W W
WBrown-out .C
00YDetector. .TW WW .100Y. .TW
on howMto.Tconfigure the W .1 O M W O M
W
WW .100Y.C M.TW
O
W O W O
9.9.3 InternalWW
W
Voltage 0 Y.C
O
Reference
0 .CO Detection,
W.1The Internal OM Voltage Reference W .CO when byW
W W or the
WW .100Y.C M.TW WW will.1be 00Y
enabled
M .TW neededW the Brown-out
. 1 00Y M.T
Analog Comparator.
O If these W
modules are O
disabled as described in W
the sections .C O above, the inter-
W
WW nal 0 Y.C reference .T W W W 0 0Y.itCwill M .Tbe W WW .100Y M .TW
1 0voltage will be disabled . 1 and not consuming power. When O
turned on again,
W W. .C OM
W the.1user 0 Y .T the reference toWstart W 1
0 mustM allow .1 up before M the output is used. If .the reference
WW Voltage OM is kept on
W .C O Wused 0immediately. Y .CO .TW W 0 Y.CReference” W on
W W in sleep
. 1 0 0 Y mode,
M
the
.T W output can W be
W .1 0
O M Refer to “Internal
W . 1 0
O M.T
W O time. 0Y.C WW .100Y .C W
WWpage.151 00Y
for.Cdetails on
.TW
the start-up WW . 10 M .TW M.T
W O M W O W W .C O
Y
M.T
W
9.9.4 Watchdog Timer O W O W W .C O
WW 00Y.C W WWin the 0Y.C M.Tthe W W 0Y
.10turned
W
M.IfTthe
WIf the Watchdog
W .1 O M.T is not needed W
Timer W .10application, O module shouldWbe
W .C off.
O
WW .10Timer 0Y.C is enabled, W it will be Y.C W W 100
Y consume
M.T
W
Watchdog
W O M.T
W enabled
W .100in all sleep O M.Tmodes, and hence, W W .always
. C O
WW In .the
power. .C sleep
deeper .TWmodes, this WW will contribute Y.C significantly W to theWtotal current Y
.100 consump- M.T
W
W 1 00Y
tion. Refer to “Interrupts” on page 64 for WW details on0Y howC
. to configure the Watchdog Timer.
Y .TW
WW .100Y.C M.TW .10 M.T
W W
W .100 OM
W O W C O W .C
W W .100
Y .TW
9.9.5 Port Pins
W O W C O W W .C OM
W Y.C W WWshould Y. W W 100
Y
WhenW entering
W .10a0sleepOmode, M.T all port pins W W .100be configured O M.T to use minimum W W .power. The
W .C Wthat no pins Y .C W W
most important
W is then
.100
Y to ensure
M.T
W drive.1resistive 00 loads.
M.T In sleep modes where the I/O
clock (clkI/O )W is stopped, C Othe input buffers of W
the WdeviceY.will C Obe disabled. This ensures that no
W Y . W W .100 In some .TW
W
power is consumed W .100by theOinput M.Tlogic when not W W
needed. .C O Mcases, the input logic is needed
WWwake-up .C .TW 00Y Refer to the section “Digital Input
for detecting . 1 00Yconditions, M and it will
W
then beW .1
enabled.
WW 00Y.Con O
Enable andW Sleep Modes” page.TW 71 for details WW on which pins are enabled. If the input buffer is
W . 1 O M
WW .100Y.C M.TW
W O
WW .100Y.C 44
W W
7799D–AVR–11/10 W
.C OM
00Y .TW
W W.1 Y.COM W
enabled and the input signal isW
W
left .100
Wfloating M.T an analog signal level close to V /2, the
orOhave
.C CC
input buffer will M .TWexcessiveWpower.
use . 100
Y
M .TW
W O
. 1 00Y input M O be disabled at all times. An analog signal
ForW analog C
Y.to
O pins, the digital WW buffer
input should
0Y.Csignificant .TW current even in active mode. Digital
WW level 1 0
close
. 0 V M /2.T W
on an input
W pin can . 10
cause M
O W O
WWbuffers .C
CC
.TW Winput .C
00Y can be TW
.disabled WW to.1the
by writing 00YDigitalM .TWDisable Registers (DIDR1). Refer to
Input
M . 1 O M W O
.CO .TW WW – 0Digital
“DIDR1 0Y.C Input W
.TDisable Register WW 1” on 0Y.C 225Mfor
10page .TW details.
.1 00Y M
W
W . 1 O M W .
.C O
W O .C W Y .TW
WW 9.9.6 .C
00Y On-chip .TW Debug System WW .100Y M .TW W . 100 M
.1 M W O W O
W
WW .100Y.C M.TW
O
WW Y.C
00debug .TW is enabled WW .100Y.C M.TW
If the On-chip . 1 M
system byW
W O WW 00Y.C O W the OCDEN O Fuse and the chip enters sleep mode,
0Y.C consumes W
WW .100Y.C M.TW the W main clock . 1 source Mis .T W
enabled, and Whence,
W . 1 0
always O M.T power. In the deeper sleep
W C O W W .C O W total 0current Y .C consumption. W
W Y. W modes, W this will Y
contribute
0 W
significantly
T W
to the 0 .T
W 00
W.1 Y.COM W
.T .10 M. .1
WW 00Y.CO .TW
M
W W WW 00Y.CO .TW W
W 00 .T 1 M .1 M
9.10W W.1Register .C OMDescription WW. Y .CO .TW W WW 00Y.CO .TW
W 00 Y .T W W .10 0 M .1 M
W
9.10.1 00
SMCR – Sleep.T Mode Control W W .1
Register M .1 M
W W.1 Y.COM W W Y .CO .TW W WW 00Y.CO .TW
W 0
W 00
W.1 Y.COM W
.T The Sleep ModeW .10 Register
Control
.CO .TW
M contains controlWbits W.1for power Y.C
OM management.
W W 00 .T Bit W W
7 .10
0 Y
M
W 3 .1
0 0 2 OM
.TW
W . 1 O M W 6
O 5 4 W
WSM2 00YSM1 . C 1 0
W Y .C W W W– 0 Y .C .T W W .T W
W .100 M.TRead/Write .10 W.1 R/W
0x33 (0x53) – – – SM0 SE SMCR
W O W C OM R W .C OM
C W . .TW Y W
WW .100Y. Y W .100 0 OM.0T
R R R R/W R/W R/W
TWValue
M.Initial
W
0 W.
1000 OM0 0 W
W O . C 0 W .C .TW
0
WW .100Y. C
.T W W W
.1 0 0Y M .TW W . 1 00Y M
OM W O W O
W
WW .100Y.C • M .TW
Bit 7:4 - Reserved WW bits.100Y.C M.TW WW .100Y.C M.TW
W O W CO read WW 00Y.CO .TW
WW .100Y.C These .T W are reserved
bits WW and . 1 0 0Y.always
will M .TW as zero.W .1 M
W W .C OM
W 00 Y W 1
W.1 Y.•CO M.T3:1 – SM[2:0]: Sleep
Bits WW Mode
.1 OM Bits 2, 1, and 0WW.
.CSelect Y.C
OM
W W 00 TheseMbits W
.T select between the W 0 Y
0 available
1five M .T W W 0 0
.1 in Table M9-2. .TW
. 1 W . O sleep modes as W
shown C O
W
WW .100Y.C M.TW
O
W
O W O W .C O
W
WW .100Table Y.C 9-2..TWSleep Mode WWSelect Y.C .TW WW .100Y M.T
W
M W .100 O M W C O
W O SM1WW Y.C WW .100Y . W
WW .100Y.CSM2M.TW . 100SM0 OM.TSleep Mode
W
W O M.T
O W .C
W
WW .100Y.C0 M.TW 0 WW Y.C .TW WW .100Y M.T
W
W .1000 O M Idle
W C O
W O W .C Reserved WW .100Y . W
WW .100Y.C 0
M .TW 0 W W.1010Y OM .TW W O M.T
W O WW .100Y .C
WW .100Y0.C M.TW 1 WW .1000Y.C Power-down M .TW M.T
W
O W O W .C O
W
WW .1000Y.C M.TW 1 WW 1.100Y.C Power-save .TW WW .100Y M.T
W
O W O M W .C O
W
WW .1010Y.C M.TW0 WW 0 .100Y.CReserved .TW WW .100Y M.T
W
W O W O M W W .C O
WW .1100Y.C M.TW WW 1 .100Y.C M .TW W .100
Y
M.T
W
W O 0 W Reserved
O W W .C O
WW 1.100Y.C M.T1W WW .100Y.C M(1).TW W .100
Y
M.T
W
W O 0 W Standby O W W .C O
WW 1 .100Y.C M.1TW WW .100Y.C M.TW (1) W .100
Y
M.T
W
W O 1 W Extended O Standby W W .C O
Y .TW
W O W C O W W .C OM
Note: W 1. Standby Y.C modes Ware only recommended WW .100for Y. use with
M.T
external crystals
W W or .resonators.100
Y .TW
W
W SE: Sleep Y.C W WW .100Y. M.T
W W .100
Y .TW
• Bit W0–
W .100 Enable O M.T W C O W W .C OM
The SE WW bit must C
0Y.written W one toW W
.10MCU 0Y. enter M.the TWsleep mode W when.1the 00YSLEEP
W .10be O Mto .Tlogic make the
W W .C O W W
instruction WWis executed. Y.C To avoid .TWthe MCU W entering the Y
.100
sleep mode
M.T
Wunless it isWthe programmer’s
W . 100 O M W C O
purpose, it W is recommended Y.C to.T write
W the Sleep WW Enable (SE) Y. bit to one Wjust before the execution of
W
the SLEEP instruction W .100 andOtoMclear it immediately W .100wakingOup.
after M.T
WW .100Y. C
WW .100Y.C M.TW
W O W
WW .100Y.C M.TW WW
W O
WW .100Y.C M.TW
W O
WW .100Y.C 45
W W
7799D–AVR–11/10 W
.C OM
00Y .TW
W W.1 Y.COM W
W 00 .T
9.10.2 PRR0 – Power Reduction Register 0 W W.1 Y.COM W
.TW W
5W.
100 4 OM.3T
Bit OM7 6 2 1 0
0 0 Y .C
.T W - WPRTIM0 .100–Y.C PRTIM1
W
M .TW PRSPI
W.1 Y.COR/W
(0x64) M - - - PRR0
W W W WW 0R0Y.COR/W .TW R/W
W .100 .T
Read/Write R/W R/W R R/W
O0M .1 OM
WValue C 0 WW 0 Y.C 0
.T W W W
Initial
1 00 Y .
M .T W 0
W . 1 0 0 M .TW 0 0 0
M . O W O
.CO .TW WW 00Y.C .TW bits W W.100Y OM.TW
W .C
.100Y M
W• Bit 7:6
W . 1 - Res: Reserved
O M
W O
WW bits.1are .C WWread.1as Y.C .TW
WW .100Y.C M.TW These 00Yreserved M
W will always
.Tand W
00zero.
O M
W O
W
WW .100Y.C M.TW
O
-W O W O
W
WW .100Y.C M.TW
O • Bit 5 PRTIM0: Power Reduction Timer/Counter0
Writing W W oneY.to
a logic CO this bit shuts down the W
Timer/Counter0 O module. When the Timer/Counter0
W O
WW .100Y.C M.TW is enabled, W 0 0 .T W WW .100Y.C M.TW
W . 1
operation OM
will continue like before the W shutdown. O
W
WW .100Y.C M.TW
O
O W O
W O WWReserved Y.C bit .TW WW .100Y.C M.TW
WW .100Y.C M.TW • Bit 4 W - Res:
1 0 0
WW 0and
. OM W O
W
WW .100Y.C M.TW
O This bit isW reserved 0 Y.C will always
.T Wread as zero. WW .100Y.C M.TW
. 1 M W O
WW .100Y.C M.TW W 1 M
• Bit 3 - PRTIM1: W.Power Reduction
O Timer/Counter1 W CO
W O
WW .100Y.C M.TWriting W WW 0Y.bitC W
.Tdown WW .100Y.module. W
M.TWhen the Timer/Counter1
a logic oneWto . 10this shuts
O M the Timer/Counter1
W C O
W O
WW .will Y.C W Y. W
WW .100Y.C M.isTW enabled, operation 100continue M .TWbefore theWshutdown.
like
W .100 O M.T
W O C
W
WW .100Y.C M.TW
O
W
W O W C O
W O • Bit 2 - PRSPI: Power
WW .100Y.C M.TW
Reduction Serial Peripheral WWInterface Y. .TW
WW .100Y.C M.TW W .100InterfaceO Mby
Writing a logic one to Wthis bit shuts O down the Serial Peripheral C stopping the clock to
W
WW .100Y.C the
O
.T W WW 0
.C
0Ythe .TW the SPI WW .100Y. M .TW
module. When waking . 1 up SPIM again, should
W W .C OM
W WW 00Y.CO .TW W WW 00Y.CO .TWto ensure proper
be re initialized
W 00 Y .T
operation. W .1 M .1 M
W 00 W .1
W.1 Y.•CO BitM1.T- Res: Reserved WW bit
.1
.CO .TW
M WW 00Y.CO .TW
M
W W W 0 Y W .1
W 00 TheseMbits
W.1 Y
M
W .C O are reserved and
W W WWwill 0always 0 Y .COread.Tas W zero. W
W 00 .T .1 M .1 M
W 00• Bit 0 - Res: .T Reserved bit W.1 W .1 M
W.1 Y.COM W Wwill always OM
.Cread WW 00Y.CO .TW
W These bits are reserved W
and 0 Y as
.T W
zero. W .1
W 00
W.1 Y.COM W
M
W W WW 00Y.CO .TW W 1
W 00 .T .1 M . M
9.10.3 PRR1 – Power
W W.1Reduction .C OMRegister 1
Y W 1
W 100
W.Bit OM 7
.T .1 M .
WW 1 00Y.CO0 .TW
M
W Y .C W
6
W WW 5
0 Y .CO .T3W
4 2
W
W .10 0 .T – .1 0 M - . 1 OM PRR1
W W(0x65) .C OM PRUSB
W
–
WRW 00RY.CO R/W
–
W
–
W WW– 00PRUSART1 Y.CR/W .TW
W 0 Y .T W .T 1
Read/Write
0
W.1 Y.COM0 W 0
R/W R
W.1 0 Y.COM 0 W
R R
W0W 00Y.C
. OM
W W W
WWInitial.1Value M.T
W 0 0 T 0 0
0 0 M .T . 1 0 M . W . 1 O
W O W O W .C
W•WBit .710- 0PRUSB: Y.C .TW Reduction WW .100Y.C M.TW W .100
Y
M.T
W
O M Power USB
W O W W .C O
W WW 00Y.C W WW .the Y.C
100USB O .TW W Y
.100module. .TW
Writing .a
W 1 logic one O Mto.Tthis bit shuts down W .C
byMstopping the clock to
W W the
Y .C O MWhen
W
WW up
waking theY.USBC again, W WW be 0Yinitialized W
M.Tto ensure proper
W operation. .100 M.T
W .100 O M.T the USB should W .10re O W W .C O
Y .TW
• BitW 6:1W- Res:YReserved O bits W C O W W .C OM
.C .TWwill always WW .100Y. M.T
W W .100
Y .TW
W
These bits W .100reserved
are O Mand read W as zero. C O W W .C OM
W W .100
Y .TW
W O W C O W W .C OM
0 -WPRUSART1: Y.C Power W WW .100Y. M.T
W W .100
Y
• Bit W
W .100 O M.T Reduction USART1 W C O W W
aW .Cthis bit W W USART1 Y. W the clock W to the module.
WritingW logic one
W .100
Yto
O M.T
shuts downWthe
W .100 byOstopping M.T
When waking C W C
Y. be re
WW up 0the 0Y.USART1 M.T
again, the W
W USART1
.100
should
M.T
initialized to ensure proper
W
operation. WW.1 O W C O
Y.C W WW .100Y.
W
W .100 O M.T W
WW .100Y.C M.TW WW
W O
WW .100Y.C M.TW
W O
WW .100Y.C 46
W W
7799D–AVR–11/10 W
.C OM
00Y .TW
W W.1 Y.COM W
W 00 .T
10. System Control and ResetW W W.1 Y.COM W
.T W 00 .T
.C OM W W.1 Y.COM W
00Y .TW W 00
W.1 Y.COM W
.T
10.1 Resetting the W AVRW.1 Y.COM W W
W During 0 .TRegisters are W 00 .T
W .10reset,
C all
O MI/O set
W Wto.1theirYinitial
.C OMvalues, and the program starts execution
.TW
W
Wfrom the 1 0Reset
.
0Y Vector. M .TWThe instruction W .
placed100 at the M .TW Vector must be a JMP – Absolute
Reset
M . O W O
.CO .TW WW– instruction
00Y
.C W reset handling WW .routine. 100
Y.C If the.Tprogram W
.100Y M
W
Jump
W . 1 O M to.Tthe
W .C O M never enables an interrupt
W O .C W Y W
WW .100Y.C M.TW WW the
source,
0Interrupt
0Y
.1This
Vectors
Mthe.TW are not Wused, .and 100 regular program code can be placed at these
M.T
W O locations.W is C O
also case if the ResetW W Vector is .Cin Othe Application section while the Interrupt
WW .100Y.C M.TW WW .100Y .
M .TW W .
Y
100 circuitOdiagram M .TW
Vectors are in the Boot
O section or vice versa. W The in Figure 10-1 shows the reset
WW .100Y.C M.TW W“System
logic. 1 and Reset M .T W
Characteristics” on page 267 defines the electrical parameters of the
W .C O W W. Y .CO W WW 00Y.CO .TW
W Y W W 0 T W
W 00
W.1 Y.COM W
.T reset circuitry..10 M. .1
WW 00Y.CO .TW
M
W W WW 00Y.CO .TW W
W 00 .T The I/O ports Wof .1 the AVR Mare immediately reset .1 their initial
to M state when a reset source goes
W 00 W
.T active. This does .1not 0
0 requireMany clock source to W be.1running.OM
W W.1 Y.COM W WW 00Y.CO .TW W W 0 0Y.C M.TW
W 0 0 .T W 1 M . 1
W.1 Y.COM W
After all reset
W W.
sources
Y
have
.CO .TW
gone inactive, a delay counter
WW 00Y.CO .TW
is invoked, stretching the internal
W W 0 W .1 normal
W 00
W.1 Y.COM period
.T reset. This allowsWthe .10 powerOtoMreach a stable level Wbefore
Wthrough OMoperation starts. The time-out
.CSUT
W of the W counter
delay Y .Cis defined W by the W
user 0Y
the .TWCKSEL Fuses. The dif-
W . 1 00 M .T W W
W . 10 0
O M .T
W .1 0
O Mand
W O ferent selectionsWfor the delay Y.C period are presented WWin “Clock .C
YSources” Wpage 29.
on
WW .100Y.C M.TW W . 100 M .TW W .100 O M.T
W O C
W
10.2 WReset . 1 Sources M W O W C O
W
WW .100Y.C The
O
W
.TATmega8U2/16U2/32U2 WW .100Y.C M.TW WW .100Y. M.T
W
M W has O five sources of reset: W C O
W
WW .100Y.C M.TW
O
W
O • Power-on Reset. W W O W .C O
W
WW .100Y.C M .TW (V W
The MCU Y is.Creset when
.TW
the supply WW voltage is
.100
Ybelow the Power-on
M.T
W Reset
threshold ). W . 100 O M W C O
W
WW .100Y.C • External
O
.TW Reset. The
POT
M.T pin for longer
M MCUW is reset O when a low level is W
present on the
C ORESET
W
WW .100Y.C than
O
TWminimumW
W
M .the pulseW . 100
length. O M W C O
W
WW .100Y.•CWatchdog
O
.TW Reset. The WWMCU.1is00reset Y.C W
.Tthe WW .100Y. M.T and the
W
O M W when
O M Watchdog Timer W periodC
. expires
O
W
WW .100Y.C Watchdog .TWis enabled. WW .100Y.C M.TW WW .100Y M.T
W
M W O W .C O
W .CO .TW
WW .100•YBrown-out Reset. TheW
W
MCU is.1reset
.C
00Y whenMthe .TW supply voltage WW V .1is00below Y the TW
M.Brown-out
O M W O WCC
.C O
W
WW .100Reset Y.C threshold .TW (VBOT)W and W the Brown-out Y.C Detector .TW is enabled. WW .100Y M.T
W
M W .100 O M W C O
W O Y.C WWand.1detects . W
WW .1• 0USB 0Y.CReset. .TTheW MCU isW W when
reset
. 100 the USB M .TW is enabled
macro 00Y a USB M.T Reset.
O M W O W .C O
W Note that with this reset the USB
WW .100Y.C M.TW WW macro C
Y.remains .Tenabled
W WWthe device
so that
.100
Y stays attached
M.T
W to
the bus. W . 100 O M W C O
W O WW .100Y .
W
O W O W .C O
W
W
W O W O W W .C O
Y
M.T
W
W O W O W W .C O
Y
M.T
W
W O W O W W .C O
Y
M.T
W
W O W O W W .C O
Y .TW
W O W C O W W .C OM
W W .100
Y .TW
W O W C O W W .C OM
W W .100
Y .TW
W O W C O W W .C OM
W W .100
Y
W O W C O W W
W W
W O W C O
W
W O W C O
W O W
WW .100Y.C M.TW WW
W O
WW .100Y.C M.TW
W O
WW .100Y.C 47
W W
7799D–AVR–11/10 W
.C OM
00Y .TW
W W.1 Y.COM W
W 00 .T
Figure 10-1. Reset Logic W W.1 Y.COM W
.TW W 00
W.1 Y.COM DATAW
.T BUS
.C OM W
Y W W 00 .T
WW .100Y .C W W 00
W O M.T W.1 Y.CRegister OMCU M.TStatus
.C W .TW
WW .100Y
(MCUSR)
M .TW M .TW W
W . 100 O M
W O
PORF
BORF
EXTRF
WDRF
WW .100Y.C M.TW
USBRF
.100Y M W O Power-onW Reset
.CO .TW
W O W
WW .100Y.C M.TW WW .100Y.C M.TW WCircuit . 1 00Y M
W W .C O
W 00 Y .T W .1 M
Brown-out
W W BODLEVEL [2..0] 0 .T W .1
W 00
W.1 Y.COM W
.T .10 OM
Reset Circuit
WW 00Y.CO .TW
M
W W WW 00Y.C T W W
W 00
W.1 Y.COM W
.T .1 M.
Pull-up Resistor .1
WW 00Y.CO .TW
M
W W WW 00Y.COSPIKE .TW W
W 00 .T .1 M .1 M
FILTER
W WW 00Y.CO .TW
W 00 .T W .1 M .1 M
W 00 .T W .1 USB Device M .1 M
W W.1 Y.COM W WW Reset Y CO
.Detection W W WW 00Y.CO .TW
W 00 .T W .10 0 M. T .1 M
W 00 .T W .1 M Watchdog .1 M
W 00 .T W .1 M Oscillator .1 M
W
W 00
W.1 Y.COM W
.T .1 M Clock W.1Counters OM
WW 00Y.CO Generator W CK
W WDelay 0 Y.C W
W W
. 1 00 M .T W
W . 1 O M .T
W .1 0
O M.TTIMEOUT
W O WW .100Y. C
W
W O W C O
W
WW .100Y.C M.TW
O
WW .100Y.CCKSEL[3:0] .TW WW .100Y. M.T
W
W O M W CO
W O WW .100Y.
SUT[1:0]
W
W O W C O
W
WW .1Reset .CO .TW WW .100Y.C M.TW WW .100Y. M.T
W
10.2.1 Power-on 00Y M W O W C O
W
A.C
O
WWpulse.1is Y.C Wan On-chip WW Y. .TW
WW .100Y Power-on
M .TWReset (POR) W
00generated
O M .Tby W .100 circuit.
detection
O MThe detection level
W .C O W . C W W Y.C W
WW .100Y is defined
M
in
.TW “System and
W Reset
W .
Characteristics”
100
Y
O M .T on page 267.
W The
W .100
POR is activated
O M.T whenever
W VCC isO WWto trigger .C
WW .10well 0Y.C
below the detection W
.TW a failureW . 0 .C circuit
level. TheYPOR
10voltage. M .TW
can be used
.100
Ythe start-up
M.T
WReset, as
as Oto Mdetect in supply
W O W .C O
W
W
O W O W .C O
W A Power-on
WW Power-on .C Reset
.TW
(POR) circuit
WW ensures Y.C that the device
.TW WWfrom .1Power-on.
is reset
00Y Reaching
.TW the
. 1 00Y M
Reset threshold voltage W . 100
invokes O
the M delay counter, which W determines C O Mhow long the
W O WW .100Y .
WW device .C
00Yis keptMin.TRESET W W
afterWVCC rise. . 0Y.CRESET
10The M
W
.Tsignal is activatedW again, without
TW
M.any delay,
W . 1 O W O W .C O
W Y .C W W W 0 Y .C .T W W 0 0 Y .T W
W when V0 decreases .T below the detection 0 level. W. 1 OM
W.1
0 CC
OM W.1 OM
W to Y CO W O
W 10-2. O
Figure
WW .100Y.C M.TW
MCU Start-up, RESET
WW Tied 0 0 V.CC
.T W WW .100Y.C M.TW
W O W.1 Y.COM W WW 00Y.CO .TW
Y.C VPOT WW W
WW .10V0CC .T W 0 0 .T
W.1 Y.COM W
W .C OM W W.1 Y.COM W W
W W
.100
Y
M.T
W W
W .100 O M.T
W
W .100 O M.T
W O W .C
WW RESET Y.C WV WW .100Y.C M.TW W .100
Y .TW
W .100 O M.T RST W C O W W . C OM
W W .100
Y .TW
W O W C O W W .C OM
WW .100Y.C M.TW tTOUT W
W Y. W W .100
Y .TW
W O W .100 O M.T W W .C OM
TIME-OUT
WW .100Y. C Y
WW .100Y.C M.TW M.T
W W
W .100
W O W C O W
W W
W O W C O
WW .100Y.C M.TW
INTERNAL
WW .100Y. M.T
W
W O W C O
WW .100Y.C M.TW
RESET WW .100Y.
W O W
WW .100Y.C M.TW WW
W O
WW .100Y.C M.TW
W O
WW .100Y.C 48
W W
7799D–AVR–11/10 W
.C OM
00Y .TW
W W.1 Y.COM W
W 00 .T
Figure 10-3. MCU Start-up, RESET W W.1Extended .C OMExternally
M .TW W . 100
Y
M .TW
W O
.CO VPOT W Y.C .TW
. 1 00YVCC M.TW W
W . 100 O M
W O
W O W O
.T W WW .1RESET 0 0Y.C M.TW WW .100YV.C RST
M .TW
M W O W O
.100Y M W O W O
W O
WW .100Y.C M.TW WWTIME-OUT 0 0 Y.C .T W WW .100Y.C tTOUT
M .TW
W . 1 O M W O
W
WW .100Y.C M.TW
O
W O W O
W
WW .100Y.C M.TW
O
W O
WW .100Y.C M.TW W
INTERNAL
1
W. OM W O
O WW .100Y.C M.TW
W RESET
W O W O
W WW 0External
10.2.2 0 Y.C
O
.T W
Reset WW .100Y.C M.TW WW .100Y.C M.TW
W.1 OM W O W O
WW .100Y.C M.TWAn External WW Reset.10 Y.C
is0generated .T Wa low level
by WW on the. 1 0 0Y.C pin.
RESET
W
M.TReset pulses longer than the
W O M W C O
W O
WW width Y.C “System WWCharacteristics” Y. W 267) will generate a
WW .100Y.C M.TW minimum pulse
. 100
(see
M .TW and Reset W .100 O Mon.Tpage
W O W O W C
. guaranteed
WW .100Y.C M.TW
reset, even W if W
the clock0is Y.C not running.
.TW
ShorterW pulses are Y
.100
not W to generate a reset.
M.T– on its positive edge, the
When the applied W .
signal10 reaches O M the Reset Threshold W Voltage C
– O
V
W O W .
WW .100Y.C M.delay TW counterWstarts the
W
. 10MCU0Y.C after M TWTime-outW
.the 00Y – has
.1tTOUT
RST TW
.
Mexpired.
W O W C O period
W W – .C O
C W . .TW Y W
WW .100Y. M .TW W . 100
Y
M
W
W .100 O M.T
W O C
W
WW .100Y.C Figure
O
.TW 10-4. External WW Reset Y.C TW WW .100Y. M.T
W
M W .100 During O M .Operation W C O
W O
WW .100Y.C M.TW CC W
W
W . 100 O M W C O
W
WW .100Y.C M.TW
O
W
W O W C O
W
WW .100Y.C M.TW
O
W
W O W CO
W
WW .100Y.C M.TW
O
W
W O W C O
W O
WW .100Y.C M.TW WW .100Y.C M.TW WW .100Y. M.T
W
O W O W .C O
W
W
O W O W .C O
W
W
O W O W .C O
W
W
O W O W .C O
W
W
O W O W .C O
W
W
O W O W .C O
W
W
O W O W .C O
W
W
W O W O W W .C O
Y
M.T
W
W O W O W W .C O
Y
M.T
W
W O W O W W .C O
Y
M.T
W
W O W O W W .C O
Y .TW
W O W C O W W .C OM
W W .100
Y .TW
W O W C O W W .C OM
W W .100
Y .TW
W O W C O W W .C OM
W W .100
Y
W O W C O W W
W W
W O W C O
W
W O W C O
W O W
WW .100Y.C M.TW WW
W O
WW .100Y.C M.TW
W O
WW .100Y.C 49
W W
7799D–AVR–11/10 W
.C OM
00Y .TW
W W.1 Y.COM W
W 00 .T
10.2.3 Brown-out Detection W W.1 Y.COM W
.TW W 00
W.1 Brown-out
.T
OM Detection (BOD) circuit for monitoring the
ATmega8U2/16U2/32U2
.C OM has an On-chip
W Y . C W
1 00YduringMoperation
VCC .level .TW W
by comparing W . 10it0to a fixed O M .T
trigger level. The trigger level for the BOD
W O Y.C
WW 0Y.C M
can be 0selected by.TtheW BODLEVEL WW Fuses. . 100 The trigger M .TW level has a hysteresis to ensure spike
W . 1 O W C O
free Brown-out .C Detection. The W
hysteresis on theY . detection .TW level should be interpreted as VBOT+ =
.TW WW .100Y M .TW W . 100 M
M O W O
.CO .TW WW
VBOT + VHYST/2 .Cand V.BOT-
00Ythe trigger TW
= VBOT - VHYST
WW /2..1When 00Y
.Cthe BOD .TW
is enabled, and VCC decreases to a
.100Y M
W
value W . 1
below O M level (V in Figure
W 10-5), O M
the Brown-out Reset is immediately acti-
W O
WW When .C BOT- W
Y.C TW
WW .100Y.C M.TW vated. 1 0 0 Y
V increases
CC OM
.T W above Wthe trigger . 1 0 0level (V M . in Figure 10-5), the delay counter
W .C O Wthe W. Y .C the .Time-out W Wt W has 0 .CO BOT+.TW
Yexpired.
W Y W W
starts MCU 0 after T periodW TOUT.1 0
W 00
W.1 Y.COM W
M
W W WW 00Y.CO .TW W
W 00
W.1 Y.COM W
.T The BOD circuit .1 will only Mdetect a drop in VW
CO“System CC Wif.1the voltage
.CO .TW
Mstays below the trigger level for lon-
W ger W
than Wt W given 0 Y .in T W and Reset W 0
Characteristics” 0 Y on page 267.
W
W .100 O M.T BOD .10
W O M. W W.1 Y.COM W
W .C
WW .100Y.C M.TW W .100
Y W
M.T During Operation
W 00
W.1 Y.COM W
.T
W O Figure 10-5.
W W Brown-out .C O Reset W
WW .100Y.C M.TW W .100
Y .TW W 00
W.1 Y.COM W
.T
W CO W W . C OM W
WW .100Y. W VY W W 00 VBOT+.T
W O M.T
W
W .100CC OM.T VBOT-
W W.1 Y.COM W
C W .C
WW .100Y. M.T
W W .100
Y .TW W 00
W.1 Y.COM W
.T
W C O W W .C OM W
WW .100Y. M.T
W W .100
Y .TW W 00
W.1 Y.COM W
.T
W C O W
RESET
W .C OM W
WW .100Y. M.T
W W .100
Y .TW W 00
W.1 Y.COM W
.T
W C O W W .C OM W
WW .100Y. M.T
W W .100
Y .TW W 00
W.1 tTOUT OM
.T
W CO W
TIME-OUTW .C OM W Y .C W
WW .100Y. M .TW W .100
Y
M .TW W
W .100 O M.T
W O C
W
WW .100Y.C M.TW
O
W
W O W C O
W
WW .100Y.C M.TW
O
WW .100Y.C M.TW
INTERNAL WW .100Y. M.T
W
W O W C O
O WW .100Y.
W RESET
W
W O W C O
W
WW .1Reset .CO .TW WW .100Y.C M.TW WW .100Y. M.T
W
10.2.4 Watchdog 00Y M W O W C O
W .CO the.TWatchdog WW out,.1it00will Y.Cgenerate .TW WW Y. CK cycle
00one W
WW .100Y When
M
W times
W O M a short reset pulse.1of
W O M.T duration. On
W O WW .C
WW .100the Y.Cfalling .edge
TW of this pulse, WW the.10delay 0Y.Ctimer M TW counting
.starts Y
.100 period
the Time-out W
M.TtTOUT. Refer to
W “Watchdog M
O Timer” on page W W O W W .C O
W 51 for.1details .Con operation of theW Watchdog Timer.
Y W
WW .100Y.C M.TW 00Y M .TW W .100 O M.T
W O .C
W
WW .Figure .CO .TW WW During Y.C .TW WW .100Y M.T
W
1 00Y 10-6. M Watchdog Reset W .100 Operation O M W C O
W O WW .100Y .
WW .100Y.C CCM.TW WW .100Y.C M.TW M.T
W
O W O W .C O
W
W
O W O W .C O
W
W
O W O W .C O
W
W
W O W O W W .C O
WW .100Y.C M.TW WW CK.100Y.C M.TW W .100
Y
M.T
W
W O W O W W .C O
Y
M.T
W
W O W O W W .C O
Y
M.T
W
W O W O W W .C O
Y .TW
W O W C O W W .C OM
W W .100
Y .TW
W O W C O W W .C OM
W W .100
Y .TW
W O W C O W W .C OM
W W .100
Y
W O W C O W W
W W
10.2.5 USB Reset W O W C O
W Y.C W WW with 0Y. USBM
.10the .TWMCU feature enabled, and
When the WUSB
W .100 is enabled
macro
O M.T and configured W C O reset
WW Reset Y.C TW
W Y.
if a valid USB
W .100signalling O M.is detected, W .100
the microcontroller
W
is reset unless the USB macro
W .C W
W 00Y .TW W
W W.1 Y.COM W
W 00 .T
W W.1 Y.COM
W 00
W W.1 50
7799D–AVR–11/10 W
.C OM
00Y .TW
W W.1 Y.COM W
that remains enabled. This allows
W
Wthe.100deviceOtoMstay .T
attached to the bus during and after the
W W
W reliability. 0Y .C TW
reset, while enhancing .T firmware . 1 0 M .
OM W O
0 0 Y.C .T W WW .100Y.C M.TW
W.1 10-7. OM
Y.C USB.TReset WW 00Y.CO .TW
WW Figure
1 0 0 M
W DuringWOperation .1 M
W W. CC CO
Y . W WW 00Y.CO .TW
.T W W 00 .T W .1 M
.COM W W.1 Y.COM W WW 00Y.CO .TW
Y W W 0 W
00
W.1 Y.COM W
.T .10 M.T .1
WW 00Y.CO .TW
M
W W WW 00Y.CO .TW W
W 00 .T .1 M .1 M
W W.1 Y.COM W WW 00Y.CO .TW W WW 00Y.COEnd of .Reset TW
W 00 .T W . 1 (USB Lines) M t . 1 M
.1 M WDP O USBRSTMIN
W O
W
WW .100Y.C M.TW
O
WW .100Y.C USB .TW
Traffic WW .100Y.C M.TW USB Traffic
W O M W O
W
WW .100Y.C M.TW
O
WW .100Y.C M.TW
DM
WW .100Y.C M.TW
W O W O
W
WW .100Y.C M.TW
O
W O W O
W
WW .100Y.C M.TW
O
W O W O
W
WW .100Y.C M.TW
O
W O W O
W
WW .100Y.C M.TW
O
W O W O
W
WW .100Y.C M.TW
O
W O W O
W
10.3WWInternal 0 CO
Y.Voltage .T W Reference WW .100Y.C M.TW WW .100Y.C M.TW
0 .CO .TW
W.1 OM W Y.C
O W
WW reference. 00Y
WW .100Y.C MATmega8U2/16U2/32U2
.TW WW .100features .TW
an internal bandgap 1 This reference is used for
W O W C O M W W .
.C OM
C W . .TWas an input Y W
WW .100Y. Brown-out
M .TW Detection,
W and .100
Y be used
it can
M
Wto the .Analog
W 100 Comparator.
O M.T
W O C
W
10.3.1 WVoltage . 1 Reference M Enable Signals andW Start-up O Time W C O
W
WW .100Y.C TheMvoltage
O
.TW reference WW has.1a00start-up Y.C .TWthat may W
W
.10the0Y. .TW be used. The
Mshould
W O M time influenceW way
C O it
W
WW .100Y.Cstart-up
O
W is given WW Y.C .TWCharacteristics” WW on 0Y. 267.
.10page .TW
M .Ttime in “System
W .100 andOReset M W C O MTo save power, the
W W Y. CO
reference is
W not always W Wturned on.0 Y .C reference
The .T W is on W
duringW the following
0 0 Y. .T W
situations:
W . 1 00 M .T W . 10 O M W .1 O M
W CO When C WW .1[2..0] .C W
WW .100Y.1. .TW the BOD isWenabled
W
.10(by0Y.programming M .TW the BODLEVEL 00Y Fuse). M.T
O M W O W . C O
W
WW .100Y2..C When W bandgap W Y.C .TWto the Analog WWComparator .100
Y (by setting
M.T
W the
M .Tthe Wreference
W .100is connected O M W C O
W O bit in ACSR).WW Y.C WW .100Y . W
WW .100Y.CACBG M .TW . 100 M .TW W O M.T
W Thus, when O the BOD is not enabled, W O bit,Wthe user .C
WW .100Y.C M.TW WW .100after Y.C setting .Tthe
W ACBG W .100
Y
must always
M.T
Wallow the
reference O to start up before the Woutput from O M
the Analog Comparator W is used. .C O
To reduce power
W
WW consumption 0 Y.C .T W WW .100Y.C M.TW WW .100Y M .TW
1 0 O
W. .CO .TW
Min Power-down mode, Wthe user .CcanO avoid the three conditions WW 00above Y.C to ensure
.TW
that
WW the.1reference
00Y is turned off WWentering
before . 1 0 0YPower-down M .TW mode. W . 1 M
OM W O W O
W
W O W O
10.4 Watchdog Timer W
WW .100Y.C M.TW
O
W O W O
W
WW .100Y.C M.TW
O
W O
10.4.1 Features
W• Clocked from separate On-chip Oscillator .1 M
W.1 Y.COM W WW 00Y.CO .TW W WW 00Y.CO .TW
•W3W Operating 0 modes .T W .1 M
0
W W
– Interrupt 0 T W 0 0 .T W 1
0
W.1 ResetOM
. W.1 OM W. OM
WW .100Y.C M.TW
– System
W O
– Interrupt
WW 00Y.CO .TW
and System ResetSelectable
W
W
WTime-out 0 .CO from
Yperiod .T W16ms to 8sWW .100Y.C M.TW
W .1 0 forM
• PossibleW
W
.1
Hardware fuse
OMWatchdog always W
.Cone W
onW (WDTON)
Y .CO .TW
fail-safe mode
W WW 00Y.CO
Y W 0
• Early Wwarning
W .10 0
after
OM
.T
Time-Out period reached, 0
programmable
W.1 Y.COM W
Reset (see W.1 modes)
operating
W
W .C W W
after W 2 Time-Out00 Y
periods .TW
reached. W 00
W.1 Y.COM W
.T
W W.1 Y.COM W W
W 00 .T W 00 .T
10.4.2 Overview W.1 Y.COM W W W.1 Y.COM
W W 00 hasM .T W 00
ATmega8U2/16U2/32U2 W.1 Y.C O an Enhanced Watchdog W W.1 Timer (WDT). The WDT is a timer count-
W 00 on-chip.T128 W kHz oscillator. W
ing cycles W of a separate The WDT gives a early warning interrupt
W W.1 Y.COM W
W 0 0 .T
W.1 OM
WW .100Y.C 51
W W
7799D–AVR–11/10 W
.C OM
00Y .TW
W W.1 Y.COM W
when the counter reaches a given
W
W .100 value.
time-out
.T
OM The WDT gives an interrupt or a system reset
W .C
when the counter M .TW reaches two
Wtimes .the Y
100 givenOtime-outM .TW value. In normal operation mode, it is
.CO .TW uses the W
required 00Ythat theMsystem WW 0Y.C MTimer
WDR.1- 0Watchdog .TW Reset - instruction to restart the coun-
W . 1 O W C O
WW ter before .C
00Ythe time-out .TWvalue is reached. WW .If10the 0Y.system M TW restart the counter, an interrupt or
.doesn't
. 1 O M W O
WW reset
Wsystem 00Y
.C will be issued.
.TW WW .100Y.C M.TW
M .TW . 1 O M W O
Y.C
O
00 .T Figure 1
10-8. Watchdog Timer
W.1 OM W. OM W O
WW .100Y.C M.TW WW .100Y.C128kHzM.TW WW .100Y.C M.TW
WCLKD1
WCLKD0
W O W O
W
WW .100Y.C M.TW
O
WW .100OSCILLATOR Y.C .T W WW .100Y.C M.TW
W OM W O
W
WW .100Y.C M.TW
O
WW .100Y.C M.T W
OSC/1
WW .100Y.C M.TW
W O OSC/3 W O
W
WW .100Y.C M.TW
O
WW .100CLOCK Y.C .T
OSC/5 W WW .100Y.C M.TW
W
DIVIDER
OMOSC/7 W O
W
WW .100Y.C M.TW
O
OSC/2K
OSC/4K
OSC/8K
OSC/16K
OSC/32K
OSC/64K
OSC/128K
OSC/256K
OSC/512K
OSC/1024K
W O W O
W
WW .100Y.C M.TW
O
WW .100Y.C M.TW WW .100Y.C M.TWDP0 W
W O W C O
W
WW .100Y.C M.TW
O
WW .100Y.CWATCHDOG RESET .T
W WW .100Y. .TW
WDP1
MWDP2
W O M W CO WDP3
W
WW .100Y.C M.TW
O
WW .100Y.C WDE .TW WW .100Y. W
M.TMCU RESET
W O M W C O
W
WW .100Y.C M.TW
O
WW .100Y.C WDIFM.TW WW .100Y. M.T
W
W O W C O
W
WW .100Y.C M.TW
O
WW .100Y.C M.TW WW .100Y. .TW
MINTERRUPT
W O W C O
W
WW .100Y.C M.TW
O
WW .100Y.WDIE C
.TW WW .100Y. M.T
W
W O M W C O
W
WW .100Y.C M.TW
O
WW .10WDEWIE 0Y.C M.TW WW .100Y. INTERRUPT EARLY
M .TW
WARNING
W O W O
W
WW .100Y.C M.TW
O
W O W O
W
WW .100Y.C M.TW
O
W InOInterrupt mode, theW W gives
WDT anO interrupt when the W W
W timer .expires .CO two times. This interrupt
WW .100Y.Ccan M .T W W .1 0 0Y.C M.TW 1 00Y M .TW
W CO
be used to wake the W
W
device from Osleep-modes, and W
Y.C allowed
W as a Y
also .CO system
general
TW
timer. One
WW .100Y.example .TisWto limit theWmaximum . 1 0 0time M .TW for certain
W .
operations,1 00giving an M .interrupt when the
W W .C OM
W 00 Yoperation .Thas run longer W than 0
expected.
.10 M .1 M
W
W 00In System .Reset
W.1 Y.COM W
T mode, the WDT .1gives a O reset
M when the timer W W.1 two
expires OM This is typically
times.
WW in 0case Y .Cof runaway W W 0 Y.C W
W W
. 1 used
00 to prevent
M .T system W
hang-up
W . 1 0
O M .T code.
W .1 0
O M.T
W .CO .TW Y.C W .C
WW .The 00Ythird mode, Interrupt and WWSystem 100ResetOmode, M .TWcombinesW the other
0Y
.10two modes Mby .TW first giving
W 1 O M W . W W .C O
W an Y .
interruptC and W then switch W W System
to 0Y .C
Reset .T
mode. W This W
mode will for 00 Y
instance .T
allow
W a safe
W . 1 00 M .T . 10 M W . 1 O M
W O W O W . C
WW shutdown 00Y
.C by saving .TW critical parameters WW .10before 0Y.C a M .TW reset. W W.100Y OM.TW
system
. 1 O M W O .C
W
WW In addition 0 Y.Cto these .T Wmodes, the W warning
Wearly 0 0Y.C interrupt .TWcan be enabled WW in.1order 00Y to generate M.T
W an
. 1 0 M W .1 O M W C O
W O
.C the .WDT W .C WW .100Y . W
WWinterrupt 1 00Y
when
M TW counterWexpires.1the 00Yfirst time. M .TW W O M.T
. O W O W .C
WThe WWWatchdog .C
00Y always .TWon (WDTON) Y.C
WWfuse,.1if00programmed, .TWwill force W the Watchdog
Y
.100 Timer Mto
W
.TSys-
. 1 O M W O M W W .C O
temWW Reset0mode.
0 Y
.C With .TW the fuse programmed WW .100the Y.CSystem WReset mode W bit (WDE) Y
.100 andOInterrupt M.T
W
W
W . 1 O M W O M.T W W . C
mode bit (WDIE) are locked to 1 and
WW .100Y.C M.TW WW 0 respectively. Y.C To further W ensureW program 0 security,
0Y W
altera-
M.Tor
tions toWthe Watchdog O set-up must follow W .100 sequences.
timed O M.T The sequenceWfor W .1clearing
.C O
WDE
WW time-out Y.C configuration W WW .100Y.C M.TW W .100
Y .TW
changing W .100 O M.T is as follows: W C O W W .C OM
M.T change enable
W .100
Y .TW
1. In the W same operation,O write a logic one W to the O
Watchdog
C W W
bits WDCE .C OM
Y.C one WW .100Yregardless . W Y W
Wand W
WDE. .100A logic
W
M.T must be writtenWtoWWDE O
W
M.T of the previousWvalue W .100of the OM.T
W O
.C if it.T Y. C W Y .C
WDE
W W bit and
.100
Yeven
M
Wbe cleared
will W after the
W .100operation. O M.T
W
W .100
W .C O W WDE00and C
Y. Watchdog W W W
2. Within WW the.1next 00Yfour clock M .TW cycles, write Wthe .1 M.T prescaler bits (WDP) as
W O W CO
. done .in
desired, but with the WDCE bit cleared.
WW .100Y.C M.TW WW This must
.100
Ybe
MT
one operation.
W
W O W C O
W O W
WW .100Y.C M.TW WW
W O
WW .100Y.C M.TW
W O
WW .100Y.C 52
W W
7799D–AVR–11/10 W
.C OM
00Y .TW
W W.1 Y.COM W
W 00 .T
While the WDT prescaler allowsWonly W.1evenY.division C OM factors (2, 4, 8...), the WDT peripheral also
includes a clock M TW that directly
.divider W .
acts100on theOclock M .TW source. This divider handles odd division
C O W W .C
factors
. 1
Y .
00(3, 5, 7).MIn W W
.T combination withWthe . 0 Y
10prescaler, M .aW
T large number of time-out values can be
W C O W .C O
Wobtained. Y . W W 0 Y .T W
W . 1 00 M .T W . 10 O M
WWdivider O Y.C
.TW WThe .C
00Yfactor change .TW is also ruled WW by the . 100secureOtimed M .TWsequence : first the WDE and WDCE
M . 1
W beY.set, O M W
.CO .TW Wmust
bits 00
C andTthen
. W four cycles WW are 0Y.C Mto
10available .TWload the new divider value into the
.100Y M
W
W . 1 O M W .
.C O
W O WDTCKD .C
register. Be aware that after W this operation
Y WDE .TW will still be set. So keep in mind the
WW .100Y.C M.TW WW .100Y M .TW W . 100 M
O W O
W O WW 00Y.C
importance of order of operations. When setting
WW .100Y.C M.TW
up the WDT in Interrupt mode with specific val-
WW .100Y.C M.TW W 1 M .T W
ues of prescalerW. andOdivider, the divider register W must be O loaded before the prescaler register :
W
WW .100Y.C M.TW
O
1. Set W
WDCE and O WDE W O
W
WW .100Y.C M.TW
O
W O 2. Load W the divider factor O into WDTCKD WW .CO .TW
WW .100Y.C M.TW 3. Wait WW .100Y.C M.TW W 1 00Y
WDCE being automatically clearedW(just .
W waitY2.Cmore OM cycles)
W .C O WW 00Y.CO .TW W 0 W
W W
. 1 00 Y
M .TW
4. Set
W again W . 1
WDCE and O MWDE W .1 0
O M.T
W O .C WW .100Y. C W
WW .100Y.C M.TW 5. Clear WW WDE, . 00Y
1set WDIE M
and
W
.Tload the prescalerWfactor into M.T
WDTCSR in a same operation
W O W O W .C O
W Y.C W W W 0 Y .C T W W 0 0 Y .T W
W 00 .T 6. Now the system
W.1 Y.COM W tions would .10 is properly M. configured for Interrupt W.1 only M Inverting the two opera-
mode.
.CO .TW
W W WWhave00been Y .COresulted
.T W into “Reset W Wand 0 0
Interrupt Y mode” and needed a third
W
W .100 O M.T operation to W .1
clear WDE..C OM W W.1 Y.COM W
C W .TW
WW .100Y. TW
M.The
W .100
Y W .100 .T
OM for turning off the Watch-
W C O following code W Wexample .C OM one assembly and
shows W Wone C Y .C
function W
WW .100Y. M .TWTimer. The W .
Y
100assumes M .TW W
W .100 O M.Tby disabling interrupts
dog example W O that interrupts are controlled C (e.g.
W
WW .100Y.C globally)
O
.TW so thatW
W
M no W .100 will O
interrupts M
occur during the execution W of these
C Ofunctions.
W
WW .100Y.C M.TW
O
W
W O W CO
W
WW .100Y.C M.TW
O
W
W O W C O
W
WW .100Y.C M.TW
O
W
W O W C O
W
WW .100Y.C M.TW
O
W
W O W C O
W
WW .100Y.C M.TW
O
W
O W O W . C O
W
W
O W O W .C O
W
W
O W O W .C O
W
W
O W O W .C O
W
W
O W O W .C O
W
W
O W O W .C O
W
W
O W O W .C O
W
W
W O W O W W .C O
Y
M.T
W
W O W O W W .C O
Y
M.T
W
W O W O W W .C O
Y
M.T
W
W O W O W W .C O
Y .TW
W O W C O W W .C OM
W W .100
Y .TW
W O W C O W W .C OM
W W .100
Y .TW
W O W C O W W .C OM
W W .100
Y
W O W C O W W
W W
W O W C O
W
W O W C O
W O W
WW .100Y.C M.TW WW
W O
WW .100Y.C M.TW
W O
WW .100Y.C 53
W W
7799D–AVR–11/10 W
.C OM
00Y .TW
W W.1 Y.COM W
W 00 .T
W W.1 Y.COM W
.TW W 00
W.1 Y.COM W
.T
.C OM W
Y
.100 Code
Assembly TW
M.Example
(1) W 00 .T
WW WDT_off:
.100
Y
M.T
W W 00 .T
W WW .1;00Turn Y off .global
MT
W W 00 .T
W.1 Y.COM W
interrupt
O M.T W .C O W
Y.C W WW cli .100
Y
M.T
W W 00 .T
W .100 O M.T W .C O W W.1 Y.COM W
WW .100Y.C M.TW WW .100Y; Reset Watchdog
M.T
W Timer W 00 .T
W O W . C O W W.1 Y.COM W
WW .100Y
wdr
WW .100Y.C M.TW Min .TW W 00
W.1 Y.COM W
.T
W O W; WClear WDRF
.C O MCUSR W
WW .100Y.C M.TW W 0Y
inW.10r16,CMCUSR M.T
W W 00
W.1 Y.COM W
.T
W O W . O W
WW .100Y.C M.TW Wandi .1r16, 00Y (0xff W
M.T& (0<<WDRF)) WW.10
W 0
OM
.T
W O W W .C O Y .C W
WW .100Y.C M.TW Wout 100
MCUSR,
.
Y r16 .TW
M
W
W .100 O M.T
W O
W
WW .100Y.C M.TW
O W
;WWrite 00Y
.C one.TW WWWDE .100Y.C M.TW
W . 1logical O M to WDCE and
W O
W O W old00prescaler Y.C WW Y.C W time-out
WW .100Y.C M.TW ;W Keep
. 1 M .T W
setting to prevent
W . 1 0 0unintentional
O M.T
W O C
W
WW .100Y.C M.TW
O in WWr16, WDTCSR Y.C .TW WW .100Y. M.T
W
W . 100 O M W C O
W
WW .100Y.C M.TW
O ori W
W r16, .1(1<<WDCE) 00Y
.C | (1<<WDE)
.TW WW .100Y. M.T
W
W O M W C O
W O
WW .100Y.C M.TW ; Turn
out
WW .100Y.C M.TW
WDTCSR, r16
WW .100Y. M.T
W
off W WDT O W C O
W O
WW .100Y.C M.TW ldi W
W
r16, W . 100
(0<<WDE) O M W C O
W O
WW .100Y.C M.TW out WDTCSR, WW .1r16 00Y
.C .TW WW .100Y. M.T
W
W O M W C O
W O
WW .100Y.C M.TW; Turn on WW Y.C .TW WW .100Y. M.T
W
global
W . 100interrupt O M W C O
W
WW .100Y.C M.TW
O sei WW .100Y.C M.TW WW .100Y. M.T
W
W O W C O
W O
WW .100Y.C M.Tret W WW .100Y.C M.TW WW .100Y. M.T
W
W O W C O
W O
WW .100Y.CC Code W
.TExample
(1)
W
M W O W C O
W O
WW .100Y.C void .TW WDT_off(void) WW .100Y.C M.TW WW .100Y. M.T
W
O M W O W .C O
W
WW .100Y.C { M.TW WW .100Y.C M.TW WW .100Y M.T
W
O W O W .C O
W
WW .100Y.C __disable_interrupt();
.TW WW .100Y.C M.TW WW .100Y M.T
W
O M W O W .C O
W
WW .100Y.C M.TW
__watchdog_reset();
W
O W O W .C O
W
WW .100Y.C
/* Clear WDRF
TW~(1<<WDRF);
.&=
in
WW .100Y.C M.TW
MCUSR */
WW .100Y M.T
W
MCUSR
O M W O W .C O
W
WW .100Y/* .C .TW WW .100Y.and C
.TW WW .100Y M.T
W
Write
O M logical one toWWDCE O M
WDE */ W .C O
W
WW .100/* Y.CKeep .old TW prescaler WWsetting Y.C prevent .TW unintentional WW .1time-out00Y .TW
M W .100 to O M W C O M*/
W O W Y.C WW .100Y . W
WW .10WDTCSR0Y.C M W
|=.T(1<<WDCE) W| (1<<WDE); . 100 M .TW W O M.T
W O W O W .C
WW .1/* .C
00YTurn off .TW WDT */ WW .100Y.C M.TW W .100
Y
M.T
W
W O M W O W W .C O
WW .WDTCSR 00Y
.C = 0x00; .TW WW .100Y.C M.TW W .100
Y
M.T
W
W 1 O M W O W W .C O
WW .100Y.C M.TW
__enable_interrupt();
WW .100Y.C M.TW W .100
Y
M.T
W
}W O W O W W .C O
Y .TW
W O W C O W W .C OM
WW 1. .The
Note: Y.C
example code Wassumes that WWthe part 0Y. header W W
M.T file is included.WW.10
0Y .TW
W 100 O M.T W .10specific O .C OM
.C is accidentally WW .for Y. C by W Y W
Note:WIfWthe Watchdog
. 1 00Y M .TW enabled,
100example M.T
a runawayW pointer .or
W 100brown-out O M.T
condition, W O
the device will be reset and the W
Watchdog .C O W .C
WW .100Y.C M.TW WW YTimer will stay
W enabled. W If the.1code 00Y is not
set up to handle the Watchdog, this might lead W
to 100eternalOloop
.an M.Tof time-out resets. W To avoid this
W O Y. C W
WWthe application 00Y
.C .TW WW . 100clear M TW
.Watchdog W
situation, . 1 Msoftware should always the System Reset Flag
WW Y .C O
W W WW 00Y.CO .TW
(WDRF)W and the.WDE 0 control M. T
bit in the initialisation routine, even if the Watchdog is not in use.
10 W.1 OM
W WW 00Y.CO .TW WW .100Y.C
The following code .1exampleOshows M one assembly W and one C function for changing the time-out
WW 00Timer.
value of theWWatchdog Y.C .T W WW
W.1 OM
WW .100Y.C M.TW
W O
WW .100Y.C 54
W W
7799D–AVR–11/10 W
.C OM
00Y .TW
W W.1 Y.COM W
W 00 .T
(1) W W.1 Y.COM W
.C OM W W.1 Y.COM W
Y
WDT_Prescaler_Change: W W 00 .T
WW .100Y ; .
TurnC off W
global interrupt
W 00 .T
W WW .100Y
cli .C W W 00 .T
O M.T W ; Reset O M.T
Watchdog Timer W W.1 Y.COM W
Y.C W WW .100Y .C W W 00 .T
W .100 O M.T Wwdr O M.T W W.1 Y.COM W
WW ; .Start .C
WW .100Y.C M.TW Y
100 timed
W
M.Tsequence
W 00
W.1 Y.COM W
.T
W O W .C O W
WW .100Y.C M.TW WW in .100r16, Y
M.T
W W 00 .T
W O W .C O WDTCSR
W W.1 Y.COM W
W
WW .100Y.C M.TW W ori .10r16, 0Y (1<<WDCE) M.T
W | (1<<WDE) W 00
W.1 Y.COM W
.T
W O W W .C O W
WW .100Y.C M.TW Wout .1WDTCSR, 00Y M.T
r16 W W 00
W.1 Y.COM W
.T
W O W W .C O W
WW .100Y.C M.TW W; -- Got0Yfour cycles
.10 M.T
W to setWthe new 00values M
W.1 = 64K O
from .T here -
W O W W .C O W Y .C W
WW .100Y.C M.TW
; Set new prescaler(time-out) value cycles (~0.5 s)
W . 1 00Y M .TW W
W .100 O M.T
W O W O | (1<<WDP2) W Y. C
WW .100Y.C M.TW
ldi W r16, (1<<WDE)
Y.C .TW W | (1<<WDP0) .100 M.T
W
out
W
W .
WDTCSR, 100 r16 O M W C O
W
WW .100Y.C M.TW
O
WW .100Y.Csetting .TWnew values, WW .100Y. M.-T
W
; -- Finished W O M W
used 2 cycles
C O
W
WW .100Y.C M.TW
O
WWon global Y.C interrupt .TW WW .100Y. M.T
W
; Turn
W . 100 O M W C O
W O
WW .100Y.C M.TW sei W
W
W . 100 O M W C O
W O
WW .100Y.C M.TW ret W
W
W . 100 O M W C O
W O
WW .100Y.C MC.TCode W Example WW (1) Y.C .TW WW .100Y. M.T
W
W .100 O M W C O
W O
WW .100Y.C M.Tvoid WW .100Y.C M.TW
W WDT_Prescaler_Change(void) WW .100Y. M.T
W
W O W C O
W O
WW .100Y.C M.{TW WW .100Y.C M.TW WW .100Y. M.T
W
W O W C O
W O
WW .100Y.C M.T__disable_interrupt();
W WW .100Y.C M.TW WW .100Y. M.T
W
W O W C O
W O
WW .100Y.C M__watchdog_reset();
W
W O W C O
W
WW .100Y.C M.TW
O /* Start timedW equenceY.C */
.TW WW .100Y. M.T
W
W
W .1|00(1<<WDE); O M W C O
W O WW .100Y .
WW .100Y.C M.TW
WDTCSR |= (1<<WDCE)
WW .100Y.C /* .T W M*/ .TW
O M Set new W
prescaler(time-out) O value = 64K cycles W (~0.5 .C O
s)
W
WW .100Y.C WDTCSR .TW = (1<<WDE) WW | .(1<<WDP2) Y.C TW WW .100Y M.T
W
M W 100 O M|. (1<<WDP0); W C O
W O WW .100Y .
WW .100Y.C__enable_interrupt();
.TW WW .100Y.C M.TW M.T
W
O M W O W .C O
W
WW .100Y }.C .TW WW .100Y.C M.TW WW .100Y M.T
W
O M W O W .C O
W
WW Note: .C .TW code W
W Y.C .TW header file WW .100Y M.T
W
. 1 00Y 1. The M example assumes W . 100 the part
that O Mspecific is included.
W C O
W O Y.C W .
0Y since W
WW Note: 0Y.CWatchdog
0The .TWTimer should WW be .reset 100 before M .TWchange ofWthe WDP
any .10bits, Ma.Tchange
W . 1 O M W O W W .C O
WWin the.1WDP .C can .TW WW .when Y.C .TW to a shorterWtime-out 0Y
.10period. M.T
W
00Y bits M result in a time-out
W 100 switching
O M W C O
W O W .
Y
M.T
W
W O W O W W .C O
10.5 Register DescriptionWW .100Y.C M.TW WW .100Y.C M.TW W .100
Y
M.T
W
W O W O W W .C O
W Y.C W WW .100Y.C M.TW W .100
Y
M.T
W
10.5.1 MCUSR – MCU W
W .100
Status Register O M.T W C O W W .C O
WW Y.C W WW .10on 0Y.which .TWsource caused W an.1MCU00Y reset. .TW
The
W 100 Register
MCU .Status
O M.T provides information W C O M reset
W W .C OM
W Y.C W WW 4 .100Y. 3 M.TW2 W .10 00
Y .TW
BitW
W .100 7 OM.T6 5
W C O 1
W W .C OM
W Y.C –W USBRFW
W – 00YWDRF .
M.T
W W PORF Y
.100 MCUSR .TW
0x34W (0x54)
W . 100 – OM.T W .1
C O
BORF EXTRF
W W .C OM
R .C
WWR/W .100Y . TW R/W W R/W 00Y
WW
Read/Write
00Y
R W
M0.T
R R/W
M .R/W W.1
Initial Value W.1 0 O 0 W .C O
See Bit Description W
W .C W Y W W
W 00Y .TW W 00
W.1 Y.COM W
.T
W W.1 Y.COM W W
• Bit 7:6 W– Res:.1Reserved 00 Bit .T W 00 .T
W .C OM W W.1 Y.COM
W
These bitsWare reserved 00Y and will.Talways W readW as zero..100
W.1 Y.COM W W
W W 00 .T WW
W . 1 O M
WW .100Y.C M.TW
W O
WW .100Y.C 55
W W
7799D–AVR–11/10 W
.C OM
00Y .TW
W W.1 Y.COM W
W 00 .T
• Bit 5 – USBRF: USB Reset Flag W W.1 Y.COM W
.TW W
W.The 100 bit isOreset M.Tby a Power-on Reset, or by writing a logic
This bit is set
C OifMa USB Reset occurs. W .C
zero.1to00the
.
Y flag. .TW
M
W . 100
Y
M .TW
W O W O
W O W O
.T W W• WBit 4.1–00Res: Y.C Reserved .T W Bit WW .100Y.C M.TW
OM This W bit is reserved OMand will always read W .CO .TW
0 Y.C .T W WW .100Y.C M.TW WW as .zero. 1 00Y M
0
W W.1 Y.COM W W W Y .CO .TW W WW 00Y.CO .TW
W 00 .T W
• Bit 3 – .WDRF: 0 0 Watchdog Reset Flag W.1 M
W.1 Y.COM W W W 1 Y.COM W W The 0bit 0 Y .CO .TW
W ThisW bit is set 0
if a Watchdog T Reset W
occurs. is reset by a Power-on Reset, or by writing a
W
W .100 O M.T W .10 O M. W W.1 Y.COM W
W . C
WW .100Y.C M.TW logicWzero to the
.100
Y flag.
M.T
W W 00
W.1 Y.COM W
.T
W O W W .C O W
WW .100Y.C M.TW • BitW 2 – BORF:
Y
.100 Brown-out
W
M.T Reset Flag WW.10
W 0
OM
.T
W O W W . C O Y .C W
WW .100Y.C M.TW This bitWis set if.1a00Brown-out Y
M TW occurs.
.Reset W
The W bit.1is00reset byMa.TPower-on
O Reset, or by writing a
W CO W W .C O W Y .C W
W Y . W W 0 Y T W W 0 0 .T
W 00
W.1 Y.COM W
.T logic zero to the .1flag.
0 M. .1
WW 00Y.CO .TW
M
W W WW 00Y.CO .TW W
W 00 .T .1 M .1 M
W W.1 Y.COM W • Bit 1 – EXTRF: WW External Y .COReset WFlag W WW 00Y.CO .TW
W 00 .T W 0 0 T
M. occurs. The bitWisWreset .1 by aOPower-on M
W.1 Y.COM This bit is set W if an W.1External .CO Reset .C Reset, or by writing a
W W 0 0 .T W W 1 0 0 Y
M .T W W . 10 0 Y
M .TW
W.1 OM logic zero to theWflag. . W O
WW .100Y.C M.TW W . 1 00Y M W O
W O
WW
WW .100Y.C M• .TBit W 0 – PORF: Power-on
. 1 00YResetMFlag O
W O WW 00Reset O
Y.C occurs. WW 00by Y.Cwriting .aTW
WW .100Y.C This M .T bit is set if W
W a Power-on
.1 M .TW The bit isWreset only
W . 1 O M
logic zero to the flag.
W O W O W Y. C
WW .100Y.C ToMmake .TW use of W theWReset . 0Y.C toM
10Flags .TW a resetWcondition,
identify .100the user .TW read and then
Mshould
W O W C O
W O Wearly as .C WW Y. is cleared W before another
WW .100Y.C Reset M
the MCUSRWas
.TW . 100
Ypossible
M .in
TW the program. If the 1register
W . 00 O M.T
O occurs, the source W O .C
W
WW .100Y.C M.TW
reset of the reset can be found by examining
WW .100Y.C M.TW WW .1the 00Y
Reset Flags.
M.T
W
W O W C O
W O
0Y.C M.Timer
WW .–10Watchdog TW Control WW Y.C .TW WW .100Y. M.T
W
10.5.2 WDTCSR Register
W . 100 O M W C O
W
WW .100YBit .CO .TW 7 WW6 .100Y5.C M.4TW 3
WW 2 .100Y.1 M.T0
W
M W O W .C O
W
WW .100Y .CO .TW WDIF WWDIE
(0x60) W 0Y.C WDCE .TW WDE WWDP2W.10WDP1
W 0Y .TW WDTCSR
M W .10WDP3 O M C O M WDP0
W O W .
WW .100Y.C M.TW Y R/W W
WW .100InitialY.C
Read/Write
.TW 0
R/W R/W R/W R/W R/W
WR/W R/W
.1000 M0 .T
Value
O M 0 W 0 O 0 X 0 W .C O
W
W
O W O W .C O
W
WW •.1Bit .C .TW
W 0Y.C M.TW WW .100Y M.T
W
00Y7 - WDIF: M
WatchdogW Interrupt
W . 10Flag O W .C O
W O
Cset when W Y.C WW Y W
WW This 1
bit .is
00Y M .TWa time-outWoccurs .
twice
100 M .TW
in the Watchdog Timer
. 00 Watchdog
and if1the
W O M.T Timer is
. O W O .C
W
configured for interrupt. WDIF isW
WW .100Y.C M.TW W automatically Y.C cleared .TW
by hardware WWwhen executing
Y
.100 a logic
the
.TW corre-
sponding interrupt handling vector. W .100
Alternatively, O M WDIF is cleared by W
writing C O Mone to the
W .C O W .C WW .100Y . .TW
WWflag. .When 00Y the I-bit .T in
WSREG and WWDIE . 1
are0 0Y set, the M . TW
Watchdog Time-out Interrupt is M
executed.
O
1 OM W O W
W
•W W6 - WDIE:
Bit .COWatchdog W Interrupt
W
WEnable Y .CO .TW W WW 00Y.CO .TW
Y W 0
W 0
.10 bit is written
Wthis
.T
OM to one and the W Win .1 0
.C OMRegister is set, the W W.1 Y.COM W
When .C I-bit the Status W Watchdog Interrupt is
W W 0Y
.1If0WDE M .TW W
W .with
Y
100 this setting,O M.T the WatchdogWTimer
W
W .100 O M.T
enabled. W is
O cleared in combination is .
inC Interrupt
WW and.1the .C
00Ycorresponding W WW .100Y.C M.TW W Y
.100 occurs. .TW
Mode, W O M.T interrupt is executed W if C time-out
O in the Watchdog W W Timer .C OM
M.T Reset Mode.W
W .100
Y .TW
If WDEWisWset, the .Watchdog O Timer is in W
Interrupt and C O
System TwoW .C
consecutivesOM
YC WW .100Y. W Y W
W in the
times-out .100Watchdog M.T
W
Timer will set WDIF. W Executing O the
W
M.Tcorresponding interrupt W .100vectorOwill M.T
W O C W .C
clear W
W 0Y.C automatically W WW .1:0the 0Y. Watchdog W
M.T goes to System
W Y
.100 Mode.
WDIE and
W .10WDIF O M.T by hardware W C O W W Reset
W for 0keeping Y.C the.TWatchdog W WW security Y. .TW the interrupt. W To reinitialize
This is W useful
W .1 0 O M
Timer
W .100 while O Musing
the Interrupt .C Reset WW C
Y. after each Winterrupt. This should how-
WWand.1System 00Y M .TMode,
W WDIE must be00set
.1 M.T
ever not be W done W within theO interrupt service W
routine itself, C
as Othis might compromise the safety-
W 00Y
.C .TW WW .100Y.
W . 1 O M W
WW .100Y.C M.TW WW
W O
WW .100Y.C M.TW
W O
WW .100Y.C 56
W W
7799D–AVR–11/10 W
.C OM
00Y .TW
W W.1 Y.COM W
function of the Watchdog System
W
W .100 mode.
Reset
.T
OMIf the interrupt is not executed before the next
W . C
time-out, a System M .TW Reset will
Wbe applied. . 100
Y
M .TW
W O
. 1 00Y M W O
O
W 10-1. Watchdog Timer Configuration
Table
WW 00Mode O
W WWWDTON
W
0 Y .CO .TW
(Fuse) WDE WWDIE Y.C .TW Action on 2x Time-out
M .T . 1 0 M W . 1 O M
W O .C
.CO .TW W1W(unprogrammed) 00Y
.C .TW0 W0W .1Stopped 00Y .TW None
.100Y M W . 1 O M W .C O M
W O W . C W Y W
WW .100Y.C M.TW W1 (unprogrammed)
.100
Y
M.T
W
0 W 1 00
Interrupt
W.1 Y.COM W
Mode.T Interrupt
W O W W .C O W
WW .100Y.C M.TW 1W (unprogrammed)
.100
Y
M.T
1W 0W 00 Reset Mode
System
W.1 Y.COM W
.T Reset
W O W W .C O W
WW .100Y.C M.TW W
1 (unprogrammed) .100
Y
M1.T
W
1
W Interrupt 00 and System
W.1 Mode OM
.T Interrupt, then go to
W O W W .C O W Reset Y .C W System Reset Mode
WW .100Y.C M.TW W . 100
Y
M .TW W
W .100 O M.T
O W O Y.C Mode.TW Reset
W
WW .100Y.C M.TW WW .100Y.C xM.TW
0 (programmed) x WW System0Reset
.1 0 M
W W .C O W W Y .C O
W W W W
0 Y .CO .TW
Y W W 0 .T 0
W 00 .T
W.1 Y.COM W• Bit 4 - WDCE:
0
.1Watchdog MChange Enable WW.1 OM
WW 00Y.CO .TW W 0 Y.C W
W W
. 1 00 M .T This bit is usedW W in.1timed sequences O M for changing WDE W
0
.1 and prescalerO M.T bits. To clear the WDE bit,
W O Y.C bits,.TWDCE W Y. C W
WW .100Y.C M.TW and/or change WWthe .prescaler 100 M
W mustWbe set. .100 M.T
W O W C O
W
WW .100Y.C M.TOnce
O
W writtenWtoWone,.1hardware 00Y
.C W
.Tclear WW .100Y. M.T
W
O W O M
will WDCE after W four clock.Ccycles.O
W
W
W O W C O
W
WW .100Y.C M• .TBit
O
W 3 - WDE:WWatchdog W .C
YSystem TW Enable
.Reset WW .100Y. M.T
W
W . 100 O M W C O
W O WDE is overridden WW that.1WDE .
WW .100Y.C M.TW WWby WDRF . 0Y.Cin MCUSR.
10must M .TW This means 00Y is always M.T
Wset when WDRF is
set. To clear WDE, W
WDRF beO cleared first. This W
feature ensures C O multiple resets during con-
W
WW .100Y.C ditions
O
OM causing failure, and a safe start-up
W O after the failure. W O
W
W O 5, 2:0 - WDP[3:0]: W O
3, W
W .CO .TW
WW .100Y.C• Bit T W WW Watchdog 0 0Y.C Timer .TW Prescaler W 2, 1 and 1 000Y
OM
. .1 M WWwhen
. OM
W . C
The WDP3..0 bits WW the
determine .CO .TTimer
Watchdog W prescaling Y.CWatchdog
the W
W W
. 1 00 Y
M .T W W
W . 10 0 Y
O M
W
W .1 00
O M.T Timer is run-
W .CO The.Tdifferent WW time-out C
Y. periods
WW .100Y.C M.TW
ning. prescaling values and their corresponding Ware shown in
WW .100Y Table M
on
W
page 58. W O W .100 O M.T
W O WW .100Y .C
W
W O W .C O
W
WW – Watchdog .CO Timer .TWClock Divider WW Register Y.C .TW WW .100Y M.T
W
10.5.3 WDTCKD
. 1 00Y M W . 100 O M W C O
W .CO .T7W Y.C W Y . W
WW .1Bit 6 WW 5 W W .1100 M.T
00Y M W .100 4 OM.T 3 2
W C O
0
W (0x62) O W Y.C WW WCLKD1 .
Y WCLKD0.TW
WW .100Y.C M.TW .TW .100
- -
WWDEWIF-
CM .10
0WCLKD2 M
WDEWIF WDEWIE
M
WDTCKD
W O W O W
W R/W 00Y R/W .TW .C O
WW Read/Write .C R.TW W Y.C .TW R/W W
. 1 00Y M
R WR/W
W . 100R/W OMR/W W .1 OM
W .C O W Y .C W W W 0 Y.C0 W
W M.T
Initial Value 0 0 0 0 0 0 0
W 0 0 Y .T W W . 1 0 0 M .T . 1 0
. 1 O M W O W .C O
W
WW• Bit.17:6 .C .TW
W Y.C .TW WW .100Y M.T
W
00Y- Res:M Reserved bitsW W . 100 O M W C O
WW bits O Y.C W Y . W
WThese .C
00Yare reserved .TW and will always WW read . 100 as zero. M .TW W .100 M.T
Y
M.T
W
W O W O W W .C O
WW Warning .CFlag Clear .TW Mode W W.100Y OM.TW
WW .100Y.C M.TW
• Bit 5 - WDEWIFCL: Watchdog Early
00Y
.1WDEWIF M
O W O by.C
When
W W Wthis bit
0
has
Y.C
been
T
set
W by software,
WW .100Y.C M.TW
the interrupt flag is notWWcleared 1 00Y
hardware.TW
when entering W .1 0 the Watchdog
O M . Interrupt subroutine W (it Chas
O to be cleared by W
software
W
. by . OM a
writing
C
Wone W .C
00Yflag). M.TW WW .100Y. M.T
W W .100
Y .TW
logic
W
to.1the
O W C O W W .C OM
WW .10the 0Y.C W WW .100Y. M.T
W W Y
.100 interrupt .TW
When cleared, W WDEWIFO M.T is cleared by hardware W when C O executing the corresponding
W W .C OM
WWvector. Y.C W WW .100Y. M.T
W W .100
Y
handling
W W
W O W C O
• Bit 4 -W WCLKD2
W Y.CWatchdog
bit:
.TW Timer Clock WW Divider Y. W
W . 100 O M W .100 O M.T
See “Bit 1:0 W - WCLKD[1:0]: Y.C Watchdog W Timer W W Divider”
Clock C
Y. on page 58.
W
W .100 O M.T W .100
WW .100Y.C M.TW WW
W O
WW .100Y.C M.TW
W O
WW .100Y.C 57
W W
7799D–AVR–11/10 W
.C OM
00Y .TW
W W.1 Y.COM W
W 00 M.T
• Bit 3 - WDEWIF: Watchdog Early W W.1Warning .C OInterrupt Flag
.T W W . 1 0 0Y M .TW
This bit is set M
when a first time-outWoccurs in Othe Watchdog Timer and if the WDEWIE bit is
0 .CO .TW
YWDEWIF WW cleared 0 0Y.C .TW when executing the corresponding
enabled.
. 1 0 M is automatically W . 1 by O hardware
M
W O Y.C
WW Y.C
interrupt00handling .TW Alternatively,
vector. WW WDIF . 100 canObe M TW
.cleared by writing a logic one to the flag.
W . 1 O M W C
When the .
I-bit C in SREG and WDEWIE W are set, Y .
the Watchdog W Time-out Interrupt is executed.
.TW WW .100Y M .TW W . 100 M .T
M O W O
.CO .TW WW 00Y.C .TW WW .100Y.C M.TW
.100Y M
W
• Bit W 2 -.1WDEWIE: O M Watchdog Early Warning W InterruptO Enable
W
WW .100Y.C M.TW
O
WW this.1bit
When 00Y
.C
has been .Tset
Wby software, WWan interrupt . 1 0 0Y.CwillM W
be.Tgenerated on the watchdog interrupt
W O W O M W W .C O
WWwhen C warning
0Y.Early 0Yhardware. .TW
WW .100Y.C M.TW vector . 1 0the M .TW flag is W set to one
W . 10by O M
W O
W
WW .100Y.C M.TW
O
W O • Bit 1:0 W O
- WCLKD[1:0]: Watchdog Timer
WWClock
W .CO .TW
Divider
W W .C O
Y W
W 00 .T
W.1 Y.COM W Table 10-2. .1
.COTimer
M W.1 Y.COM W
W W WWWatchdog 0 Y .T W
Clock Divider W WConfiguration 00 .T
W
W .100 O M.T W .10
C W YWCLKD1.TW
WW .100Y. M.T
W WCLKD2 W .100
WCLKD0W 00Mode
W.1 Y.COM W
.T
W C O W W .C OM W
WW .100Y. W Y W 0W 0 WDT = M
0Clk .T
W O M.T
0W
W .100 0 OM.T W W.1 Y .C
Clk
O 128k
C W .C W TW/ 3
WW .100Y. M .TW 0 W .
Y
100 0 OM.T 1W
W
00WDT = Clk
.1Clk O M.128k
W O W W C
0Y. = ClkM.TW
WW .100Y.C M.TW 0 WW .100Y1.C M.TW 0 W .10WDT
Clk /5
W W .C O W W Y .C O
W W W W
0 Y .CO 128k.TW
W 00 Y .TW 0 W .10 1 0 M. T 1 .1
Clk 0 = Clk M /7
W.1 Y.COM W WW WDT O128k
W W
. 1 00 M .T 1 W
W .10 O M 0 Clk
W .WDT0
1 = ClkO M./T9
W O WW .100Y. C 128k
WW .100Y.C M.TW 1 WW .1000Y.C M.TW 1 Clk = Clk
TW
M/ .11
W O W C O
W O WW .100Y.
WDT 128k
WW .100Y.C M.TW1 WW .100Y.C M.TW M13 .TW
W 1 O 0 Clk W = Clk C O /
W
WW .100Y.C M.T1W
O
WDT 128k
M.T
W
O W 1 O 1 Clk W = Clk .C O
/ 15
W
WW .100Y.C M.TW WW .100Y.C M.TW WW WDT
.100
Y128k
M.T
W
W O W C O
W
WW .100Y.C M.TW
O
W
O W O W .C O
W
W
O W O W .C O
W
W
O W O W .C O
Table 10-3. Watchdog W Timer Prescale
WW .100Y.C M.TW
Select, DIVW =W 0 (CLKwdt Y=.CCLK128 .TW / 1) WW .100Y M.T
W
W .100 O M W C O
W O WW .100Y Watchdog .
M.T Typical
O Number of WDT W
Oscillator O Early warning Typical W C
Reset/Interrupt
. O
W
WW .100Y.C M.T W beforeW1st W Y.C W WW .100YTime-out W
M.Tat
Cycles
W . 100
time-out
O M .TTime-out at W C O
WW 0WDP0 O W= 5.0V WW .100YVCC = 5.0V .
WDP3 WDP2 WWDP1 0Y.C M.TW (Early warning) WW .100Y.C M.VTCC M.T
W
. 1 O W O W .C O
0 0
W
W0W .1000Y.C M.TW2K (2048) cycles WW .100Y.C M.T16Wms WW .100Y32 msM.TW
W .C O W W Y .C O
W W WW 00Y.CO .TW
0 0 0W
W 10 Y .T W
4K (4096) W
cycles 0 0 .T
32 ms .1 64 ms M
0
0 0 1W W 000 .T
8K (8192) cycles W 00 64.Tms W .1 128 ms M
0 0 1W W 1 00 16K.T (16384) cycles W 00 0.125.T s W .10.250 s M
W W 00 W
0 1 0 W 0 00
W.1 Y.COM W
32K.T (32768) cycles
W.1 Y.CO M.sT
0.25 .10.5 s
WW 00Y.CO .TW
M
W W W 0 0 .T W W 1
0 1 0 W 1 .10 0 64K .T
M(65536) cycles .1 0.5M s W1.0 . s OM
W
0 1 1 0 .1 128KM (131072) cycles W.1 1.0OsM W2.0 s O
W WW 00Y.CO .TW WW .100Y.C M.TW WW .100Y.C
0 1 1 1 W.1 256KO(262144)M cycles W 2.0 Os Ws
4.0
1 0 0 0 W 512K O (524288) cycles W 4.0 s O 8.0 s
1 0 0 1 W 1024K (1048576) O cycles W 8.0 s O 16.0 s
W O W
WW .100Y.C M.TW WW
W O
WW .100Y.C M.TW
W O
WW .100Y.C 58
W W
7799D–AVR–11/10 W
.C OM
00Y .TW
W W.1 Y.COM W
W 00 .T
Table 10-3. Watchdog Timer Prescale Select, DIV = 0 (CLKwdt W W.1 = CLK128 .C OM / 1) (Continued)
M .TW W . 100
Y
M .TW
O W O
0Y.CEarlyMwarning
W Watchdog
0 0 Y.C .T W of WDTWOscillator . 1 0 .TW Typical
W W.1 Y.COM Number
W WW 00Y.CO Time-out W
Reset/Interrupt Typical
Cycles before 1st W time-out .T at Time-out at
W 100
WDP1WW. WDP0 .COM (Early warning)WW
.T .1 M
WDP3 WDP2
Y W W 0 Y.CO VCC.T =W5.0V VCC = 5.0V
.T W W . 1 00 M .T . 1 0 M
M 1 WW 0 Y.C O W O
1.CO 0
.TW 00 .TW WW .100Y.C M.TW
.100Y M
W
W . 1 O M W O
W 1 O 0
WW .100Y.C M.TW
1
WW 1.100Y.C M.TW WW .100Y.C M.TW
O W O
W 1 O 1 0 WWW Y.C WW .100Y.C M.TW
WW .100Y.C M.TW
0 0 T W
1 0 .
W. OM W O
Reserved
W O
WW .1100Y.C 1M.TW 0 WW1 .100Y.C M.TW WW .100Y.C M.TW
W O W O
W O
WW 1.100Y.C 1 M.TW 1 WW 0 0 0 Y.C .T W WW .100Y.C M.TW
W. 1 OM W O
W O
WW 1 .100Y.C 1 M.TW 1 W1W .100Y.C M.TW WW .100Y.C M.TW
W O W O
W
WW .100Y.C M.TW
O
W O W O
W WW 00Y.CO .TW WW .100Y.C M.TW WW .100Y.C M.TW
W.1
Table 10-4. OM Timer Prescale
Watchdog Select,
W DIV O = 1 (CLKwdt = CLK128 W/ 3) O
W O W .CO .TW WW 00Y.CO .TW Watchdog
WW .100Y.C M.TW WWNumber . 1 00Yof WDTMOscillator W
Early warning . 1 Typical M Reset/Interrupt Typical
W W .C O W W before
Cycles Y .CO1st time-out W W
W
WTime-out 0 Y
at.CO .TW Time-out at
Y W W 0 M. T 0
W .100 M.T .10 warning)
.CO .TW W=.15.0VY.COM W VCC = 5.0V
WDP3 WWDP2
.C OWDP1 WDP0 WW (Early WVCC
W W
.0100
Y
M.T
W W
W
0 Y
.10(2048) cycles OM
W
Wms.100 OM
.T
0 W C O 0 0 W 2K .C W 48 Y .C W 96 ms
WW .100Y. M.TW W .100
Y
M .TW W
W .100 O M.T
O W O Y. C
0 W0
WW .100Y.C M.TW
0 1
WW4K (4096) C
Y.cycles .TW WW 96 ms
.100 M.T
W 192 ms
W . 100 O M W C O
W 1O .C Wms 00Y. W 384 ms
0
WW .100Y.C M.TW
0 0 WW 8K (8192)
. 100
Y cycles
M .TW W192
.1 M.T
W O W C O
0 W
WW0 .100Y1.C M.T1W
O 16KW (16384) Y .C
cycles .TW WW s .100Y.
0.375
M.T 0.75 s
W
W
W .100 O M W C O
W O
WW(32768) Y.C WW Y. W
0 W1W .1000Y.C M.T 0W 32K
. 100cycles OM.T
W 0.75 s
W .100 O M.T 1.5 s
W .CO 1.TW W .C W Y. C W
0 W1W 000Y 64K WW (65536)1cycles
. 00Y M .TW 1.5W s .100 M.T 3 s
100Y.C W .C .TW Y W
0 1WW
. 1 M
0 .TW 128KW (131072)
W . 00Y
1cycles O M 3 sW
W .100 O M.T6 s
W CO 1 TW 256K (262144) Y.C W .C
0 1 WW 1100Y. . WW .cycles 100 M .TW 6s W .100
Y
M12 .TW s
W . O M W O W W .C O
W Y.C W W W 0 Y .C .T W W 0 0 Y .T W
1 0 W 0.100 0 M.T 512K (524288) cycles .10 M 12 s W . 1 O M 24 s
W O W O W .C
WW 0 .100Y.C1 M.TW1024K (1048576) WW cycles Y.C .TW 24 s W W.100Y O48 Ms.T
W
1 0 W . 100 O M C
W O WW .100Y .
WW1 .100Y.C .TW WW .100Y.C M.TW M.T
W
1 0 0
O M W O W .C O
WW
W Y.C W WW .100Y.C M.TW WW .100Y M.T
W
1 0 1 W.100 1 OM.T W O W .C O
W0W .1000Y.C M.TW WW .100Y.C M.TW WW .100Y M.T
W
1 1 W O W O W W .C O
WW .100Y.C M.TW WW .100Y.C Reserved M .TW W .100
Y
M.T
W
1 1 0 W 1 O W O W W . C O
Y
M.T
W
W O W O W W .C O
WW .100Y.C M.TW
1 1 1 0 Y W
WW .100Y.C M.TW W
W .100 O M.T
W O W O W .C
1 1 1 1
Y .TW
W O W C O W W .C OM
W W .100
Y .TW
W O W C O W W .C OM
W W .100
Y .TW
W O W C O W W .C OM
W W .100
Y
W O W C O W W
W W
W O W C O
W
W O W C O
W O W
WW .100Y.C M.TW WW
W O
WW .100Y.C M.TW
W O
WW .100Y.C 59
W W
7799D–AVR–11/10 W
.C OM
00Y .TW
W W.1 Y.COM W
W 00 .T
W W.1 Y.COM W
W W 00 .T
O M.T W W.1 Y.COM W
Table 10-5. Watchdog Timer Prescale Y .C Select, W DIV = 2 (CLKwdt
W =0CLK128
0 / 5)
.T
WW .100Y .C W W 00 .T Watchdog
W O M.T of WDT Oscillator
Number W W.1 YEarly .C OM warning Typical Reset/Interrupt Typical
WW .100Y Cycles .C W
M .TW M .TW before 1st
W
time-out W . 100 O M .T at
Time-out Time-out at
W O
O
0Y.C MWDP2 .TW WW WDP0 00Y
.C TW warning) WW .100Y.C VCCM=.T5.0V W
.10WDP3 WDP1
W . 1 O M .(Early W .C O
VCC = 5.0V
W O .C W Y W
WW .1000Y.C M.0TW 0 WW 0 100Y 2K W cyclesW
.T(2048) 00 80 ms.T 160 ms
W O W .
.C O M W W.1 Y.COM W
W Y.C W W W 0 Y T W W 0 0 .T
W 000
W.1 Y.COM W
0.T 0 1 .10 M.(4096) cycles
4K .1
WW 00Y.CO .TW
160M ms 320 ms
W W WW 00Y.CO .TW W
W 000 0 .T 1 0 .1 8KM(8192) cycles .1 320 ms M 640 ms
W 0 00 0 .T 1 W 1 .1 16K M (16384) cycles .1 0.625 sM 1.25 s
W 0 00 1 .T 0 W 0 W.1 32KO M
(32768) cycles .1 1.25 s M 2.5 s
W W.1 Y.COM W W Y .C W W WW 00Y.CO .TW
W 0 .100 1 M.T 0 W 1 0 0 .T . 1 M
1 W. 64K (65536) OM cycles W 2.5 s O 5s
W
WW0 .100Y.1C M.TW
O
1 0 W 128K (131072) O cycles W 5s O 10 s
W
WW .100Y.C M.TW
O
W 256K (262144) O cycles W 10 s O
WW .100Y.C M.TW
0 W 1 O 1 1 20 s
W512K (524288) O cycles W O
1 W 0
WW .100Y.C M.TW
O 0 0
WW .100Y.C M.TW WW 20.10s 0Y.C M.TW 40 s
W O W C O
1 WW 0 .CO 0 .TW 1 WW .100Y.C M.TW
1024K (1048576) cycles WW 40.s100Y. M.T
W 80 s
W . 1 00Y M W O W CO
1 W0
WW .100Y.C M.TW
O1 0
W
W O W C O
1 W0
WW .100Y.C M.TW
O
1 1 WW .100Y.C M.TW WW .100Y. M.T
W
W O W CO
1 W
WW 1 .100Y.C0 M.TW0
O
W
W O Reserved W CO
1 W
WW1 .100Y0.C M.T1W
O
W
W O W CO
1
W
W1W .1001Y.C M.T
O
0W WW .100Y.C M.TW WW .100Y. M.T
W
W O W C O
1W
W .CO 1.TW WW .100Y.C M.TW WW .100Y. M.T
W
1 W . 1 010Y M W O W .C O
W O WW .100Y
W
W O W .C O
W
WW .1Timer .CO .TW WW .100Y.C M.TW WW .100Y M.T
W
Table 10-6. Watchdog 00Y Prescale
M Select, DIV = 3 (CLKwdt
W = O
CLK128 / 7) W .C O
W O WW .100Y
W
O W O W .C O
Watchdog
W
WW .100Y.C M.TNumber W WW Oscillator Y.C .TW WW 00Y W
M.T Typical
of WDT W . 100 O M
Early warning Typical W.1Reset/Interrupt
C O
W O W time-out Y.C W Y . W
WW .100Y.C M.T W beforeW1st
Cycles
. 100 M
W
.TTime-out at W
W.100 Time-out O M.Tat
W O W O V W= 5.0V WW .C
WW .100Y.C M.TCC
WDP3 WDP2 WDP1 WDP0 (Early warning) V
Y CC = 5.0V.TW
WW .100Y.C M.TW .100 M
0 W O W O W
WW .100Y224 .COms .TW
0 0 0
WW .100Y.C M.TW WW .100Y.C M.112
2K (2048) cycles
TWms
W O W OM
0 W O
WW .100Y.C M224 WW .100448 Y.Cms .TW
WW .100Y.C M.TW
0 0 1 4K (4096) cycles ms
.TW OM
1 WW 0 Y.CO WW 00Y.CO 448 W W WW 0896 0 Y.C W
0 0
W .10 0 M.
8KW(8192) cycles
T W
W .1 O M .T ms
W . 1 ms
O M.T
W O W .C
0 0 1 WW 1 0Y.C 16K W WW .100Y.C 0.875
(16384) cycles
M.T
W
s W 00Y s
.11.75 M.T
W
W .10 O M.T W O W W .C O
0 1 0 WW 0 00Y.C 32K.T W
(32768) cyclesWW .100Y.C 1.75 M.sT
W W 00Y
.13.5 s .TW
0 1 0 WW 1 .100Y.C 64K W cyclesWW .100Y. 3.5M
(65536) s .TW W .710s0
Y .TW
WW0 .100Y.C W cycles WW .100Y. 7 s M.TW W 14.1s00
Y .TW
0 1 1
W O M.T
128K (131072)
W C O W W .C OM
WW Y.C W WW .100Y.14 s M.TW W 28 .s100Y
0 1 1 1
W .100 256KO(262144)
M.T cycles W W . C O WW
W W 0 Y .C T W W 0 0 Y .T W W
1 0 0 0 M.
.10 512K (524288) cycles .1 28 s M
WW 00Y.CO .TW
56 s
W WW 00Y.CO .TW W
1 0 0 1
W.11024K (1048576)
OM cycles W.1 56 s OM 112 s
W O W
WW .100Y.C M.TW WW
W O
WW .100Y.C M.TW
W O
WW .100Y.C 60
W W
7799D–AVR–11/10 W
.C OM
00Y .TW
W W.1 Y.COM W
W 00 .T
Table 10-6. Watchdog Timer Prescale Select, DIV = 3 (CLKwdt W W.1 = CLK128 .C OM / 7) (Continued)
M .TW W . 100
Y
M .TW
O W O
0Y.CEarlyMwarning
W Watchdog
W W.1 Y.COM Number
W 100
.T .1 M
WDP3 WDP2
.T W W . 1 00 M .T . 1 0 M
M 1 WW 0 Y.C O W O
1.CO 0
.100Y M
W
W . 1 O M W O
W 1 O 0
WW .100Y.C M.TW
1
O W O
WW .100Y.C M.TW
0 0 T W
1 0 .
W. OM W O
Reserved
W O
W O W O
W O
W. 1 OM W O
W O
W O W O
W
WW .100Y.C M.TW
O
W O W O
W.1
Watchdog Select,
Early warning. 1 Typical M Reset/Interrupt Typical
W W .C O W W before
W
WTime-out 0 Y
Y W W 0 M. T 0
WDP3 WWDP2
W Y .C OWDP1
W
WDP0
W WW (Early 0 Y W WVCC
00 .T
0
W
W .0100 O 0 M.T 0 W .10(2048) cycles
2K .C OM W W.1 Y.COM W 144 ms
72ms
C W .TW
WW .100Y. M.T
W W .100
Y W .100 OM
.T
0 W 0 C O
0 1 W W
4K (4096) .C OM
cycles W
144
W ms Y .C W 288 ms
WW .100Y. M.TW W . 100
Y
M .TW W
W .100 O M.T
W 1O W .C O Wms 00Y. C W 576 ms
0
WW .100Y.C M.TW
0 0 WW 8K (8192)
. 100
Y cycles
M .TW W288
.1 M.T
W O W C O
W O W (16384) .C Ws Y. W
0
WW0 .100Y1.C M.T1W W16K
.100
Ycycles
M .TW W576
W .100 O M.T 1.15 s
O W O Y.C
0 W
W1W .1000Y.C M.T 0W WW(32768)
32K Y.C W WW .100 M.T 2.3 s
W
W . 100cycles OM.T 1.1 s
W C O
W .CO 1.TW WW .C .TW
W Y. W
0 W1W
. 1 000Y M
64K (65536)1cycles
W . 00Y
O M 2.3W s
W .100 O M.T4.6 s
W O W .C W Y.C TWs
0 1WW 100Y.C 0 .TW 128KW (131072) . 00Y
1cycles M .TW 4.6 sW .100 M.9.2
. 1 M W O W .C O
1 WW
W
1100Y.
CO 1 TW 256K (262144) WW .cycles Y.C W
.TW 9.2 s W W.100Y OM18.4s .TW
0
. M . W 100 O M C
WW0 00Y.CO0 .TW 512K (524288) Y.C W . W
1 0 W 1 M
WW cycles .100 M .TW 18.4 s W W.100Y O36.8 M.Ts
W . O W O W .C
WW 0 .100Y.C1 M.TW1024K (1048576) WW cycles Y.C .TW 36.8 s W W.100Y O73 Ms.T
W
1 0 W . 100 O M C
W O WW .100Y .
WW1 .100Y.C .TW WW .100Y.C M.TW M.T
W
1 0 0
O M W O W .C O
WW
W
1 0 1 W.100 1 OM.T W O W .C O
W
Y
M.T
W
1 1 0 W 1 O W O W W .C O
Y
M.T
W
W O W O W W .C O
WW .100Y.C M.TW
1 1 1 0 Y W
WW .100Y.C M.TW W
W .100 O M.T
W O W O W .C
1 1 1 1
Y .TW
W O W C O W W .C OM
W W .100
Y .TW
W O W C O W W .C OM
W W .100
Y .TW
W O W C O W W .C OM
W W .100
Y
W O W C O W W
W W
W O W C O
W
W O W C O
W O W
WW .100Y.C M.TW WW
W O
WW .100Y.C M.TW
W O
WW .100Y.C 61
W W
7799D–AVR–11/10 W
.C OM
00Y .TW
W W.1 Y.COM W
W 00 .T
W W.1 Y.COM W
W W 00 .T
O M.T W W.1 Y.COM W
Table 10-8. Watchdog Timer Prescale Y .C Select, W DIV = 5 (CLKwdt
W =0CLK128
0 / 11)
.T
WW .100Y .C W W 00 .T Watchdog
W O M.T of WDT Oscillator
Number W W.1 YEarly .C OM warning Typical Reset/Interrupt Typical
WW .100Y Cycles .C W
M .TW M .TW before 1st
W
time-out W . 100 O M .T at
Time-out Time-out at
W O
O
0Y.C MWDP2 .TW WW WDP0 00Y
.C TW warning) WW .100Y.C VCCM=.T5.0V W
.10WDP3 WDP1
W . 1 O M .(Early W .C O
VCC = 5.0V
W O .C W Y W
WW .1000Y.C M.0TW 0 WW 0 100Y 2K W cyclesW
.T(2048) 00 88 ms .T 176 ms
W O W .
W Y.C W W W 0 Y T W W 0 0 .T
W 000
W.1 Y.COM W
0.T 0 1 .10 M.(4096) cycles
4K .1
WW 00Y.CO .TW
176M ms 352 ms
W W WW 00Y.CO .TW W
W 000 0 .T 1 0 .1 8KM(8192) cycles .1 352 ms M 704 ms
W 0 00 0 .T 1 W 1 .1 16K M (16384) cycles .1 704 msM 1.4 s
W 0 00 1 .T 0 W 0 W.1 32KO M
(32768) cycles .1 1.4 s M 2.8 s
W W.1 Y.COM W W Y .C W W WW 00Y.CO .TW
W 0 .100 1 M.T 0 W 1 0 0 .T . 1 M
1 W. 64K (65536) OM cycles W 2.8 s O 5.6 s
W
WW0 .100Y.1C M.TW
O
1 0 W 128K (131072) O cycles W 5.6 s O 11.2 s
W
WW .100Y.C M.TW
O
W 256K (262144) O cycles W 11.2 s O
WW .100Y.C M.TW
0 W 1 O 1 1 22.5 s
1 W 0 O 0 0 W512K (524288) O cycles W s Y.CO
WW .100Y.C M.TW WW .100Y.C M.TW WW 22.5 .100 M.T
W 45 s
W O W C O
1 WW 0 .CO 0 .TW 1 WW .100Y.C M.TW
1024K (1048576) cycles WW 45s.100Y. M.T
W 90 s
W . 1 00Y M W O W CO
1 W0
WW .100Y.C M.TW
O1 0
W
W O W C O
1 W0
WW .100Y.C M.TW
O
1 1 WW .100Y.C M.TW WW .100Y. M.T
W
W O W CO
1 W
WW 1 .100Y.C0 M.TW0
O
W
W O Reserved W CO
1 W
WW1 .100Y0.C M.T1W
O
W
W O W CO
1
W
W1W .1001Y.C M.T
O
0W WW .100Y.C M.TW WW .100Y. M.T
W
W O W C O
1W
W .CO 1.TW WW .100Y.C M.TW WW .100Y. M.T
W
1 W . 1 010Y M W O W .C O
W O WW .100Y
W
W O W .C O
W
WW .1Timer .CO .TW WW .100Y.C M.TW WW .100Y M.T
W
Table 10-9. Watchdog 00Y Prescale
M Select, DIV = 6(CLKwdt
W = O
CLK128 / 13) W .C O
W O WW .100Y
W
O W O W .C O
Watchdog
W
WW .100Y.C M.TNumber W WW Oscillator Y.C .TW WW 00Y W
M.T Typical
of WDT W . 100 O M
Early warning Typical W.1Reset/Interrupt
C O
W O W time-out Y.C W Y . W
WW .100Y.C M.T W beforeW1st
Cycles
. 100 M
W
.TTime-out at W
W.100 Time-out O M.Tat
W O W O V W= 5.0V WW .C
WW .100Y.C M.TCC
WDP3 WDP2 WDP1 WDP0 (Early warning) V
Y CC = 5.0V.TW
WW .100Y.C M.TW .100 M
0 W O W O W
WW .100Y208 .COms .TW
0 0 0
WW .100Y.C M.TW WW .100Y.C M.104
2K (2048) cycles
TWms
W O W OM
0 W O
WW .100Y.C M208 WW .100416 Y.Cms .TW
WW .100Y.C M.TW
0 0 1 4K (4096) cycles ms
.TW OM
1 WW 0 Y.CO WW 00Y.CO 416 W W WW 0832 0 Y.C W
0 0
W .10 0 M.
8KW(8192) cycles
T W
W .1 O M .T ms
W . 1 ms
O M.T
W O W .C
0 0 1 WW 1 0Y.C 16K W WW .100Y.C 832
(16384) cycles
M.T
msW W 00Y s
.11.64 M.T
W
0 1 0 WW 0 00Y.C 32K.T W
(32768) cyclesWW .100Y.C 1.6 Ms.T
W W 00Y
.13.3 s .TW
0 1 0 WW 1 .100Y.C 64K W cyclesWW .100Y. 3.3M
(65536) s .TW W .100s
6.6
Y .TW
WW0 .100Y.C W cycles WW .100Y. 6.6 sM.TW W 13.3 .10s0
Y .TW
0 1 1
W O M.T
128K (131072)
W .C O W W .C OM
WW Y.C W WW .100Y13.3 s M.T
W W 26.6.1s00Y
0 1 1 1
W .100 256KO(262144)
M.T cycles W W . C O WW
W W 0 Y .C T W W 0 0 Y .T W W
1 0 0 0 M.
.10 512K (524288) cycles .1 26.6 s M
WW 00Y.CO .TW
53.2 s
W WW 00Y.CO .TW W
1 0 0 1
W.11024K (1048576)
OM cycles W.1 53.2 s OM 106.4 s
W O W
WW .100Y.C M.TW WW
W O
WW .100Y.C M.TW
W O
WW .100Y.C 62
W W
7799D–AVR–11/10 W
.C OM
00Y .TW
W W.1 Y.COM W
W 00 .T
Table 10-9. Watchdog Timer Prescale Select, DIV = 6(CLKwdt W W.1 = CLK128 .C OM / 13) (Continued)
M .TW W . 100
Y
M .TW
O W O
0Y.CEarlyMwarning
W Watchdog
W W.1 Y.COM Number
W 100
.T .1 M
WDP3 WDP2
.T W W . 1 00 M .T . 1 0 M
M 1 WW 0 Y.C O W O
1.CO 0
.100Y M
W
W . 1 O M W O
W 1 O 0
WW .100Y.C M.TW
1
O W O
WW .100Y.C M.TW
0 0 T W
1 0 .
W. OM W O
Reserved
W O
W O W O
W O
W. 1 OM W O
W O
W O W O
W
WW .100Y.C M.TW
O
W O W O
W.1
Watchdog Select,
Early warning . 1 Typical M Reset/Interrupt Typical
W W .C O W W before
W
WTime-out 0 Y
Y W W 0 M. T 0
WDP3 WWDP2
W Y .C OWDP1
W
WDP0
W WW (Early 0 Y W WVCC
100 .T
W
W .0100 O M.T W .10(2048) cycles OM W W.ms .C OM
0 C 0 0 W 2K .C 120 Y W 240 ms
WW .100Y. M.TW W .100
Y
M .TW W
W .100 O M.T
W0 O W C O W ms 00Y. C W 480 ms
0
WW .100Y.C M.TW
0 1
WW4K (4096) Y.cycles .TW W240 M.T
W . 100 O M W .1
C O
W 1O .C Wms 00Y. W 960 ms
0
WW .100Y.C M.TW
0 0 WW 8K (8192)
. 100
Y cycles
M .TW W480
.1 M.T
W O W C O
0 W
WW0 .100Y1.C M.T1W
O 16KW (16384) Y .C
cycles .TW WW s .100Y.
0.960
M.T 1.9 s
W
W
W .100 O M W C O
W O
WW(32768) Y.C WW Y. W
0 W1W .1000Y.C M.T 0W 32K
. 100cycles OM.T
W 1.92 s
W .100 O M.T 3.8 s
W .CO 1.TW W .C W Y. C W
0 W1W 000Y 64K WW (65536)1cycles
. 00Y M .TW 3.8W s .100 M.T7.6 s
100Y.C W .C .TW Y TWs
0 1WW
. 1 M
0 .TW 128KW (131072)
W . 00Y
1cycles O M 7.6 sW
W .100 O M.15.3
W CO 1 TW 256K (262144) Y.C W .C
0 1 WW 1100Y. . WW .cycles 100 M .TW 15.3 sW W.100Y OM .TW
30.7 s
W . O M W W .C O W Y .C W
W Y.C W W 0 Y .T W W 10 0 .T
1 0 W 0.100 0 M.T 512K (524288) cycles
W .10 O M 30.7 s W .
C O M s
61.4
W O Y.C W . W
1 0 WW 0 .100Y.C1 M.TW1024K (1048576) WW cycles . 100 M .TW 61.4 s W W.100Y O 122 M.sT
O W O .C
W
WW1 .100Y.C .TW WW .100Y.C M.TW WW .100Y M.T
W
1 0 0
O M W O W .C O
WW
W
1 0 1 W.100 1 OM.T W O W .C O
W
Y
M.T
W
1 1 0 W 1 O W O W W . C O
Y
M.T
W
W O W O W W .C O
WW .100Y.C M.TW
1 1 1 0 Y W
WW .100Y.C M.TW W
W .100 O M.T
W O W O W .C
1 1 1 1
Y .TW
W O W C O W W .C OM
W W .100
Y .TW
W O W C O W W .C OM
W W .100
Y .TW
W O W C O W W .C OM
W W .100
Y
W O W C O W W
W W
W O W C O
W
W O W C O
W O W
WW .100Y.C M.TW WW
W O
WW .100Y.C M.TW
W O
WW .100Y.C 63
W W
7799D–AVR–11/10 W
.C OM
00Y .TW
W W.1 Y.COM W
W 00 .T
11. Interrupts W W.1 Y.COM W
.TW W 00
W.1 Y.COM W
.T
. C OM W
Y W W 00 .T
WW 0Y .C TW W 00 .T
s .1s0e c t i o nOdM
T h iW e .s c r i b e s t h e s pW e cW i f.1
i c s o f.Ct h OeMi n t e r r u p t h a n d l i n g a s p e r f o r m e d i n
W .C 00Y TW
M .TW . 1 00Y
WATmega8U2/16U2/32U2. M .TW For a W general W . 1explanation O M .of the AVR interrupt handling, refer to
CO W W .C O W 13. 00Y.C W
Y. W W“Reset and 0 0 Y
Interrupt .T W
Handling” on W
page 1 .T
.100 M .T W . 1 O M W . O M
W
WW .100Y.C M.TW
O
O W O
O
W11.2 Interrupt VectorsWin WW Y.C
ATmega8U2/16U2/32U2 WW .100Y.C M.TW
WW .100Y.C M.TW 1 0 0 .T W
W. OM W O
W
WW .100Y.C M.TW
O
W O Table 11-1. W Reset and O Interrupt VectorsWW .CO .TW
W W .C O
W
Vector WWProgram.CO
Y W W WW 00Y.CO .TW
W 00 Y .T No. W .10
Address 0 (2)
M.
Source T .1 Definition
Interrupt M
W 00 .T W .1 M
W.1 Y.COM W W.1 (1) Y.COM W
W$0000
External
WW Pin, 0 Y .CO .TReset,
Power-on Brown-out Reset,
W and debugWIRE AVR
W W 0 .T 1 W 0 0 RESET .T W Watchdog . 1 0 Reset, USB
M Reset
0 W. 1 OM
W.1 OM WW 00Y.CO .TW
WW .100Y.C M.TW WW .100Y.C M.TW Reset
W .1
WWInterrupt OM
W W Y .C O
W 2 W WW 00YINT0
$0002 .CO .TW External
W 0 0 Y.C Request.T0W
W 00 .T .1 M .1 M
W W.1 Y.COM W3 WW 00INT1
$0004 Y .CO .TW W
ExternalWW Interrupt 0 .CO 1.TW
YRequest
W 0
W 00
W.1 Y.COM W
.T .1
.CO .TW
M W.1 Y.COM W
W 4 $0006
W WW 0INT2 0 Y W
External WInterrupt 00Request 2 .T
W
W .100 O M.T W .1
.C OM W W.1 Y.COM W
C W .TW External
WW .100Y. M.T
5W W
$0008
.100
INT3 Y W Interrupt 0
0Request
W.1 Y.COM W
3 .T
W CO W W . C OM W
WW .100Y. M.T
6W $000A W .100
INT4 Y .TW ExternalWInterrupt 00
Request
W.1 Y.COM W
4 .T
W C O W W .C OM W
WW .100Y. M7.T
W $000C W .100
INT5 Y .TW External W 00
W 1 Y.C5OM W
Interrupt .Request .T
W C O W W .C OM W
WW .100Y. 8 .TW $000EW INT6 .100
Y .TWExternal Interrupt W .100 6 OM.T
Request
W O M W .C OM W W .C W
WW .100Y. C
9M.TW $0010 W INT7.100
W Y
M .TW External
W Request
Interrupt . 1 00Y7 M.T
W O W C O
W O
WW .100Y.C 10 M.TW $0012 W PCINT0
W Y.C W WW .100Y. .TW
W .100 O M .TPin Change InterruptWRequest 0COM
W O W .C WW .100Y . W
WW .100Y.C11 M.TW$0014 WPCINT1.100Y M .TWChange Interrupt
Pin W
Request 1 O M.T
W O .C
W
WW .100Y12 .CO .TW WW .100Y.C M.TW WW .100Y M.T
W
O M $0016 USB General
W O USB General Interrupt Wrequest .C O
W
W
13 O $0018 USB W
Endpoint O USB Endpoint Interrupt W
request .C O
W
W
O W O W .C O
W 14
WW .100Y.C M.TW
$001A WDT
WW .100Y.C M.TW
Watchdog Time-out
WW .100Y
Interrupt
M.T
W
O W O W .C O
W 15
WW .100Y.C M.TW
$001C TIMER1W CAPT Y.CTimer/Counter1
.TW
Capture WW Event
.100
Y
M.T
W
W
W .100 O M W C O
W 16 O .C WW Match A 0Y . W
WW .100Y.C M.TW
$001E
WW .100YTimer/Counter1
TIMER1 COMPA
M .TW
Compare
.10 M.T
W17 O W O W W .C O
W .C .TW CompareWMatchWB.100Y OM.TW
WW .100Y.C M.TW
$0020 TIMER1W COMPB Timer/Counter1
Y
W . 100 O M
W O W C 00Y.C
WW18 .100Y.C $0022
.T WTIMER1 COMPC WW .10Timer/Counter1 0Y.C M.TWCompare W Match
.1 M.T
W
W O M W O W W .C O
.C WW .1Timer/Counter1 .C W Y W
WW 19
.100
Y$0024
M.T
W TIMER1 OVF
W
00Y
O M.T
Overflow W
W .100 O M.T
W O Y.C W .C
W20 W Y.C
$0026 W
TIMER0 WW .Timer/Counter0
COMPA 100
W W
M.TCompare Match AWW.10
0Y .TW
W .100 O M.T W C O .C OM
21W Y.C W COMPB WW Timer/Counter0 Y. TW WB .100
Y .TW
W
W .100
$0028
O M.T
TIMER0
W .100 O M.Compare match
W W .C OM
.C W Y. C Y .TW
WW .1$002A
22 00Y .TW OVF W Timer/Counter0
MTIMER0 .100 .TW
MOverflow
W
W .100 OM
W O W C O W .C
W $002C Y.C SPI, W WWSPI .Serial Y. W W .100
Y
23W .100 M.TSTC W 100 Transfer O M.T Complete W
W O Y. C W
W Y.C USART1 W WW .100Rx Complete M.T
W W
24 W
W .100
$002E
O M.T RX USART1
W C O
W Y.C USART1 W W
WUSART1 .10Data0Y. Register M.TEmpty
W
25 W $0030
W .100 O M.T UDRE W C O
WW$0032 Y.C W WW .100Y.
26 W .100 USART1TX O M.T USART1 W Tx Complete
WW .100Y.C M.TW WW
W O
WW .100Y.C M.TW
W O
WW .100Y.C 64
W W
7799D–AVR–11/10 W
.C OM
00Y .TW
W W.1 Y.COM W
Table 11-1. Reset and Interrupt
W
W .100 (Continued)
Vectors OM
.T
W .C
M .TW W . 100
Y
M .TW
Vector .CO Program W C O
00Y Address .TW (2) WW .100Y.Interrupt M
W
.TDefinition
W No.
. 1 O M Source W O
WW 27.100Y.C $0034 .TW ANALOG WW .100Y.C M.TW
W O M COMP W Analog O Comparator
.T W WW 28 .100Y.C$0036 .T W WW .100Y.C M.TW
OM W OM EE READY W EEPROM O Ready
0 O
W.1 OM 29
WW 00Y.CO .TW
$0038 SPM READY WW Store.C
0Y
Program
TW
Memory Ready
WW .100Y.C M.TW W
Notes: W 1
1.. When the M
BOOTRST
W
Fuse is programmed, . 10 the M .
device will jump to the Boot Loader address at
W O .CO .TW Programming” W
WW on .page .CO
0Y246. .TW
WW .100Y.C M.TW WW .1reset, 00Y see “Memory M 1 0 M
W O W O
W O
WW2. When .C IVSEL.Tbit Win MCUCRWisW Y.CVectors.Twill Wbe moved to the start of the Boot
WW .100Y.C M.TW .
Ythe
100 Section. M W .100 Vector
set, Interrupt
O M
W O W Flash .C O The address of each W Interrupt Y.C will then be the address in this table
WW .100Y.C M.TW WW added 0 0 Y .T W WBoot . 1 0 0Section. M . TW contrary to other 8K/16K
W. 1 to the start
M address of the Flash
W O Moreover,
W O
WW devices, .CO WWremains Y.C W for both 8KB and 16KB
WW .100Y.C M.TW . 1 0 0 Ythe interrupt
M .T W
vectors spacing
W . 1 0 0identical
O M(2.T words)
W O
W
WW .100Y.C M.TW
O
WW .100Y.C M.TW
versions.
WW .100Y.C M.TW
W O WplacementOfor the various combinations of
WW .100Y.C M.TW
W O Table 11-2 shows reset and Interrupt Vectors
WW .100Y.C M.TWBOOTRST WW 0 0 Y.C .T W
andW .
IVSEL1 OM If the program W
settings. never
W enables Oan interrupt source, the Interrupt
W O W Y.C regular Y.C TW locations. This is also
WW .100Y.C M.TW Vectors are Wnot used, . 1 0 0and M .T Wprogram W can.1be
code W
0 0placed
O Mat .these
O W O C
Y. the Interrupt
W
WW .100Y.C M.Tthe W case if the WWReset 0Y.C is M W Application WWsection .100while O M.T
W
W . 10Vector O
in.Tthe
W C
Vectors are in the
W C O Boot section or W
vice versa. . C W Y . W
WW .100Y. M.T
W W .100
Y .TW W 00
W.1 Y.COM W
.T
W CO W W . C OM W
WW .100Y. .TW 11-2. W
MTable Reset and Y
.100Interrupt .TW Placement
Vectors W (1) .100
OM
.T
W O W C OM W W .C
WW .100Y. C W
BOOTRST W IVSEL
.T
W Y .
100 ResetOAddress M .TW W Y
.100 Vectors .TW Address
MStart
M W . Interrupt
W C O
W
WW .100Y.C M.TW1
O
WW0 .1000x0000 Y.C .TW WW .100Y. M.T
W
W O M W
0x0002 C O
W
WW .100Y.C M.TW
O
WW .100Y.C M.TW WW .100Y. M+.T
W
1 1 W 0x0000 O Boot WReset Address
C O 0x0002
W
WW .100Y.C M.T0W
O
W
0 W Boot Reset O Address 0x0002 W C O
W
WW .100Y.C M.TW
O
W
W O W C O
W
WW .100Y.C M.TW
O 0 1 Boot
WW .100Y.C M.TW
Reset Address
WW .100Y.
Boot Reset Address + 0x0002
M.T
W
O W O W .C O
W
WW .100Note:Y.C 1. .TThe W Boot Reset WW Address is0Y .C
0 shown in .TW 23-8 on page
Table WW239..1For 00Y the BOOTRST
M.T
W Fuse “1”
M means unprogrammed W .1while “0” O M
means programmed. W C O
W O WW .100Y .
W
O W O W .C O
W
W
O W O W .C O
11.2.1 Moving W WW 00Between
Interrupts Y.C .TW
Application WWBoot.1Space
and 00Y
.C .TW WW .100Y M.T
W
. 1
W General O M W O M W
W Interrupt .C O
WW The .C Interrupt .TW ControlWRegister
W Y.C the.Tplacement
controls W ofWthe Y
.100 Vector .TW
Mtable.
. 1 00Y M W . 100 O M W C O
W O WW .100Y .
W
11.3 Register Description O W O W .C O
W
W
W O W O W W .C O
11.3.1 MCUCR – MCU WW Control Y.C
00Register .TW WW .100Y.C M.TW W .100
Y
M.T
W
. 1 O M W O W W .C O
WBitWW 00Y.C 7 .TW 6 W5W .1040Y.C M 3 .T
W 2 W1 .1000
Y
M.T
W
W .1 O M W O
C – TW – W W .C O
W(0x55) 00Y.CJTD .TW– – W PUD0Y. W 00Y MCUCR W
W0x35
.1 M
W
W 10
.R/W O M.
IVSEL
W .1IVCE O M.T
W O W .C
0Y.C0 M.TW WW .100Y.C M.TW Y .TW
Read/Write R/W R R R R R/W R/W
WW
Initial Value .10 W 0O
W
W .1000 OM
W O 0 0 0
C 0 0
W .C
W W .100
Y .TW
W O W C O W W .C OM
• Bit W1W– IVSEL: .C
YInterrupt W
Vector Select WW .100Y. M.T
W W .100
Y .TW
WhenW the
W IVSEL bit.Cis cleared
.TW(zero), the
W
WInterrupt Y.
Vectors are W placed at the W start .of 0Y Flash
10the
00Y
W.1 thisYbit O M W .100 O M.T W W
memory. W When .C is set (one), the Interrupt
WW .100Y. Vectors C
are moved to the beginning of the Boot
W 1 0 0 M .T W M .TW W
Loader section .of the Flash. The actual address WWof the startOof the Boot Flash Section is deter-
WW 00Y.CO .TW
Wthe Wsection 1 0Y.C M
0“Memory .TW
mined by BOOTSZ
W . 1 Fuses.
O M Refer to the W . O Programming” on page 246 for
W unintentional Y .C W W W Vector 0 Y .C
details. ToWavoid 0 .T
changes of Interrupt 0 tables, a special write procedure must
W.1 the
0
.C OM bit: W W.1
be followedW toWchange IVSEL .TW
00Y W
W W.1 Y.COM W
W 00 .T
W W.1 Y.COM
W 00
W W.1 65
7799D–AVR–11/10 W
.C OM
00Y .TW
W W.1 Y.COM W
a. Write the Interrupt Vector
W .100 Enable
WChange
.T
OM (IVCE) bit to one.
W .C
M TW cycles, write
.four W . 100
Y
M .TW
b. Within O the
W desired O
value to IVSEL while writing a zero to IVCE.
0 0 Y.C .T W WW .100Y.C M.TW
W.1 Ywill
Interrupts
.CO
M
automatically be disabled while this sequence is executed. Interrupts are disabled
WW 00Y.CO .TW
WW 00 IVCEMis.Tset,
in the.1cycle W and theyWremain .1disabledOuntil M after the instruction following the write to
W W W
IVSEL. If Y .
IVSEL C O
is not Wwritten, W WW remain
interrupts 0 0 Y .Cdisabled .TW for four cycles. The I-bit in the Status
M .T W . 1 00 M .T W . 1 O M
O W C O W .C
00Y
.C .TW
Register
WW .100Y is .
unaffected
M
by
.TW the automaticW disabling.
. 100
Y
M .TW
.1 M W O W O
W O
WW If .Interrupt .C W Boot Loader Y.C section W Boot Lock bit BLB02 is pro-
WW .100Y.C M.TW Note:
1 00Y Vectors M .TW are placed in Wthe
W . 100 O M .Tand
O W O Y.Cfrom the.TApplication
W
WW .100Y.C M.TW
grammed,.Cinterrupts W
WW are.1placed 00Y in theMApplication .T
are disabled while
WW executing . 100 Lock bit M
W section. If Interrupt Vectors
W O section and W Boot O BLB12 is programed, interrupts are dis-
W W .C O Wabled Y .Cexecuting W W W 0 Y .C .T W
W 00 Y .TW W 0 0
while T from the
M. page 246 for details Boot Loader .1 0
section. Refer
M to the section “Memory
W.1 Y.COM W W W.1 Y.COon
Programming” W WW on Boot 0 Y .CObits..TW
Lock
W W 0 T W 0
W 00
W.1 Y.COM W
.T .10 M. .1
WW 00Y.CO .TW
M
W W WW 00Y.CO .TW W
W 00 .T • Bit 0 – IVCE: Interrupt Vector Change Enable
W.1 Y.COM W .1 M
The IVCE W bit must 0
be written M. T
to logic one to enable change of the IVSEL bit. IVCE is cleared by
W
W .100 O M.T W .10
.C O W W.1 Y.COM W
C W TW or when
WW .100Y. WhardwareW
M.T interrupts, asW
four cycles Yafter it is .written
.100 in the
W IVSEL.10is0written.M Setting
.T the IVCE bit will disable
W C O W
explained .C OMIVSEL descriptionWabove. W See
Y .C O Example below.
Code W
WW .100Y. M.T
W W .100
Y .TW W 00
W.1 Y.COM W
.T
W C O W W .C OM W
WW .100Y. M.T
WAssembly W Code Example
.100
Y .TW W 00
W.1 Y.COM W
.T
W C O W W .C OM W
WW .100Y. M.T
W Move_interrupts: W .100
Y .TW W 00
W.1 Y.COM W
.T
W C O W W .C OM W
WW .100Y. M.T
W ; Enable W change .100
Yof Interrupt .TW Vectors W 00
W.1 Y.COM W
.T
W C O W W .C OM W
WW .100Y. W ldi
M.T out MCUCR,Wr16
r16, W (1<<IVCE)
.100
Y .TW W 00
W.1 Y.COM W
.T
W C O W .C OM W
WW .100Y. W
M.T ; Move interrupts
W Y
.100 to Boot .TW W 100 OM
.T
W CO W W .C OM Flash section WW. Y .C W
WW .100Y. M .TW W . 100
Y
M .TW W
W .100 O M.T
ldi r16, (1<<IVSEL)W O C
W
WW .100Y.C M.Tout
O
W MCUCR,Wr16 W Y.C .TW WW .100Y. M.T
W
W .100 O M W C O
W
WW .100Y.C Mret
O
W
W O W C O
W
WW .100Y.CCCode
O
.T W WW .100Y.C M.TW WW .100Y. M.T
W
M Example W O W C O
W O WW .100Y .
WW .100Y.C void W
.TMove_interrupts(void) WW .100Y.C M.TW M.T
W
O M W O W .C O
W
WW .100Y.C{ M.TW WW .100Y.C M.TW WW .100Y M.T
W
O W O W .C O
W
WW .100Y.C/* M .TW changeWof Interrupt
W Y.C Vectors .TW */ WW .100Y M.T
W
Enable
W .100 O M W C O
W O WW .100Y .
WW .100Y.C MCUCR .= TW (1<<IVCE); WW .100Y.C M.TW M.T
W
W O M W O W W .C O
WW .100Y/* .C Move.Tinterrupts W WtoW Boot00Flash Y.C section .TW */ W W.100Y OM.TW
M W . 1 O M
W
WW .100Y.C M.TW
O
MCUCR = (1<<IVSEL);WW
00Y
W .1 O M W O
W }
WW .100Y.C M.TW
O
W O W O
W
WW .100Y.C M.TW
O
W O W O
W
WW .100Y.C M.TW
O
W O W O
W
WW .100Y.C M.TW
O
W O W O
W
WW .100Y.C M.TW
O
W O W O
W
WW .100Y.C M.TW
O
W O W O
W
WW .100Y.C M.TW
O
W O W O
W
WW .100Y.C M.TW
O
O W O W
W
W O W O
W O W O
W O W
WW .100Y.C M.TW WW
W O
WW .100Y.C M.TW
W O
WW .100Y.C 66
W W
7799D–AVR–11/10 W
.C OM
00Y .TW
W W.1 Y.COM W
W 00 .T
12. I/O-Ports W W.1 Y.COM W
.TW W 00
W.1 Y.COM W
.T
.C OM W
Y W W 00 .T
WW Y . C W W 00 .T
All AVRW .100ports have O M.T true Read-Modify-Write W W.1 functionality .C OM when used as general digital I/O ports.
W .C W Y .TW without unintentionally changing
M .TW WThis means
. 1 00Ythat the M .T
direction of one W port .pin
W 100 can be O Mchanged
W O Y.C
.CO .TW theWdirection .C other
00Yof anyM .TWpin with the WW 100CBI instructions. .TW The same applies when chang-
.100Y M
W . 1
W valueY(if O
SBI and
W . O M
W O
WW .C configured WW Y.C .TW
WW .100Y.C M.TW ing drive
. 1 00 M .TW as output) or enabling/disabling
W . 100 O M
of pull-up resistors (if configured as
W O input). W
Each output O buffer has symmetrical W drive .C
characteristics
WW .100Y.C M.TW WW .100Y .C
M .TW W .
Y
100 LEDOdisplays M .TW with both high sink and source
capability. W The pin driver
O is strong enough W
to drive directly. All port pins have indi-
W
WW .100Y.C M.TW
O
WWselectable 0 0 Y.C .T W WW .100Y.C M.TW
vidually W. 1 pull-up M resistors with a supply-voltage invariant resistance. All I/O pins have
W W .C O
Y W
protection diodes 0
.10 to both T
V.CC and Ground as indicated
W 00 .T
W.1 Y.COM W acteristics” M
.COfor a.Tcomplete W.1 Y.in CO
Figure
M 12-1. Refer to “Electrical Char-
WW Y W W Wparameters. 0 W
W W
. 1 00 M .T W on
W
page
. 10 0 264
O M
list of
W .1 0
O M.T
W O
WW .100Y.C M.TW Figure 12-1. WW .100Y.C M.TW WW .100Y.C M.TW
W I/O Pin O
Equivalent Schematic W O
W
WW .100Y.C M.TW
O
W O W O
W
WW .100Y.C M.TW
O
W O W O
W
WW .100Y.C M.TW
O
W O W O
W
WW .100Y.C M.TW
O
W O W O
W
WW .100Y.C M.TW
O
W O W O
W
WW .100Y.C M.TW
O
W O W O W
WW .100YR .CO .TW
WW .100Y.C M.TW WW .100Y.C M.TW pu M
W O W O
W
WW .100Y. CO
.T W W W 0 0 Y.C
.T W W W
. 1 0 0 C M.TW
Y .
. 1 M W OLogic
W OM Pxn W O
WW .100Y.C M.TW
W O W O
W
WW .100Y.C M.TW
O
WW .100YC.C M.TW WW .100Y.C M.TW
W O W pinO
WW .See
W .CO
WW .100Y.C M.TW WW .100Y.C M.TW 1 00YFigure M.TW
W O W O "GeneralW Digital
WW .Details .CO I/O" for W
WW .100Y.C M.TW WW .100Y.C M.TW 1 00Y .T
W O W C O W W .C OM
.C W . W Y W
WW .100Y M .TW W
W . 100
Y
O M .T W
W .100 O M.T
W O WW .100Y . C
W
O W O W .C O
W registers
WW All .C and .TW bit references WWin this Y.C are .written
section TW in general WW form. Y
.10A0 lowerOcase
W
M.T “x” repre-
. 1 00Y M W . 100 O M W C
Wsents the O Y.aClower .case WW the .
WW when Y.Cnumbering
00using
letter for the
TW or bitW
.register
Wport, and
. 10a0 program, M TW “n” represents 0bit
.1be 0Ynumber. However,
W
M.Texample,
. 1 O theM defines W in O the precise form W
must used. .C O For
W
WW PORTB3 .C .TW
W Y.C .TW as PORTxn. WW .100Y .TW
. 1 00Y for bitMno. 3 in Port B,Where W .100
documented O Mgenerally W The physical C O MI/O Regis-
W O
.Clocations W Y .C W W W 0 Y . T W
WWters and .1 0 0 Y
bit M .T W are listed W
in “Register . 1 0 0 Description M .T for I/O-Ports” on page
W . 1 0 82. O M .
O W O W .C
WW 00Y.C
WThree .TW locations WWare .allocated 100
Y.C .TW port, oneWeachWfor .10the 0Y M .TW
W .I/O
1 memory O M address W for
O M each
W Data
.C O Register
–W Y.C W WW .10and 0Y.C W
M.TInput Pins – PINx.
W Y
.100Port Input M.T
W
W PORTx,
W .100Data Direction O M.T Register – DDRx, W
the Port
O
.C the .Data W W The
.C O Pins
W
WW
I/O location00isY.read C only,
.TW while the Data WWRegister Yand W W 0Y read/write. M.T
W . 1 O M W .100 O M T Direction Register W W .10are
.C O
WW .100Y.C M.TW
However, writing a logic one to a bit inWthe W PINx0Register, Y.C will Wresult in a toggle
W in the
.100
Y
correspond- .TW
ing bitWinWthe Data O
Register. In addition, theW .1 0 Disable
Pull-up O M.T – PUD bit in MCUCR W W .C
disables OMthe
Y.C WW .100Y. C W Y .TW
W function
pull-up .100 for allOpins
W
M.Tin all ports when set.
W O M.T
W
W .100 OM
W C W . C
M.T as General Digital
W .100
Y .TW
Using the I/O
W port as O
General Digital I/O is W
described in
C O
“Ports W W I/O” on.C OM
page
WWport .1pins .C
00Yare multiplexed W WW .100Y. .TW W Y
.100 on the
68. Most W O M.T with alternate W functions C O Mfor the peripheralW W
features
W Y.C TW WW with 0Y. port M
.10the
W W
pin.Tis described in “Alternate Port
device.W How each
W .100alternate O M.function interferes W C O
WW Y.CRefer .to W WWmodule Y. .TW
Functions” on page
W .100
72.
O MT
the individual
W .100sections O Mfor a full description of the alter-
nate functions. W .C W Y .C
W 00Y .TW W
W.1
00
W W.1 Y.COM W W
W 00 .T W
W W.1 Y.COM W
W 00 .T
W W.1 Y.COM
W 00
W W.1 67
7799D–AVR–11/10 W
.C OM
00Y .TW
W W.1 Y.COM W
W 00 .T
Note that enabling the alternateW W.1 ofY.some
function C OM of the port pins does not affect the use of the
W
other pins inO TW as general
M.port
the 00
W digital.1I/O.
O M.T
W
00Y
W . 1 O M W O
12.2 Ports as General WW Digital 0 0 Y.CI/O .TW WW .100Y.C M.TW
. 1 OM W O
W WTheWWports00are Y.Cbi-directional
.T W I/O ports WWwith.1optional
0 0Y.C internal .TWpull-ups. Figure 12-2 shows a func-
M .T . 1 O M W O M
.CO .TW WWdescription
tional
00Y
.C of one .TW I/O-port pin, WW Y.C called
here generically
100 .TWPxn.
.100Y M
W
W . 1 O M W . O M
W O
WW 12-2. .C W Y.C .TW
WW .100Y.C M.TW Figure . 1 00YGeneral M TW I/O(1) W
.Digital W . 100 O M
W O
W
WW .100Y.C M.TW
O
W O W O
W
WW .100Y.C M.TW
O
W O W O
W
WW .100Y.C M.TW
O
WW .100Y.C M.TW WW .100Y.C M.TW PUD
W O W O
W
WW .100Y.C M.TW
O
W O W O Q D
W
WW .100Y.C M.TW
O
WW .100Y.C M.TW WW .100Y.C M.TW DDxn
W O W OQ CLR
W O
WW .100Y.C M.TW WW .100RESET Y.C W
WW .100Y.C M.TW M.TRDx
WDx
W O W C O
W
WW .100Y.C M.TW
O
W
W O W C O
W
WW .100Y.C M.TW
O
W
DATA BUS
W O W C O
W O
WW .100Y.C M.TW Pxn W
W Y.C .TW WW .100Y. M1 .T
W
W . 100 O M W Q
C OD
W
WW .100Y.C M.TW
O
WW .100Y.C M.TW WW .100Y. PORTxn 0
M.T
W
W O W Q CLR
C O
W O
WW .100Y.C M.TW WWRESET Y. W
WW .100Y.C M.TW W .100 O M.T
O W O .C WPx
W
WW .100Y.C M.TW WW .100Y.CSLEEPM.TW WW .1RRx 00Y
WRx W
M .T
W O W O
W
WW .100Y.C M.TW
O
W O W O SYNCHRONIZER
WW .100Y
W .CO .TW
WW .100Y.C M.TW WW .100Y.C M.TW RPx
M
W W .C O
W WW 00Y.CO .TW D Q D
W
Q
WW 00Y.CO .TW
W 00 Y .T W .1 M
PINxn
.1 M
L Q Q
W WW 00Y.CO .TW
W 00 .T W .1 M .1 M
W W.1 Y.COM W WW 00Y.CO .TW W WW clk0I/O0Y.CO .TW
W 00 .T W .1 M .1 M
W
W 00
W.1 Y.COM W PUD:
.T W.1 DISABLE M
.CO .TW WRx:
WDx:
W W.1DDRx
WRITE DDRx
Y.C
OM
W
WPULLUP
Y RDx:
W READ
0
W W
.1 00 M .T SLEEP:
clk :
W SLEEP
.
I/O CLOCK
W 10 0
CONTROL
O M RRx:
WRITE
READ W . 1
PORTx
0
PORTx
REGISTERO M.T
W O W PORTx .C
WW .100Y.C M.TW WPx: WWRITE PINx
I/O
Y W
WW .100Y.C M.TW
RPx: READ
0PIN
.10REGISTER M.T
O W O W .C O
W
W
O W O W .C O
W
Note:
WW .100Y.CSLEEP,
1. WRx, WPx, WDx, RRx,W
W
.Tand W RPx, and Y.C are common
RDx
00all .TW WW
to all pins within the0same
.10
Y port. .clk
M T I/O
W,
M PUD are commonW .1to ports.
O M W C O
W O WW .100Y .
W
W O W O W W .C O
12.2.1 WWPin .100Y.C M.TW
Configuring the WW .100Y.C M.TW W .100
Y
M.T
W
O
Wport pin consists of three register W O W W .C O
Each
WW .100Y.C M.TW WW bits: Y.C PORTxn,
DDxn, W and PINxn. W As shown .100
Y in “Register
M.T
W
Description
W for.CI/O-Ports”
O on page 82,W the .100 bitsOare
WDDxn M.T accessed at the W W
DDRx I/O C O
address,
. the
.C .TW Y W
WW .1bits
PORTxn 00Yat the PORTx W
M.T I/O address,Wand
W
W
00YPINxnMbits
.1the O at the PINx
W
I/O W .100
address. O M.T
W O W .C
WW .100Y.C M.TW W 0Y.C M.TW
.10direction
W .100
Y .TW
The DDxn W bit in the O DDRx Register selects W the C O of this pin. If DDxn W is W written .C
logicOM one,
Y.C W . TW Y W
W
PxnWis configured .100 asOan TW pin. If W
M.output DDxnW 00Y logic
is.1written O M.zero,
W
Pxn is configured W .100as an O M.T
input
W C W .C
pin. WW Y.C W WW .100Y. M.T
W W .100
Y .TW
WW is written Y.C .TWwhen the W
W Y. .TW W 0Y
.10resistor
If PORTxn W .100 logic O Mone pin is W .100
configured asMan input pin, the pull-up
O W W is
W Y .C W W W 0 Y .C T W W
W
activated. To switch 0
0 the pull-up T
. resistor off, PORTxn 0
.1 has to be .
written logic zero or the pin has to
W.1 Y.COM W WW OM
.Cwhen
be configured WW as.1an 0 0output pin.
M. TThe port W
pins are 0
tri-stated
.1 0 Y .TW condition becomes active,
Mreset
W O W C O
even if noW clocks
W are00running. Y.C W WW .100Y.
W .1 O M.T W
WW .100Y.C M.TW WW
W O
WW .100Y.C M.TW
W O
WW .100Y.C 68
W W
7799D–AVR–11/10 W
.C OM
00Y .TW
W W.1 Y.COM W
If PORTxn is written logic one when
W 100pin isOconfigured
W.the M.T
. T W W
W logic .zero 0
.C
0Ywhen M . W as an output pin, the port pin is driven
Tpin
high (one). IfOPORTxn M is written 1 the is configured as an output pin, the port
Y .C W W WW 00Y.CO .TW
00
pin is.1driven .T
lowM(zero). .1 M
W W Y .C O
W W WW 00Y.CO .TW
W 100 OM
.T .1 M
12.2.2 Toggling the PinWW. Y . C W W WW 00Y.CO .TW
.T W W 00 .T .1 of PORTxn, M
.C OM Writing
W W.1a logic Y .C OMto PINxn toggles the
one
W WW value
0 Y .CO .TW independent on the value of DDRxn.
0 Y .T W W 0 0 .T W . 1 0 M
0 Note that 1
W. the SBI O M
instruction can be usedW to toggle one O single bit in a port.
W.1 OM WW .100Y.C M.TW
W O
W O
Y.C Switching WW
W .CO .TW
YOutput WW .100Y.C M.TW
WW 12.2.300 .T W Between Input and
1 0 0 M
W.1 OM W. .CO .tri-state W
0Y.=C0b00)
O
WW .100Y.C M.TW
When WW switching
0 0 Ybetween T W ({DDxn,WWPORTxn} . 1 0 M.T
W output high ({DDxn, PORTxn}
and
W . 1 O M W O
W O = 0b11),Wan intermediate Y.C state with eitherW
W pull-up .C {DDxn,
enabled
.TW
PORTxn} = 0b01) or output
WW .100Y.C M.TW low ({DDxn, W . 100 M .TWoccurs. Normally, 00Y
.1the M
O W PORTxn} =
O 0b10) W pull-up
.C O enabled state is fully acceptable, as
W
WW .100Y.C M.TW a high-impedant WW .10environment 0Y.C M.TW will not notice
WWthe difference . 1 00Y M .TW a strong high driver and a
between
W O
W O WWis not .CO WW 0Y.CRegister W
WW .100Y.C M.TW pull-up. W If this . 1 0 0 Ythe case, M . T WPUD bit in
the the MCUCR
W . 10
O M.T can be set to disable all pull-
W O C
W O
WW .100Y.C M.TWups in allW
W
ports. Y.C .TW WW .100Y. M.T
W
W . 100 O M W C O
W O .C WW low.1generates . .TW
WW .100Y.C M.TW Switching W W
between . 00Y withMpull-up
1input .TW and output 00Y Mthe same problem. The user
W O W C O W W .C O
WW .100Y. C
.Tmust
W use either W
W the tri-state 100
.
Y ({DDxn,
M .TW PORTxn} =W0b00) or10the Y
. 0 output .TWstate ({DDxn, PORTxn}
Mhigh
M W . O W C O
W
WW .100Y.C M.TW
O = 0b11) as an intermediate
WW .100Y.C step.
.TW WW .100Y. M.T
W
W O W O M W
Wvalue.00Y. C O
WW .1the .C W
WW .100Y.C MTable .TW 12-1 summarizes 00YcontrolMsignals .TW for theW pin
W .1 O M.T
W O C
W
WW .100Y.C Table
O
.TW12-1. Port WWPin Configurations Y.C .TW WW .100Y. M.T
W
M W .100 O M W C O
W
WW .100Y.C M.TW
O
WW .1PUD 00Y
W
W O M W C O
W O DDxn PORTxn W(in MCUCR) Y.C I/OW Pull-up WWComment Y. W
WW .100Y.C M.TW W . 100 M .T W .100 O M.T
W O 0 W O No WW Y. C
WW .100Y.C M.TW
0
WW .X100Y.C Input M .TW
Tri-state 0(Hi-Z)
.10 M.T
W
W O W C O
W O
WW 0.100Y.C Input
W will source Y. current.TifW
WW .100Y.C 0 M.TW 1 M .TW Yes WPxn W .100 O M
ext. pulled low.
W O W O W .C
WW .100Y.C 0 M.TW 1 WW 1 .100Y.C Input M .TW No W Tri-state 00Y
.1(Hi-Z) M.T
W
O W O W .C O
W
WW .100Y.C1 M.TW0 WWX .100Y.Output C
.TWNo WW Low
Output 0Y
.10(Sink) M.T
W
O W O M W .C O
W
WW .100Y.1C M.TW WW Y.C .TWNo WW High.1(Source)00Y M.T
W
1 X
W . 100 Output O M Output
W C O
W O WW .100Y .
W
12.2.4 Reading the Pin Value O W O W .C O
W
WW Independent .C .TW WW .100Y.C M.TW WW .100Y .TW
. 1 00Y M of the setting of Data Direction O bit DDxn, the port pinW can be O
read Mthrough
W .C O W W
0Y.Cthe M TW RegisterW
W Y .C
00preceding .T W the
WW PINxn 1 0 0 Y
Register .T
bit.
WAs shownW in Figure . 1 0
12-2, .
PINxn bit and . 1
the O M latch con-
W W. .C OM
W WW to00avoid Y .CO .TW W WW 00Y.C .T W
W 0 Y W 1
stitute 0
W.1 edge
a M.T
synchronizer. This is needed
W.1 Y.COM W
metastability if the physical
WW
. pin changes
OM
Y.C a timing
value
WWnear .the 0 Y .COof the .T Winternal clock,
W Wbut it also
0 0 introduces .T a delay. W
Figure 12-3 . 1 0
shows
0 W
M.T dia-
1 0 M W . 1 O M W C O
O
W of the synchronization when W C
Y.externally W . W
gram
WW .100Y.C M.TW W reading .
an
1t00 and M .TWapplied pin Wvalue..1The 00Ymaximum M.T
and
minimum
W propagation
O delays are denoted W O t respectively. W W .C O
WW .1pd,max .C pd,min Y W
WW .100Y.C M.TW 00Y M.T
W W
W .100 O M.T
W O W O W .C
Y
M.T
W
W O W O W W .C O
Y .TW
W O W C O W W . C OM
W W .100
Y .TW
W O W C O W W .C OM
W W .100
Y .TW
W O W C O W W .C OM
W W .100
Y
W O W C O W W
W W
W O W C O
W
W O W C O
W O W
WW .100Y.C M.TW WW
W O
WW .100Y.C M.TW
W O
WW .100Y.C 69
W W
7799D–AVR–11/10 W
.C OM
00Y .TW
W W.1 Y.COM W
W 00 .T
Figure 12-3. Synchronization when W W.1Reading .C Oan MExternally Applied Pin value
.T W W . 1 0 0Y M .TW
OM W O
0 0 Y.C .T W WW .100Y.C M.TW
W.1 Y.COM W W O
WW .100SYSTEM .T
CLK WW .100Y.C M.TW
W OM W O
OM WINSTRUCTIONS O XXX W O
XXX in r17, PINx
00 Y.C .T W
.1 M W O W O
W
WW .100Y.C M.TW
O
WW SYNC .C
00Y LATCH .TW WW .100Y.C M.TW
W . 1 O M W O
W
WW .100Y.C M.TW
O
W O W O
W
WW .100Y.C M.TW
O
WW .100Y.C M.TW
PINxn WW .100Y.C M.TW
W O W O
WW .10x00
W .CO .TW
WW .100Y.C M.TW WW .100Y.C r17 M.TW 00Y M 0xFF
W W . C O
W 00 Y .T W .1 M .1
t pd, max M
W 00 .T W .1 M .1 M
W W.1 Y.COM W WW 00Y.CO .TW W WW 0t0pd,Ymin .CO .TW
W 00 .T W .1 M .1 M
W 00 .T W .1 M .1 M
W 00 .T W .1 M .1 M
W.1 Y.COM Consider the W WWperiod
clock Y .CO shortly
starting W after the W WWfalling
first 0 Y .CO of the
edge Wsystem clock. The latch
W W
. 1 00 M .T W
W . 0
10 is low,Oand M .T
W .1 0
O M.T
W O is closed when the clock goes transparent
WW .100Y. when the C
clock is high, as indicated by the
WW .100Y.C Mshaded .TW regionW
W
. 1 0 0Y.C M.TW M .TW
W O of theW “SYNC LATCH” O
Y.CPINxn.TRegister
signal. The signal WWvalue CO
is .latched when the system clock
WW .100Y.C goes .T Wlow. It is WW into
clocked 1 0 0the M
W at Wthe . 1
succeeding 00Y positive M .TWclock edge. As indi-
OM . O W .CO .TW
W WW tpd,max 0Y.CandM WW 00Y
WW .100Y.C cated M .T W
by the two W arrows . 1 0 .TW a single
tpd,min, signal.1transition
W Oon M the pin will be delayed
W C O W W .C O W Y .C W
WW .100Y. between
M .TW
½ and 1½ W system
.
clock
100
Y period
M .TW
depending uponW the
W
time
.100 of assertion.
O M.T
W O W O W Y. C
WW .100Y.CWhen TW aW Y.C Wvalue, a W .100 must .TW
M .reading backW software
W .100 assigned O M .Tpin nop instruction
W C O Mbe inserted as indi-
W C O W . C W Y . W
WW .100Y. cated
M
in
.TW
Figure 12-4. W The out
.
instruction
100
Y
M .TW
sets the “SYNC W LATCH”
W .100 signal at
O M.Tpositive edge of
the
the O W O .C
W
WW .100Y.C M.TW
clock. In this case, the
WWdelay tpd C
Y.through the synchronizer
.TW WW is 1.1system 00Y clock M.T
period.
W
W .100 O M W C O
W O Y.C WW .1Pin .
WW .100Figure Y.C 12-4. .TWSynchronization WW when .100 Reading M .TaW Software Assigned 00YValue M.TW
M W O W O
W
WW .100Y.C M.TW
O
W O W O
W
WW .100Y.C M.TW
O
W W .C O
SYSTEM W CLK WW 00Y.CO .TW W WW 00Y.CO .TW
Y W
W
.C W
WW .100Y M .TWr16 W
W . 100 O M .T 0xFF W
W .100 OM
.T
WW .100Y M .TW W
W .100 O M .T W .10 O M.T
W .C O W r1600Y.C W Y .C W
WW .1INSTRUCTIONS
00Y M .TW WPORTx,
out
. 1 M
nop .TW inWr17, PINx
W .100 O M.T
W O W O W .C
WW .10SYNC 0Y.C LATCH .TW WW .100Y.C M.TW W .100
Y
M.T
W
W O M W O W W .C O
Y
M.T
W
W O W O W W .C O
WW .100Y.C PINxn W WW .100Y.C M.TW W .100
Y
M.T
W
W O M.T W O W W .C O
WW .100Y.C r17 W WW .100Y.C M.TW W .100xFF0Y .TW
W O M.T W 0x00 O
C W W .C OM
W W .100
Y .TW
W O W t pdC O W W .C OM
W W .100
Y .TW
W O W C O W W .C OM
W W .100
Y
W O W C O W W
W W
W O W C O
The following WW code Y.C
example shows W how to W setWport .B10pins 0Y. 0 and W
M1.Thigh, 2 and 3 low, and define
W .100 O M.T W C O
the port pinsWfrom 4 toY7.Cas input W with pull-ups WW assigned Yto. port pins 6 and 7. The resulting pin
values are read
W
Wback.100again,Obut M.T as previously W
discussed,
.100 a nop instruction is included to be able
W Y.C .TW WW
to read back Wthe value
W .100recently O Massigned to some of the pins.
WW .100Y.C M.TW
W O
WW .100Y.C 70
W W
7799D–AVR–11/10 W
.C OM
00Y .TW
W W.1 Y.COM W
W 00 .T
(1) W W.1 Y.COM W
.C OM W W.1 Y.COM W
...Y W W 100 .T
W .100 O M.T W W.outputs .C OM
WW .100Y .C Y .TW
; Define
M .TW
pull-ups and W set
W . 100
high
O M
O
W ; Define directions for W .C
.TW WW .100Y.C M.TW W port.1pins 00Y M .TW
M O
W ldi r16,(1<<PB7)|(1<<PB6)|(1<<PB1)|(1<<PB0) W O
.100Y M W ldi O
r17,(1<<DDB3)|(1<<DDB2)|(1<<DDB1)|(1<<DDB0) W O
W O
WW .100Y.C M.TW WW out 0 0 Y.C .T W WW .100Y.C M.TW
1
W. PORTB,r16 OM W O
W
WW .100Y.C M.TW
O
WW out.10DDRB,r17 0Y.C M.TW WW .100Y.C M.TW
W O W O
W
WW .100Y.C M.TW
O
WW; Insert 0 0 Y.C nop for .T Wsynchronization WW .100Y.C M.TW
. 1 M W O
WW .100Y.C M.TW Wnop 1
W. port OM W O
W
WW .100Y.C M.TW
O
W;W Read
0 0 Y.Cpins .TW WW .100Y.C M.TW
. 1 OM W O
W O in WW Y.C WW .100Y.C M.TW
WW .100Y.C M.TW W r16,PINB 1 0 0 .T W
... WW. OM W O
W
WW .100Y.C M.TW
O
W. 1 OM W O
W
WW .100Y.C M.TW
O C Code Example
W i;Y.CO W O
W
WW .100Y.C M.TW
O unsigned WWchar 00 .TW WW .100Y.C M.TW
W . 1 O M W O
W
WW .100Y.C M.TW
O ...
Wpull-ups O W*/ O
O WW .100Y.C M.TW
W /* Define and set outputs high
WW .100Y.C M.TW /* Define WW .100Y.C M.TW
W O directions for port pins */ WW
WW 00Y.CO .TW .CO .TW
WW .100Y.C M.TW PORTB =W(1<<PB7)|(1<<PB6)|(1<<PB1)|(1<<PB0); .1 M
W . 1 00Y M
W W .C O
W 00 Y W
.T DDRB = (1<<DDB3)|(1<<DDB2)|(1<<DDB1)|(1<<DDB0);
.1 M .1 M
W W.1 Y.COM W WWfor0synchronization*/
Y .CO .TW W WW 00Y.CO .TW
W 00 .T /* Insert W nop .1 0 M .1 M
W W.1 Y.COM __no_operation(); W WW 00Y.CO .TW W WW 00Y.CO .TW
W 00 .T W .1 M
W.1 Y.COM /*WRead port W W.1*/ Y.COM W WW 00Y.CO .TW
W W pins 0 .T W .1
W 00
W.1 Y.COMi = W
M
W PINB;
W WW 00Y.CO .TW W
W 00 .T .1 M .1 M
W W.1 Y.COM ...
W 00 .T W .1
W.1 Note: OM W.1 two OM WWto minimize OM
.C 1. ForW the assembly W
program, Y .Ctemporary W registers are W used 0Y.C the time Wfrom pull-
W W
. 1 00 Y
M .T are set on pins 0,W
ups
W
1,. 0
16,0and 7, until
O M . T
the direction bits are W .1 0
correctly set, O M.T bit 2 and 3
defining
W O WW .100Y . C
WW .100Y.C M as.T lowW and redefining WW bits.100and 0Y.1Cas strong M .TWhigh drivers. M.T
W
O W O W .C O
W
W
12.2.5 Digital InputWEnable and O Sleep Modes W O W .C O
W .C .TW 12-2, theWdigital
W Y.C .TW WW .100Y .TW
W As.1shown 00Y in Figure M W . 100 signal
input O M can be clamped to W
ground at C O
the Minput of the
W O C WW .100Y . .TW
WW schmitt-trigger.
0 0 Y.C .T
The
Wsignal denoted WW SLEEP .1 0 0Y.in the M .TW is set by
figure, the MCU Sleep M
Controller in
W. 1 M WW 00Y.C O
.COmode, WW and Y .CO .TW W T W
WWPower-down 0 Y
M. T W
Power-save W mode, 0 0 Standby mode to avoid high 1
power
W. consumption
M . if
W .10
.C O W W.1 Y.COM W W 0 Y . CO W
W
Wsome .input W M. T
00Ysignals are .TWleft floating, W or have 0an0 analog signal
W.1 Y.COM W
.T level close to V.CC 10/2.
W W 1 Y.COM W W W WW 00Y.CO .TW
W SLEEP.1is00overridden W 0 external.Tinterrupt pins. If the.1external interrupt
0as
W O M.Tfor port pins enabled W W.1 Y.COM W W
Woverridden OM
Y.Cby various W
.C W 0
W W
request is not
. 10 0 Y enabled,
M .T W
SLEEP is active
W also
W .1
for
0 0 these
O
pins.
M .T SLEEP is also
W . 10
O M.T
W O Y.C W .C
otherWalternateYfunctions .C asWdescribedWinW“Alternate Port Functions” W W 72. .100Y
on page .TW
W
W .100 O M.T W .100 O M.T W W .C OM
W high00level Y.C (“one”) onWan asynchronous Y. C TW W pin.1configured00Y .TW
If aWlogic
. 1 M .TW is present W
W .100 O M.external interrupt
W COM
as
W O orW .C W .
Yinterrupt.TW
WW .100Y.C M.TW
“Interrupt on Rising Edge, Falling Edge,W Any Logic YChange onWPin” whileW the external
W .100 Flag O M .T W .100 OM
is not enabled,
W W the
Y .C O
corresponding
W
External
W W Interrupt
0 Y .C will
.T
beW set when W resuming
W 00 Y.C the
from
W 0 0 . T 0
.1in these sleep M mode produces . 1
above mentioned
W W.1 Sleep Y .CO .TW
M
mode, as the clamping
WW 00Y.CO .TW W WW the requested
W 0 W
logic change. .10
W OM W.1 OM
W O W O
W O W
WW .100Y.C M.TW WW
W O
WW .100Y.C M.TW
W O
WW .100Y.C 71
W W
7799D–AVR–11/10 W
.C OM
00Y .TW
W W.1 Y.COM W
W 00 .T
12.2.6 Unconnected Pins W W.1 Y.COM W
TW
M.unused,
W 00 .T
If some pins O
C
are
W W.1 Yto
it is recommended
.C OM that these pins have a defined level. Even
ensure
though 1
.
Y of the.Tdigital
00most M
W inputsWare disabled . 100 in the Mdeep.TWsleep modes as described above, float-
W . O W O
WW .C W WW current Y.C .TW in all other modes where the digital
ing inputs
. 1 00YshouldM be .Tavoided to reduce
W . 100 consumption O M
WW are .C O W and00Idle Y.Cmode)..TW
.TW Winputs . 1 00Y
enabled
M
(Reset,
.TW ActiveW mode
. 1 M
O M W C O W
W level00of CO
.an
00 Y.C
.TW The
W W simplest
1 0 0 Y .
method
M
to
.T Wensure a W
defined . 1
Y unused
M .TWpin, is to enable the internal pull-up.
.1 M . O W O
W O WW
InWthis case, 0the .Cpull-up.Twill W be disabled WW during Y.C If low
reset. .TW power consumption during reset is
WW .100Y.C M.TW . 1 0 Y M W . 100 O M
important, O
W it is recommended to use anW Y.C or.T
W
WW .100Y.C M.TW
O
WW .100Y.C M.TW W external .
pull-up
100 this may M
pull-down.
W Connecting unused pins
directly to V
W CC Y.C or GND O is not recommended, W since O cause excessive currents if the pin is
W
WW .100Y.C M.TW
O
WW .configured
accidentally 00 as .Tan
Woutput. WW .100Y.C M.TW
W 1 OM W O
W
WW .100Y.C M.TW
O
W O W O
WW 0Alternate
W12.3 0 Y.C
O
.TPort
W Functions WW .100Y.C M.TW WW .100Y.C M.TW
W.1 OM W .CO .Tfunctions WW 0to0Ybeing .CO general W digital I/Os. Figure 12-5
WW .100Y.C M.TW Most port WW pins have
. 1 0 0 Yalternate
M
W inWaddition . 1 M.T
W O W O W
W simplified .C O
WW .100Y.C M.TW
shows how WW the port0pin Y.Ccontrol.Tsignals W from Wthe 00Y Figure
.1be
W
12-2 can be overridden by
M.inT all port pins, but the figure
alternate functions.W . 10 The overridingO M signals may W
not C
present O
W
WW .100Y.C M.TW
O
W W 00Y
.C .TW WW .100Y. W
M.Tmicrocontroller family.
serves as a generic W . 1description O M applicable to all port W pins in the
C O AVR
W
WW .100Y.C M.TW
O
W
W O W C O
W O
WW .100Y.C M.Figure TW 12-5. WAlternate
W Y.C .TW
(1)
WW .100Y. M.T
W
W . 100Port Functions
O M W C O
W
WW .100Y.C M.TW
O
WW .100Y.C M.TPUOExn W WW .100Y. M.T
W
W O W C O
W
WW .100Y.C M.TW
O
WW .100Y.C M.PUOVxn TW WW .100Y. M.T
W
W O
1
W C O
W
WW .100Y.C M.TW
O
WW .100Y.C M.TW 0 WW .100Y.PUD M.TW
W O W O
W
WW .100Y.C M.TW
O
WW .100Y.C DDOExn .TW WW .100Y.C M.TW
W O M W O
W
WW .100Y.C M.TW
O
WW .100Y.C DDOVxn .TW WW .100Y.C M.TW
W O M W O
W
WW .100Y.C M.TW
O
1
Q D
W
0
O W O
W O
DDxn
WW .100Y.C M.TW Q CLR
W WDx Y.CO
W O W
WW .100Y.PVOExn CO RESETW W
WW .100Y.C M.TW M .TW W
W .100
RDx
O M.T
O W O .C
W
PVOVxn
WW .100Y M.T
W
W O W O
DATA BUS
W O WW .100Y .C
WW .100Y.C M.TW Pxn WW .100Y.C M.TW
1 1
M.T
W
O W 0
O Q D
W 0
.C O
W
WW .100Y.C M.TW WW .10DIEOExn 0Y.C M.TW
PORTxn
WW .100PTOExn Y
M.T
W
O W O
Q CLR
W .C O
W
WW .100Y.C M.TW WW .1DIEOVxn 00Y
.C .TW WW .100Y WPx M.TW
W O M RESET
W O
W .C O 1
W SLEEP Y .C W W WWRx 0 Y.C W
W W M.T
RRx
W 0 0 Y .T W 0
.1 0 0 M .T . 1 0
WW .100Y.C M.TW WW .10SYNCHRONIZER 0Y.C M.TW W .100
Y
M.T
W
W O W O RPx
W W .C O
Y
M.T
W
SET
D Q D Q
W O W O
PINxn
W W .C O
Y
M.T
W
L CLR Q CLR Q
W O W O W W .C O
WW .100Y.C M.TW WW .100Y.C M.TW Y W
clk
W .100 M.T
I/O
W O W O W W .C O
WW .100Y.C M.TW WW .100Y.C M.TW DIxn W .100
Y .TW
W O W C O W W .C OM
W W .100
Y .TW
W O W C O W W .C OM
WW .100Y.C M.TW WW .100Y. Y .TW
AIOxn
W W .100
W O W O M.T W W .C OM
WW .1PUD: C
. PULLUP Y
W W Pxn0PULL-UP
PUOExn:
. 0Y.C OVERRIDE
1 PULL-UP M
W
.TVALUE
ENABLE 00Y W
M.TDDRx
DISABLE W
W .100
PUOVxn: Pxn
W O
OVERRIDE W WDx:
C OWRITE
W
WW Pxn.1DATA .C W VALUE WW RDx: Y. READ DDRxW
.T REGISTER W
00Y .100
DDOExn: Pxn DATA DIRECTION OVERRIDE ENABLE
DDOVxn:
PVOExn: W Pxn PORT VALUE O M.T ENABLE
DIRECTION OVERRIDE
W RRx:
C
READ
O MPORTx
WW Pxn PORT Y.C OVERRIDE
OVERRIDE
W WW RPx:
WRx:
Y. WRITE PORTx
.TW
PVOVxn:
DIEOExn: Pxn DIGITAL
W . 100 INPUT-ENABLE
VALUE
O M .TOVERRIDE
VALUE
ENABLE
W .100 READ
WPx: O
WRITE
PORTx
MPINx
PIN
DIEOVxn:W .C W Y . C
.TW
Pxn DIGITAL INPUT-ENABLE OVERRIDE VALUE
Y W DIxn:.100 DIGITAL INPUT PIN n ON PORTx
clk : I/O CLOCK
W SLEEP .CONTROL 100
I/O
SLEEP:
PTOExn: Pxn,W OM ENABLE W
C WW
PORT TOGGLE OVERRIDE AIOxn: ANALOG INPUT/OUTPUT PIN n ON PORTx
W . .TW
W . 1 00Y M
W O
WW .100Y.C M.TW
W O
WW .100Y.C 72
W W
7799D–AVR–11/10 W
.C OM
00Y .TW
W W.1 Y.COM W
W 00 T
M.common
Note: 1. WRx, WPx, WDx, RRx, RPx,
W W.1and Y RDx.C Oare to all pins within the same port. clk ,
W signals are unique for each pin. I/O
SLEEP, .T W and PUD are Wcommon . 1 0to0 all ports.MAll . Tother
OM W Y.C
O
Table1012-2 0 Y.Csummarizes .T W the function WW of the . 1 0 0overriding M .T W
signals. The pin and port indexes from Fig-
W . O M W W .C O
WW ure 12-5 0are .C 00Y The overriding W
0 Y not shown W in the succeeding
M.T the alternate W
W tables.
W.1 Y.COM W
.T signals are generated internally
inWtheW.1modules .C O having W function.
W W .100
Y
M.T
W 00 .T
O M.T W .C O W W.1 Y.COM W
Y.C W W 12-2. Y W W 00 Signals .for T Alternate Functions
W .100 O M.T
W
Table
W .100 Generic O M.TDescription of Overriding W W.1 Y.COM W
W .C
WW .100Y.C M.TW W
Signal Name .100
Y Full Name
M.T
W WDescription 00
W.1 Y.COM W
.T
W O W . C O W
WW .100Y.C M.TW WW .100Y TW
M.Override
W 00 .T enable is controlled by the PUOV
W O W O
Pull-up
C W W.1 is set,
If this signal
.C OM
the pull-up
WW .100Y.C M.TW PUOE W Y . .TW W If this
signal. 0
.10signal
Y is cleared,TW the pull-up is enabled when
M=.0b010.
W
W . 100 Enable O M W O
WW .100Y.C M.TW
W O {DDxn, PORTxn, PUD}
W O W theYpull-up O
W O
WW .100Y.C M.TW PUOVW
W 0 0 Y.C Override
Pull-up .T W If PUOE
WWis set, . 1 0 0 .C Mis.T enabled/disabled
W when PUOV is
W . 1 O M set/cleared, W regardless Oof the setting of the DDxn, PORTxn,
W W .C O W Value Y .C W W WRegister 0 Y .C .T W
W 00 Y .T W W .10 0 M. T and PUD .1 0 bits. M
W W.1 Y.COM W WW 00Y.CO .TW If this signal W WW 00Y.CO .TW
W is set, .1 the Output
W
W .100 O M.T DDOE W 1 Direction
.Data
C OM W W .C OMDriver Enable is controlled by the
WW .100Y. C
.TW W W Y .
100 Enable
Override M
DDOV
.TW enabled W signal. If this Y
signal
.100Register
is cleared,
M .TW the Output driver is
M W . O by the WDDxn C O bit.
W
WW .100Y.C M.TW
O
Mis.Tenabled/disabled when
O W O If DDOE is set, W
the Output C O
Driver
.
W
WW .100Y.C M.TDDOV W WWData.1Direction 00Y
.C .TW DDOV is set/cleared,
WW .1regardless 00Y TW
of .the setting of the DDxn
M
W O M W C O
W O Override
WW .100Y.C M.TRegister
Value
bit. WW Y. W
WW .100Y.C M.TW W
W .100 O M.T
W O W O W C
Y. Driver
WW .100Y.C M.TW WW .100Y.C M.IfTthis W signal isW set and the .100Output O
W
M.Tis enabled, the port
O W O W C
Y. signal. If.TPVOE
W
WW .100Y.C PVOE .TW W
Port W Value00Y.C value
.TW
is controlled WW by the PVOV
.100the port M
W is cleared, and
M Override W . 1Enable OMthe Output Driver is enabled, W C O Value is controlled by the
W W Y.C O
W W W 0 Y .C PORTxn .T W Register W W
bit. 0 0 Y. .T W
W 00 .T 0
W.1 Y.COM W .1 M
W 0 .T
W
W .100 PVOV
O M.T Port Value
W .10
.C
If MPVOE
Osetting
is set, the port
W W.1 Y.COM regardless
value is set to PVOV,
W
of the
C W .TW
WW .100Y. W Override Value Y of the PORTxn W Register bit.
00 .T
W O M.T
W
C W .C
WW .100Y.PTOEM.TW Port Toggle
W 00Y .TW W .100 bit isOinverted. M.T
W .C O Override W W.1 Y.IfCPTOE
Enable OM is set, the PORTxn
W W
Register
W Y .C W
WW .100Y M .TW W
W .100 O M .T W
W .100 O M.T
W O Digital Input If.Cthis bit is set, the Digital WW .100Y
Input Enable .C
is controlledTWby the
WW .100DIEOE Y.C .T W Enable Override WW .100YDIEOV M .TWIf this signal M .Input
OM signal. is cleared,
W the O
Digital Enable
W W Y .C W Enable W WW 00isYdetermined .CO .TW by MCU stateW W
(Normal 0 0 Y.C sleep .mode).
mode, T W
W 00 .T .1 M . 1 M
W W.1 Y.COM W WW 0If0DIEOE Y .CO is set, W W WW 00Y.CO .TW
W .T 1
W
W 100
.DIEOV O M.T Enable Override
Digital Input
W.1 DIEOV C
M
Oset/cleared,
the Digital Input
W
is enabled/disabled
Wthe.
.C OM when
.C W . is W regardless of MCU0 Y state W
(Normal
WW .100Y M
W
.TValue W . 00Y sleepMmode).
1mode, .T W
W .10 O M.T
O W O .C
W
O W This is the O
Digital Input to alternate W
functions. In.C O
the figure, the
W
WW .100Y.C M.TW WW signal 00is
C
Y.connected .TW WW schmitt .
Y
100 trigger M .TW
W . 1 O M to the output of theW O but
W O Digital Input Y.C WW .C .TW
WWDI .100Y.C M .TW WW before . 1 00the synchronizer.
M .TW Unless the Digital 1Input
. 00Yis usedMas a
W O W
clock source, O
the module with the W
alternate W function .C O
will use its
WWown synchronizer. .C Y .TW
WW .100Y.C M.TW .1 00Y M .TW W
W . 100 O M
W O
W
WW .100Y.C M.TW
O
WW Y.C
00Analog .TW WW .100Y.C M.TW
. 1 M O The
W O
Analog
This is the
WWis connected
Input/output
.CO directly
to/from
WW functions.
alternate
Y.C bi- .TW
WW .100Y.CInput/Output
AIO .T W W signal 0 0 Y .T W to the pad, W and can
W. 1 0
be 0 used
OM
OM W.1 OM
W
directionally. WW .100Y.C M.TW
WW subsections .CO .Tshortly W Wthe W O
Y.C functions W for each Wport,WW 00Y.CO .TW
The W following Y describe W 0
alternate . T and relate the
W .10 0
OM
0
W.1 to the .C OM W W.1 Y.COM
overriding signals to .Cthe alternate function. WRefer Y alternate W function description 0 further
W W 00Y M.T
W W .100 M.T
W .10for
details. WW.1 O W C O W W
Y.C W WW .100Y. M.T
W W
W
W .100 O M.T W C O
W
W O W C O
W O W
WW .100Y.C M.TW WW
W O
WW .100Y.C M.TW
W O
WW .100Y.C 73
W W
7799D–AVR–11/10 W
.C OM
00Y .TW
W W.1 Y.COM W
W 00 .T
12.3.1 Alternate Functions of Port B W W.1 Y.COM W
.TW W 00
W.1 areYshown
.T
OMin Table 12-3.
The Port B pins
C OMwith alternate functions W . C
1 00Y
.
M .TW W . 100 M .TW
.
W 12-3. O W O
WW Table .C Port .B TW Pins Alternate WWFunctions Y.C .TW
. 1 00Y M W . 100 O M
W Pin Y.Alternate O
.TW WW Port
00
C
.TFunctions
W WW .100Y.C M.TW
M W . 1 O M W O
0 Y.C
O
.T W WWPB7 .100YOC0A/OC1C/PCINT7.C .T W WW Compare
(Output
. 1 0 0Y.C and PWM
M .TW Output A for Timer/Counter0, Output
.10 M W Compare O M and PWM Output C W
for Timer/Counter1 .C O or Pin Change Interrupt 7)
W O .C W Y TW
WW .100Y.C M.TW WW .100Y .T W W . 1 0 0 M .
PB6W OM W O
W
WW .100Y.C M.TW
O
WW .100Y.C M.TW
PCINT6 (Pin Change InterruptW
W 6) .100Y.C M.TW
W O PB5 W PCINT5O WW 00Y.CO .TW
WW .100Y.C M.TW
(Pin Change Interrupt W5)
WW .100Y.C M.TW .1 OM Interrupt 4)
W .C O PB4WW T1/PCINT4 Y .CO (Timer/Counter1
W Clock
W WW Input or 0 Y
Pin.CChange W
WW
.1 00 Y
M .TW W
W . 10 0
O M .T
W .1 0
O M.T
W O
WW PDO/MISO/PCINT3 .C WWData .Output Y.C SPI Bus WMaster Input/Slave Output or
WW .100Y.C M.TW PB3 . 00Y Interrupt
1Change M .TW(Programming W 100 or O M.T
W O
WW .100Y.C M.TW
W O Pin 3)
W O WW O Master Output/Slave Input or Pin
W O
WW .100Y.C M.TW PB2 W Change
WPDI/MOSI/PCINT2
0 0 Y.C 2)(Programming
.T W Data
W Input or SPI
. 1 0 0Y.CBusM .TW
W . 1 Interrupt O M W C O
W O
WW .100Y.C M.TW PB1 W SCLK/PCINT1
W Y.C .TW WW .100Y. M.T1)
W
W . 100 (SPI O M Bus Serial Clock or PinW Change Interrupt
C O
W
WW .100Y.C M.TW PB0
O
WW .100Y.C M.TW WW .100Y. M0).T
W
SS/PCINT0W (SPI Slave
O Select input or Pin W
Change O
Interrupt
C
W
WW .100Y.C M.TW
O
W
W O W C O
W
WW .100Y.C M.TW
O The alternate pinW
W configuration Y.C is as .follows: TW WW .100Y. M.T
W
W . 100 O M W C O
W O
WW .100Y.C •MOC0A/OC1C/PCINT7,
.TW WW .1Bit 00Y7
W
W O M W C O
W O
WW .Match Y.C output: W Y. .TW
WW .100Y.C OC0A, M .TWOutput Compare 100 A O M .TWThe PB7 W pin can W 100 as O
.serve anMexternal output for the
W .C O W
W Compare. Y .CThe pin W W 0Yan C
. output.T(DDB7 W
W Y Timer/Counter0 W Output
W 0 .T has to be W
configured as
0 set “one”) to
W
W .100 O M.Tthis function. The W .10
.C
M
Oalso W W.1 Y.COM W
Cserve W OC0A pin is the
.TW output pin for the PWM mode timer function.
WW .100Y. M.T
W W .100
Y W 00
W.1 Y.COM W
.T
W C O W W .C OM W
WW .100Y.OC1C, M.T
W Compare
Output W Match Y
.100C output: .TWPB7 pin W
The can serve 0 an external
0as
W.1 Y.COM W
.T output for the
W C O
Timer/Counter1 Output W W
Compare C. .C OM
The pin has to be configuredW as an output (DDB7 set “one”)
WW .100Y. M .TW W .
Y
100pin is also M .TW W
W .100 O M.T
to serve O this function. The OC1CW O the output pin for the PWM .C
mode timer function.
W
W O
W PCINT7, O Pin Change Interrupt W
WW source .CO .TWpin can serve WWas an 0Y.C M .TW source.
WW .100Y.C M.TW 00Y7: TheMPB7 0external interrupt
. 1 W . 1 O
O W O .C
W
0Y.C MBit
WW .•10PCINT6, .TW WW .100Y.C M.TW WW .100Y M.T
W
O 6 W O W .C O
W
WW PCINT6, .C .TW Interrupt WW 0YThe .C W WW external .100
Y W
M.T source.
. 1 00Y PinMChange source
W . 106: OPB6M .Tpin can serve as an W .C interrupt
O
W O WW .100Y
W
O W O W . C O
W
WW • PCINT5, .C Bit 5 .TW WW .100Y.C M.TW WW .100Y M.T
W
. 1 00Y M W O W .C O
W
PCINT5, O
Pin Change Interrupt source C pin T Wexternal
WW .100Y.C M.TW WW 5:.1The 00Y
.PB5
M
can serve asW
. W
an
.100
Yinterrupt .source.
MT
W
W O W O W W .C O
W•WT1/PCINT4, .C
00Y BitM4.TW WW .100Y.C M.TW W .100
Y
M.T
W
. 1 O W O W W .C O
WW Y.C .TW source. WW .100Y.C M.TW W .100
Y
M.T
W
WT1,
W .100
Timer/Counter1
O Mcounter W .C O W W .C O
W
WW .1Pin
PCINT4, 00Y
.C
Change .TW WW .1PB4 00Y pin can W
M.Tserve as an external
W 00Y source.
.1interrupt M.T
W O MInterrupt source 4: The W O W W .C O
Y .TW
W O W C O W W .C OM
WW .100Y.C M
• PDO/MISO/PCINT3 – .Port
TW B, Bit 3W
W Y. W W .100
Y .TW
WW During C
Y. Serial .Program Y pin is.TW
WW .100Y.C M.TW
PDO, SPI Serial Programming Data Output. W Downloading, this
W .100 O MT
W
W .100 OM
used as W dataW output Y
line
.C O for the
W
AT90USB82/162.
W W 0 Y .C
.T W W W 00 Y.C
W 0 0 M. T 1 0 . 1
W.1 Yinput, W.for OM When the SPIWisWenabled as a
MISO: Master
WW Data .CO Slave W Data output W W pin SPI
0 Y .C
channel. W W
master, this pin
W
0
.1is 0
configured O
T
M. as an input regardless W
0
.1 of theOsetting M.T of DDB3. When the SPI is
Y.C W Y. C
W .TW of thisWpin isW .100 .TW When the pin is forced to
enabled W as a slave,
W .100the data O M direction controlled C by
O MDDB3.
WW Y.C TWcontrolledW
W Y.
be an input, .100 canOstill
the pull-up
W M.be by theWPORTB3.100 bit.
W Y .C W W W
W 0 0 .T
PCINT3, Pin Change W.1 Interrupt OM source 3: The PB3 pin can serve as an external interrupt source.
WW .100Y.C M.TW
W O
WW .100Y.C 74
W W
7799D–AVR–11/10 W
.C OM
00Y .TW
W W.1 Y.COM W
W 00 .T
• PDI/MOSI/PCINT2 – Port B, W BitW2.1 .C OM
PDI, SPI Serial M .TW
Programming
W
Data .
Input.
Y
100 During M .TW Program Downloading, this pin is used
Serial
O W O
as data Y.C line .for
00input TWthe AT90USB82/162. WW .100Y.C M.TW
W . 1 O M W O
WW 0 0 Y.C .T W WW .100Y.C M.TW
MOSI: 1
. SPI Master MData output, Slave Data
W input for
O SPI channel. When the SPI is enabled as a
WW this Y .CO .TW WW 0Y.C M W
.T W Wslave, . 1 0 0 pin is configured
M as an input W . 1 0
regardless O of.Tthe setting of DDB2. When the SPI is
M WW as00aYmaster, O Y.C controlled
.CO .TW enabled .C TWdata direction
.the WW of this 100pin is O .TW by DDB2. When the pin is forced
.100Y M
W . 1
W input,Ythe O M W . M
W O toWbe Wan .C pull-up can still beWcontrolledW Y.C
by the PORTB2.TW bit.
WW .100Y.C M.TW . 1 00 M .TW W . 100 O M
O W O Y.C
W
WW .100Y.C M.TW WW Pin
PCINT2, 1 0Y.C Interrupt
0Change .TW sourceW 2:W The PB2 . 100 pin can M .TW as an external interrupt source.
serve
W . O M W O
W
WW .100Y.C M.TW
O
• SCK/PCINT1 W – Port O B, Bit 1 W O
W O
WW .100Y.C M.TW SCK:W
Master 1
.Clock output, M Slave Clock inputWpin W for SPI O
Cchannel. When the SPI is enabled as a
W O WW 00Y.CO .TW 0ofY.the TWof DDB1. When the SPI0 is
WW .100Y.C M.TW slave, W this pin .is 1 configured M as an input
W
regardless W . 1 0
O M .
setting
W O W
asWa master, Y.theCOdata Tdirection WWpin is.1controlled 0Y.C M W
WW .100Y.C M.TW enabledW . 1 0 0 M . W of this
W
0
O by.TDDB1. When the pin is forced
WW .100Y. Wto be an W input, the0pull-up 0Y can.TstillW be controlled W by the00 PORTB1 .Tbit. This pin also serves as
W O M.T Clock for theW W
Serial
.1 Programming
.C OM interface. W W.1 Y.COM W
WW .100Y. C W Y .TW W 00 .T
W O M.T
W
C W .C
WW .100Y. M.T
PCINT1,
W PinWChange 0
.1 0
Y
Interrupt .TW 1: The PB1
source W pin can 00serve as an
W.1 Y.COM W
.Texternal interrupt source.
W CO W W . C OM W
WW .100Y. W Y W W 00 .T
M.•T SS/PCINT0 – W
W
PortW 100Bit 0 OM.T
.B, W.1 Y.COM W
W CO .C W
WW .100Y. .TW Slave PortWSelect 100 When
Y .TW W
as.1a 00slave, this .T
OM pin is configured as an
W C OMSS: W W .input.
. C OM the SPI is enabled W W Y .C W
WW .100Y. .TW
input
M regardlessWof the setting .100 of O
Y DDB0.
M .TWAs a slave, Wthe SPI
W .10is0 activated
O M.T when this pin is driven
W O W Y.C W 0YthisC
. pin is.Tcontrolled
W
WW .100Y.C low. .TWhen
W the SPI WW is enabled
. 100 as aOmaster, M .TW the dataWdirection .10of M by DDB0.
W O M W C W W .C O
C When the pin is forced W to be an .
input, the
.TW pull-up can still be Y
controlled by the W PORTB0 bit.
WW .100Y. M .TW W . 100
Y
M
W
W .100 O M.T
O W O .C
W
WW .100Y.CPCINT0, .TW Pin Change W
WInterrupt Y.C .TWPB0 pin can WWserve.1as 00Yan external W
M.T interrupt source.
M W .100sourceO0:MThe W C O
W CO 12-4 WW Y.C .TW functions WWof Port Y. .TW
WW .100Y.Table M .TWand Table 12-5 relate . 100 theOalternateM W .100B to the O Moverriding signals
W .C O in Figure 12-5 onWpage 72.YSPI W .C MSTR W W SLAVE 0 C
Y. OUTPUT W
W Yshown W W 0 .T INPUT and W SPI 0 .T constitute the
W
W.100 MISOOsignal,M.T while MOSI is 0
W.1 into .C O M W W.1 Y.COM W
.C W divided
00Y SPI MSTR W OUTPUT W and SPI 00 SLAVE INPUT.
.T
WW .100Y M.T
W W .T W.1 Y.COM W
WW .10PCINT0,
0Y W
Pin.TChange Interrupt
W source 00 0: The PB0 .T pin can serve W as an 0external .T
interrupt source
W O M W.1 Y.COM W W W.1 Y.COM W
.C W W 00 .T
WW .100Y M.T
WW .100Y W W 00 .T W 00 .T
.C W W 0 .T
WW .100Y M.T
W W 00 .T 0
W.1 Y.COM W
W . C O W W.1 Y.COM W W 0
WW .100Y W W 00 .T W 0 .T
.C W W 0
WW .100Y M .TW W
W . 100 O M .T W .10 O M.T
W O W .C
Y
M.T
W
W O W O W W .C O
Y
M.T
W
W O W O W W .C O
Y
M.T
W
W O W O W W .C O
Y .TW
W O W C O W W .C OM
W W .100
Y .TW
W O W C O W W .C OM
W W .100
Y .TW
W O W C O W W .C OM
W W .100
Y
W O W C O W W
W W
W O W C O
W
W O W C O
W O W
WW .100Y.C M.TW WW
W O
WW .100Y.C M.TW
W O
WW .100Y.C 75
W W
7799D–AVR–11/10 W
.C OM
00Y .TW
W W.1 Y.COM W
.Table 12-4 and Table 12-5 relate
W .100alternate
Wthe
.T
OM functions of Port B to the overriding signals
W .C
shown in Figure M .T W
12-5 on page
W72. SPI . 0Y INPUT
10MSTR M .TWand SPI SLAVE OUTPUT constitute the
O W .C O
MISO 0Y.C while
0signal, W is divided
.TMOSI WW into.1SPI 00YMSTRMOUTPUT .TW and SPI SLAVE INPUT..
W . 1 O M W O
W Y .C W W W 0 Y .C .T W
W 00 .T 0
Table W.112-4.Y.COverriding OM W.1 YFunctions
Signals forWAlternate .CO .Tin
M
WPB7..PB4
W W W 0 0 .T W W 1 0 0
.T . 1 OM . M
OM WW 00PB7/OC0A/OC1C/
Signal
Y.C WW 00Y.CO .TW
00 Y.C .T W WName . 1 PCINT7 M .T W WPB6/PCINT6 .1 M PB5/PCINT5 PB4/T1/PCINT4
W 00 .T W
PUOE W.1 0 M 0 .1 M0 0
W 00 .T W
PUOV W.100
0 M .1 M
W W.1 Y.COM W W Y .CO .TW
0
W WW 00Y.CO 0 .TW 0
W 00 .T W 1 0 0 . 1 M
W.1 OM DDOE W0. OM 0 W O0 0
W O W 0O
WW .100Y.C M.TW
W O DDOV 0 0 0
W O W O
W
WW .100Y.C M.TW
O PVOE OC0A/OC1C
WW .100Y.C M.TW
ENABLE 0
WW .100Y.0C M.TW 0
W O W C O
W
WW .100Y.C M.TW
O PVOV
WW .100Y.C M.TW
OC0A/OC1C 0 WW .100Y0. M.T
W 0
W O W C O
W O DIEOE
WPCINT7
W • PCIE0Y.C PCINT6 • W PCIE0 W Y.
PCINT5 • PCIE0W PCINT4 • PCIE0
WW .100Y.C M.TW . 100 M .TW W .100 O M.T
W O C
W
WW .100Y.C M.TW
O DIEOV 1 W Y.C .TW 1 WW .1010Y. M.T
W 1
W
W . 100 O M W C O
W O Y.C WW .1PCINT5 . W PCINT4 INPUT
WW .100Y.C M.TDI W WW INPUT
PCINT7 . 100 M
W
.TPCINT6 INPUT 00Y INPUT M.T
W O W C O
W
WW .100Y.C M.TW
O
W T1 INPUT
W O W C O
W
WW .100Y.C M.TW
O AIO –
WW .100Y.C M–.TW WW – .100Y. M.T
W–
W O W C O
W
WW .100Y.C M.TW
O
W
W O W C O
W O
WW Signals Y.Cfor Alternate WWin PB3..PB0 Y. W
WW .100Y.C Table M .T12-5.
W Overriding
. 100 M .TW Functions W .100 O M.T
O W O Y. C
W
WW .100Y.C Signal .TW PB3/MISO/PCINT3/ WW .100Y.C PB2/MOSI/PCINT2/ .TW WW PB1/SCK/.100 M.T
W
M W O M W C O
W O
Name PDO
WW .100Y.CPDI M.TW WWPCINT1 Y. W
PB0/SS/PCINT0
WW .100Y.C M.TW W .100 O M.T
O W O Y. C
W
WW .100Y.C M.TW
PUOE SPE • MSTR W .C • MSTR
YSPE .TW WW SPE • MSTR
.100 M.T
SPE W• MSTR
W
W .100 O M W C O
W .CO .TPORTB3 .C W Y . W • PUD
WW .100Y PUOV W • PUDWW .100Y PORTB2
M
•.TPUDW WPORTB1 • PUD
.100
PORTB0
M.T
W M
O SPE • MSTR W W O W
W• MSTR .C O
WW .100DDOE Y.C .TW Y.C• MSTR
SPE .TW W
SPE
.100
Y
M.T• MSTR
SPE W
M
W
W . 100 O M W C O
W O W .
WW .10DDOV 0Y.C M0.TW WW .1000Y.C M.TW 0W .100
Y 0 .TW
W O W OM
W PVOE .C O W Y .C W W W 0 Y.C0 W
W W
. 1 00 Y SPE
M .T W
• MSTR W
W .SPE
1 0 0 • MSTR
O M .T SPE • MSTR
W . 1 0
O M.T
W O Y.C W Y .C W
WW PVOV 00Y SPI
.C TW OUTPUT
.SLAVE WW SPI . 100MSTR OUTPUT M .TW SCKW OUTPUT.100 0 M.T
. 1 O M W O W .C O
W
WW DIEOE .C .TW WW PCINT2 Y.C .TW PCINT1 WW Y
.100 PCINT0 M•.T
W
. 1 00Y PCINT3 M • PCIE0
W .100 • PCIE0 O M • PCIE0
W C O PCIE0
W O WW .1001Y .
WW DIEOV .C
00Y 1 M.TW WW1 .100Y.C M.TW 1 M.T
W
W .1 O W O W W .C O
WW .100Y.SPI C
.TW WW Y.C .TW SCK INPUT W 0Y
.10SPI M.T
W
MSTR
M INPUT SPIW . 100 INPUT
SLAVE O M W SSC O
DI W O .C W . W
WW .100Y .C
PCINT3 .TW
W
WPCINT2 00Y W W
M.T PCINT1 INPUTWW.1PCINT0 00Y INPUT M.T
W O MINPUT W .1INPUT O .C O
W Y.C W W Y.C W W .100
Y
M.T
W
WAIO
W .100– O M.T
W–
W .100 O M.T – W W –
.C O
Y .TW
W O W C O W W .C OM
W W .100
Y .TW
W O W C O W W .C OM
W W .100
Y .TW
W O W C O W W .C OM
W W .100
Y
W O W C O W W
W W
W O W C O
W
W O W CO
W O W
WW .100Y.C M.TW WW
W O
WW .100Y.C M.TW
W O
WW .100Y.C 76
W W
7799D–AVR–11/10 W
.C OM
00Y .TW
W W.1 Y.COM W
W 00 .T
12.3.2 Alternate Functions of Port C W W.1 Y.COM W
.TWfunction W 00
W.1 Y.COM W
.T
The Port C alternate
.C OM is as follows:
W
Y W W 00 .T
Table
WW .100Y 12-6. .C Port C WPins Alternate Functions
W O M.T
W
W .100 OM
.T
C W .C
.TW WW .100YPort Pin .
M .TW Alternate Function
W . 100
Y
M .TW
M W O W O
.CO .TW WW .100Y.PC7 C
.TW WW .100Y.C M.TW
ICP1/INT4/CLKO
.100Y M W O M W O
W O
WW .100Y.C M.TW WW .100YPC6 .C .T W WW .100Y.C M.TW
PCINT8/OC1A
W OM W O
W
WW .100Y.C M.TW
O
WW .100PC5 Y.C .T W WW .100Y.C M.TW
PCINT9/OC1B
W OM W O
W
WW .100Y.C M.TW
O
WW .10PC4 0Y.C M.TW PCINT10 WW .100Y.C M.TW
W O W O
W
WW .100Y.C M.TW
O
WW .10-0Y.C M.TW - WW .100Y.C M.TW
W O W O
W
WW .100Y.C M.TW
O
WW PC2 0 0 Y.C .T W PCINT11WW .100Y.C M.TW
W. 1 OM W O
W
WW .100Y.C M.TW
O
WW PC1 0 0 Y.C .T W WW .100Y.C M.TW
W. 1 OM Reset, dW W O
W
WW .100Y.C M.TW
O
WW PC0.100Y.C M.TW WW .100Y.C M.TW
W O XTAL2 W O
W
WW .100Y.C M.TW
O
W O WWconfiguration .CO is .as WW 00Y.CO .TW
WW .100Y.C M.TThe W alternate Wpin . 1 00Y M TW follows: W .1 M
W W .C O
W 00 Y .T W .1 M .1 M
W W.1 Y.COM • ICP1/INT4/CLK0,
W WWBit 070Y.CO .TW W WW 00Y.CO .TW
W
W 00 .T
W.1 Y.COMICP1,WInput Capture pin.11 :The OM pin can act as anWinput
.CPC7 W.1 capture OM
Y.C for Timer/Counter1.
WW Y W W 0 W
W W
. 1 00 M .T W
W .10 0
O M .T
W .1 0
O M.T
W OINT4, External Interrupt source 4 : The PC7 pin canW W as an
serve .C
Yexternal interrupt source to the
WW .100Y.C MCU. .TW WW .100Y.C M.TW .100 M.T
W
M W O W C O
W
WW .100Y.C M.TW
O
W
W O W C O
W O
CLK0, Clock Output : The PC7 pin can serve as oscillator
WW .100Y.C M.TW WW clock ouput Y. if the feature W is enabled by
WW .100Y.Cfuse.M.TW W .100 O M.T
W O C
W
WW .100Y.C M.TW
O
W
W O W C O
W
WW .100Y • .C
O
.TW 6 W Y.C .TW WW .100Y. M.T
W
PCINT8/OC1A,
M
Bit W
W .100 O M W C O
W O Pin Change Interrupt Y.C The .PC6 W as an Y . .TW source.
WW .100PCINT8,Y.C .TW WW source .100 8 : O M TW pin can W serve .100external Minterrupt
W O M W W W .C O
W .C 0Yexternal W
WW .10OC1A, 0Y.C Output M .TWCompare W 00Y The
Match A.1output: M TW pin canW
.PC6 serveW as.10an O M.T output for the
W O .C
W .CO .TWOutput Compare.
WW .Timer/Counter1 WW The Y.C Wconfigured Was W an output Y
.100 (DDC6
W
M.Tset “one”) to
1 00Y M W .100 pin has O M
to.Tbe
W C O
O
W serve this function. The OC1AW C output
.the W mode .
Ytimer function. W
WW .100Y.C M.TW W pin is.1also 00Y M .TW pin for theW PWM
.100 M.T
O W O W .C O
W
WW • .PCINT9/OC1B, .C .TW WW .100Y.C M.TW WW .100Y M.T
W
1 00Y M Bit 5 W O W .C O
W O WW
WW PCINT9, .C
00YPin Change .TW InterruptW
W
source 9: .10The0Y.CPC5M .TW
pin can serve as an external
Y
.100 interrupt
W
M.Tsource.
. 1 O M W O W .C O
W
WWOC1B, 0Y.C Compare .TW MatchW
W 0Y.C M.TW WW .100Y W
M.Tfor the
.1 0Output M B output:
W . 10The PC5O pin can serve as an W external O
output
C
WW 00Y.C Output O W .C W Y . .TWto
WTimer/Counter1
1 M .TWCompare.WThe pin . 1has M .TW
00Yto be configured as an Woutput .(DDC5
W 100 set O M“one”)
. O W O W .C
WWthis0function. Y.C TheW is W Y.C TWthe PWM W Y
.100function. M.T
W
serve
W
W .1 0 O M.T
OC1B pinW also the
W .100outputOpin M.for mode timer
W W .C O
Y
M.T
W
• PCINT10, W Bit.C 4O W O W W .C O
WW .1Pin 00YChange W WW .100Y.C M.TW W Y
.100 interrupt .TW
PCINT10, W O M.T Interrupt sourceW10 W : The PC4 C O pin can serve as an
W Wexternal .C OM
WW .100Y.C M.TW Y. W W .100
Y .TW
source.
W O
W
WW .100Y. C Y .TW
WW .100Y.C M.TW M.T
W W
W .100 OM
W O W C O W .C
• PCINT11,WW Bit 2 Y.C
.TW WW .100Y. M.T
W W .100
Y
W . 100 O M W C O W W
PCINT11,WPin Change Y.C Interrupt W source 11 WW : The PC2 Y.pin can.TserveW as anWexternal interrupt
source.
W
W .100 O M.T W .100 O M
WW .100Y. C
WW .100Y.C M.TW M.T
W
W O W C O
• Reset/dW, WWBit 1.100Y.C M.TW WW .100Y.
W O W
WW .100Y.C M.TW WW
W O
WW .100Y.C M.TW
W O
WW .100Y.C 77
W W
7799D–AVR–11/10 W
.C OM
00Y .TW
W W.1 Y.COM W
Reset, Reset input. External Reset
W .100 is active
Winput
.T
OM low and enabled by unprogramming ("1") the
W .C
RSTDISBL Fuse. M
W
.TPullup is
W
activated .
and
Y
100outputOdriver M .TW and digital input are deactivated when the
.C O W W Y .C W
Y
00 as the
pin is.1used T W
.RESET pin. W . 10 0 M .T
W O M W O
WW Y.C channel. W WW .100Y.C Enable W
M.T (DWEN) Fuse is programmed and Lock
.100
dW,WdebugWire O M.T When the debugWIRE W O
.TW 0Y.C M.TW the debugWIRE
W are 0unprogrammed,
Wbits WW .10system 0Y.C within M .TWthe target device is activated. The
M . 1 O W O
.CO .TW WW port
RESET .C configured
00Ypin is M .TW as aWwiredW -AND Y.C
100 (open-drain) .TW bi-directional I/O pin with pull-up
.100Y M
W
W . 1 O W . O M
W O enabled
WW and .C
becomes theWcommunication WW gateway Y.Cbetween .TW the target and the emulator.
WW .100Y.C M.TW . 1 00Y M .T W . 100 O M
WW 00Y.C O
W
WW .100Y.C M.TW
O
.TW WW .100Y.C M.TW
• WXTAL2, W . 1
Bit 0 O M W O
W
WW .100Y.C M.TW
O
WWOscillator.
XTAL2, 0 0 Y.CThe PC0 .T W
pin can serveWWas Inverting. 1 0 0Y.COutput W
M.Tfor internal Oscillator amplifier.
W . 1 O M W O
W
WW .100Y.C M.TW
O
W O W O
W
WW .100Y.C M.TW
O
W Table O relate the alternate WfunctionsOof Port C to the overriding signals
WW .100Y.C M.TW
W O Table 12-7 Wand .C12-8
WW .100Y.C M.TW shown inWFigure.112-5 00Yon page .T W
W OM 72. W O
W
WW .100Y.C M.TW
O
W O W O
W
WW .100Y.C M.TW
O
Table 12-7. Overriding W Signals
O for Alternate Functions W in PC7..PC4 O
W
WW .100Y.C M.TW
O
W O Signal W O PC6/PCINT8/ WW PC5/PCINT9/ .CO .TW
WW .100Y.C M.TName W WW .100Y.C M.T
PC7/ICP1/INT4/CLK0
W
OC1A
W . 1
OC1B00Y M PC4/PCINT10
W W .C O
W 00 Y T
.PUOE 0 W .1 M0 0 .1 M 0
W 00 .T W .1 M .1 M
W W.1 Y.COMPUOVW 0
WW 00Y.CO .TW
0
W W0W 00Y.CO .TW 0
W 00 .T W . 1 M . 1 M
W.1 M
ODDOE 0 W O0 0W O 0
WW .100Y.C DDOV .T W WW .100Y.C M.TW WW .100Y.C M.TW
OM 0 W 0O 0 W O
WW .100Y.C M.TW
W 0
W PVOE
O 0 W O ENABLE
OC1A OC1BWWENABLE .CO 0.TW
W W .C O
PVOV
W
0 WW 00YOC1A .CO .TW OC1B
W WW 00Y.CO 0 .TW
W 00 Y .T W .1
W.1 Y OM INT4 ENABLE WW.
1 M WW OM
DIEOE
.C Y .CO ENABLE
PCINT8 W PCINT9
W ENABLE 0 Y.C PCINT10 W ENABLE
W W
. 1 00 M .T W W
W .10 0
O M .T
W .1 0
O M.T
W O 1 WW .C
WW .100Y.C M.TW
DIEOV 1 WW .1010Y.C M.TW .100
Y 1 .TW
W O W OM
W DI Y.CO INT4 INPUT WW PCINT8Y .C INPUT W PCINT9 W INPUT 00Y.CPCINT10
W W
INPUT
W W
.1 00 M .T W
W .10 0
O M .T
W . 1 O M.T
W O WW .100Y – .C
WW .AIO 00Y
.C – TW
. WW –.100Y.C M.TW – M.T
W
1 O M W O W .C O
W
W
O W O W .C O
Table
W
WW .100Y.C M.TW
12-8. Overriding Signals for Alternate
WW .100Y.C M.TW
Functions in PC2..PC0WW .100Y M.T
W
O W O W .C O
WW Name
WSignal .C
W
.1 00Y MPC2/PCINT11 W PC1/RESET/dWO W
PC0/XTAL2 .C O
W O W
WWPUOE.100Y.C 0M.TW WW .100Y.C M.TW W .100
Y
M.T
W
W O W 0 O 0 W W .C O
Y
M.T
W
PUOV W 0O W 0 O 0 W W .C O
Y
M.T
W
DDOEW O W O W W .C O
WW .100Y.C M.TW
0 0 0 Y W
WW .100Y.C M.TW W
W .100 O M.T
W O W C O W .C
DDOV
WW .100Y.C M.TW
0
WW 0 .100Y. M.T
W 0 W
.100
Y .TW
W O W C O W W .C OM
PVOEW 0Y.C W WW0 .100Y. M.T
W 0 W
.100
Y .TW
W
PVOV W 0 Y.C W WW 0 Y. W 0 W .100
Y
W
W .100 O M.T W .100 O M.T W W
DIEOEWW Y.C ENABLE
PCINT11 W W0W .100Y. C W 0 W
W .100 O M.T W O M.T
DIEOV WW 1 0Y.C W 0 W Y. C W0
W .10 O M.T
W
W .100 O M.T
Y.CINPUT.TW –WW Y. C
DI WW PCINT11 .100 M .100 –
W .C O W W
AIO W
W – .100Y .TW – W –
W W .C OM
W 00Y .TW
W W.1 Y.COM
W 00
W W.1 78
7799D–AVR–11/10 W
.C OM
00Y .TW
W W.1 Y.COM W
W 00 .T
12.3.3 Alternate Functions of Port D W W.1 Y.COM W
.TW W 00
W.1 areYshown
.T
OMin Table 12-9.
The Port D pins
C OMwith alternate functions W .C
1 00Y
.
M .TW W . 100 M .TW
.
W 12-9. O W O
WWTable .C Port .D TW Pins Alternate WWFunctions Y.C .TW
. 1 00Y M W . 100 O M
W O
.C Alternate W .C
M .TW WWPort.1Pin 00Y M .TW FunctionW W.100Y OM.TW
W O
.CO .TW WW PD7.100Y.CHWB/TO/INT7/CTS .TW WW .100Y.C M.TW
.100Y M W O M W O
W O
WW .100Y.C M.TW WWPD6 .100Y.C INT6/RTS .T W WW .100Y.C M.TW
M W O
W O
WW
W .CO .TW (USART1 WW 0Y.CInput/Output).TW
WW .100Y.C M.TW PD5
. 1 0 0 YXCK1/PCINT12
M External
W . 1 0
Clock
O M
WW 00INT5 O
W
WW .100Y.C M.TW
O
WPD4 Y.C .TW WW .100Y.C M.TW
W . 1 O M W O
W O W Y.C WWInput.1or Y.C .TW Pin)
WW .100Y.C M.TW W
PD3 . 1 0 0
INT3/TXD1 M .T W Interrupt3
(External
W
0 0USART1
O MTransmit
O W O Y.C
W
WW .100Y.C M.TW PD2 00Y
.C
WW .1INT2/AIN1/RXD1(External .TW WW Input
Interrupt2 .100 or USART1
W
M.T Receive Pin)
W O W O M W W .CO
WW .100Y.C M.TW WW INT1/AIN0 Y.C (External .TW Interrupt1WInput)W.100Y OM.TW
PD1
W . 100 O M
W
WW .100Y.C M.TW
O
W W 0 0 Y.C .T W WW .100Y.C M.TW
PD0 W . 1
INT0/OC0B O M
(External Interrupt0 Input)W O
W
WW .100Y.C M.TW
O
W O WWconfiguration .CO is .as WW 00Y.CO .TW
WW .100Y.C M.TThe W alternate Wpin . 1 00Y M TW follows: W .1 M
W W .C O
W 00 Y .T W .1 M .1 M
W W.1 Y.COM • HWB/TO/INT7/CTS
W WW, Bit070Y.CO .TW W WW 00Y.CO .TW
W 00 .T W M can serve as WW.1
W.1 Y.COMHWB,WHardware Boot .1 PD7Opin OM
WW: The Y .C W W 0 Y.C W
W W
. 1 00 M .T W
W .10 0
O M .T
W .1 0
O M.T
W OTO, Timer/Counter0Wcounter source. Y.C WW .100Y. C W
WW .100Y.C M.TW W . 100 M .TW W O M.T
O W O Y.C
W
WW .100Y.C INT7, .TW
External Interrupt WW source .CThe PD7
Y7: .TWpin can serve WW as .an 100external
W source to the
interrupt
M.T
M W . 100 O M W C O
W
WW .100Y.C M.TW
O
MCU.
W
W O W C O
W CO USART1 WW Flow .C TW pin can W Y.
W the00transmitter W
WW .100Y.CTS, M .TW
Transmitter
. 100
YControl.
M .This control
W .1 O M.Tin function of its
W O C
W state.
WW .100Y.C M.TW
O
W
W O W .C O
W .CO .TW
WW .100• YINT6/RTS WW .100Y.C M.TW WW .100Y M.T
W
M ,Bit 6 W O W O
W O .C W Y .C W
WW .10INT6, 0Y.CExternal .TWInterrupt source WW 6:.1The 00Y PD6 pin M
W serve asWan
.Tcan .100 interrupt
external M.Tsource to the
M W O W .C O
W
WW .MCU. .CO .TW WW .100Y.C M.TW WW .100Y M.T
W
1 00Y M W O W .C O
W O Y.C can W Y W
WW RTS, .C
00YUSART1 W
.TReceiver Flow WW Control.
. 100This pin M .TW control theW receiver .1in00function Mof.Tits state.
. 1 O M W O W .C O
W
W
O W O W .C O
W
• XCK1/PCINT12, Bit 5
W
XCK1, USART1 O External Clock : TheW data directionO register DDRD5 W
controls C
whether
. O the clock
W
WWis output 0 Y.C .T W WW .100Y.C M.TW WW .100Y M .TW
.1 0 (DDRD5 M set) or input (DDRD5 W cleared). The
O XCK1 pin is active W
only when O
the USART1
WW 00inY.Synchronous
Woperates CO
.T W Mode. WW .100Y.C M.TW WW .100Y.C M.TW
. 1 M W O W O
PCINT12,W.1 Pin Change M Interrupt source 12: The PD5 pin can serve asWan W external O
interrupt
.CO WW 00Y.CO .TW W 0Y.C W
W W
source. .10 0 Y
M. T W W
W .1 O M W . 1 0
O M.T
W O W .C
Y .TW
W O W C O W W .C OM
WW .100Y.C M.TW
• INT5 , Bit 4 WW .100Y. W W
Mas.Tan external interrupt .100
Y .TW
INT5, External W Interrupt O source 5: The PD4 W
pin can C
serveO W W source .C OM
to the
W W .100
Y .TW
MCU. W O W C O W W .C OM
W W .100
Y
W O W C O W W
• INT3/TXD1 WW , Bit 3 Y.C W WW .100Y. M.T
W W
W .100 O M.T W C O
INT3, ExternalWW Interrupt Y.Csource.T3: WThe PD3W pinWcan serve Y. as an externalW interrupt source to the
W . 100 O M W .100 O M.T
MCU. WW .100Y. C
WW .100Y.C M.TW
W O W
WW .100Y.C M.TW WW
W O
WW .100Y.C M.TW
W O
WW .100Y.C 79
W W
7799D–AVR–11/10 W
.C OM
00Y .TW
W W.1 Y.COM W
W 00 .T
TXD1, USART1 Transmit Data W W.1 the
: When .C OM
USART1 Transmitter is enabled, this pin is config-
ured as an ouput .T W
regardless
WDDRD3.
of . 1 0 0Y M .TW
OM W O
0 0 Y.C .T W WW .100Y.C M.TW
.1 OM , Bit 2 W O
WW• WINT2/AIN1/RXD1
0 Y.C .T W WW .100Y.C M.TW
1 0
.
WW External OM WW CO serve
.T W WINT2, 0 0 Y.C Interrupt .T Wsource 2:W The PD2 pin
. 1 0 0Y.can M .TW as an external interrupt source to the
M MCU. W . 1 O M W O
100Y O
W . O M AIN1, W .C O WWThis00pin Y.Cis directly
WW .100Y.C M.TW WW Analog . 1 0 0 YComparator
M .T WNegative W input.
. 1 M .TWconnected to the negative input of
the Analog W Comparator. O W O
W
WW .100Y.C M.TW
O
W O RXD1,W W .C O WW CO
0Y.Receiver
WW .100Y.C M.TW W USART1 . 1 0 0 YReceive
M .
Data
T W : WhenW the USART1
. 1 0 is enabled, this pin is configured
W
M.Tthis pin to be an input, the pull-up
as an input W regardless O of DDRD2. When the W USART O
forces
W O
WW .100Y.C M.TW can still WW Y.C W WW .100Y.C M.TW
be W . 100
controlled by
O M
the .TPORTD2 bit. W O
W
WW .100Y.C M.TW
O
W O W O
W O
WW .100Y.C M.TW • INT1/AIN0 WW, Bit.1100Y.C M.TW WW .100Y.C M.TW
W O W O
Y.Csource.T1:WThe PD1 W
W
pinWcan serve COan external
0Y.as W interrupt source to the
WW .100Y.C M.TW
INT1, External WW Interrupt . 1 0 0 M . 1 0 M.T
W O W CO
W
WW .100Y.C M.TW
O MCU.
W
W O W C O
W O
WW Y.CPositive Wis directly Y. connected W to the positive input of
WW .100Y.C M.TAIN0, W Analog Comparator
. 100 M .TWinput. ThisW pin
W .100 O M.T
W O C
W
WW .100Y.C M.TW
O the Analog Comparator.
W
W O W C O
W O
WW .100Y.C M• .TINT0/OC0B
W ,W
W
Bit 0 .100Y
W
W O M W C O
W O
WW .100Y.C INT0, .TWExternal Interrupt WW .source Y.C W pin canWserve W 0Y.external
.10an
W
M.Tinterrupt source to the
M W 100 0:OThe M .TPD0 W as
C O
W
WW .100Y.C MCU.
O
W
M W O W C O
W O
WW Match Y.C WW Y. .TW output for the
WW .100Y.C OC0B, M .TW Output Compare . 100 B output: M .TW The PD0 pin .100 as an
can serve
W O Mexternal
O W O Y. C
W
WW .100Y.CTimer/Counter0
.TW OutputWWCompare. Y.C The pin.T W to be configured
has WW .as 100an output TW set “one”) to
M.(DDD0
M W .100 O M W C O
W O this function. TheW
serve .Calso the forW . timerWfunction.
WW .100Y.C M.TW W OC0B.1pin 00Y
is
M .TW
output pin W the PWM
.100
Ymode
M.T
W O W C O
W O
W
O W O W .C O
W Y.C 12-10
WW .100Table .TW
W Y.C .TW functions WW Y
.10D0 to theOM .TW
M and Table W 12-11 relates
W .100 theOalternate M of Port
W C
overriding signals
W .C O W .C W W Y . W
WW .10shown
0Y in M Figure
.TW 12-5 on W page 72. 00Y .T W 00 .T
.C W W 00 .T
WW .100Y M.T
WW .100Y W W 00 .T W 00 .T
.C W W 0 .T
WW .100Y M.T
W W 00 .T 0
W.1 Y.COM W
WW .100Y W W 00 .T W 0 .T
.C W W 0
WW .100Y M .TW W
W . 100 O M .T W .10 O M.T
W O W .C
Y
M.T
W
W O W O W W .C O
Y
M.T
W
W O W O W W .C O
Y
M.T
W
W O W O W W .C O
Y .TW
W O W C O W W .C OM
W W .100
Y .TW
W O W C O W W .C OM
W W .100
Y .TW
W O W C O W W .C OM
W W .100
Y
W O W C O W W
W W
W O W C O
W
W O W C O
W O W
WW .100Y.C M.TW WW
W O
WW .100Y.C M.TW
W O
WW .100Y.C 80
W W
7799D–AVR–11/10 W
.C OM
00Y .TW
W W.1 Y.COM W
W 00 .T
W W.1 Y.COM W
Table 12-10.OM .TW
Overriding
W
Signals forWAlternate .100 OM
.T PD7..PD4
Functions
C W .C
1 00Y
.
M
W
.TPD7/T0/INT7/ W . 100
Y
M .TW
W . O W
PD6/INT6/ O
WWSignal 0Y.C M.HBW/CTS TW WW RTS .100
Y.C PD5/XCK/PCINT12
.TW
. 1 0Name W O M PD4/INT5
W W .C O W Y .C W
.TW W PUOE.100 Y CTS.T W W RTS W.1 0 0 0 M .T 0
C OM W W .C OM W Y .CO .TW
Y. W W 0 Y W W 0 0
00
W.1 Y.COM W
.T .10 M.T
PORTD7 •
0 WW
.1 OM
W W WW 00Y.COPUD.TW
PUOV
W 10 0 Y.0C .TW
0
W .100 M .T W . 1 O M W . O M
W
WW .100Y.C M.TW
O
WW .100Y.C CTS
DDOE .TW RTS WW .100Y0.C M.TW 0
W O W O M W W .C O
W .C Y W
WW .100Y.C M.TW W
DDOV Y
.100 0 OM.T
W 1 W 000
W.1 Y.COM W
.T 0
W .C O W W Y .C W W 0
W Y W W 0 .T W .1 0 .T
W 00 .T 10 OM
RTS M
W W.1 Y.COM W PVOE WW. 0Y 0 .C W OUTPUT W WW XCK 0 0 Y .CO .TENABLE
OUTPUT W 0
W 00 .T W . 10 M .T .1 M
. 1 M W O W O
WW .100Y.C M.TW
W O ENABLE
W O W O
W O W 00Y.C WRTS WW XCK1 Y.C W
WW .100Y.C M.TW PVOV W . 1 0 M . T OUTPUT W . 1 0 0OUTPUT
O M.T 0
WW .100Y. W
M.T DIEOE
W 100
Y .TW W
W.1 Y
00
OM
.T
W O W .INT7/CTS
C OM INT6 W .C INT5
WW .100Y. C
.T W W W ENABLE
1 0 0Y .
M . W
TENABLE W PCINT12
. 100 ENABLE
M .TW ENABLE
W OM W . O W W . CO
C W . C Y W
WW .100Y. M.T
W
DIEOV W 1 .100Y .1TW W1 00
W.1 Y.COM W
.T 1
W C O W W . C OM W
WW .100Y. M.T
W W T0 INPUT .100
Y .TW W 00
W.1 Y.COM W
.T
W C O W W .C OM XCK W INPUT
WW .100Y. DI W
M.T
W INT7 .INPUT 100
Y INT6.TW INPUT W 100
W.INPUT OM
.T INT5 INPUT
W CO W
CTS W INPUT .C OM PCINT12
W Y .C W
WW .100Y. W Y W W 00 .T
W O M.T
W
C W .C
WW .100Y. AIO M.T
W W –
.100
Y – .TW – W 00
W.1 Y.COM W
.T –
W CO W W . C OM W
WW .100Y. TW
M.12-11.
W Y
.100 for Alternate .TW W 00
W.1 Y(1) OM
.T
W Table
C O Overriding W W
Signals .C OM Functions in
W PD3..PD0 .C W
WW .100Y. M .TW W . 100
Y
M .TW W
W .100 O M.T
W O C
W
WW .100Y.Signal CO
.TW WW .100Y.C PD2/INT2/RXD1/
.TW WW .100Y. .TW
MPD0/INT0/OC0B
M Name PD3/INT3/TXD1 W AIN1 O M W
PD1/INT1/AIN0 .C O
W
WW .100Y .CO .TW WW .100Y.C M.TW WW .100Y M .TW
PUOE O M TXEN1 W RXEN1 O 0 W .C O 0
W
WW .100PUOV Y.C .TW 0 WW .100Y.C M.TW WW .100Y M.T
W
O M W PORTD2 O • PUD 0 W .C O 0
W
W
DDOE O TXEN1 W RXEN1 O 0 W .C 0O
W
W
O W O W .C O
W DDOV
WW .100Y.C M.TW
1
WW .100Y.C M.TW
0 0 WW .100Y 0 M.TW
WPVOE Y.C O TXEN1 W
W 0 00Y.C O
W 0 W WW 00YOC0B .CO ENABLE W
W W
. 1 0 0 M .T W W
W .1 O M .T
W . 1 O M.T
W O WW .100OC0B .C
WW .100Y.C M.TW
PVOV TXD1 WW 0 .100Y.C M.TW 0 Y
M.T
W
W O W O W W .C O
WWDIEOE .C .TW
WINT2 ENABLE Y.C .TW INT1 ENABLE W .10INT00Y M.T
W
. 1 00Y MINT3 ENABLE W
W . 100 O M W ENABLE
C O
W O W .
WW .100Y.C M.TW W
AIN1 ENABLE AIN0 ENABLE Y
WW .100Y.C M.TW W
W .100 O M.T
W O W O W .C
WW .100Y.C M.TW
DIEOV 1 W ENABLE
WAIN1 Y.C AIN0
W ENABLE W 1 00Y
M.T
W
W O W .100 O M.T W W .1
.C O
DI W Y.CINT3 INPUT W INT2W INPUT/RXD1 Y.C W INPUT W
INT1 INT0
.100
Y
INPUT .TW
W
W .100 O M.T
W
WWINPUT Y. C WINPUT W – .100Y .TW
WW .100Y.C
AIO –
M.T
W AIN1
.100 M.T
AIN0
W OM
W O W C O W .C
Note:WW1. When .C
0Yenabled, theW 2-wire Serial W
WInterface Y. Slew-Rate
enables .TW controlsW on the output Y
.100 pins PD0 .TW
W .10PD1.
and O
This Mis.T not shown in this table.W .1In00addition, O M
spike filters are connectedW W between .C OM
the
.C WW 0Y. C W Y
WW AIO.1outputs 00Y shown W
M.Tin the port figure.WW.10 O M.T
W
W .100
W O Y. C W
WW .100Y.C M.TW W .100 M.T
W W
W O W C O
W
W O W C O
W O W
WW .100Y.C M.TW WW
W O
WW .100Y.C M.TW
W O
WW .100Y.C 81
W W
7799D–AVR–11/10 W
.C OM
00Y .TW
W W.1 Y.COM W
W 00 .T
12.4 Register Description for I/O-Ports W W.1 Y.COM W
.TW W 00
W.1 Y.COM W
.T
.C OM W
Y W W 00 .T
12.4.1 MCUCR – MCU Control
W .100 Register O M.T W W.1 Y.COM W
WWBit .100Y .C 7 .TW 6 W 5 00 4 .T3
W.1 PUD
2 1 0
W C O M W .C OM
WW .100Y . .TW Y W
W 100 .T
0x35 (0x55) JTD – – – – IVSEL IVCE MCUCR
M .TW O M W . O M
.CO .TW WW 00Y.C
Read/Write R/W
.TW0
R
W
R W R/W
1000
Y.C R
.TW 0
R R/W R/W
.100Y M
WInitial Value . 1 0
O M 0 W . O M0 0 0
W W Y .CO
W W WW 00Y.C W W W 0 0 Y .C .T W
W 00
W.1 Y.COM W
.T .1 M.T .1
WW 00Y.CO .TW
M
W • W BitW 4W – PUD: 0 Y .CO .Disable
Pull-up T W W
W 00 .T W.bit10 M .1 OM
W.1 Y.COM W When W this is0Y .CO to.Tone,
written W the pull-upsW WWin the 0 Y.Cports .are
I/O Wdisabled even if the DDxn and
W W
.1 00 M .T PORTxn
W
W . 10
Registers are O Mconfigured to enable W
the
0
.1 pull-upsO({DDxn, M T PORTxn} = 0b01). See “Con-
W O
WW .100Y.C M.TW figuring WW Y.C W WW .100Y.C M.TW
the W .
Pin” 100on page O M68 .Tfor more details about
W this feature. O
W
WW .100Y.C M.TW
O
W O W O
WW 0PORTB
12.4.2
W 0
O
Y.C – Port .T W B Data Register WW .100Y.C M.TW WW .100Y.C M.TW
W.1 OM W O 4 W
W .CO 2 .TW 1
WW .100Y.C M.TW Bit WW 7.100Y.C 6 M.TW5 W 1300Y 0
W O W C O PORTB5 PORTB4WW .
PORTB3 Y.C
OM PORTB1 PORTB0 PORTB
C 0x05 (0x25) W PORTB7 .
PORTB6
W PORTB2 W
WW .100Y. W
M.T Read/Write
W R/W .100YR/W M.TR/W W
W .100 OM
.T
W O W C O R/W
W R/W
.CR/W R/W R/W
WW .100Y. C
.T W
Initial Value W
W 0 0Y0 . .T0W 0 W 0 .10
0 0 M.TW0
Y
0 . 1 M 0
W W .C OM
W 00 Y .T W .1 M .1 M
12.4.3 WDDRBW.1 –YPort .C OMB Data W Direction Register WW 00Y.CO .TW W WW 00Y.CO .TW
W 00 .T W .1
W.1 Y.COMBit W .1 6 M 3 W
OM 1
W W
7 WW
0 Y .CO 5 .TW 4 W W 0 02Y.C
.TW 0
W . 1 00 M .T (0x24) .10 M 1
DDB3 W. DDB2 COM
W O 0x04 DDB7 W DDB6 O
DDB5 DDB4
W . DDB1 DDB0 DDRB
WW .100Y.C Read/Write .T W R/WWW R/W . 1 0 0Y.C R/WM.TWR/W WR/W . 1 00Y
R/W M
R/W .TW R/W
W OM Value W0 O WW 000Y.CO 0 .TW 0
WW .100Y.C Initial . T W 0 WW
. 1 0 0Y.C 0 M.TW0 W0
.1 M
W W . C OM
W – Port 00 Y .T W 1 M .1 M
12.4.4 PINB
W W.1 BYInput . C OMPins Address WW. Y .CO .TW W WW 00Y.CO .TW
W 00 .T W W .10 5 0 1
M 4 2. 1 OM
W W.1 YBit .C OM 7
WW 00Y.CO .TW
6 3
W WW 0Y.C TW
0
W 0 0 0x03 (0x23).T W PINB7 W PINB6 .1 PINB5 M PINB4 PINB3 PINB2.1 0 PINB1 M.PINB0 PINB
W W.1 Y .C OM WW 0R/W Y .CO R/W.TW R/W WW W
0 Y .CO .R/W T W
W 00 Read/Write
.T W R/W W R/W 0 R/W
.1 0 R/W
W.1 Initial OM .1
N/AWW N/A .CO N/A
M WW 00N/A OM N/A
. C Value N/A
Y W N/A
W N/A Y.C W
W W
. 1 00 Y
M .T W W
W . 10 0
O M .T
W .1 O M.T
WW 0Data O WW .100Y .C
12.4.5 PORTCW– Port .C 0Y.CRegister .TW WW .100Y.C M.TW M.T
W
W 1 O M W O W W .C O
WW .Bit .C .T7W
W
5.100
Y.C 4 .TW3 W .1100
Y
0M.
TW
1 00Y M 6 W
W O M 2
W .C O
W O W Y.C WW PORTC1 Y W
WW 0x08 . 1 0Y.C M
0(0x28) .TW PORTC6W PORTC5
PORTC7
. 100 PORTC4 M .TW - PORTC2
W .100 PORTC0 O M.TPORTC
WRead/Write O W .C O R/W WW R/W 0Y R/W .C W
WW Initial 0Y.C M0.TW
0Value
R/W R/W
WWR/W .100YR/W M .TW
R
.10 M.T
. 1 O 0 0W 0 O 0 0 W 0 .C0 O
W
W
W O W O W W .C O
12.4.6 DDRC – PortW CW Data Direction 00Y
.C Register .TW WW .100Y.C M.TW W .100
Y
M.T
W
WW 00Y.C 7 .TW 6 5W 4 Y.
C 3 TW 2 W1 .1000
Y
M.T
W
WBit
W . 1 O M
W
W .100 O M. W W .C O
DDC4 Y.C - W
W
0x07W(0x27) 00Y.DDC7 C
.TW
DDC6 DDC5 W
W .100 M.T R/W
WDDC2 WDDC1
00Y DDRC
DDC0
.1R/W M.T
Read/Write W .1 R/WOM R/W R/W W R/W O
R R/W W W .C O
WWValue .100Y.C W 0 W
W
0.100
Y.C 0 W W .1000
Y .TW
Initial
W
0
O M.T0 W O M.T 0 0
W W .C OM
WW .100Y. C Y .TW
WW .100Y.C M.TW M.T
W W
W .100 OM
W O W C O W .C W
12.4.7 PINC – Port C Input Pins
WW .100Y.C M.TW
Address WW .100Y. M.T
W W .100
Y
M.T
W O W C O W W .C O
Bit
WW
7 .C
00Y
6
W 5 WW4 .100Y3 . .2TW 1 W 0 .100Y
0x06 (0x26) W.1 PINC7 O M.T PINC5
PINC6 PINC4W
W - COM
. PINC2 PINC1 WPINC0W PINC
W W 0 Y .C T W W 0 0 Y .T W W
Read/Write
W.1 Y.CO
R/W0 R/W M. R/W R/W
WW N/A
.1 R M
R/W
.CO N/A .TW N/A
R/W R/W
Initial Value WW N/A 0 N/A .T W N/A WN/A 0 0 Y N/A
0
W W 00 .T W 00
W.1 Y.COM W W W.1
W W 00 .T W
W W.1 Y.COM W
W 00 .T
W W.1 Y.COM
W 00
W W.1 82
7799D–AVR–11/10 W
.C OM
00Y .TW
W W.1 Y.COM W
W 00 .T
12.4.8 PORTD – Port D Data Register W W.1 Y.COM W
.TW W
5W.
100 4 OM.T3
Bit OM7 6 2 1 0
.C
00Y PORTD7
0x0B.1(0x2B) .T
W
W PORTD6 WPORTD5 .10PORTD4 0Y.C M .TW PORTD2 PORTD1 PORTD0 PORTD
PORTD3
W OM WW 0R/W O
WWRead/Write 0 0 Y.C R/W .TW R/W WR/W . 1 0Y.C M R/W.TW R/W R/W R/W
W . 1 O M W C O
.C W Y . W
WW .100Y
Initial Value 0 0 0 0 0 0 0 0
M .TW M .TW W
W . 100 O M .T
WW 00Y.C O
.CO DDRD .TW– Port DW .TW WW .100Y.C M.TW
.100Y
12.4.9 M Data Direction. 1 Register
O M W O
W O WW 00Y.C7 WW 4.100Y.C 3 M.TW 2
WW .100Y.C M.TW W
Bit 1 M .T W6 5 1 0
W .C O W W. Y .CO DDD6 W WW 0 Y CO
.DDD3 W
W Y W W
0x0A (0x2A) 0DDD7 T DDD5 W DDD4 0 .T DDD2 DDD1 DDD0 DDRD
W
W .100 O M.T W .10 R/W OM.R/W W W.1 YR/W . C OM R/W
W . C W
WW .100Y.C M.TW
Read/Write R/W R/W R/W R/W
W 00Y W W 100 0 OM.T0
Initial Value W.1 O M.0T 0W.
0Y.C M.TW
0 0 0 0
W O W .C W
WW .100Y.C M.TW W 1 0 0 Y .T W W . 1 0
W. OM W O
WW 00Y
W12.4.10 .CO – Port
PIND .T WD Input Pins WWAddress 0 0 Y.C .T W WW .100Y.C M.TW
W. 1 OM O
W.1 OM W
W4W .1030Y.C M
WW .100Y.C M.TW Bit WW .7100Y.C 6 M.TW 5 2 .TW 1 0
W O W C O W W .C O
C 0x09 (0x29) W PIND7 . PIND6 PIND5
W PIND4 PIND3 Y PIND2 W PIND1 PIND0 PIND
WW .100Y. M .TW Read/WriteW W .
Y
100 R/WOM.T R/W
W
W 100
.R/W O M.T R/W
W O W
R/W
.C R/W
WW N/A Y. C R/W
W R/W
WW .100Y.C M.TWInitial Value W N/A .100Y N/A M.TN/A W N/A
W .100 N/A
O M.T N/A N/A
W Y . W W 0 Y T W W 0 0 .T
W 00
W.1 Y.COM W
.T .10 M. .1
WW 00Y.CO .TW
M
W W WW 00Y.CO .TW W
W 00 .T .1 M .1 M
W 00 .T W .1 M .1 M
W 00 .T W .1 M .1 M
W 00 .T W .1 M .1 M
W 00 .T W .1 M .1 M
W 00 .T W .1 M .1 M
W 00 .T W .1 M .1 M
W 00 .T W .1 M .1 M
W 00 .T W .1 M .1 M
W 00 .T W .1 M .1 M
W 00 .T W .1 M . 1 M
W 00 .T W .1 M . 1 M
W 0 0 .T W .1 M . 1 M
W 0 .T W 1
W.1
0
OM W.1 OM W. OM
W O W O
W
WW .100Y.C M.TW
O
W O W O
W
WW .100Y.C M.TW
O
W O W O
W
WW .100Y.C M.TW
O
W O W O
W
WW .100Y.C M.TW
O
W O W O
W
WW .100Y.C M.TW
O
W O W O
W
WW .100Y.C M.TW
O
W O W O
W
WW .100Y.C M.TW
O
O W O W
W
W O W O
W O W O
W O W
WW .100Y.C M.TW WW
W O
WW .100Y.C M.TW
W O
WW .100Y.C 83
W W
7799D–AVR–11/10 W
.C OM
00Y .TW
W W.1 Y.COM W
W 00 .T
13. External Interrupts W W.1 Y.COM W
.TW W 00
W.1 Y.COM W
.T
.C OM W
Y W W 00 .T
WW .C W
TheW External
Y
.100 Interrupts O M.T are triggeredW
W
byWthe.100INT[7:0] OM
.T
pin or any of the PCINT[12:0] pins. Observe
C .C
.TW
W
Wthat, if .enabled,
1
.
00Y theMinterrupts .TW will WtriggerWeven .
Y
100 if theOINT[7:0] M .TW or PCINT[12:0] pins are configured
M W O Y.C a software
.CO .TW asW Y.C feature
00This .TW provides aW
W
100 .TW
.100Y M
W outputs.
W . 1 O M way of generating
W .
.C O M interrupt.
W O .C W Y W
WW .100Y.C M.TW WW Y
.100 interrupt
W
M.T PCI0 will trigger
W if any 00 .T
W O
The Pin change
W C O W W.1 enabled . C OMPCINT[7:0] pin toggles. PCMSK0 Reg-
WW .100Y.C M.TW WW
ister control 1 0which
.
0Y pins M .TW
contribute to W the pin change .
Y
100 interrupts. M .TW The Pin change interrupt PCI1
. O W O
W O WWif any .C WWtoggles. Y.C W
WW .100Y.C M.TW will W trigger
. 100
Yenabled
M
PCINT[12:8]
.TW pin
W .100
PCMSK1
O M.T
Register control which pins contrib-
W O ute to the
W W pin change.C O interrupts. Pin W
change .C
interrupts
Y on
W PCINT[12:0] are detected
WW .100Y.C M.TW asynchronously. W .
Y
100This O M
implies
.TW
that these
W
W
interrupts .100can be O M .T
used for waking the part also from
W
W O
WW .100Y.C M.TW sleep modes WW other 0 0 Y.C .T W WW .100Y.C M.TW
W. 1 than Idle
OM mode. W O
W O
WW .100Y.C M.TW The External WW .100Y.C M.TW WW .100Y.C M.TW
Interrupts
W can O be triggered by a falling W or risingOedge or a low level. This is set up
W O
WW .100Y.C M.TWas indicated WWin the 0 0 Y.C .T W WW .100Y.C M.TW
W. 1 specification M for the External Interrupt Control Registers – EICRA (INT[3:0])
W W .C O
W W Y .CO .TW W WW 00Y.CO .TW
W 00 Y .T and EICRB (INT[7:4]). W 0
.10 When Mthe external interruptWis.1enabledOand M is configured as level trig-
W.1 Y.COM gered, WW will Y .CO as.Tlong W W Wis held0low. 0 Y.CNote that W
W W
. 1 00 M .T W the interrupt
W
W . 10 0 trigger
O M
as the pin
W .1 O M.T recognition of falling or
W O rising edge interrupts .C WW .1of C
. I/O clock, Wdescribed in “System
WW .100Y.C M.TW WW .1on 00Y
INT[7:4]
M
requires
.TW the presence 00Y an
M.T
Clock and Clock W
Options” on O
page 26. Low level interrupts W and C
the O edge interrupt on INT[3:0] are
W O
WW .100Y.C Mdetected .TW asynchronously. WW .100This Y.C .T W WW .100Y. M .TW
M .CO
W O
WW
W
0Y.IdleCimplies
O that these interrupts W canYbe
WW is halted
used for waking the part also
.TW modes except Idle
WW .100Y.C from M .T Wsleep modes other .1 0
than mode.
M .TWThe I/O clock
W . 1 00 in allM
O sleep
W O C
W
WW .100Y.C mode.
O
W
M W O W C O
W
WW .100Y.C Note
O
TW if a levelW
W 0Y.C M TW for wake-up
is .used WW from 0Y.
.10Power-down,
W
M.T the required level
M .that triggered
W . 10interrupt O W C O
W O
WW for 0Y.C
W Y. .TW
WW .100Y.CmustMbe .TW held long enough .10the MCUMto.Tcomplete W theWwake-up
W .100to trigger O Mthe level interrupt. If
W C O W W . C O W Y .C W
WW .100Y. the level
M .TW
disappears before
W the
. 100
end
Y of the
M .TW
Start-up Time, W the MCU
W .100
will still
O
wake
M.T up, but no inter-
W O Y. C
W
WW .100Y .COwill be
rupt
.TW
generated. The
WW .100Y.C M.TW
start-up time is defined by theWSUT W and0CKSEL
.1 0
Fuses
M.T
Was described
in “System
O M Clock and Clock Options”
W on O page 26. W .C O
W
W
W O W .C O
WW
W .CO .TW WW .100Y.C M.TW WW .100Y M.T
W
13.2 Register . 1 00Y
Description M W O W .C O
W O WW .100Y
W
O W O W .C O
13.2.1 W
EICRA – External
WW .10Interrupt0Y.C MControl .TW
Register WWA .100Y.C M.TW WW .100Y M.T
W
O
WThe External Interrupt Control Register W O W W .C O
WW .10A0Ycontains .C control bits for Winterrupt sense
Y control. W
WBit O W O 2 WW 1 .C
WW .100Y.C M.TW
7 6
WW 5 .100Y.4C M.T3W Y 0
.100 ISC00OMEICRA .TW
W
(0x69) O ISC31 ISC30 ISC21W ISC20 O ISC11 ISC10 W W
ISC01 .C
WWRead/Write .C .TW R/W W R/WW.100R/W
W Y.C .TW R/W W R/WW.100YR/W OM.TW
. 1 00Y MR/W
O M R/W
.C
W O WW0 .100Y
WW Initial Value0Y.C
0 0 .TW 0 WW 0
. 1 0 00Y.C M0 .TW 0 0 M.T
W
Y
M.T
W
W O W O W W .C O
WW .100Y.C M.TW
• Bits 7:0 – ISC31, ISC30 – ISC00, ISC00: External Interrupt 3:0 Sense Control Y Bits W
WW .100Y.C M.TW W
W .100I-flag O M.T
The External W Interrupts
O 3:0 are activated W
by the external
.C O pins INT[3:0] if the W SREG .C and the
WW .100Yinterrupt .C TW in the EIMSK WW is.1set. 00YThe level W
M.Tand edges on the
W Y
.100 pins .TW
corresponding
W O M.mask W C O W W external . C OMthat
WW the.1interrupts .C .TW
W Y. W areWregistered
Y
.100 asynchro- .TW
activate
W
00Y
O Mare defined in W Table 13-1.
W .100 Edges O on.TINT[3:0]
M W W .C OM
.C WWthe minimum C
Y. pulse.Twidth W given W Y .TW
nously. WW Pulses0on
. 1 0
YINT[3:0]
M.T
W wider than
pins
W .100 O M in “External
W .100Interrupts OM
W O .C W Y .C
Characteristics”
WW .10on C
0Y.page 268W will generate WWan interrupt. 00Y Shorter M.T
Wpulses are Wnot guaranteed .100
to
generate W anW interrupt..CIfOlow M.Tlevel interrupt isW W.1 Ythe
selected, .C O
low level must be heldW Wuntil the com-
W W W
pletion W of the W currently
Y
.100 executing O M.T instruction toW
W .100 an interrupt.
generate
W O M.T If enabled, a level triggered
W Y.C interrupt W C
Y. pin is.T W
interruptW will generate .100 an O M.T request as W
W long.1as 00the M held low. When changing the
W W C O
WW Y.Coccur..T W Y. to first disable INTn by clearing its
ISCn bit, an interrupt00can
W .1 O M
Therefore, it Wis recommended
W .100
Interrupt Enable WW bit.in Y.C
the EIMSK T Register.
W Then,WWthe ISCn bit can be changed. Finally, the INTn
W 100 O M.
WW .100Y.C M.TW
W O
WW .100Y.C 84
W W
7799D–AVR–11/10 W
.C OM
00Y .TW
W W.1 Y.COM W
interrupt flag should be clearedW
W
by .100 a logical
Wwriting
.T
OM one to its Interrupt Flag bit (INTFn) in the
.C
EIFR Register M .TW the interrupt
before
W is re-enabled. . 100
Y
M .TW
W O
. 1 00Y M W O
W O
WW 0 0 Y.C .T W WW (1).100Y.C M.TW
Table 1
W. 13-1. O M
Interrupt Sense ControlW O
OM ISCn1 W ISCn0 O Description W O
0 anO
W.1 OM 0W 0 O The low level of INTn W
generates
WW .100Y.C M.TW
interrupt request.
0 W O Any edge of INTn generates W asynchronously O
WW .100Y.C M.TW
W O 1 an interrupt request.
W 0 O W C O
W O 1
WW .100Y.C M.TW
The falling edge of INTn
WWgenerates Y.asynchronously W an interrupt request.
WW .100Y.C M.TW W .100 O M.T
O W O Y.C
W
WW .100Y.C M.TW
1 W 1 Y.CThe risingW edge of INTn WW generates0asynchronously
.10 M.T
W an interrupt request.
W
W . 100 O M .T W O
W
WW .100Y.C M.TW
O Note:
W1.W nWhen = 3, 2, Y
0 1or.C 0. .TW WW .100Y.C M.TW
W . 10changing O M
the ISCn1/ISCn0 bits, the Winterrupt O be disabled by clearing its Interrupt
must
W O
WWEnable Yin.Cthe EIMSK WW .1an00interrupt Y.C can.Toccur W when the bits are changed.
WW .100Y.C M.TW . 1 0 0
bit M . T WRegister. Otherwise
W O M
W O C
W
WW .100Y.C M.TW
O
W
W O W C O
WW
W Y.C
O
W WW .100Y.C M.TW WW .100Y. M.T
W
100 –O
13.2.2 W.EICRB M.T Interrupt Control
External W Register O B W C O
WW .100Y.C M.TW WW .100Y.C M.TW WW .100Y. M.T 1
W
W O Bit W
7 6 O 5 4 W W3 .C2 O 0
WW .100Y.C M.T(0x6A) W WW ISC71 .10 ISC70
0Y.C MISC61 .TW ISC60 W ISC51 . 1 00Y M TW
.ISC41
.CO .TW
W ISC50 ISC40 EICRB
W W Y.C O
W W WW 0R/W 0 Y .CO R/W .T W W W 0 0 Y
W 00 .T W.1 0Y.COM 0 W 0
W.1 Y.COMInitialW .1 OM0
0WW 0 Y.C W W
W Value
W 0 .T 0 W 0
00 .T
W
W .100 O M.T W .10
.C OM W W.1 Y.COM W
C W .TW External
WW .100Y. • M .TW7:0 – ISC71, W ISC70 Y
.10-0ISC41,
W 00 Sense
W.1 7:4
.T
OM Control Bits
W O Bits W C OM ISC40: Interrupt
W .C
C
WW .100Y. TheMExternal .TW
W
W [7:4] .
0Y activated .TWby the external W 0Y
.10INT[7:4] TWSREG I-flag and
if .the
Interrupts
W . 10are O M pins
W C O M
W O
WW .100Y.Cthe corresponding .TW WW .mask Y.C .TW is set. W
W 0Y.edgesMon
.10and .TW
M
interrupt
W 100 in the O MEIMSK The level
W C O
the external pins
W C O W .C W Y . W
WW .100Y. that activate
M .TW
the interrupts
W are
.
defined
100
Y in
M .TW
Table 13-2. The W value
W
on
.100
the INT[7:4]
O M.T are sampled
pins
W O .C
W
WW .100Y .CO detecting
before
.TWwill generate
edges. W If edge orYtoggle .C interrupt .TW WW pulses
is selected,
.100
Ythat last.T longer
W than one
clock M
period
W
an W .100
interrupt. O M
Shorter pulses are not W
guaranteed C Oto Mgenerate an inter-
WW .100rupt. Y.C Observe .TW that CPUWclock .100
frequency M
can .TbeW
lower than theWXTAL frequency M.T if the XTAL
W O M W O W .C O
0Y.C is M
WW .10divider .TW If low W
W Y.C .TW the low W .10be 0Y held until W
M.T the comple-
enabled. level interrupt
W . 100 is selected, O M level mustW C O
W .CO currently Y.C WW If .enabled, Y . .TWtriggered
WW .tion 00Yof the M .TW executing WW instruction .100 toOgenerate M .TW an interrupt. 100 aM level
1 O
W interrupt will generate an interrupt W W
W low. 00Y .C O
WW .100Y.C M.TW WW request Y.Cas long.Tas Wthe pin isW held
M.T
W
W . 100 O M W .1
C O
W O (1) Y.C WW .100Y . W
WW Table 00Y
.C
13-2. .TW
Interrupt Sense WW Control . 100 M .TW M.T
. 1 O M W O W .C O
W
WW ISCn1 .C .TW WW .100Y.C M.TW WW .100Y M.T
W
. 1 00Y ISCn0 M Description
W O W .C O
W O Y.C WW .100Y W
WW 0.100Y.C 0 M.TThe W low levelWofWINTn .generates 100 .TW request.
anMinterrupt M.T
W O W O W W .C O
WW 0 .100Y.C1 M.T W WW INTn Y.C W W 00Y M.T
W
Any logical change on W . 100 generates O M .T
an interrupt request W.1 C O
W O W .C W Y . W
WW 1 .100Y.0C MThe .TWfalling edgeWbetween 00Ysamples
.1two Mof
W
.TINTn generates
W
an W .100 request.
interrupt O M.T
W O W O W .C
WW1 .100Y1.C M W
.Trising WW .100Y.C M.TW W Y
.100 request. M.T
W
W O The edge between W two samples O of INTn generates an W W
interrupt .C O
Y .TW
W O W C O W W .C OM
Note: W 1. n = 7, Y.6,C5 or 4..TW WW .100Y. .TW W Y
.100its Interrupt .TW
W
W 100 changing
.When O M the ISCn1/ISCn0 W bits,W the interruptC O M
must be disabled by clearing W W .C OM
WW Enable Y.C TW Register. Y. W W 00Ychanged. .TW
W .100 bit inOthe M.EIMSK
W Otherwise
W .100an interrupt O M.Tcan occur when the W
bits
W .1are
.C OM
WW .100Y. C Y
WW .100Y.C M.TW M.T
W W
W .100
W O W C O W
W W
W O W C O
W
W O W C O
W O W
WW .100Y.C M.TW WW
W O
WW .100Y.C M.TW
W O
WW .100Y.C 85
W W
7799D–AVR–11/10 W
.C OM
00Y .TW
W W.1 Y.COM W
W 00 .T
13.2.3 EIMSK – External Interrupt Mask Register WW.1 .C OM
.T7 W Y W
M
W
W . 100 4 OM.T3
.CO .TW
Bit 6 5 2 1 0
WW Y.C
0INT4 TW
00Y
0x1D.1(0x3D) INT7 INT6 INT5 . 1 0 M .
INT3 INT2 INT1 IINT0 EIMSK
W W .C OM WW 0R/W Y .CO R/W W
Y W W 0 . T
W .100 .T
OM .1 OM0
WValue C 0WW 0 Y.C
.T W W WInitial
1 00 Y . 0
M .T W 0
W . 1 0 0 M .TW 0 0 0
M . O W O
.CO .TW WW 00Y.C W WW Request 100
Y.C .TW
.100Y M
W
• Bits 7:0
W . 1 – INT[7:0]:
O M .TExternal Interrupt W .
.C
7:0
O M Enable
W O .C is .written W .TW Register (SREG) is set (one), the
WW .100Y.C M.TW WW an .INT[7:0]
When 1 00Y bitM TW to oneWand the.1I-bit 00Yin the M Status
W O W O
W
WW .100Y.C M.TW
O
WW .100Y
corresponding .C
external .TW
pin interrupt isWenabled. W
. 0Y.CInterrupt
10The M .TW Sense Control bits in the External
W O W O M W W . C O
Interrupt W Control . C
Registers – EICRA and EICRB – defines
Y whether
.TW the external interrupt is acti-
WW .100Y.C M.TW W .
Y
100 or falling M .TW W
W .100Activity O M
vated on Wrising O edge or level sensed. on any of these pins will trigger an
W O
WW .100Y.C M.TW interrupt WWrequest 0 0 Y.C . T W WW .100Y.C M.TW
1
W. even OifM the pin is enabled asWan output. OThis provides a way of generating a
W O
WW .100Y.C M.TW software WW interrupt. 0 0 Y.C .T W WW .100Y.C M.TW
W. 1 OM W O
W
WW .100Y.C M.TW
O
W O W O
13.2.4W EIFR –OExternal Interrupt Flag
WW .100Y.C M.TW WW Register 0 0 Y.C .T W WW .100Y.C M.TW
. 1 M W 3 Y.CO2
W O WW7 00Y.C6O .TW5 4 W W1
WW .100Y.C M.TW0x1C (0x3C) W INTF7
Bit 0
W . 1 O M
W
W .100 INTF2 O M.T INTF1
W O INTF6
.C INTF5 INTF4 INTF3
WW R/W.100Y. R/W M.TR/W C W INTF0 EIFR
WW .100Y.C M.TW Read/Write WWR/W .100YR/W M
W
.TR/W R/W R/W
W O W O
W O
WW .100Y.C M.TInitial W Value WW0 .100Y0.C M.T 0W 0 WW 0 .100Y.C 0
M.T0
W 0
W O W C O W W .C O
C W . .TW Y W
WW .100Y. W
M• .TBits 7:0 – INTF[7:0]:
W 00Y
.1External Interrupt Flags 7:0WW.
W 100 OM
.T
W C O W W . C OM Y .C W
WW .100Y. When
M .TWan edgeW or logic . 00Y onMthe
1change .TWINT[7:0] W pin W
triggers .100 an interrupt
O M.T request, INTF[7:0]
O W O .C
W
WW .100Y.C becomes .TW set (one). WWIf the.1I-bit 00Yin SREG
.C .TandW the corresponding WW .100Y interrupt TW bit, INT[7:0] in
M.enable
M W O M W C O
W O
WW the.1MCU .C WW vector. Y. flag.T W
WW .100Y.C EIMSK, M .TWare set (one), 00Y will jump M .TW to the interrupt
W .100 The O M is cleared when the
W O W O Wcleared C
. writing.TaWlogical one to it.
WW .100Y.Cinterrupt .TW
routine is executed.WW .10Alternatively, 0Y.C M.Tthe W flag canWbe .100
Yby
M W O W OM
W W Y
These
.C O flags are alwaysW
W W
cleared when
0 Y .C INT[7:0] .T W are configured W W as level 0 0 Y.Cinterrupt. .TW Note that when
W . 1 00 entering M .Tsleep mode with the . 0
1INT[3:0] M
interrupts disabled, the W .1 buffersOM
input on these
W .CO .TW W
WW a logic Y.C
O
W WW .100Y. C W pins will be
.TINTF[3:0]
WW .100Y disabled. This may cause .1 0 0change M in .Tinternal signals which will set M
the flags.
W W .C OM
W WWSleep Y .CO .TW W WW 00Y.CO .TW
W 00 Y
See “Digital .T Input Enable W and .10 0 Modes” M on page 71 for more .1
information. M
W .1
13.2.5
W
PCICR – W Pin .100
WChange OM
Interrupt
.T
Control Register
.1
WW 00Y.CO .TW
M WW 00Y.CO .TW
M
Y .C W W W 1
W 00 .T .1 M . OM
W.1Bit Y.COM W7 6 WW 5
Y .CO4 .TW 3 W2 WW 1 Y.C
0 0 W
W W
. 1 0
(0x68)
0 M .T - -
W
W .
– 1 0 0
O
– M – – W . 1
PCIE1
0
O M.T PCICR
PCIE0
W .C O W R 00Y.CR WW R/W Y .C TW
WW Read/Write 1 00Y M .TRW R W . 1 M .TW R R
W .100 R/W M.
O
.
W Value O W O W 0 00Y 0 .C
WW Initial 00Y
.C .T0W 0 WW 0 .100Y.C 0
M .T0W 0 W
.1 M.T
W
. 1 O M W O W .C O
W
WW• Bit.11:0 .C .TW Pin Change WW .100Y.C M.TW WW .100Y M.T
W
00Y– PCIE[1:0]: M Interrupt
W Enable
O 1:0 W .C O
WW 00Y.C O W
WWhen the PCIE1/0 TWis set (one)
.bit WW andW the. 0Y.Cin the
10I-bit M TW Register
.Status W
(SREG)
Y
.100is set O(one), M.T Pin
W
. 1 O M O W W .C
WW interrupt Y.C 1/0 .is W WW .10on 0Y.any C W W .10pin0Ywill cause M.T an
W
WChange
W .100 O M T enabled. Any change W O M.T PCINT[12:8]/[7:0]
enabled
W W .C O
WW .1The
interrupt. .C .TW interrupt WWof Pin Y.C .TW Request W is executed .100
Y from .T W
00Y corresponding M W .100
Change
O M Interrupt
W .C O M the
W O C enabled
.are W Y .TW
WW .100Y.C M.TW
PCI1/0 Interrupt Vector. PCINT[12:8]/[7:0] WW .1pins 00Y M.T
W individually W by .the 100 PCMSK1/0
Register. W O W C O W W .C OM
W W .100
Y .TW
W O W C O W W .C OM
W W .100
Y .TW
13.2.6 PCIFR – Pin Change WInterrupt
W .100Flag RegisterO M.T W .C O W W .C OM
WW .1007Y.C M6.TW 5 W 4 .100Y3
W W W 0 .100Y
Bit
O W O M.T 2 1
W
0x1B (0x3B)W W - Y.C - W – W W– 0 –Y. C – TW PCIF1 WW PCIF0 PCIFR
W 0 .T 0
.1 R .
W .10R O M W C O MR
W0W .1000Y.
Read/Write R R R R/W R/W
WW .1000Y.C 0 M.TW 0 M .TW 0
Initial Value
W O W C O 0 0
W O W
WW .100Y.C M.TW WW
W O
WW .100Y.C M.TW
W O
WW .100Y.C 86
W W
7799D–AVR–11/10 W
.C OM
00Y .TW
W W.1 Y.COM W
• Bit 1:0 – PCIF[1:0]: Pin Change
W .100
WInterrupt O M.T1:0
Flag
W Y . C TW
When a logic M .TW on any
change
W . 100
PCINT[12:8]/[7:0]
W O M .pin triggers an interrupt request, PCIF1/0
0 Yset.CO .TW W
WSREG 0 0Y .C .TWbit in EIMSK are set (one), the MCU will
becomes 0 (one). If the I-bit in 1
and
. the PCIE1/0M
W.1 Y.COM W W O
Y.Cflag is.T
WW jump to0the 0 corresponding.T Interrupt WWVector. . 1 0 0The M
W
cleared when the interrupt routine is exe-
W . 1 O M W C O
cuted. .C
Alternatively, the flag can be W
cleared by Y .
writing a W
logical one to it.
.TW WW .100Y M .TW W . 100 M .T
M O W O
.CO .TW WW 00Y.C .TW0 WW .100Y.C M.TW
.100Y
13.2.7 PCMSK0
M – Pin W Change . 1
Mask Register
O M W O
WW .100Y.C M.TW W . 1 M .T W
W .CO .TW
Bit 7 6 5 4 3 2 1 0
W W Y.C O
W W WW 0PCINT7 0 Y .CO PCINT6 T W W WPCINT4 0 0 Y
W
W .100 O M.T
(0x6B)
W .1 O M. PCINT5
W W.1 YR/W
PCINT3
. C OM
PCINT2 PCINT1 PCINT0 PCMSK0
W .C W
WW .100Y.C M.TW Y W W .100 0 OM.T0
Read/Write R/W R/W R/W R/W R/W R/W R/W
W
Initial Value W.
1000 O M0.T 0W
W O C W 0Y.C M.TW
0 0 0
W .
WW .100Y.C M.TW W 1 0 0 Y .T W W . 1 0
W. OM W O
W O
WW .100Y.C M.TW • Bit 7:0 WW– PCINT[7:0]: 0 0 Y.C Pin.T W
Change Enable WWMask . 1 0 0Y.C M.TW
7:0
W. 1 M W O
W O
WW .10bit .CO whether WW interrupt 0Y.C is enabled W
WW .100Y.C M.TW Each PCINT[7:0] 0Yselects M . T W pin change
W . 1 0
O M.T on the corresponding I/O
W O W O W is 0set, C
Y.pin change
WW .100Y.C M.TW
pin. If PCINT[7:0]WW .is 1 0Y.C
0set and the.T
M
PCIE0
W bit in W PCICR
.1 0 M.T
Winterrupt is enabled on the
W O W C O
W O corresponding I/O pin. If PCINT[7:0] is cleared,
WW .100Y.C M.TW WWpin change Y. interrupt W on the corresponding I/O
WW .100Y.C M.TW pin is disabled. W .100 O M.T
W O C
W
WW .100Y.C M.TW
O
W
W O W C O
W
WW PCMSK1 .CO .ChangeTW WW Y.C .TW WW .100Y. M.T
W
13.2.8
. 1 00Y – Pin M
Mask Register
W . 1001 O M W C O
W
WW .100Y.C M.Bit
O
TW W7W .1060Y.C M 5 .TW 4 WW3 .100Y2 . M.1T
W 0
W O W C O W W .C O
C (0x6C) - W - . -
.TW
PCINT12 PCINT11 Y
PCINT10 PCINT9 W PCINT8 PCMSK1
WW .100Y. M .TW W .1R00
Y
M
W
W
0
.10R/W O M .T
W O Read/Write R W O
R/W R/W R/W W Y. C R/W R/W
WW .100Y.C Initial W
.TValue 0W
W
0.100
Y.C 0 .TW 0 W .1000 M .TW 0
M W O M 0 W C O 0
W
WW .100Y.C M.TW
O
W
W O W C O
W
WW .100Y.C M.TW
• OBit 4:0 – PCINT[12:8]: WW Pin Y.C Enable
Change
.TW Mask 12:8 WW .100Y. M.T
W
W .100 O M W C O
W CO PCINT[12:8] WWis enabled . on the .corresponding
WW .100Y.C M.TW
Each bit selects whether pin change interrupt W I/O
WW .100Y.pin. .TW 00Y
.1change M T is enabled on
IfM PCINT[12:8] is set and
W the PCIE1 O bit in PCICR is set, W
pin C O
interrupt
W
WW .100Y .CO .TW W Y.C W WW .100Y. .TW
the corresponding
M I/O W pin. IfW .100
PCINT[12:8] O Mis.T cleared, pin change W interruptCon O Mthe corresponding
W W . C O W Y.C W W W 0 Y . .T W
W 00 Y
I/O pin is W
disabled.
.T W .10 0 M .T .1 0 M
. 1 O M W O W .C O
W
W
O W O W .C O
W
W
O W O W .C O
W
W
O W O W .C O
W
W
O W O W .C O
W
W
O W O W . C O
W
W
W O W O W W .C O
Y
M.T
W
W O W O W W .C O
Y
M.T
W
W O W O W W .C O
Y
M.T
W
W O W O W W .C O
Y .TW
W O W C O W W .C OM
W W .100
Y .TW
W O W C O W W .C OM
W W .100
Y .TW
W O W C O W W .C OM
W W .100
Y
W O W C O W W
W W
W O W C O
W
W O W C O
W O W
WW .100Y.C M.TW WW
W O
WW .100Y.C M.TW
W O
WW .100Y.C 87
W W
7799D–AVR–11/10 W
.C OM
00Y .TW
W W.1 Y.COM W
W
W .100 OM
.T
14. Timer/Counter0 and Timer/Counter1 W Prescalers Y .C
.TW
M .TW W
W . 100 O M
14.1 Overview . 1 00Y M W O
W O
. 1
Timer/Counter0 M 1 share the same
and Wprescaler O
module, but the Timer/Counters can have dif-
W WW 00Y.CO .TW
Wferent WW .1below 0 0Y.Capplies . W
Tto
.T prescaler
1 OMsettings. The description M all Timer/Counters. Tn is used as a
.C OM W W. Y .C W WW 00Y.CO .TW
Y W W 0 W
00
W.1 Y.COM W
.T general name,
.10 n = 0
M.T or 1. .1
WW 00Y.CO .TW
M
W W WW 00Y.CO .TW W
W .100 Internal .T .1 M .1 M
W W14.2 .C OM Clock
W Source WW 00Y.CO .TW W WW 00Y.CO .TW
W 00 Y .T W .1 M .1 M
W.1 Y.COM W WW 00Y.CO
The Timer/Counter can be W clocked directly W WWby the 0 Y .CO clock
system W (by setting the CSn[2:0] = 1).
W W
.1 00 M .T This
W
provides W . 1 the fastest O M .T
operation, with a W .1
maximum
0
O M.T
Timer/Counter clock frequency equal to
W O
WW .100Y.C M.TW system WW 0 0 Y.C .T W WW .100Y.C M.TW
clock 1
W.frequency O(fMCLK_I/O). Alternatively, Wone ofYfour Otaps from the prescaler can be used
W O
WW .100Y.C M.TW as a clock WW source. 0 0 Y.C The .T
prescaled W clock WW has a. 1 0 0 .C Mof
frequency .TW either f CLK_I/O /8, f CLK_I/O /64,
W . 1 O M W O
W W .C O W Y C
./1024. W W W 0Y .C .T W
W 00 Y W f
.T CLK_I/O /256,
W or f 10
CLK_I/O
. 0 M .T .1 0 M
. 1 M W O W C O
W
WW .100Y.C M.TW
O
W
W O W C O
14.3WWPrescaler .CO Reset .TW WW .100Y.C M.TW WW .100Y. M.T
W
W . 1 00Y M W O W C O
W O The prescalerWis free running, Y.C i.e.,Woperates W W
independently Y. of the.TClock W Select logic of the
WW .100Y.C M.TTimer/Counter, W W . 10is0 shared M .T W .100Since O M prescaler is not affected by
andW it O by the Timer/Counter Tn. C the
W
WW .100Y.C M.the
O
TWTimer/Counter’s WW clock Y.C .TWstate of the WW .100Y. TW
M.implications
W . 100 select, O M the prescaler
W will.Chave
O for situations
W W .C O W Y .C W W W 0 Y .T W
Y W W 0 T
. example of prescaling 0
W 00
W.1 Y.COMenabled
.T a prescaled clock
where .10is used. One
M
.CO .T(6 W.1 artifacts Moccurs when the timer is
.CO .of
WWby the Y W W W 0 Ynumber W
W W
. 1 00 M .T W and clocked
W
W .10 0 prescaler
O M
> CSn[2:0] > 1).
W
The
.1 0
O M T system clock cycles
W Ofrom when the timer WW can C
Y. from 1.T
WW .100Y.C M.TW WW is enabled . 0Y.C to the
10prescaler M .Tfirst
W count occurs .100
be
M
toWN+1 system clock
cycles, where N equals Wthe O divisor (8, 64, 256, W
or 1024). C O
W
WW .100Y.C M.TW
O
W
W O W C O
W ItOis possible to useW the Wprescaler 0Y.C reset forTsynchronizing WWthe Timer/Counter Y. toWprogram execu-
WW .100Y.C M.TW .10taken M . W W .100 O M.T
W O C
W
WW .100Y.also
tion.
CO However,
.T W
care must be
WW .100Y.C M.TW
if the other Timer/Counter WW .100Y. that shares
M
the
.TW
same prescaler
uses
M prescaling. A prescaler W resetOwill affect the prescaler Wperiod for all O Timer/Counters it is
W
WW .100Y .CO .Tto.
connected W WW .100Y.C M.TW WW .100Y.C M.TW
OM W O W O
W
W O W O
14.4 External WW
W
Clock Y.C
Source
0
O
0 .CO .T(clk
W.1 external .CO clock
M W .COpin can WW
W
00Y clock W Tn). The
WW .An 00Y .T W source applied WW to.10the 0YTn M .TWbe used as Timer/Counter
. 1 M
1 O M W O W .C O
W Tn pin is sampled once every W
WW .100Y.C M.TW W system 0Y.C cycle
clock
.by WW .100Y logic.M
TWthe pin synchronization The .TW synchro-
nized (sampled) signal is then W
passed . 10through O M
the edge detector. W
Figure 14-1 C
shows O a functional
W .C O W Y.C WW .100Y . W
WW equivalent
1 00Y block M
W
.Tdiagram of
Wthe Tn . 100
synchronization M .TW and edge detector W logic. The O M.T
registers are
W . O W W .C O W Y .C W
W
W clocked 0 Y .C W W 0 0 Y .T W W 1 0 0 .T
0 at the M .T
positive edge of the internal
W.1 Y system M clock (clkI/O). TheWlatch W. is transparent OM in the
W.1 Y.CofOthe W .CO .TW W 0 Y.C W
WWhigh .period
1 0 0 M .T W
internal system W clock.
W . 1 0 0
O M W . 1 0
O M.T
WWedge O Y.C W .C
WThe Y.C
00detector .TW
generates
W
oneWclkTn pulse 100 for each M .TW (CSn2:0
positive W = 7) or 0Y
.10negative M .TW
(CSn2:0
W . 1 O M W . O W W .C O
W=W 6) edge0it0Y .C
detects. W WW .100Y.C M.TW W .100
Y
M.T
W
Y
M.T
W
FigureW 14-1. Tn/T0 O Pin Sampling W O W W .C O
Y .TW
WW .100Y. Y W
WW .100Y.C M.TW M.T
W W
W .100 OM.T
Tn W O W C O W .C
WW .100Y. 0Y .TW
Tn_sync
WW .100Y.C M.TW
D Q D Q D W Q W
M.T 0Clock
.1(To
Select Logic) OM
W O W C O W W .C
WW .100YLE .C W WW .100Y. M.T
W W .100
Y
W O M.T W C O W W
WclkW .100Y.C M.TW I/O WW .100Y. M.T
W W
W O W C O
WW .100Y.C Synchronization W WW .100Y. M.T
W Edge Detector
W O M.T W C O
W O W
WW .100Y.C M.TW WW
W O
WW .100Y.C M.TW
W O
WW .100Y.C 88
W W
7799D–AVR–11/10 W
.C OM
00Y .TW
W W.1 Y.COM W
W 00 .T
The synchronization and edge detector W W.1 logic .C OM
introduces a delay of 2.5 to 3.5 system clock cycles
from an edgeOhas .T W
been applied
Wto the .Tn 1 0 Y
0pin to theM .TW is updated.
counter
M W O
0 0 Y.C .T W WW .100Y.C M.TW
W.1 and
Enabling M
disabling
O
Y.Ccycle,.Totherwise
of the clockW W mustY.be
input
0a C
Odone when Tn has been stable for at least one
WW system 1 0 0
clock M
W
it
W
is a risk . 1
that0 false M .TW
Timer/Counter clock pulse is generated.
W . O W W .C O
W W Y .C W W 0 0 Y .T W
OM
.T W
EachWhalf .100periodOof M.theT
external clock W.1 Y
Wapplied
M
.CO be .longer
must than one system clock cycle to
Y.C W W W 0 Y .C T W W 0 0 TW
0 0 .T ensure 1 0
correct sampling.M . The external clock . 1 must be M
guaranteed to have less than half the sys-
W.1 Y.COM W W W. Y .CO W WW 00Y.CO .TW
W W
tem clock.1frequency 0 0 .T < fclk_I/O/2) given
(fExtClk W .a1 50/50%Oduty M cycle. Since the edge detector uses
W 00 .T M
W W.1 Y.COM W sampling,WW the 0 Y .CO .Tfrequency
maximum W W
of WW
an external 00 C
Y.clock TW detect is half the sampling fre-
it .can
W 00 .T W . 1 0 M . 1 M
.1 O M W O W .C O
W
WW .100Y.C M.TW
quency
WW(Nyquist .C
Ysampling .TW
theorem). However, WW .1due 00Y to variation Wof the system clock frequency
M.T and capacitors) tolerances, it is
and duty W
cycle. 100caused O M
by Oscillator source W
(crystal, O
resonator,
W O
WW .100Y.C M.TW recommended WW .1that .C
00Y maximum .TW WW .100Y.C M.TW
W O M frequency of an W external clock O source is less than fclk_I/O/2.5.
W
WW .100Y.C M.TW
O
W sourceOcan not be prescaled. W O
WW .100Y.C M.TW
W O An external clock
W O W O
W O
WW .100Y.C M.TWFigure 14-2. WW Prescaler 0 0 Y.Cfor synchronous.T W WW .100Y.C M.TW
Timer/Counters
. 1 M W O
WW .100Y.C M.TW clkI/O W 1 M
W. O W O
W
WW .100Y.C M.TW
O
WW .100Y.C M.TW
Clear
WW .100Y.C M.TW
W O
WW .100Y.C M.TW PSR10 W . 1 M W O
W O
W
WW .100Y.C M.TW
O
W O W O
W O
WW .100Y.C M.TWTn WW .100Y.C M.TW WW .100Y.C M.TW
W O W O
W
WW .100Y.C M.TW
O
WW .100Y.C M.TW
Synchronization
WW .100Y.C M.TW
W O W O
W
WW .100Y.C M.TW
O
W O W O
W O Tn
WW .100Y.C M.TW Synchronization WW .100Y.C M.TW WW .100Y.C M.TW
W O W O
W
WW .100Y.C M.TW
O
WW .100Y.C CSn0 T W WW .100Y.C M.TW WCSn0
.1
M . CSn1 W OM
W . C OCSn1 WW 00Y.CO .TW W W 0 Y.C W
W W
. 1 00 Y CSn2
M .T W W
W .1 O M CSn2
W .1 0
O M.T
W O WW .100Y .C
W
O W O W .C O
W
WW .100Y.C M.TW WWTIMER/COUNTERn Y.C .TW WW TIMER/COUNTERn Y CLOCK.TSOURCE
.100 clk O
W
W .100 clk CLOCK O M SOURCE
W C
M
W O WW .100Y .
Tn Tn
W O W O M.T
W O WW .100Y .C
W
14.5 Register Description O W O W .C O
W
W
O W O W .C O
W
WW Timer/Counter .C W WW .100Y.C M.TW WW .100Y M.T
W
14.5.1 GTCCR – General
. 1 00Y M .TControl Register
W O W .C O
W O Y.C W
W 1 .100Y0 W
WW Bit
00Y
.C 7 .TW 6 WW 5
. 1004 M
3.TW 2
M.T
WW(0x43)00Y.CTSM .TW –
0x23
WRead/Write W–W .10–0Y.C M –
.TW
– W- 0Y
PSRSYNC
.10R/W
W
GTCCR
M.T
W .1 R/W O M R R W R O R R R WW .C O
W .C W W Y.C 0 .TW 0 W .1000
Y
M.T
W
WInitial Value100Y 0
W . O M.T 0
W
0
W .1000 O M 0
W W .C O
Y .TW
W O W C O W W .C OM
• BitW 7 – TSM: Y .C
Timer/Counter W Synchronization WW .100Y .
Mode
M.T
W W .100
Y .TW
W
WritingW W.TSM
the 100 bit toOone M.Tactivates the Timer/Counter W C O
Synchronization mode.W W
In this .
mode,C OMthe
Y.C TW WW .100Y. .TW W 00Y
.1correspond- .TW
W is .written
value that W 100 toOthe M.PSRASY and PSRSYNC W bits C is
O M
kept, hence keeping W W
the .C OM
WW .reset Y.C TW WW Y. .TW W .100
Y
ing prescaler
W 100 signals O M.asserted. This ensures W .100that the O M
corresponding Timer/Counters
W W are
.C W without Y .C W W
halted and WWcan .be 0 0 Y
configured .Tto W the same W
value .1 0 0 the risk
M .T
of one of them advancing during
W1 Y OM bit is written to zero,
.CTSM WW the00PSRASY Y .CO and WPSRSYNC bits are cleared
configuration. WW When . 10 0 the
M . T W W .1 M.T
W O W C O
by hardware, and the Timer/Counters start counting
WW .100Y.C M.TW WW simultaneously. Y.
W O W .100
WW .100Y.C M.TW WW
W O
WW .100Y.C M.TW
W O
WW .100Y.C 89
W W
7799D–AVR–11/10 W
.C OM
00Y .TW
W W.1 Y.COM W
W 00 .T
• Bits 6:1 – Res: Reserved WW.1 .C OM
These bits are M .TW and will
reserved
W
always . 0Y
10read as M
zero.
.TW
W O
. 1 00Y M O
W .C O WW for00Synchronous
Y.C .TW Timer/Counters
WW• Bit 00–0Y
. 1
PSRSYNC:
M .T W PrescalerW Reset
. 1 M
O W O
WW this
WWhen 00Y
bit.C
is one, T
.Timer/Counter0
W 100
Y.C
WWand .Timer/Counter1, .TWTimer/Counter3, Timer/Counter4 and
M .TW . 1 O M W O M
.CO .TW WW 00Y.C prescaler
Timer/Counter5 W will be Reset.
WW This 100
Y.C
bit is normally
.TW
cleared immediately by hardware,
.100Y M
W
except W if. 1
the TSM M
bit
O
.Tset.
is Note that .
Timer/Counter0
W O M
and Timer/Counter1 share the same pres-
W O
WW .100Y.C M.TW WWand .a10reset
caler 0Y.Cof this .T W
prescaler will
W
Waffect .
all10 0Y.C M.TW
timers.
W OM W O
W
WW .100Y.C M.TW
O
W O W O
W
WW .100Y.C M.TW
O
W O W O
W
WW .100Y.C M.TW
O
W O W O
W
WW .100Y.C M.TW
O
W O W O
W
WW .100Y.C M.TW
O
W O W O
W
WW .100Y.C M.TW
O
W O W O
W
WW .100Y.C M.TW
O
W O W O
W
WW .100Y.C M.TW
O
W O W O
W
WW .100Y.C M.TW
O
W O W O
W
WW .100Y.C M.TW
O
W O W O
W
WW .100Y.C M.TW
O
W O W O
W
WW .100Y.C M.TW
O
W O W O
W
WW .100Y.C M.TW
O
W O W O
W O
W O W O
W O
W O W O
W O
W O W O
W
WW .100Y.C M.TW
O
W O W O
W
WW .100Y.C M.TW
O
W O W O
W
WW .100Y.C M.TW
O
W W .C O
Y W
W
. C W
WW .100Y M .TW W
W . 100 O M .T W
W .100 OM
.T
WW .100Y M .TW W
W .100 O M .T W .10 O M.T
W O WW .100Y .C
W
W O W O W W .C O
Y
M.T
W
W O W O W W .C O
Y
M.T
W
W O W O W W .C O
Y
M.T
W
W O W O W W .C O
Y .TW
W O W C O W W .C OM
W W .100
Y .TW
W O W C O W W .C OM
W W .100
Y .TW
W O W C O W W .C OM
W W .100
Y
W O W C O W W
W W
W O W C O
W
W O W CO
W O W
WW .100Y.C M.TW WW
W O
WW .100Y.C M.TW
W O
WW .100Y.C 90
W W
7799D–AVR–11/10 W
.C OM
00Y .TW
W W.1 Y.COM W
W 00 .T
15. 8-bit Timer/Counter0 with PWM W W.1 Y.COM W
.TW W 00
W.1 Y.COM W
.T
.C OM W
Y W W 00 .T
15.1 Features W .100 O M.T W W.1 Y.COM W
WW .C TW Compare W Units.100
00Y
• Two.1Independent M.Output W OM
.T
W C O W .C
.TW W• WDouble 1 0Y .
0Buffered .TW CompareWRegisters
Output
M . 100
Y
M .TW
M . O W O
.CO .TW WW Timer
• Clear .C
00Yon Compare .TWMatch (Auto WWReload) 100
Y.C .TW
.100Y M
W . 1 O M
WFree, Phase Correct Pulse Width W . O M
W O
WW .100Y.C M.TW
• Glitch WWModulator Y.C (PWM) TW
WW .100Y.C M.TW • W . 100 OM
.
W O W
Variable PWM Period
C O W .C
WW .100Y.C M.TW WW .10Generator
• Frequency 0Y .
M .TW W . 100
Y
M .TW
W O W O
W O
WWIndependent Y.C Interrupt WW OCF0A, Y.C W
WW .100Y.C M.TW • Three . 100 M .TWSources (TOV0, W .100 andOOCF0B) M.T
W O
W
WW .100Y.C M.TW
O
W O W O
WW 0Overview
W15.2 0 Y.C
O
W.1 OM WW 00Y.Cmodule, O
WW .is
W .CO .TW 8-bit W W
WW .100Y.C M.TW Timer/Counter0 1 0a0YgeneralMpurpose Timer/Counter
W . 1 O M.T with two independent Output
O W O C
Y.program.Texecution
W Compare Units,
WW .100Y.C M.TWagement)Wand wave
W and00with Y.CPWM .support. TW
It allowsWWaccurate .100 M
W timing (event man-
W . 1 generation. O M W C O
W
WW .100Y.C M.TW
O
W
W O W C O
W O A simplified block
WW diagram Y.Cof the.T8-bit W Timer/Counter WW .1is00shown Y. in Figure
.TW 15-1. For the actual
WW .100Y.C M.Tplacement W
of I/O .
pins, 100refer toO“Pinout”
M on page 2. CPUW accessible O MI/O Registers, including I/O
W C
W
WW .100Y.C M.bits
O
TWand I/O pins, WWare .shown .C
00Y in bold. W
.TThe WW .100Y. M .TWbit locations are listed
1 M device-specific W I/O Register O and
W O WW 00Y.on CO WW .100Y.C M.TW
WW .100Y.C Min.Tthe W “RegisterWDescription” . 1 page
M
W
.T102. W O
W O
W
WW .100Y.C M.TW
O
W OFigure 15-1. 8-bit W W .COBlock Diagram WWW .CO .TW
WW .100Y.C M.TW W Timer/Counter
. 1 00Y M .TW . 1 00Y M
W W .C O
W WW 00Y.CO Count .TW W WW TOVn00Y.CO .TW
W 00 Y .T W .1
W.1 Y.COM W .1 M Control Logic
Clear (Int.Req.)
WWClock Select OM
WW 00Y.CO W W 0 Y.C W
W M.TTn
Direction clk
W 00 .T W .1 M .T Tn
1 0
.Edge
W . 1 O M W O W
W Detector00Y. CO
WW .100Y.C M.TW WW .100Y.C M.TTOPW BOTTOM W .1 M.T
W
W O W C O
W O
WW .100Y.C M.TW WW( From Prescaler Y. W
WW .100Y.C M.TW W .100 ) O M.T
O W O .C
W
WWTCNTn .100Y.C M=.TW = 0 WW .100Y
Timer/Counter
W
W O W O W .C
WW .100Y.C M.TW WW .100Y.C M.TW WOCnA
.100
Y
M.T
W
W O W O (Int.Req.)
W W .C O
WW .100Y.C M.TW WW Y.C .TW W Y
.100 OCnAOM.T
W
100
Waveform
= . M
O W O Generation
W .C
W
W
W O W O W W .C O
WW .100Y.C Fixed
OCRnA
Y W
WW .100Y.C M.TW M
TOP .TW OCnBW
W .100 O M.T
O W O (Int.Req.)
.C
W
Value
WW .100Y W
DATA BUS
=
W O
Waveform
W OCnB O M.T
W O WW .100Y .C
WW .100Y.C M.TW
Generation
W
W O W O W .C
WW .100Y.C M.TW WW .100Y.C M.TW Y W
OCRnB
W O
W
W .100 O M.T
W O W .C
WW .100Y.C M.TW TCCRnA W
W 0Y.C M.TW
.10TCCRnB
W .100
Y
M.T
W
W O W O W W .C O
Y
M.T
W
W O W O W W .C O
Y .TW
W O W C O W W .C OM
W W .100
Y .TW
W O W C O W W .C OM
15.2.1 Registers
M.T (OCR0A and OCR0B)
W .100
Y .TW
The Timer/Counter
W O
(TCNT0) and Output W
Compare O
Registers
C W W are .C OM
8-bit
WWInterrupt Y.C W WW .100Y. .TW W Y
.100 in the
registers. W .100 request O M.T(abbreviated to W Int.Req.
W in .the
C O M
figure) signals are W allWvisible
WW .Flag Y.C W W 00Yindividually W W
M.T masked with the Timer Inter-
Timer Interrupt
W 100 Register O M.T (TIFR0). All interrupts W .1are
C O
W Y.C W and TIMSK0 WW are Y. inW
rupt Mask WRegister
W .100
(TIMSK0).
O M.T
TIFR0
W .100not shown O M.T the figure.
W .C W Y .C
W
The Timer/Counter 00Ybe clocked
can .TWinternally,W via the .100
Wprescaler, or by an external clock source on
W W.1 Y.COM W W
the T0 pin. W The Clock 0Select
0 logic . block
T controls W which clock source and edge the Timer/Counter
W W.1 Y.COM W
W 00 .T
W W.1 Y.COM
W 00
W W.1 91
7799D–AVR–11/10 W
.C OM
00Y .TW
W W.1 Y.COM W
uses to increment (or decrement)
W 100 The
W.value.
its OM
.T
Timer/Counter is inactive when no clock source
W .C W
is selected. The M TW from the
.output W Clock.1Select 00Y logicMis.Treferred to as the timer clock (clkT0).
C O W W .C O
Y . W W 0 Y .T W
100
W.double
.T
OM Output Compare .10 M
The
W Y .Cbuffered
W W WWRegisters 0 Y .CO(OCR0A .
and OCR0B) are compared with the
TW can be used by the Waveform Gen-
W Timer/Counter
1 0 0 value .T at all times. The .
result 1 0 of the M
compare
.
WW to 0generate OM W O
.T W Werator 0 Y.C a .PWM TW or variable WWfrequency . 1 0 0Y.Coutput M TWthe Output Compare pins (OC0A and
.on
M . 1 O M W O
.CO .TW WW See
OC0B). .C
00Y“OutputMCompare .TW Unit” WonW page 093. Y.C details.
1 0 for O .TWThe Compare Match event will also
.100Y M
W
W . 1 O W . M
C be used
W O set W
W the Compare .C Flag (OCF0A WW which
or OCF0B) Y.can .TW to generate an Output Compare
WW .100Y.C M.TW . 1 00Y M .TW W . 100 O M
interrupt W request. O
W
WW .100Y.C M.TW
O
W O W O
W
WW15.2.2 0
O
Y.CDefinitions
0 .CO in
W.1 OM WW 00Y.bit COreferences WW are 0Ywritten W
WW .100Y.C M.TW ManyWregister.1and M .T W in thisWsection
W . 1 0
O M.T general form. A lower case “n”
O W O .C case
W
WW .100Y.C M.TW
replaces WW the Timer/Counter
00Y
.C .number,
TW in this WW case 0.0A
.1 0
Ylower
M.T
W“x” replaces the Output Com-
W . 1 O M W O
C However,
W O pare Unit, W in this case Compare Unit A or Compare WW .1Unit .B. W when using the register or
WW .100Y.C M.TW bit defines W . 0Y.C M.TW
10program, 00Y M.Ti.e., TCNT0 for accessing
W O in
W a O the precise form W Wmust be .C O
used,
WW .100Y.C M.TWTimer/Counter0 WW counter Y.C .TWso on. W W.100Y OM.TW
W . 100 value O M and
W
WW .100Y.C M.TW
O
The definitions inWTable 15-1 Oare also used extensively W throughout O the document.
W O
WW .100Y.C M.TTable W WW .100Y.C M.TW WW .100Y.C M.TW
15-1. Definitions W O W O
W O
WW .100Y.C M.TBOTTOM W WW .100Y.C M.TW WW .100Y.C M.TW
The W counter reaches O the BOTTOM when W it becomes O 0x00.
W
WW .100Y.C M.TW
O
W O MAX TheWcounter W .CO its
reaches MAXimum when W
WW it becomes .CO0xFF.T(decimal
W 255).
WW .100Y.C M.TW W .1 00Y M .TW . 1 00Y M
WW 0equal O the highest value in the
W O TOP The W
W counter
W reaches .CO the.TTOP W when itWbecomes 0Y.C to M .TW
WW .100Y.C M.TW . 1 00Y M W . 1 O
count W
sequence. TheO TOP value can be assigned to
C be the fixed value 0xFF
W
WW .100Y.C M.TW
O
WWor the 0Y.C stored
0value .TW WW .100Y. M .TW
(MAX) . 1 M in the OCR0A Register. The assignment is depen-
W W .C O
W 00 Y .T W
dent on the mode .1 of operation. M .1 M
W 00 .T W .1 M
15.3 Timer/CounterW W 0 T W
W 00 Clock .Sources T 0
W.1 Y.COM W
. .1 M
W W.1 Y.COM W Wclocked W WW 00Y.CO .TW
The Timer/Counter can W
be 0by an internal.T or an external clock source. The clock source
W
W .100 O M.T 0
W.1 logic .C OM is controlled byWthe W.1 Y.COM W
is .C
selected by the Clock W
Select which W Clock Select
WW .100Y M .TW W
W . 100
Y
O M .T W
W .100 O M.(CS02:0)
T bits
W located .CO in the Timer/CounterW Y.C (TCCR0B). W on0clock .C
WW .caler, .TW
00Y see “Timer/Counter0 W Control .100
Register
M .TW
ForW details
.1 0
Y sources
M.T
Wand pres-
1 O M and Timer/Counter1
W O Prescalers” on page W 88. .C O
W
W
O W O W .C O
W
W
15.4 Counter Unit O W O W .C O
W
WW The.1main .C of .the TW8-bit Timer/Counter WW .100isYthe .C .TW WW .100counter Y .TW
00Y part M W programmable
O M bi-directional
W .C O M
unit. Figure
W O
.Ca block.Tdiagram Wcounter00and Y.Cits surroundings. W WW .100Y T W
WW15-2 .shows
1 0 0 Y
M
W of W
the . 1 M . T
W O M .
W O W O W .C
Y
M.T
W
Figure
W 15-2. Counter
O Unit Block Diagram W O W W .C O
Y
M.T
W
W O W O TOVn W W .C O
WW .100Y.DATA C BUS W WW .100Y.C (Int.Req.) M.T
W W .100
Y
M.T
W
Y .TW
W O W C O Clock Select WW .C OM
W W .100
Y .TW
W O count
W C O Edge
W W . C OM
WWControl.1Logic . Y .TW
Tn
WW .100YTCNTn .C W 00Y clk M.TW Detector W W.100
M.T OM
clear Tn
W O W C O W .C
WW .100Y.C M.TW
direction W Y. W W .100
Y
W O
W
W .100 O M.T W W
WW .100Y. C
WW .100Y.C M.TW W W)
( From Prescaler
W O W O M.T
WW .top Y. C
WW .100Y.C M.TW bottom
100 M.T
W
W O W C O
Signal description W (internal O
signals): W
WW .100Y.C M.TW WW
W O
WW .100Y.C M.TW
W O
WW .100Y.C 92
W W
7799D–AVR–11/10 W
.C OM
00Y .TW
W W.1 Y.COM W
W 00 .T
count W W.1 or
Increment . OM
decrement
C TCNT0 by 1.
.T W W . 1 0 0Y M . TW
OM W O
direction
0 0 Y.C .T W Select
WW between . 1 0 0Y.Cincrement M .TW
and decrement.
W . 1 O M W O
WW .1clear .C WWTCNT0
Clear Y.C bits Wzero).
00Y M .TW W . 100(set all O M .Tto
W O Y.C referred
.TW WW clk 0Tn0Y.C M.TW WW .100clock,
Timer/Counter M .TW to as clkT0 in the following.
M W . 1 O W O
.CO .TW .C WW that.1TCNT0 .C TW
00Y WW top . 1 00Y M .TW Signalize 00Y has M .reached maximum value.
.1 M O W O
W W Y .CO
W W WW 00Y.C W W W 0 0Y .C .T W
W 00
W.1 Y.COM W
.T bottom .1 M.T SignalizeW that 1
W.TCNT0 OMreached minimum value (zero).
has
W W WW 00Y.CO .TW W 1 0 0 Y.C .TW
W .1 00 M.T . 1 O M
W of the mode of operation used, W . O M
W O Depending
WW .100Y.C M.TW WWthe .counter Y.C is cleared, .TW
incremented, or decremented
WW .100Y.C M.TW at each timer clock (clk ). clk can be W
generated 100 fromOM an external or internal clock source,
O W O .C
W
WW .100Y.C M.TW selected WWby the 0 0 Y.C Select
Clock
T0
.T W T0
bits (CS0[2:0]). WW When . 1 0 0Y no clock M .TW is selected (CS0[2:0] = 0)
source
W. 1 OM
W O Y.CHowever, WW
W
0Ybe .CO .TW
WW .100Y.C M.TW the timer WW is stopped. 0 0 .T Wthe TCNT0 value 0
can
1 accessed by the CPU, regardless of
W O W . 1
C O M W W .
.C OM
W . Y W
WW .100Y.C M.TW whetherWclkT0 is.1present 00Y orMnot. .TWA CPU write W overrides 00 (has priority
W.1 Y.COM W
.T over) all counter clear or
W C O count operations. W W .C O W
WW .100Y. W Y W W 00 .T
W O M.T
W
C W .C
WW .100Y. WThe counting
M.T the Timer/Counter
W sequence 100
Yis determined .TW by the W setting of10the
. 0 WGM01 M.Tand WGM00 bits located in
W C O W W .Control
.C OM (TCCR0A) and
Register W Wthe WGM02 Y .C Obit located
W in the Timer/Counter
WW .100Y. M
W
.TControl W . 100
Y
M .TW W
W .100 between O M.Thow the counter behaves
Register BW (TCCR0B). O There are close connections C
W O
WW .100Y.C M.(counts) TW
W Y.C .TW WW .100Y. .TW OC0A and OC0B.
and W how waveforms
W . 100 are
O M generated on the Output W Compare C O Moutputs
W O .C WW and.1waveform . .TW
WW .100Y.C MFor .TW more details WW 00Y
about.1advanced .TW sequences
counting
M 00Y Mgeneration, see “Modes of
W O W C O
W W Y .C O Operation” on page
W W W96. 00Y.C .T W W W 0 0 Y. . T W
W 00 .T W.1 Y.COM W .1 M
W 00 W 0 .T
0 Flag (TOV0) is set accordingW to.1the mode
W.1 Y.CO M.T
The Timer/Counter Overflow
W W.1 Y.COM W WCPU interrupt. Y.C
OM of operation selected by
W
W the WGM0[2:0]
W bits. W TOV0 can 0 be used for
.T generating W a .1 0 0 M.T
W . 1 00 M .T W . 10 O M W C O
W
WW .100Y.C M.TW
O
W
W O W C O
15.5 Output CompareOUnit
W
W
W O W C O
W .CO8-bit.Tcomparator
The
WW .100Y.C M.TW
continuously compares TCNT0 W W the Output
with Y. Compare W Registers
WW .100Y (OCR0A M and
W
OCR0B). WheneverW TCNT0 O equals OCR0A or W
OCR0B,.100 the comparator
O M.T signals a
W O .C WW .100Y .C
WW .100match. Y.C A match .T W will setWthe W
1 0 0Y M . W
TFlag M .TWtimer clock
OM .
Output Compare (OCF0A or OCF0B)
WW 00Y.CO .TW
at the next
W
WW
W CO
0isY.enabled,
WW .10cycle. 0Y.C If the M .T W
corresponding interrupt. 10 M . W Output W
Tthe Compare W.1FlagYgenerates OM an Output
W C O W W . C O W .C W
WW .Compare . interrupt.W The Output W Compare Y W
automaticallyWcleared.1when 00 the interrupt .T
100
Y
M.T W.be 100 Flag OM
is.T
W a logical C OM
is exe-
W cuted. .C O
Alternatively, the flag Wcan cleared .C by software
W by W
writing Y . one to Wits I/O bit
WW .100Y M .TW W
W . 00Y
1uses O M .T W
W .100 O M.T
W location. The
O Waveform Generator the match signal to generate
WW .100Y an C
output
. according to
WW operating0 0 Y.C .T W WW .10bits 0Y.C M.TW M .TW
W. 1 mode M set by the WGM0[2:0] W and O Compare Output mode (COM0x[1:0])
WW 00Y.C O bits. The
WW max.1and .CO .signals W are used WWby the 0Y.C M.Generator TW Whandling M.T
W
00Y bottom M T
W .1 0 Waveform O for W .1 the special
.C O cases of
W O Y.C (“Modes WW on page Y W
WWthe extreme .C
00Y values .TinWsome modes WWof operation . 100 M .TWof Operation” .100 96).OM.T
.1 O M W O W W .C
WW 15-3
WFigure 00Y shows
.C W diagram
a.Tblock WW of the.1Output
.C
00Y Compare .TW unit. W W.100Y OM.TW
. 1 M W O M
W
WW .100Y.C M.TW
O
W O W O
W
WW .100Y.C M.TW
O
W O W O
W
WW .100Y.C M.TW
O
W O W O
W
WW .100Y.C M.TW
O
W O W O
W
WW .100Y.C M.TW
O
W O W O
W
WW .100Y.C M.TW
O
O W O W
W
W O W O
W O W O
W O W
WW .100Y.C M.TW WW
W O
WW .100Y.C M.TW
W O
WW .100Y.C 93
W W
7799D–AVR–11/10 W
.C OM
00Y .TW
W W.1 Y.COM W
W 00 .T
Figure 15-3. Output Compare W W.1BlockY.Diagram
Unit, C OM
M .TW W . 100 M .TW
W O
00Y
.CO .TW WW .10DATA 0Y.C BUS M .TW
W . 1 O M W O
W O W O
OM W O W O
OCRnx WW .100Y.C M.TW TCNTn
.10 M W O W O
W O
W O W O
W
WW .100Y.C M.TW
O
W O = (8-bitWComparatorO)
W
WW .100Y.C M.TW
O
W O W O
W
WW .100Y.C M.TW
O
WW .100Y.C M.TW WW .100Y.C M.TW OCFnx (Int.Req.)
W O W O
W
WW .100Y.C M.TW
O
W O W O
W
WW .100Y.C M.TW
O
WW top.100Y.C M.TW WW .100Y.C M.TW
W O W O
W
WW .100Y.C M.TW
O
WWbottom 0 0 Y.C . T W Waveform WWGenerator . 1 0 0Y.C M.TW
W. 1 M W O OCnx
W O
WW .CO .TW WW .100Y.C M.TW
WW .100Y.C M.TW FOCn .100Y M W O
W O
W
WW .100Y.C M.TW
O
W O W O
W
WW .100Y.C M.TW
O
WW .100Y.C M.TW WW .100Y.C M.TWGMn1:0 W WCOMnX1:0 .1 M
W W .C O
W 00 Y W .1
W.1 Y.COThe M.T OCR0x Registers .1
WW are00double
M
.CO buffered when W WWany00ofY.the
using
M
CO Pulse WWidth Modulation
W W W Y .T W 1 M.T
W . 1 00 M
(PWM) .T modes. For the W .
normal1 andO M
Clear Timer on Compare W .(CTC) O
modes
C of operation, the dou-
W
WW .100Y.C bleM
O
.TW is disabled. WW The Y.C
00double .TW synchronizes WW .100Y. M .TWOCR0x Compare
buffering . 1 O buffering
M W the update O of the
W O WW 00Y.C WW The Y.C W
WW .100Y.CRegisters M . T Wto either W top or bottom .1 .
of theMcountingTW sequence.
W . 1 00synchronization
O M.T prevents the
WW .100Y.occurrence Wof odd-length, W non-symmetrical Y .TPWMW pulses,Wthereby.1making 00 .T
the output glitch-free.
W O M.T W .100 OM W W .C OM
C W .C Y W
WW .100Y . OCR0x
The W
M.T Register access
W may Y complex,
00seem .TW but thisW is not W .100WhenOthe
case. M.T double buffering
WW .100isYenabled, .C
.Tthe
W CPU has W
W access 10to0 the OCR0x M .T Buffer Register,W and Y
.100if double .TW
Mbuffering is dis-
W O M W . O W W .C O
abled .C the CPU will access the
W OCR0x . C
directly. W 00 Y W
WW .100Y M.T
W W 00Y .T W
W.1 Y.COM W
.T
WW Compare Y W W 00 .T W 00 .T
15.5.1 Force Output
.C W W comparator 00 .T
WW In.1non-PWM
00Y .TW
Mwaveform
W
generation .100 theOmatch M.T output of theW W.1 Y.Ccan OMbe forced by
W O Wmodes, C
WW writing .C
00Ya one M TWForce Output
to .the W
W Compare Y .
100 (FOC0x) M
W
.T bit. ForcingWCompare 0
.10Match O will .TWset the
Mnot
W . 1 O W . O W W .C
.C or reload/clear WW .C OC0x as Y W
WW OCF0x . 1 00Y
Flag
M .TW
the timer, but
.100
Ythe
M .TW pin will be W updated
W .100
if a real Compare
O M.T
O W O .C
W
Match
WWtoggled).
had
0 Y.C
occurred
.T
(the
W COM0x1:0 bits
WW .100Y.C M.TW
settings define whether WW .100Y
the OC0x pin is set, cleared
M .TW or
1 0 W O
W. OM W O
WW .100Y.C M.TW
W O
.CTCNT0 WW 00Y.CO .TW W WW 00Y.CO .TW
15.5.2 Compare Match WW Blocking 0 Y
by .T W
Write W
W.1 Y.COM W
0
W.1writeYoperations
.C OM W W.1 Y.COM W W
All
W WCPU
00 .TW to the TCNT0 W Register
.100
will block
M.T
any Compare W Match 00 occur M
.1that in.T
the
nextW timer clock cycle, even
.C .TW
when the WtimerW is 0stopped. Y.C This Wfeature allows W OCR0x .100
Yto be initial-.TW
W
ized to the W
00Y valueMas
.1same O TCNT0 without W .1 0 anO
triggering M.T when the Timer/Counter
interrupt W W .C OM is
clock
WW .100Y. C Y .TW
WW .100Y.C M.TW
enabled. M.T
W W
W .100 OM
W O W C O W .C
W W .100
Y .TW
W O W CO W W .C OM
15.5.3 Using the Output Compare WW Unit Y.C W WW .100Y. M.T
W W .100
Y
Since writing
WW TCNT0 Y.Cin any.T mode
W of operation WW will Y. all Compare
block .TW MatchesW for one timer
clock cycle, W
there .100are risks O Minvolved when changing W .100TCNT0 O Mwhen using the Output Compare
C WW .100Y. C
WW .100ofY.whether M
W
.Tthe M .TW
Unit, independently Timer/Counter is running or not. If the value written to TCNT0
WW 00Y.CO .TW W WW 00Y.CO
equals the OCR0x W value, theMCompare Match willWbe .1 missed, resulting in incorrect waveform
W.1 O
WW .100Y.C M.TW WW
W O
WW .100Y.C M.TW
W O
WW .100Y.C 94
W W
7799D–AVR–11/10 W
.C OM
00Y .TW
W W.1 Y.COM W
generation. Similarly, do not write
W .100TCNT0
Wthe OM
.T
value equal to BOTTOM when the counter is
W .C
down-counting. M .TW W . 100
Y
M .TW
W O
. 1 00Y of the M
The
W setup
.C O OC0x should be W W
performed CO setting
before
0Y.the TW
the Data Direction Register for the
WWportWpin 1 0 0
to
Youtput. .T
The
W
easiest
W of setting
way . 1 0 OC0xM . value is to use the Force Output Com-
W
.
.C OM WW 00Y.CO .TW
.TW Wpare (FOC0x) 00 Y strobe W
.Tbits in Normal mode. W .1 The OC0x M Registers keep their values even when
.C OM W W.1 between Y .C OM
W WWmodes. 0 Y .CO .TW
Y W changing
W 0 0 Waveform
.T W
Generation
.1 0
00 .T W.1 Y.COM W M
W 00 .T W
Be aware.1that 0
0 the COM0x[1:0] M.T bits are not .double1 buffered together with the compare value.
W.1 Y.COM W WW immediately. OM
W WW the00COM0x[1:0]
Changing
W Y .CO .TW bits will W
take effect 0 0 Y.C .T W
W 00 .T .1 M .1 M
W 00 .T W .1 M .1 M
W W.1 Compare
15.6 .C OM Match Output
W WW Unit Y .CO .TW W WW 00Y.CO .TW
W 00 Y .T W .10 0 1 M
W.1 Y.COM W The Compare OM (COM0x[1:0]) W W.have .COfunctions.
WW Output Y .Cmode W W bits 0 Ytwo W The Waveform Generator
W W
. 1 00 M .T uses
W
the COM0x[1:0]
W . 10 0
bits
O M for
T
. defining the Output W
0
.1CompareO(OC0x) M.T state at the next Compare
W O .C WW .C .TW Figure 15-4 shows a sim-
WW .100Y.C M.TW Match. Also, WW the.1COM0x[1:0] 00Y M TWcontrol the
.bits OC0x 00Y
.1pin output M
source.
W O W C O
W O
WW .of 0Y.C
W Y. W
WW .100Y.C M.TWplified schematic 10the logicM .TW by theW
affected COM0x[1:0]
W .100 bit setting.
O M.T The I/O Registers, I/O bits,
O W O Y. C
W
WW .100Y.C M.TW and I/O pins WW in the figure Y.C are shown .TWin bold. Only WWthe parts .100 of the .TW I/O Port Control Regis-
general
W . 100 O M W C O M
W O ters (DDR andW
W PORT) Y.Care affected
that WW .100bits
by the COM0x[1:0] Y. are shown. .TW When referring to the
WW .100Y.C M.TOC0x W . 100 is for M .TW W O MOC0x
state, the reference
W O the internal OC0x Register, not C the pin. If a system reset
W
WW .100Y.C M.occur,
O
TW the OC0x WWRegister .C
00Yis resetMto.T“0”. W WW .100Y. M.TW
W . 1 O W O
W
WW .100Y.C M.TW
O
W O W O
W
WW .100Y.C Figure
O
.T W 15-4. Compare WW .1Match 0 0Y.COutput . W Schematic
TUnit, WW .100Y.C M.TW
OM W O M W O
W
W O W O
W
WW .100Y.C M.TW
O
COMnx1 WW .100Y.C M.TW WW .100Y.C M.TW
W O W O
W O
WW .100Y.C M.TW COMnx0 WW .Waveform 0 0Y.C M.TW D Q WW .100Y.C M.TW
W 1
Generator O W O
WW 1 .100Y.C M.TW
O FOCn
W
W O W O OCnx
W
WW .100Y.C M.TW
O
WW .100Y.C M.TOCnx W WW .100Y.C M .TW
Pin
O W O W .C O
W WW .100Y
0
W
O W O W .C O
W
WW .100Y.C M.TW WW .100Y.C D .TQW WW .100Y M.T
W
O W O M W .C O
W
W
O
DATA BUS
O W O W .C
W
WW .100Y.C M.TW WW .100Y.C PORT .TW WW .100Y M.T
W
O W O M W .C O
W
W
O W D O Q W .C O
W
W
O W O W .C O
W
W
W O W O W W .C O
WW .100Y.C clkI/OM.TW WW .100DDR Y.C .TW W .100
Y
M.T
W
W O W O M W W .C O
Y
M.T
W
W O W O W W .C O
WWgeneral .Cport function W is overridden WW .by Y.C W W from Y
.100the Waveform M.T
W
The
.100
Y
I/O
M.T W 100the Output O M.TCompare (OC0x) W C O
W O Ware set. .C W .
Y or out- W
WW .1if0either
Generator 0Y.C of M theTCOM0x1:0
. W bits
W .100
Y
However,
M.T
W OC0x pin
the Wdirection
W .100(input O M.T
W
put) isWstill controlled O W C O W .C
W 00the Y.C by the WData Direction WW Register .10be 0Y. (DDR) for the port pin.
.TW W The .Data 100
YDirection.TW
Register W bit.1for OC0x
O M.Tpin (DDR_OC0x) W W
must set
.C OasMoutput before the W OC0xW value OM
Y.Cis visi-.TW
W W 0 Y .C T W W 0 0 Y . T W W 1 0 0
ble on the pin. 0
W.1 The port OM
.
override W.1
function is independent OM
of the Waveform Generation W. mode.OM
WW .100Y.C M.TW WW .100Y.C M.TW WW .100Y.C
.CO of W
The design W
W
of the Output
Y .CO Compare W W WW initialization
pin logic allows
0 0 Y .T
the OC0x state
W W Wbefore the out-
W
put is enabled..1Note 0 0 that M .T
some COM0x1:0 bit . 1
settings are M reserved for certain modes of
W .CODescription” WW 00Y.CO .TW
operation. WW See “Register 0 Y .T W on W
page 102.
W.1
0
OM W.1 OM
W O W
WW .100Y.C M.TW WW
W O
WW .100Y.C M.TW
W O
WW .100Y.C 95
W W
7799D–AVR–11/10 W
.C OM
00Y .TW
W W.1 Y.COM W
W 00 .T
15.6.1 Compare Output Mode and Waveform Generation W W.1 Y.COM W
.TW W 100
W.COM0x[1:0]
.T
OM bits differently in Normal, CTC, and PWM
The Waveform
C OMGenerator uses W the
.C
modes. 1 00For
.
Y all modes,
M .TW setting W the COM0x[1:0] . 100
Y = 0 tells
M .TWthe Waveform Generator that no action
W . O W O
WW 0Y.C Register .TW is to be W
W Y.C .TW
on the 0OC0x
. 1 M
performed
W . 100on theOnext M Compare Match. For compare output
W C O W . C
.TW
actions
WW .100Y in the . non-PWM
M .TW modes refer
W to Table
. 100
Y 15-2 on
M .TW 102. For fast PWM mode, refer to
page
M O
TableW15-3 on page 102, and for phase W O
.C refer
.CO .TW WW .100Y.C M.TW WW correct 100
PWM
Y .TW
to Table 15-4 on page 103.
.100Y M O W . O M
W O AW WW of00the
change Y.CCOM0x1:0 .TW bits stateWwill have
W Y.C at the.Tfirst
effect W Compare Match after the bits are
WW .100Y.C M.TW . 1 M W . 100 O M
written. W O
For non-PWM modes, the action .C to.T
W
WW .100Y.C M.TW
O
WW .100Y.C M.TW WW can.1be 00Y
forced
M
have
W immediate effect by using the
FOC0x strobe
W bits. O W O
W
WW .100Y.C M.TW
O
W O W O
WW
W Y.C
15.7.100Modes
O
of.T W
Operation WW .100Y.C M.TW WW .100Y.C M.TW
W OM W O
Y.C i.e., .the WW 00Y.CO .TW
WW .100Y.C M.TW The mode WWof operation, 0 T Wbehavior W of the Timer/Counter
W O W. 1 0
.CO of.T
M W W.1 Y.COMandW the Output Compare pins, is
W Y .C W defined Wby Wthe Y
combination
0 theW Waveform W Generation 0 0 mode T
(WGM0[2:0])
. and Compare Out-
W
W .100 O M.T put mode (COM0x[1:0]) W .10
.C
M
Obits. The Compare W W.1 mode
Output Y .C OM bits W
do not affect the counting
C W .TW
WW .100Y. M .TWsequence, W .
Y
100Waveform M
W
W .10do.0
O M.T
while W the O Generation mode bits TheC COM0x[1:0] bits control whether
W
WW .100Y.C M.TW
O
W W 0 0 Y.C .T W WW .100Y. M .TW
. 1 M
W O the PWM outputW generated should be inverted orW
.CO .TW
not
W (inverted .COor non-inverted PWM). For non-
.TbeWset, cleared, or toggled
WW .100Y.C M.TPWM W modes Wthe W 00Y
COM0x[1:0]
. 1 bits
M control whether W the .output 1 00Y should M
W O
W O WW (See .CO .TW WWUnit”.1on Y.C 95.)..TW
WW .100Y.C M.at TWa CompareWMatch
. 1 00Y“Compare M Match Output 00page M
W W .C O
W 00 Y W
.T detailed timing information
For .1 seeM“Timer/Counter Timing .1Diagrams”Mon page 100.
W 00 .T W .1 M .1 M
15.7.1 W.1 Mode
Normal
W .C OM
W 00 Y W .1
W.1 Y.CO TheM.T simplest mode ofWoperation W.1 Y.isCO M
the Normal mode (WGM0[2:0] WW 00=Y.0).
M
COIn thisTW mode the counting
W W W 0 .T W W 1 performed. M. The counter simply
W . 1 00 M .T is always up (incrementing),
direction W . 10 O M and no counter clear W .is
C O
W
WW .100Y.Coverruns
O
.TW WW its .maximum Y.C .TW WW .100Y. .TW from the bot-
M when it passes W 100 O 8-bit
M value (TOP = 0xFF) W and then C O M restarts
W CO (0x00). Y.C WWFlag.1(TOV0) . .TW
WW .100Y.tom .TWIn normalWoperation
W
. 100the Timer/Counter M .TW Overflow 00Y will Mbe set in the same
C
. clock W . .TWThe TOV0WFlagW Y
00 case behaves W like a ninth
WW .100Y timer
M .TW cycle as the WTCNT0.1becomes 00Y zero.
M
in.1this
O M.T
O W O .C
W bit, except
WW .100Y.C M.TW
that it is onlyWset, W not cleared. Y.C However, .TW
combined WW with.1the 00Ytimer M .TW interrupt
overflow
that automatically clears the WTOV0.100 Flag,OM the timer resolution W
can be C O
increased by software.
W O .C W . .TW
WW .10There 0Y.C areMno W
.Tspecial WW . 1 00Y in theMNormal .TW mode,W . 1 00Y value M
W W .C O
W
cases to consider
WW 00Y.CO .TW
a
W WW 00Y.CO .TW
new counter can be written
W 00 Y
anytime. .T W .1 M . 1 M
W 1
W .100OutputOCompare
WThe M.T Unit can be W
W
.1 to generate
used
.CO .TW
M interrupts at some WWgiven
. time.
Y.C
M the Out-
OUsing
W
. C Y W 0
W 0 Y
W put.10CompareMto.Tgenerate waveforms W W
W . 0 0
1 in Normal O M mode is not recommended, W . 1 0
O M.T this will
since
W O WW .100Y .C
WW occupy 00Y too.C much.T ofW the CPU time. WW .100Y.C M.TW M.T
W
. 1 O M W O W .C O
W
W
15.7.2 Clear Timer on Compare Match O (CTC) Mode W O W W .C O
WW 00Y.C
WIn .TW WW .100Y.C M.TW W 100
Y
.Register M .TW
Clear . 1 Timer on
O M Compare or CTC mode
W (WGM0[2:0] O = 2), the OCR0A W W .C O
is used to
W WW 00Y.C .T W W W
1 0 0Y.C .TW is cleared W . 1 00Y the counter M .TW
manipulate 1 the counter resolution. In CTC .mode the counter
M to zeroW when O
W. OM W O
WW 0Y.C hence
WW (TCNT0)
value 0 0 Y.Cmatches .T Wthe OCR0A. WW The OCR0A . 1 0 0Y.Cdefines M .TW the top value for the . 1 0counter, M.T
W
WW
also its resolution. .C This .mode TW allowsW
W
greater controlY.Cof the.TCompare W MatchW output Y
.100frequency.
W
M.TIt
W . 1 00Y
O M W .100 O M W W .C O
also simplifies the operation of counting WW external events. Y. C Y .TW
WW .100Y.C M.TW .100 M.T
W W
W .100 OM
W O W C O W .C W
The W timingW diagram .C CTC modeWisWshown00inY.Figure 15-5. W The counter W value Y
.100(TCNT0) M.T
. 1 00Y forM the.TW W .1 O M.T W .C O
increases W O
until a Compare Match occurs .C W
WW .100Y.C M.TW WWbetween .100
YTCNT0
M.T
and
W OCR0A,Wand then .100
counter
Y
(TCNT0) is cleared. W O W C O W W
W W
W O W C O
W
W O W C O
W O W
WW .100Y.C M.TW WW
W O
WW .100Y.C M.TW
W O
WW .100Y.C 96
W W
7799D–AVR–11/10 W
. C OM
00Y .TW
W W.1 Y.COM W
Figure 15-5. CTC Mode, Timing
W
W .100
Diagram OM
.T
W . C
M .TW W . 100
Y
M .TW
W O
00Y
OCnx Interrupt Flag Set
W . 1 O M W C O
.C W . W
WW .100Y M.T
W W 00Y .T
W WW .100Y M.T
W W 00 .T
Y.C W WW .100Y M.T
W W 00 .T
W .100 O M.T W
TCNTn . C O W W.1 Y.COM W
W W 00 .T
W O W .C O W W.1 Y.COM W
W W 00 .T
W O OCnW
.C O W W.1 Y.COM W
W
WW .100Y.C M.TW
(COMnx1:0 = 1)
W(Toggle) .100Y M .TW W
W .100 O M.T
W O
W
WW .100Y.C M.TW
O W Y.C 1 .TW WW3 .100Y4.C M.TW
WPeriod
W . 100 O M 2
W O
W
WW .100Y.C M.TW
O
W O W O
W O
WW .100Y.C M.TW An interrupt WWcan.1be Y.C
00generated .T W time the
each WW counter . 1 0 0Y.C reaches
value W
M.T the TOP value by using the
W O M W C O
W O OCF0A Flag. WW If the .C
interrupt is T
. enabled, theW W
interrupt Y.
handler routine Wcan be used for updating
WW .100Y.C M.TW . 1 00Y M
W
W .100 O M.T
the TOP value. W O
However, changing TOP to a value C
W
WW .100Y.C M.TW
O
WW .100Y.C M.TW WW close .10with 0Yto. BOTTOM M .TW
when the counter is run-
O ning with none orW a low prescaler
O value must be done W care
. C O since the CTC mode does not
W
WW .100Y.C M.Thave W the double WW buffering .C
00Y feature. .TIfWthe new value WW written . 1 00Yto OCR0A M .TW is lower than the current
. 1 M
W W .C O
W Wthe W Y
O
.Cwill W W WW 00Y.CO .TW
Y value of TCNT0, W counter 0 miss
M. T the Compare Match. The counter will then have to count to
W
W .100 O M.T W .10
.C O W W.1 Y.COM W
C W .TW
WW .100Y. itsTmaximum
. W
value
W (0xFF) .100
Yand wrap around starting W at .0x00
W 1 Y.COM W
00 before the .T Compare Match can
W CO Moccur. W W . C OM W
WW .100Y. W Y W W 00 .T
W O M.T
W
C W . C
WW .100Y. For generating
W
M.Ton each Compare
aW waveform0output
.1Match0Y in M CTC .TWmode, theW OC0A output
.100 canObe
WOutput M.setT to toggle its logical
W C Olevel W W .C byO setting the Compare W Y .Cmode bits Wto toggle mode
WW .100Y. (COM0A[1:0] M .TW W .
Y
100 valueOwill M .TW W
W
00
.1port O M.T the data direction
= 1). The OC0A
W not be visible on the pin C unless
W
WW .100Y.Cfor the
O
W W Y.C W WW .100Y. TW
M.frequency
M .Tpin is set to W output. W .100 waveform
The O M .Tgenerated will have W a maximum C O of fOC0 =
W W .C O W Y .C W W W 0 Y . .T W
W Y
00 fclk_I/OM T
/2 .whenW W
OCR0A is set to 0
.10zero (0x00). .T
M The waveform frequency .1 0 is definedM by the following
W W.1 Y .C O
equation: W WW 00Y.CO .TW W WW 00Y.CO .TW
W
W 00
W.1 Y.COM W
.T .1 M W.1 Y.COM W
W W WW 00Y.CO .TWf clk_I/O WW 00 .T
W
W .100 O M.T W.1 f OCnx C =OM --------------------------------------------------WW.1 .C OM
.C W . 2  W  1  Y W
WW .100Y M .TW W
W . 100
Y
O M
N.T + OCRnx W
W .100 O M.T
W .CO .TW W Y.C (1,.T8,W64, 256, or W Y .C W
WW .The 1 00YN variable M representsW the prescale
W .100 factor O M
W1024).
W .100 O M.T
W O WW .100Y .C
WW As 0Y.the
0for
C
.TWmode of operation, WW .100Y.C M.TW M .TW
. 1 ONormal
M W the TOV0 O Flag is set in the same W timer clock
. C O cycle that the
W
WW counter 0 C
Y.counts .T
from W MAX to W 0x00.
W 0 0Y.C M.TW WW .100Y M .TW
1 0 . 1 W O
W. OM W O
WW .100Y.C M.TW
W O W O
15.7.3 Fast PWM Mode W
WW .100Y.C M.TW
O
W PWM CO (WGM0[2:0] orW O
WWfast0Pulse
The O
Y.C Width Modulation orWfast Y .mode W =W 3W 7) provides 0Y.C a high Wfre-
Wquency . 1 0
PWM M
waveform .T W
generation
W
option.
W . 0 0
1 The fast O MPWM
. T
differs from the W . 1
other
0
PWM O M.T by
option
WW 00Y.C O Y.C W .C
W The counter WW counts W W Y
.100 from .TW
W its single-slope
W .1 O M.T
operation. W .100 fromOBOTTOM M.T to TOP thenWrestarts
W .C O MBOT-
WW TOP .C .TW
W Y.C and.T W W Y
.100 = 7.OInMnon- .TW
TOM.
W .10is0Ydefined
O Mas 0xFF whenWWGM0[2:0]
W .100 = 3, O M OCR0A when WGM0[2:0] W W .C
WW Compare
inverting Y.C Output .TW mode, theW W Compare
Output Y.C (OC0x) Wis clearedWon the Compare .100
Y .TW
Match
W .100 O M W .100 O M.T W W .C OM
between TCNT0 and OCR0x, and set W atW BOTTOM. C
Y.In inverting WCompareW Output mode, Y the out-.TW
WW .100Y.C M.TW .100 M.T to the single-slope W .100 OM
put is setW on Compare O Match and cleared W W
at BOTTOM. .C O Due W Y.C the.TW
operation,
W W 0 Y .C T W W 0 0 Y . T W W 1 0 0
operating W .10
frequency of M the . fast PWM mode W can .1 be twice M as high as the phase .
WWcorrect OM
PWM
W Y . CO W W W 0 Y .CO .TW W 00 Y.C
W
mode that use.1dual-slope 0 .T
Moperation. This high frequency 0 makes . 1
W
0
CO WW 00Y.CHigh
.1 OM the fast PWM mode WW
well suited
for power WW regulation, 0 Y .rectification, .T W and DAC W applications. T W
frequency
. allows W physically small
sized external
.10
Wcomponents .C OM(coils, capacitors),W and W.1therefore Y . C
M
Oreduces
W total system cost.
W W 00Y .TW W 00 .T
In fast PWM W
W mode, 0the
0 counter .Tis incremented W until .the 100counter value matches the TOP value.
The counter is
W W.1 cleared
then Y .C OM at the W following timer W W clock cycle. The timing diagram for the fast
W
W
W .100 O M.T
WW .100Y.C M.TW
W O
WW .100Y.C 97
W W
7799D–AVR–11/10 W
.C OM
00Y .TW
W W.1 Y.COM W
W 00 .T
PWM mode is shown in Figure 15-6. W W.1The TCNT0 Y .C OMvalue is in the timing diagram shown as a his-
W
togram for illustrating M .TW the single-slope W
W . 100operation. O M .TThe diagram includes non-inverted and
.C O W Y .C W
inverted Y
00 PWM outputs. .T W W
The small horizontal 0 .T
0 line marks on the TCNT0 slopes represent Com-
W.1Matches . C OM W.1 Y.COM W
WTCNT0.
W
pare Y between W OCR0x and
W 00 .T
W
WW .100Y .C
M.T
W
Figure 15-6. .C Fast MPWM .TW Mode, Timing W
W .100
Diagram OM
.T
O W O W .C
00Y
.C .TW WW .100Y M .TW W . 100
Y
M .TW
.1 M W O W O
W
WW .100Y.C M.TW
O
WW .100Y.C M.TW WW .100Y.C M.TW OCRnx Interrupt Flag Set
W O W C O W W .C O
WW .100Y . Y W
WW .100Y.C M.TW M.T
W W 00
W.1 Y.COM W
.T
W O W W . C O W
WW .100Y.C M.TW W .100
Y
M.T
W W 00
W.1 Y.COM W
.T OCRnx Update and
W C O W W .C O W TOVn Interrupt Flag Set
W Y. W W 0 Y .T W W .1 0 0 .T
W .1 00 M .T W . 10 O M W O M
W
WW .100Y.C M.TW
O
W O W O
W
WW .100Y.C M.TW
O
TCNTn WW O W O
W
WW .100Y.C M.TW
O
W. 1 OM W O
W
WW .100Y.C M.TW
O
W O
W O WW 00Y.CO .TW WW .100Y.C M.TW (COMnx1:0 = 2)
WW .100Y.C M.TW OCnx W . 1 M W O
W O WW 00Y.CO .TW WW .100Y.C M.TW(COMnx1:0 = 3)
WW .100Y.C M.TW OCnx W . 1 M W O
W O
W
WW .100Y.C M.TW
O
W O W .CO WW .CO .TW
WW .100Y.C M.TW Period WW 1
.1 02 0Y 3 M.TW4 5 W 6
. 1 00Y7 M
W W .C O
W 00 Y W .1
W.1 Y.CO M.T
The Timer/Counter WW 0Flag
Overflow
.1 OM is set each time
.C(TOV0) WW the counter
OM
Y.C reaches WTOP. If the inter-
W W W 0 Y .T W W .1 0 0 M.T
W . 1 00 M .T W . 1 O M W C O
W O is enabled, the interrupt
rupt
WW .100Y.C M.TW
handler routine can be used WW for updating Y. the compare W value.
WW .100Y.C M.TW W .100 O M.T
W CO W O
.C allows ofW Y. C onW
WW .100Y.In fast PWM
.TW
mode, the WW compare0Y
. 10
unit
M .TW generationW PWM waveforms
.100 M.T
the OC0x pins.
M W O W C O
W .CO the
Setting COM0x[1:0] bits to two will produce a non-inverted
WW .100Y.C M.TW WW PWM Y. an inverted
0and W PWM out-
WW .100Y put can M .TW
be generated by setting
W the COM0x[1:0]
O to three: Setting W .10the O M.T
COM0A[1:0] bits to one
W O W .C
WW .100allows Y.C the .OC0A T W pin toW W
toggle on
.1 0 0Y.C MMatches
Compare .TW if the
WWGM02 . 1 0Y
0bit is set. M .TW
This option is not
W W .C OM
W W W Y .C O
W W WW 00Y.CO .TW
Y
available for the OC0B W
pin (See 0
Table 15-3 on .T page 102). The actual OC0x value will only be
W
W .100 O M.T W .10
.C W 00Y for the W
port pin is setWas output. 00The PWM
WW .visible 100
Y on the.T
M
port
W pin if theWdata direction
W.1the OC0x M.T
ORegister W.1 Match O M.Twaveform is
W generated O by setting (or clearing) C at the W
Compare .C between
WW .100Y .C
.TWclearing (or W W
10the0Y .
M .T W W Y
.100 cycleOM .TWOCR0x
and TCNT0, O M and W
setting) . OC0x O Register at the timer W clock .C the counter is
W
WW cleared 0 C
Y.(changes .T W W
WBOTTOM). 0 0Y.C M.TW WW .100Y M .TW
1 0 from TOP to . 1 W O
W. OM W O
WW .100Y.C M.TW
W be calculated O W O
The
W PWM frequency O for the outputWcan
Y.C
by the followingW equation: Y.C W
WW .100Y.C M.TW W . 1 0 0 M .T W W
W . 1 0 0
O M.T
W O W O f W .C
WW .100Y.C M.TW WWf OCnxPWM Y.C= ------------------
clk_I/O
.TW- W .100
Y
M.T
W
W . 100 ON M  256 W C O
W O W .
Y
M.T
W
W O W O W W .C O
WWfactor .C 64, 256, Y W
WW .100Y.C M.TW
The N variable represents the prescale (1,Y8, Wor 1024). W
W .100 O M.T W .100 O M.T
W O Y.C special W .C
TheWW extreme00values Y.C for .the WOCR0A Register WW .represents 100
W
M.T cases whenWgenerating
W .100
Y a PWM .TW
W .1 O MT W C O W .C OM
waveform
WW output 00Y
C the fast
.in WPWM mode. WWIf the.1OCR0A .
00Y isM set .TW equal to BOTTOM, W the Y
.100
output will .TW
be a narrow W .1spike for O M.TMAX+1 timer clock
each W cycle. Setting
C O the OCR0A equal W W
to MAX .C
will OM
result
W 0Y.Cor low W WW .100Y. .TW W 0Y
.10COM0A1:0 .TW
in a WconstantlyW .10high O M.T output (depending W on the polarity C O Mof the output set by
W Wthe .C OM
W W .100
Y
bits.) W
WW (with Y.C .TW waveform WW .100Y. W W
M.Tmode can be achieved by set-
A frequency W .10050% duty O Mcycle) outputW in fast C PWM
O
WW Y.C W on eachWCompare W Y. W
ting OC0x to toggle
W .100its logical O M.T level W .100MatchO(COM0x[1:0] M.T = 1). The waveform
W have0a0Ymaximum .C W W W 0 Y C
. /2 when OCR0A is set to zero. This
generatedWwill .T frequency of f = f
OC0 .1clk_I/O 0
W.1 OM W
WW .100Y.C M.TW WW
W O
WW .100Y.C M.TW
W O
WW .100Y.C 98
W W
7799D–AVR–11/10 W
.C OM
00Y .TW
W W.1 Y.COM W
W 00 .T
feature is similar to the OC0A toggle W W.1in CTC .C OM except the double buffer feature of the Out-
mode,
W
put CompareOunit
W
M.Tis enabled in the
W fast.1PWM 00Y mode. M.T
W O
00Y
. 1
W Mode O M W O
15.7.4 Phase Correct WWPWM
0 0 Y.C .T W WW .100Y.C M.TW
. 1 M W O
W WWphase
WThe 0 .CO PWM
Ycorrect .T W mode (WGM0[2:0] WW .100=Y1.Cor 5)Mprovides .TW a high resolution phase correct
M .T . 1 0 M W O
PWM waveform
WW 00Y.C O generation option. The phase correct PWM mode is based on a dual-slope
0 Y.C
O
.T W W .T W WW .100Y.C M.TW
0 operation.W. The1 counterM counts repeatedly
W.1 OM .CO .TW WWfrom 0Y
BOTTOM
.CO .TtoWTOP and then from TOP to BOT-
WW .100Y.C M.TW WW TOP
TOM. . 1 0is0 Y
defined M as 0xFF when W WGM0[2:0] . 1 0 = 1, and MOCR0A when WGM0[2:0] = 5. In non-
W W .C O WWCompare
inverting Y .CO Output W
mode, the W WW Compare
Output 0 Y .CO(OC0x) .TWis cleared on the Compare Match
W 00 Y .T W W . 1 0 0 M .T . 1 0 M
.1 M W O W O
W
WW .100Y.C M.TW
O
WW TCNT0
between
00Y
C OCR0x
.and .TW while upcounting, WW .10and 0Y.Cset M on.Tthe W Compare Match while down-
W . 1 O M W O
W O counting. In inverting Output Compare mode,
WW the.1operation .C is inverted. The dual-slope operation
WW .100Y.C M.TW has lower WW .100Y.C M.TW 00Y M.T
W
maximum
W operation
O frequency than Wsingle slope
C O operation. However, due to the sym-
W O
WW .100Y.C M.TW metricW
W Y.C
feature.1of00the dual-slope .T W PWM modes, WW these . 1 0 0Y.modes M .TW preferred for motor control
are
W OM W O
W O
WW .100Y.C M.TW applications. WW .100Y.C M.TW WW .100Y.C M.TW
W O WW 00Y.CO .TW WW 00Y.CO .TW
WW .100Y.C M.TWIn phase W correct . 1
PWM mode M the counter is
Wincremented .1 until the M counter value matches TOP.
W W .C O
W WW reaches Y .COTOP,.TitW W WW 00Y.CO .TW
Y When the W
counter 0 changes the count direction. The TCNT0 value will be equal
W
W .100 O M.T W .10
.C OM W W.1 Y.COM W
C W .TWtiming diagram
WW .100Y. to
WTOP for one
M.Ton Figure 15-7.W
W timer.1clock 00Y cycle. The W 00 phaseMcorrect
for the
W.1 shown
.T PWM mode is shown
W CO TheW TCNT0 .C OM is in the timing W
value diagram Y .C O as a histogram for illustrating
W
WW .100Y. TWdual-slope Y W W 00 .T
W O M.the
W
operation.
W .100 The O M.T includes non-inverted
diagram W W.1 Yand . COMinverted PWM outputs. The
C W . C TW slopes W .TW between OCR0x
WW .100Y. .T
small
W horizontal Wline marks . 1 0 0Yon theM .
TCNT0 representW . 1 0
0Compare
O MMatches
W OM W O
WW .100Y.C M.TW
WW .100Y.C and .T W
TCNT0. WW .100Y.C M.TW
OM W O W O
W
W O
W O
Figure 15-7. PhaseW
W Correct
W PWM .COMode, Timing Diagram WW .100Y.C M.TW
WW .100Y.C M.TW . 1 00Y M .TW W O
W O
W
WW .100Y.C M.TW
O
W O W OOCnx Interrupt Flag Set
W
WW .100Y.C M.TW
O
W O W O
W
WW .100Y.C M.TW
O
W O W O Update
W
WW .100Y.C M.TW
O
WW .100Y.C M.TW WW .100Y.COCRnxM .TW
O W O W .C O
W
W
O W O W .C O
W
WW .100Y.C M.TW WW .100Y.C M.TW WW .100TOVn Y Interrupt.Flag
M T Set
W
O W O W .C O
W
W
O W O W .C O
W
W
O W O W .C O
W
W
O W O W .C O
W TCNTn
W
W O W O W W .C O
Y
M.T
W
W O W O W W .C O
WW .100Y.C M.TW Y W
OCnx
WW .100Y.C M.TW
(COMnx1:0 = 2)
W O
W
W .100 O M.T
W O W .C
WW OCnx Y.C W WW .100Y.C M.TW W (COMnx1:0 .10=03)
Y
M.T
W
Y .TW
W O W C O W W .C OM
WW .100Y.C M.TW
Period 1
WW 2 .100Y. M.T
3 W W .100
Y .TW
W O W C O W W .C OM
WW .100Y. Y W
WW .100Y.C M.TW .TW
Mthe
W
W .100 O M.T
The Timer/Counter W O
Overflow Flag (TOV0) is W
set each C O
time counter reaches W BOTTOM. .C The
WW .can Y.C W WW .100Y. .TW W 0Y
.10BOTTOM
Interrupt Flag W 100 be used O Mto .Tgenerate an interrupt W each Ctime
O Mthe counter reaches W W the
W W
value. W
W .100 O M.T W C O
WW .1PWM .C
00Y mode, W WW .100Y. W
M.T of PWM waveforms on the
In phase correct W O M.Tthe compare unit allows
W O
generation
C
WW 0Y.C W WW produce Y.
OC0x pins. Setting
W .10the COM0x1:0
O M.T bits to two will W .100 a non-inverted PWM. An inverted
Y.C W
PWM output WW 0
can be10generated by
.T Wsetting theW COM0x[1:0] to three: Setting the COM0A0 bit to
W. OM
WW .100Y.C M.TW
W O
WW .100Y.C 99
W W
7799D–AVR–11/10 W
.C OM
00Y .TW
W W.1 Y.COM W
W 0
.10Compare .T
one allows the OC0A pin to toggle W W on .C OM Matches if the WGM02 bit is set. This option is
TWOC0B pin Y W
not availableOfor M.the
W(See Table
W .100 15-4Oon M.T page 103). The actual OC0x value will only
.C .TWpin if theW
W Y.C W pin is set as output. The PWM wave-
be visible
. 1 00Y on the M port data direction
W . 100 forOthe M .Tport
W O
WW form is 0generated0Y.C Mby .TW clearing (or WW setting)
. 10the0Y.C OC0x Register
M .TW at the Compare Match between
W . 1 O W C O
OCR0x and .C
TCNT0 when the counter W increments, Y . and setting
W (or clearing) the OC0x Register at
.TW WW .100Y M .TW W . 100 M .T
M Compare Match O between OCR0x and WTCNT0 when O the counter decrements. The PWM fre-
Y.C
O
00 .T 1
W.1 OM quency W.for the output OM when using phase W correct O PWM can be calculated by the following
equation: WW .100Y.C M.TW
W O W O
W
WW .100Y.C M.TW
O
W O W fCclk_I/O
O
W
WW .100Y.C M.TW
O
WW .100Y.C M.TW WW .100=Y.------------------
f OCnxPCPWM - W
M.T
W O W N C510
O
W
WW .100Y.C M.TW
O
W
W O W C O
W O
WW .100Y.C M.TW The N W
W
variable 00Y
.C .TW WW(1, 8, 0Y.256, TW
M.1024).
W . 1represents O Mthe prescale factor
W .1064, O
or
W O
WW values Y.C WW Y.C .TW when generating a PWM
WW .100Y.C M.TW The extreme . 100 for the M .TW Register
OCR0A represent
W .100 special O Mcases
W O C
W O
WW .100Y.C M.TWwaveformWoutput .in
W 0Y.C TW PWMW
W 0Y.OCR0A M.T isW
W 10the phase .correct
O M mode. If.10
W
the
C O
set equal to BOTTOM, the
W CO output will beW continuously .C low and if set equal W to MAX Y
the . output Wbe continuously high for
will
WW .100Y. M .TW W . 1 00Y M .TW W
W .100 O M.T
O non-inverted PWM W O
mode. For inverted PWM the output will .
YhaveC the Topposite logic values.
W
WW .100Y.C M.TW WW .100Y.C M.TW WW .100 M.
W
W O W C O
W O
WWof period Y2.Cin Figure W a transition Y. from.Thigh W to low even though
WW .100Y.C M.At TW the very start
. 100 M .TW15-7 OCnx Whas
W .100 O M
O there is no Compare W O
Match. The point of this transition Y. C
W
WW .100Y.C MTOM. .TW There are WW .100Y.C M.TW WW is.1to00guarantee M.T
symmetry
W around BOT-
two Wcases that give
O a transition without WCompare C O
Match.
W
WW .100Y.C M.TW
O
W
W O W C O
W O • OCR0A changesWits value Y from
.C MAX, like in Figure W15-7.W When Y.the OCR0A .TW value is MAX the
WW .100Y.C MOCn .TW pin valueWis theWsame . 100 as the M .TW
result of a down-counting W .100Compare O MMatch. To ensure
O C
W
WW .100Y.C M
O
.TW WW .C
00Ythe OCn .T W WW .100Y. M TW
.the
symmetry around BOTTOM . 1 M value at MAX must correspond to result of an up-
W W .C O
W 00 Y counting
.T Compare W Match. .10 0 .1 M
W.1 Y.COM W WW from .C OM WW 00Y.CO .TW
W • The timer starts W
counting 0 Ya value .T
higherW than the W one
W
W.100 O M.T W .10
. C OM W W.1 Y.COM for W
in OCR0A, and that reason
C W .TW
WW .100Y. misses Mup..Tthe
W Compare W Match.1and 00YhenceMthe OCn change W that would 00 have happened
W.1 Y.COM W
.T on the
W Cway O W W .C O W
WW .100Y . W W 00Y .T W W 00 .T
.C W W 00 .T
WW .10Timing0Y .TW W 00 .T W.1 Y.COM W
15.8 Timer/Counter W . C O MDiagrams W W.1 Y.COM W W 0
WW .The Y W W 00 W .1)0is .T
W 100 Timer/Counter O M.T is a synchronous W.1 design M.Tthe timer clock W
Oand WT0
(clk therefore
.C OM shown as a
.C W .C W Y W
WW clock . 1 00YenableMsignal .TW in the following W
W . 00Y The
1figures. O M T
.figures W
include information
W .100 onOwhen M.T Interrupt
W O Y.C WW .10operation. .C
WW Flags 00Y are.C set. Figure
.TW 15-8 contains WW timing 100 data M for W Timer/Counter
.Tbasic 0Y MThe.TWfigure
. 1 O M W . O W .C O
W
WW shows the.Ccount .sequence
TW closeWWto the.10MAX 0Y.Cvalue .inTW all modes other WW than 0Y correct
.10phase M.T PWM
W
. 1 00Y M W O M W .C O
W O WW .100Y
mode.
W
O W O W W .C O
WW 00Y.C
WFigure .TW WWDiagram, Y.C
100 no Prescaling .TW W .100
Y
M.T
W
. 1 15-8. Timer/Counter
M Timing W . O M W C O
W O W .
Y
M.T
W
W O W O W W .C O
WW clkI/O.100Y.C M.TW WW .100Y.C M.TW W .100
Y
M.T
W
W O W O W W .C O
WWclkTn .100Y.C M.TW WW .100Y.C M.TW W .100
Y .TW
W O W C O W W .C OM
WW .100Y.C M.TW
(clk /1) I/O
WW .100Y. M.T
W W .100
Y .TW
W O W C O W W .C OM
Y.C WW MAX.100Y. W Y W
W W
TCNTn
.100 M MAX.TW -1
W O M.TBOTTOM
W BOTTOM
W .100+ 1 OM.T
W O C W .C
W W .100
Y
TOVn W O W C O W W
W W
W O W C O
W
W O W W .C O
WW .C timing .TWdata, butW 00Y
Figure 15-9 shows.1the 00Ysame M with the.1prescaler
W
enabled.
W W .C O W
W 00Y .TW W
W W.1 Y.COM W
W 00 .T
W W.1 Y.COM
W 00
W W.1 100
7799D–AVR–11/10 W
.C OM
00Y .TW
W W.1 Y.COM W
W 00 M.TPrescaler (f
Figure 15-9. Timer/Counter Timing W W.1Diagram, . C Owith clk_I/O/8)
.T W W . 1 0 0Y M .TW
OM W O
0 0
clk Y.C .T W WW .100Y.C M.TW
W.1 I/O
OM W O
W clkTn O W O
.T W WW (clk.10/8)0Y.C M.TW I/O
WW .100Y.C M.TW
OM W O W O
0 Y.C .T W WW TCNTn 0 0 Y.C .T W WW .10MAX 0Y.C M.TW BOTTOM
0 . 1 M
MAX - 1 BOTTOM + 1
W W WW 00Y.CO .TW W
W 00 .T W.1 Y.COM W .1 M
W W.1 Y.COM W WTOVn W WW 00Y.CO .TW
W 00 .T W .10 0 M. T .1 M
W 00 .T W .1 M .1 M
W 00 .T W 1 the M all.1modesCand M
W.1 Y.COM W
Figure 15-10 W.shows .CO .TW
setting of OCF0B in W
W . O OCF0A in all modes except CTC
W W 0 .T mode W
and
W PWM 0 0 Y
mode, where OCR0A is W
TOP. . 1 0 0 Y
M .TW
0 W. 1 OM O
W.1 OM W
WW .100Y.C M.TW
W O Timing Diagram,W W ofYOCF0x, O
W
WW .100Y.C M.TW
O Figure 15-10.
WW Timer/Counter 0 0 Y.C .T W W Setting . 1 0 0 .C Mwith .TWPrescaler (fclk_I/O/8)
W . 1 O M W C O
W
WW .100Y.C M.TW
O
W
clkI/O W O W C O
W
WW .100Y.C M.TW
O
W
W O W C O
W O
WW .100Y.C M.TW (clk Tn/8) W
clk W Y.C .TW WW .100Y. M.T
W
I/O
W . 100 O M W CO
W O W .C W Y. .TW
WW .100Y.C M.TWTCNTn W . 00Y - 1 M.TW OCRnxW W.100 OCRnxO+M
1OCRnx
W O C
O WW .100Y.
W 1 OCRnx + 2
WW .100Y.C M.TW WW .100Y.C M.TW M .TW
W O W O
W O
WW .100Y.C M.TW WW Y.C W
WW .100Y.C M.TOCRnx W OCRnx Value .100
W O M.T
W O C
W
WW .100Y.C M.TW
O
W
W O W C O
W
WW .100Y.C M.TW
O OCFnx
W
W O W C O
W
WW .100Y.C M.TW
O
W
W O W C O
W .CO 15-11 WW .C TW the clearing WWof TCNT0 Y. CTC.Tmode W
WW .100Y Figure
M .TW shows the setting
W . 0YOCF0A
10of O M .and W .100 in O M and fast
W .C O W .C W W Y .C W
WW .100PWM Y mode where
W OCR0A W is TOP. 00Y .T W 00 .T
.C W W 00
WW .10Figure
0Y 15-11. W
M.T Timer/CounterWTiming
W 00
W.1 Diagram,
.T
OM Clear Timer on Compare W.1 Match M.T with Pres-
Omode,
W .C O . C W W Y.C W
WW .100Y M
W (f
.Tcaler W
clk_I/O/8) W .100
Y
O M .T W
W .100 O M.T
W O WW .100Y .C
W
O W O W .C O
W
WW .100clk Y.I/OC .TW WW .100Y.C M.TW WW .100Y M.T
W
O M W O W .C O
W
WW .10clk 0YTn.C M.TW WW .100Y.C M.TW WW .100Y M.T
W
O W O W .C O
W (clk /8)
WW .100Y.C M.TW I/O
W
W TCNTnY.C O W O W W .C O
WW (CTC) .TW TOP - 1 W W.100TOP
W Y.C .TW BOTTOM W 0Y
.10BOTTOM 1 .T
W
. 1 00 M O M W .C
+M
O
W O W
Y
M.T
W
W O W O W W .C O
WW .100Y.C M.TW Y W
OCRnx TOP
WW .100Y.C M.TW W
W .100 O M.T
W O W O W .C
WWOCFnx.100Y.C M.TW WW .100Y.C M.TW W .100
Y .TW
W O W C O W W .C OM
W W .100
Y .TW
W O W C O W W .C OM
W W .100
Y .TW
W O W C O W W .C OM
W W .100
Y
W O W C O W W
W W
W O W C O
W
W O W C O
W O W
WW .100Y.C M.TW WW
W O
WW .100Y.C M.TW
W O
WW .100Y.C 101
W W
7799D–AVR–11/10 W
.C OM
00Y .TW
W W.1 Y.COM W
W 00 .T
15.9 Register Description W W.1 Y.COM W
.TW W 00
W.1 Y.COM W
.T
.C OM W
Y W W 0 .T
15.9.1 TCCR0A – Timer/Counter
W .100 Control O M.T Register A WW.10 .C OM
WWBit .100Y .C 7 .TW 6 W 5 .100Y4 .T
3
W 2 1 0
W O M W O M
.C W Y .C W
.TW WW .100Y
0x24 (0x44) COM0A1
M .TW COM0A0 W
COM0B1
. 100
COM0B0
M
–
.T – WGM01 WGM00 TCCR0A
M O W O
.CO .TW WW 00Y.C
Read/Write R/W
TW 0
R/W
W0W .1000Y.C M
R/W R/W R
.TW 0
R R/W R/W
.100Y M
WInitial Value . 1 0 M.
O W O 0 0 0
W W Y .CO
W 00
W.1 Y.COM W
.T .1 M.T WW Output
.1 OM
W • WBits WW 7:6 – COM0A[1:0]:
0 Y .CO .TW CompareW Match 0 0 Y.CA Mode .TW
W .1 00 M .T . 1 0 M W . 1 O M
W O W O W (OC0A) C
Y.behavior.
WW .100Y.C M.TW
TheseW
W bits control Y.Cthe Output .TW
Compare Wpin .100port functionality M.T
WIf one or both of the COM0A1:0
bits are set, W . 100OC0AOoutput
the M overrides the W
normal O of the I/O pin it is connected
W O
WW .100Y.C M.TW to. However, WW .note .C
00Ythat the .T W WW .100Y.C M.TW
1 M Data Direction Register
W O WW 00Y.CO .TW WW 00(DDR) Y.C
O bit corresponding to the OC0A pin
W
WW .100Y.C M.TW must be Wset in .order
1 to enableM the output W
driver. W . 1 O M.T
W O
W O
WW .100Y.C M.TW When OC0A WW is .1connected 00Y
.C W
.Tthe WW .100Y.C M.TW
W O M to pin, the function
WW of the O COM0A[1:0] bits depends on the
W O
WW .100Y.C M.TWWGM0[2:0] WW bit setting. 0 0 C
Y.Table .T
15-2 Wshows theWCOM0A[1:0] . 1 0 0Y.C bit M.T
W
functionality when the WGM0[2:0]
W . 1 O M W C O
W W .C O Wa normal Y .CCTC mode W W W 0 Y . .T W
W 00 Y .TWbits are set W to
.10 0 or
M. T (non-PWM). .1 0 M
W 00 .T W .1 OutputM .1 M
W W.1 Y.COM Table W
15-2. Compare
WW 00Y.CO .TW
Mode, non-PWM Mode
W WW 00Y.CO .TW
W 00 .T W .1 M
W.1 Y.COM COM0A1 W.1 Y.CDescription
COM0A0
W OM
W WW 00Y.CO .TW
W W W 0 T W
W 00
W.1 Y.COM W0
.T 0 .1
0 M. .1
WWdisconnected. OM
WW Y CO port
.Normal W operation, OC0A
W 0 Y.C W
W W
. 1 00 M .T W
W .1 0 0
O M . T
W .1 0
O M.T
W O 0 1 Toggle OC0A on Compare W
W Match.100Y. C
W
W O W C O
W O 1
WW .100Y.C M.TW
0 Clear OC0A on Compare W W
Match Y. W
WW .100Y.C M.TW W .100 O M.T
W O C
W
WW .100Y.C M.TW
O 1
W1W .10Set .C on.TCompare
0YOC0A W Match WW .100Y. M.T
W
W O M W C O
W
WW .100Y.Table CO
.TWshows the WW .100Y.C M.TW WW .100Y. .TW
Mbits
M15-3 COM0A[1:0]
W bit O functionality when theW WGM0[1:0] C O are set to fast
W
WW .100Y .CO .TW
PWM mode. WW .100Y.C M.TW WW .100Y. M .TW
OM W O W O
W
W Mode, Fast O PWM Mode (1) W O
W Table O
WW .100Y.C M.TW
15-3. Compare Output
W O
W COM0A1 O COM0A0 WDescription W .CO .TW WW .100Y.C M.TW
WW .100Y.C M.TW W .1 00Y M
W W 0CO
. W 0 W
Normal .CO .TOC0A
W portYoperation, W disconnected.
W WW 00Y.CO .TW
Y W 0
W
W .100 O M.T 0
W.1 = 0:YNormal .C OMPort Operation, OC0A W W.1 Y.COM W
.C W W
WW .100Y .100
W Disconnected. .T
WGM02
0 M .TW 1 W
WGM02 W . 1=01:0
Toggle O M
OC0A
.T
on Compare W
Match. C OM
W .C O W Y . C W W W 0 Y . W
WW .100Y M .TW W
W .100on Compare O M .T W .10 O M.T
W 1 O 0 Clear OC0A Match, set OC0A
WW .100Y
at TOP .C
W
W 1 O W O W W .C O
WW .100Y.C M.TW
1 Set OC0A on Compare Match, clear OC0A Wat TOP .100Y W
O W O W .C
WW 1.00AY.special
Note: C case Woccurs when WW OCR0A0equals 0Y.C TOP and WCOM0A1 W Y
.100case, the
is set. In this .TW
MCom-
W
W .1 pare Match O M.Tis ignored, but theWset W .1 clear O M.T W W .C O
0Y.C M.TW
or is done at TOP. See “Fast PWM Mode” on page 97
WW .10for .C
0Ymore .T W W 10 W . 100Y M .TW
OM details. W . O W O
W
W O W O
W
WW .100Y.C M.TW
O
W O W O
W
WW .100Y.C M.TW
O
W O W O
W
WW .100Y.C M.TW
O
O W O W
W
W O W O
W O W O
W O W
WW .100Y.C M.TW WW
W O
WW .100Y.C M.TW
W O
WW .100Y.C 102
W W
7799D–AVR–11/10 W
.C OM
00Y .TW
W W.1 Y.COM W
Table 15-4 shows the COM0A1:0
W 100
W.functionality
bit
.T
OMwhen the WGM0[2:0] bits are set to phase cor-
W .C
rect PWM mode. M .TW W . 100
Y
M .TW
W O
. 1 00Y M
O
W 15-4. Compare Output Mode,
Table W
WW Phase .CO .PWM
Correct TW Mode
(1)
WW .100Y.C M.TW . 1 00Y M
W O W O
.T W WWCOM0A1 0 0 Y.C COM0A0 .T W WW .100Y.C M.TW
Description
W. 1 OM
OM WWoperation, .CO .disconnected.
00 Y.C .T W WW 0 .100Y.C M0.TW Normal Wport . 1 00Y OC0A M TW
.1 M W O W O
W O
WW 0 .100Y.C M W WGM02W=W0: Normal Y.C .TW OC0A Disconnected.
WW .100Y.C M.TW 1 .T W . 100 Port Operation,
O M
W O
WW .100Y.C M.TW
W O WGM02 = 1: Toggle OC0A on Compare Match.
W O W O
Y.C 0 .TWClear OC0A WW onW Compare CO when
0Y.Match Wup-counting. Set OC0A on
WW .100Y.C M.TW WW 1
. 1 0 0 M Compare Match .
when 1 0 down-counting. M.T
W O W O
W
WW .100Y.C M.TW
O
W O Set OC0A on CompareW Match O up-counting. Clear OC0A on
when
W
WW .100Y.C M.TW
O 1 W
W 0 0 Y.1C .T W
Compare WWwhen.1down-counting.
Match 0 0Y.C M.TW
. 1 M W O
WW .100Y.C M.TW Note: W 1
1. A special
WWMatch
. case occurs OM when OCR0A equals WW TOP O
andCCOM0A1 is set. In this case, the Com-
W
WW .100Y.C M.TW
O
Wpare 0 0 Yis.Cignored,.T Wthe set or W
but clear is done . 1 0 0atY.TOP. See
M . W
T“Phase Correct PWM Mode” on
W . 1 M
Odetails. W C O
W CO pageW 99 for more.C W Y . W
WW .100Y. M.T
W W .100
Y .TW W 00
W.1 Y.COM W
.T
W CO W W .C OM W
WW .100Y. W W
M.T• Bits 5:4 – COM0B[1:0]:
Y
.100 Compare .TWMatch Output W B.1 00
Mode OM
.T
W CO W W .C OM W W Y .C W of the COM0B[1:0]
WW .100Y. M TW bits control
.These W the.1Output 00Y Compare M .TW pin (OC0B) W behavior.
W .100 If one O Mor.Tboth
W O W O W functionality Y. C
WW .100Y.C Mbits .TWare set, the W output
WOC0B Y.Coverrides .TWthe normalWport W .100
W
M.T I/O pin it is connected
of the
W . 100 O M C O
W O to. However, noteWthat the Data Y.C Direction Register WW (DDR) bit0Y .
corresponding W to the OC0B pin
WW .100Y.C M.TW W .100 theOoutput M .TW W .10 O M.T
must be set in order W
to enable driver. C
W
WW .100Y.C M.TW
O
W
W O W C O
W OWhen OC0B is connected
WW .10to0Ythe .C pin, .the TWfunction W ofW the COM0B[1:0] Y. bits
.TWdepends on the
WW .100Y.C M.TW M W 100
.functionalityO Mwhen
WGM0[2:0] bit setting. W
Table 15-2 O
shows the COM0A[1:0] bit C the WGM0[2:0]
W
WW .100Y.Cbits M
O
W to a normal
.Tset WWor CTC Y.C
00mode .TW WW .100Y. M .TW
are W .1 O M
(non-PWM). W O
W
WW .100Y.C M.TW
O
W O W O
WW .100Y.C M.TW
[
W
WW .100Y .CO .TW WW .100Y.C M.TW
TableO15-5.M Compare Output W Mode, non-PWM O Mode W O
W
WW .100Y.COM0B1C
OM DescriptionO
W W O
WW .100Y.C M.TW
W COM0B0
W port operation, O W O
W
WW .100Y.C M.TW
0O 0 Normal
WW .100Y.C M.TW
OC0B disconnected.
WW .100Y.C M.TW
W W 0CO
. W 1 W OC0B
Toggle
W Y .Con OCompare Match
W W WW 00Y.CO .TW
Y W 0 .T
W
W .100 1 OM.T .1
WOC0B
0
.C OM W W.1 Y.COM W
.C 0 W
Clear on Compare WMatch
WW .100Y M .TW W
W . 100
Y
O M .T W
W .100 OM
.T
W 1 .C O 1 SetWOC0B on .C
Compare
Y Match W W W 0 Y .C W
WW .100Y M .TW W
W .100 O M .T W .10 O M.T
W O WW .100Y .C
WWTable.1015-3 0Y.Cshows W
.Tthe WW .100Y.C M.TW W
M.Tto fast
O M COM0B[1:0] bit
W functionality O when the WGM0[2:0]
W W bits are
.C O set
WW mode.
WPWM 00Y
.C .TW WW .100Y.C M.TW W .100
Y
M.T
W
WW .100Y.C M.TW WW .100Y.C M.(1) TW W .100
Y
M.T
W
TableW15-6. .Compare O Output Mode, W
Fast PWM O
Mode W W .C O
WW .100Y C M.TW WW .100Y.C M.TW W .100
Y
M.T
W
W O W O W W .C O
COM0B1
WW .100Y.C M.TW
COM0B0
WW .100Y.C M.TW
Description W .100
Y .TW
W O W C O W W .C OM
WW .100Y.C M.TW
0 0 Normal portWW operation,0Y .
OC0B disconnected.
M.T
W W .100
Y .TW
W O W .10 O W W .C OM
W Y. C Y .TW
W0W .100Y.C 1 M.TWReserved W .100 M.T
W W
W .100 OM
W O W .C O W Y .C
Y.C0 onW W at TOPW
W 1W
.100 M.T
Clear OC0BW
W Compare
W .100
Y
Match,
O
set.T
M
OC0B
W .100
W O W C
Y. clear OC0B W
1WW Y1.C W OC0B onW
Set Compare
.100
Match,
M.T
W at TOP W
W .100 O M.T W C O
WW Y.C W WW TOP Y. W
Note: 1. A special
W .100case occurs O M.Twhen OCR0B equals W .100 and COM0B1 O M.T is set. In this case, the Com-
W Match C
is.ignored, WW is done C
Y.TOP. See “Fast PWM Mode” on page 97
Wpare 00Y
.1details.
but
M.T
Wthe set or clear .100
at
for more W O W
WW .100Y.C M.TW WW
W O
WW .100Y.C M.TW
W O
WW .100Y.C 103
W W
7799D–AVR–11/10 W
.C OM
00Y .TW
W W.1 Y.COM W
W 0
.10functionality .T
Table 15-4 shows the COM0B[1:0] W Wbit .C OM when the WGM0[2:0] bits are set to phase
W Y W
correct PWMOmode. M.T
W
W .100 O M.T
00Y
. 1 M
O
W 15-7. Compare Output Mode,
Table WW Phase
W .CO .PWM
Correct TW Mode
(1)
WW .100Y.C M.TW . 1 00Y M
W O W O
.T W WWCOM0B1 0 0 Y.C COM0B0 .T W WW .100Y.C M.TW
Description
W. 1 OM
OM WWoperation, .CO .disconnected.
00 Y.C .T W WW 0 .100Y.C M0.TW Normal Wport . 1 00Y OC0B M TW
.1 M W O W O
W O
WW .100Y.C M.TW WW 0 .100Y.C M 1 .TW Reserved WW .100Y.C M.TW
W O W O W
WWon Compare .CO .when
WW .100Y.C M.TW WW1 .100Y.C 0M.TW Clear OC0B . 1 00Y Match M TW up-counting. Set OC0B on
W O W O
W O
WW .100Y.C M.TW
Compare Match
WW when Y.C
down-counting. W
WW .100Y.C M.TW W .100 O M.T
O W O Y.C when.Tup-counting.
W
WW .100Y.C M.TW W1W .100Y.C1 M.TW
Set OC0B on WW Compare 0 Match
.10down-counting. M
W Clear OC0B on
W O Compare Match W
when O
W
WW .100Y.C M.TW
O
W O Note: W
1. A special Y case O
.C occurs when
W OCR0B WW TOP
Wequals .COCOM0B1
0Yand .TW is set. In this case, the Com-
WW .100Y.C M.TW WWpare Match . 1 0 0 M .T . 10 MSee
W is ignored,
O but the set or clear is
W done at O
TOP.
C “Phase Correct PWM Mode” on
W
WW .100Y.C M.TW
O W 99 0for Y.C .TW WW .100Y. M.T
W
Wpage
W . 1 0 moreOdetails.M W C O
W
WW .100Y.C M.TW
O
W
W O • Bits 3:2 – Res: W Reserved O Bits W W .C O
WW .100Y.C M.TThese W WW Y.C .TW read asWzero.W.100Y OM.TW
bits are reserved
W . 100 and will O Malways
W
WW .100Y.C M.TW
O
W O W Y.C
O WW 00Y.CO .TW
WW .100Y.C M• .TBits WW .100Waveform
W 1:0 – WGM0[1:0]: W
.TGeneration WMode
W O Combined with theWWGM02 W .CO
M W.1 Y.COM W
WRegister,
.C bit found.TinWthe TCCR0B these bits control the counting
W W
. 1 00 Y
M .T W W
W .10 0 Y
O M
W
W .100 O M.T
W Osequence of the counter, the source for maximum (TOP) WW counter .C
Yvalue, andW what type of wave-
WW .100Y.C form W
.Tgeneration WW .100Y.C M.TW .100supported M.Tby the Timer/Counter
M to be used,
W see Table
O 15-8. Modes of W
operation C O
W
WW .100Y.C unitMare:
O
.TWNormal mode WW(counter), Y.C .TW on Compare WW .100Y. W
M.T and two types of
W . 100 Clear O M Timer Match
W (CTC)
C O mode,
W O
WW (PWM) Y.C (see W Y. .TW
WW .100Y.CPulse M .TW Modulation
Width .100 modes M .TW “Modes ofW Operation”
W .100on page O M96).
W O C
W
WW .100Y.C M.TW
O
W
W O W C O
W
WW .100Y .CO 15-8. .TW Waveform WW Y.C .TW WW .100Y. M.T
W
Table M Generation
W .100 Mode O M Bit Description W C O
W O WW .100Y .
WW .100Y.C M.TW WW .100Y.C Timer/Counter M .TW M.T
W
O W O W .C O
W
WW .100Y.C M.TW WW .100Y.CModeMof.TW WW .10Update 0Y ofM.TW TOV Flag
W Mode O WGM2 WGM1 W
WGM0 C O
Operation TOPW W OCRx .C O
at (1)(2)
WW .100Y .C
.T W W W
1 0 0Y .
M .T W W . 1 00 Y
M .TWon
Set
OM 0 . W O
W 0 0 W
WW 0 .100Y .CO .TW
Normal WW Immediate
0xFF
00Y
.C W
MAX
WW .100Y.C M.TW M W . 1 O M.T
O W O .C
W
WW .1100Y.C 0M.TW 0 WW1 .10PWM, 0Y.C Phase .TW WW .TOP
0xFF 100
Y .TW
MBOTTOM
O W Correct O M W .C O
W
WW .100Y.C M.TW WW .100Y.C M.TW WW .100Y MMAX.TW
2 O0 1 0 W CTC O OCRA W
Immediate .C O
W
W
W 3 0O 1 1 W Fast PWM O 0xFF W WTOP .C O MAX
Y
M.T
W
W O W O W W .C O
4
WW .100Y.C M.TW
1 0 0 W Reserved Y.C W – W – .100Y – TW
M.
W O
W
W .100 O M.T W W .C O
.C W PWM, Phase
Y .C W W 0 Y W
W
W 5 .100Y 1
M.T
0W 1 W
Correct
W .100 O M.T OCRA TOP .10 BOTTOM
W O M.T
W O W .C
W6W .1001Y.C M1.TW WW .100Y.C M.TW W .100
Y .TW
W O 0 W
Reserved C O – – W W .C– OM
WW .100Y.C M.TW WW .100Y. TW
M.OCRA
W .100
Y .TW
7 W 1 O 1 1 Fast WPWM C O TOP W W .
TOPC OM
W W .100
Y .TW
Notes:WW Y.C W WW .100Y. M.T
W W .100
Y
1. MAX
W .10=00xFF OM.T W C O W W
W2.WBOTTOM Y=.C0x00 .TW WW .100Y. M.T
W W
W .100 O M W C O
W
W O W C O
W O W
WW .100Y.C M.TW WW
W O
WW .100Y.C M.TW
W O
WW .100Y.C 104
W W
7799D–AVR–11/10 W
.C OM
00Y .TW
W W.1 Y.COM W
W 00 .T
15.9.2 TCCR0B – Timer/Counter Control Register BWW.1 .C OM
.T7 W Y W
M
W
W . 100 4 OM.T 3
.CO .TW
Bit 6 5 2 1 0
0x25.1 00Y
(0x45) FOC0A FOC0B WW – .100Y.C – M .TW
WGM02 CS02 CS01 CS00 TCCR0B
W W .C OM WRW 00YR.CO R/W W
Y W W .T
W .100 .T
Read/Write W W R/W R/W R/W
OM .1 OM 0
WValue C 0 W
W 0Y.C
.TW W WInitial
1 00 Y . 0
M .T W 0
W . 1 0 0 M .TW 0 0 0
M . O W O
.CO .TW WW 00Y.C .TWOutput Compare WW .1A00Y.C M.TW
.100Y M
W
• Bit 7 –.1FOC0A:
W O Force
M W .CO .TW
W O Y.isC WW 0Yspecify
WW .100Y.C M.TW WW
The FOC0A . 1 0 0
bit only M .T
activeW when the WGM . 1 0
bits Ma non-PWM mode.
W W .C O
W 00 Y .T W
However, 1 ensuring .1 devices, M this bit must be set to zero when
W.1 Y.COM W W W.for Y . CO
M compatibility with
W
future
WW 00Y.CO .TW
W W
TCCR0B is written 0 when .T W
W 00 .T
W.1 Y.COM W an immediate .10 Moperating in PWM mode.
W.1 When writing
M
.CO Generation
a logical one to the FOC0A bit,
W W WW Compare 0 Y .CO Match T W is forced Won Wthe 0
Waveform
0 Y .T W unit. The OC0A output is
W
W .100 O M.T W .10 O M. W W.1NoteY.that C OM
changed W according .
toC its COM0A1:0 bits setting. the W
FOC0A bit is implemented as a
WW .100Y.C M.TW W .
Y
100it is the M .TW W
W .100 O M.thatT
W O
WW .100Y.C M.TW
W O strobe. Therefore value present in the COM0A1:0 bits determines the effect of the
WW .100Y.C M.TW forced compare. WW .100Y.C M.TW
W O W O
W
WW .100Y.C M.TW
O
O W O the timer in CTC mode using
W O A FOC0A strobe WW will00not Y.Cgenerate Wany interrupt, WW .100Y.C M.TW
nor will it clear
WW .100Y.C M.TW OCR0A as TOP.W.
W 1 M .T
W O
O
W
WW .100Y.C M.TW
O
W O
W O The FOC0A bit W is Walways read .COas zero. WW .100Y.C M.TW
WW .100Y.C M.TW W . 1 00Y M .TW
W O W O
Y.C Compare WW .CO
WW .100Y.C M• .TBit W 6 – FOC0B: WWForce . 1 00Output M .TW B W W.100Y OM.TW
W O
is W
W .CO the.TWGM WW a .non-PWM 00Y
.C .TW
WW .100Y.C The M . T W
FOC0B bit W only active
.1 0 0Ywhen M
W bits specify
W 1 O
mode.
M
O W O Y. C
W
WW .100Y.C However, .TW for ensuring WW compatibility Y.C TW future devices, WW .this 100 bit must M.T
W
M W . 100 O M .with W C O be set to zero when
W O W operating Y.C in PWM WWwriting Y. .TWto the FOC0B bit,
WW .100Y.C TCCR0B M .TWis writtenWwhenW . 100 M .TWmode. When W .100a logical O Mone
O O C
Y. unit. The
W
WW .100Y.Can immediate .TW
Compare WW Match C
isY.forced on.TW the Waveform WWGeneration .100 M.T
WOC0B output is
M W .100 O M W C O
W CO
changed according to its
WW .100Y.C M.TW
COM0B[1:0] bits setting. Note W Wthe FOC0B
that Y. bit is .implemented
W as a
WW .100Y.strobe. M .TW
Therefore it is the value present in the COM0B[1:0] W
bits .100determines
that O M T the effect of the
W O C
W
WW .100Y .CO .TW WW .100Y.C M.TW WW .100Y. M.T
W
forced M compare. W O W C O
W .CO .TW WW .100Y .
WW .100AYFOC0B WW .100Y.C M.TW M .TW
O M strobe will not generate
W any O
interrupt, nor will it clear W the timer .C O
in CTC mode using
W
0Y.C as
WW .10OCR0B .T W WW .100Y.C M.TW WW .100Y M .TW
M TOP. W O W O
W
WW .The .CO .TW WW .100Y.C M.TW WW .100Y.C M.TW
00YFOC0B
W W 1
.C OMbit is always readW
W
asWzero. .CO
Y W W WW 00Y.CO .TW
Y W 0 .T
W
W .100 O M.T 0
W.1 Y.COM W W W.1 Y.COM W
.C W
WW • .Bits
1 00Y5:4 – Res: M .TW ReservedW Bits .100
W O M .T W
W .100 OM
.T
WW These . 1 00bitsY are reserved
M .TW bits and W will always
W . 100 readOas M
zero.
.T W .10 O M.T
W O WW .100Y .C
W
• Bit 3 – WGM02: O Waveform GenerationW Mode O W W .C O
WW 00Y.C
WSee TW
.in WW .100Y.C M.TW W 00Y
.1page M.T
W
W the. 1 description O M the “TCCR0A – Timer/Counter
W O Control Register A”
W W
on 102.
.C O
Y
M.T
W
W O W O W W .C O
W 2:00–0Y
•WBits .C
CS0[2:0]: W Select
Clock WW .100Y.C M.TW W .100
Y
M.T
W
TheWW three Clock Y.C Select bits Wselect theWclock W source Y.C to be used Wby the Timer/Counter.
W .100
Y .TW
W .100 O M.T W .100 O M.T W W .C OM
Y.C Select WW 0Y. C W Y .TW
TableWW15-9..100Clock W
M.T Bit DescriptionWW.10 O M.T
W
W .100 OM
W O C W .C
WW CS01 Y.C W W 0Y. M.T
W W .100
Y .TW
CS02
W .100 CS00 O M.TDescription WW.10 C O W W .C OM
W Y.C W Y. W W .100
Y
0W W 0.100 0 OM.T
W
No clock source (Timer/Counter W .100 M.T
stopped)
O W W
WW .100Y. C
WW 0 .100Y.C 1 OMclk .TW/(No prescaling) M.T
W W
0 W W C O
WW .100Y.
I/O
WW .100Y.C M.TW M.T
W
0 1W 0 O clkI/O/8 (From prescaler) W C O
0 1 W 1 .COclkI/O/64 (From prescaler) W
WW .100Y .TW WW
W O M
WW .100Y.C M.TW
W O
WW .100Y.C 105
W W
7799D–AVR–11/10 W
.C OM
00Y .TW
W W.1 Y.COM W
W 00 .T
Table 15-9. Clock Select Bit Description W W.1 Y.(Continued) C OM
M .TW W . 100 M .TW
O W O
WW .100Y.C M.TW
CS02 .C CS01 CS00 Description
. 1 00Y M .TW
W1 0 O 0 clkI/O/256
WW (From
W .CO .TW
prescaler)
WW .100Y.C M.TW . 1 00Y M
W W1 Y 0CO
. 1W clkI/O/1024
W WW (From prescaler)
0 Y .CO .TW
.T W W .100 M.T .1 0
OM 1W 1.CO WWsource .CT0 OM
Y.C W W W 0 Y 0 W ExternalWclock
.T 0 0 Y on pin..T W on falling edge.
Clock
.100 M .T . 1 0 M W . 1 O M
W O 1 W 1 .C O W source Y.C
WW .100Y.C M.TW WW 1 00Y M
1 TW External W
. clock
. 100
on T0 pin. Clock
M .TW on rising edge.
W . O W O
W
WW .100Y.C M.TW
O
WW .pin Y.C
00modes W
.Tused WW .100Y.C M.TW
If external 1 are
M for the Timer/Counter0, transitions on the T0 pin will clock the
W W .C O
W W W Y .C O
W W WW 00Y.CO .TW
W 00 Y .T W
counter even 0
.10if the pin M T
is. configured as an output. .1 This feature M allows software control of the
W W.1 Y.COM W counting. WW 00Y.CO .TW W WW 00Y.CO .TW
W 00 .T W .1 M .1 M
W15.9.3.100 TCNT0M–.T W .1 M .1 M
W W .C O Timer/Counter Register
W 00 Y .T W .17 .1 M
6M
W W.1 Y.COM W Bit WW 00Y.CO .TW
5
W
4
WW 300Y.CO 2 .TW 1 0
W 0 0 .T W 1 . 1 M
W.1 Y.COM WRead/Write WWR/W
0x26 (0x46) . OM
.CR/W
TCNT0[7:0]
WWR/W00Y.CR/W O
W
TCNT0
W W 0 Y T W W .T
M.
R/W R/W R/W R/W
W 00 .T .10 .1 M
W W.1 Y.COM W Initial Value WW 0
Y 0O
.C 0W 0
W WW0 00Y.C0O .TW 0 0
W 00 .T W . 10 0 M .T .1 M
. 1 O M W O W .C O
W
WW .100Y.C M.The TW Timer/Counter WW Register Y.C gives.Tdirect W access, WWboth.1for 00Yread and W
M.Twrite operations, to the
W . 100 O M W C O
W O Timer/Counter unit
WW 8-bit .C Writing
counter. to the TCNT0 WW Register Y. blocks.T (removes)
W the Compare
WW .100Y.C MMatch .TW on the following . 00Y
1timer M .TW W 100
.(TCNT0) O M the counter is running,
W O
clock. Modifying the counter C while
W
WW .100Y.C introduces
O
.TW WofWmissing Y.C .TW WW .100Y. .TW
M a risk W .100a Compare O M Match between TCNT0
W andC
MOCR0x
the
O Registers.
W W Y . C O
W W W 0 Y .C .T W W W 0 0 Y. .T W
W 00 .T 0
W.1 Y.COM W .1 M
15.9.4 W
OCR0A W.1 – Output .C OMCompare Register
W WA W WW 00Y.CO .TW
Y W 0 .T
W 00
W.1 Y.CO M.T 0
W.1 Y.C5OM W W.1 Y.COM W
7 WW 6 3 WW 2 00
W W M.T
Bit 0 T 4 1 0
W 1 00 M .T .10 M . W .1 O
. W O C
W
WW .100Y.CRead/Write
O
0x27 (0x47)
.T W WWR/W .100YR/W .C .T WOCR0A[7:0]
WW .100Y. M .TW
OCR0A
M R/W W O M R/W R/W W
R/W R/W O R/W
W
WW .100YInitial .COValue.TW 0 WW0 .100Y0.C M.0TW 0 WW 0 .100Y.0C M.T0W
OM W O W O
W
WW .100The Y.COutput.TCompare W WW A.1contains 0 0Y.C an .TW value that WW .100Y.C M.TW
OM Register M 8-bit is continuously
WW 00Y.CO .TW
compared with the
W W Y .C W W W W
0 Y .CO .TW W
W
W
counter
.100 O
value
M.T (TCNT0). A match 0
can
W.1 Y.COM W
be used to generate an W.1 Y.COMinterrupt,
Output
W
Compare
W
or to
.C W W 00 .T
WW .generate 100
Y a waveform
M.T
W output W on the.1OC0A 00 pin. .T
W.1 Y.COM W
W C O W W . C OM W
WW .10Compare 0Y . .TW W 00Y .T W W 00 .T
15.9.5 OCR0B – Output W O MRegister B W.1 Y.COM W W W.1 Y.COM W
. C W W 0 .T
WW Bit.100Y M.T7
W W
5 .1
00 4 M.T 3 0
W1.1 Y.C0OM W
W C O 6
W W .C O 2 W
WW 0x28.1(0x48) . W 00 Y W W 0 0 .T
00Y M.T
W
W.1 YOCR0B[7:0] OM
.T W.1 Y.COMOCR0B
W .C O W . C W W W 0 W
WWRead/Write .1 00Y M
R/WTW
. R/W W R/W .100R/W
W O M .T
R/W R/W R/W 10 R/W
W . O M.T
W Value O 0Y.C W
W 0 .100Y .C W
WW .100Y.C M.TW
Initial 0 0
WW 0
. 100 M
0 W
.T
0 0
M.T
O W O W W .C O
WTheWW Output0Y
0
.C
Compare
.TRegister
W WW .an
B contains
100
Y.C value.Tthat
8-bit W is continuously
W 100
Y
.compared M.Tthe
with W
W . 1 O M W O M W W .C O
counter
WW .100Y.C M.TW
value (TCNT0). A match can WW be used0to Y.C generateW an OutputW Compare0interrupt,
.1 0
Y W
or to
M.T
generate W a waveform O output on the OC0B W .10
pin. O M.T W W .C O
Y .TW
W O W C O W W .C OM
15.9.6 TIMSK0 – Timer/Counter WW Interrupt Y.C Mask W WW .100Y. M.T
W W .100
Y .TW
W .100 O M.T Register W C O W W .C OM
Bit WW Y.C W WW 4 .100Y.3 M.T2
W 1 W 0 .100
Y .TW
W . 100 7 OM.6T 5
W C O W W .C OM
–. 0Y
(0x6E) W – .C
Y – W –
WW– .100Y OCIE0B
M.T
W OCIE0A W TOIE0 .10TIMSK0
W
Read/Write W .100R O MR.T R R W R .CO R/W R/W W
R/W W
WW .1000Y.C 0M.TW 0
Initial Value
WW 0 .1000
Y
M0 .T
W
0
W
0
W O W C O
WW .100Y.C M.TW WW .100Y. M .T W
• Bits 7:3W–W W Reserved
Res: Y .CO Bits W W WW 00Y.CO
0 0 M. T .1
These bits areWreserved W.1 Ybits .COand .will W always read Was Wzero.
W 0 0 T W
W.1 OM
WW .100Y.C M.TW
W O
WW .100Y.C 106
W W
7799D–AVR–11/10 W
.C OM
00Y .TW
W W.1 Y.COM W
• Bit 2 – OCIE0B: Timer/Counter
W .100 Compare
WOutput OM
.T
Match B Interrupt Enable
W W W 0Y .C TW
.T . 1 0 M .
When the OCIE0B OM bit is written W to one, and CO theTI-bit in the Status Register is set, the
0
Timer/Counter 0 Y.C Compare .T W MatchW B
W
interrupt . 1 0 0isY.enabled. M . W
The corresponding interrupt is executed if
W W.1 Y.COM W W
Woccurs, 0 Y
O
.Cwhen W
a Compare Match in Timer/Counter W 0 i.e., .T
the OCF0B bit is set in the Timer/Counter
W
W Interrupt
WW .100Y Flag .C Register W – TIFR0. W 00 .T
Y.C W .C
W W 00Y .TW W 00
W.1 Compare
.T
W .100 O M.T • Bit W 1 –.1OCIE0A:
C O MTimer/Counter0 Output
W .C OMMatch A Interrupt Enable
WW .100Y.C M.TW WW the.10OCIE0A
When 0Y .
M
W
bit.Tis written W to one, .and
Y
100 the O M
I-bit .TinWthe Status Register is set, the
O W O W .C
W
WW .100Y.C M.TW WW .100YCompare
Timer/Counter0 .C W
.TMatch WW is.1enabled.
A interrupt 00Y The
M
W
.Tcorresponding interrupt is executed
W O W O M W W . C O
W . C Y W
WW .100Y.C M.TW if a W Compare00Match Y
.1 0 Interrupt
in .Timer/Counter0
M Flag TW W occurs, 00 i.e., when
W.1 Y.COM W
.T the OCF0A bit is set in the
W O Timer/Counter W W .C O Register – W
TIFR0.
WW .100Y.C M.TW W .100
Y
M.T
W W 00
W.1 Y.COM W
.T
W O W W .C O W
WW .100Y.C M.TW • Bit 0W– TOIE0: Y
.100Timer/Counter0 M.T
W Overflow W Interrupt
W.1 Y
00 Enable
OM
.T
W O W W .C O W .C W
WW .100Y.C M.TW When the W TOIE0 .
Y
100bit isOwritten M .TW to one,W and the
W .10I-bit0 in the
O M.TStatus Register is set, the
O W .C
W
WW .100Y.C M.TWTimer/Counter0 WW Overflow Y.C interrupt .TW is enabled. WWThe.1corresponding00Y W
M.T interrupt is executed if an
W . 100 O M W C O
W O overflow inWTimer/Counter0
W 0Y.C occurs, i.e., whenWthe W TOV0 Y. is set in
bit W
the Timer/Counter 0 Inter-
WW .100Y.C M.TW . 10TIFR0. M .TW W .100 O M.T
rupt Flag Register W – O C
W
WW .100Y.C M.TW
O
W
W O W C O
W
WW TIFR0 .CO .TW WW Flag Y.C .TW WW .100Y. M.T
W
15.9.7
. 1 00Y– Timer/Counter
M 0 Interrupt
W . 100 Register O M W C O
W
WW .100Y.C M.Bit
O
TW WW Y.C 5.TW WW3 .100Y2. M.1T
W
7
W . 1006 O M 4
W C O 0
W C O W .C W Y . W
WW .100Y. M
0x15
.TW
(0x35) W –
.10R0
– Y –
M .TW – W –
W .100
OCF0B
O M.T
OCF0A TOV0 TIFR0
W O C
W
WW .100Y.C Initial
O Read/Write
W
R W Y.C R
.TW 0
R
WW .100Y.
R R/W R/W
.TW
R/W
M .TValue W0 W . 1000 O 0M 0 W 0
C O M
0 0
W W Y .C O
W W W 0 Y .C .T W W W 0 0 Y. . T W
W 00 M.T .10 M .1 M
W W.1 Y.C• OBits 7:3
W – Res: ReservedWW Bits Y .CO .TW W WW 00Y.CO .TW
W 0
W 00
W.1 Y.These
.T
OM bits are reservedWand
0
W.1will always .CO read
M W.1 Y.COM W
W C W W 0 Y .T Was zero. WW 00 .T
W
W .100 O M.T W .10
.C W .TW
WW .100Y • BitO2M–.T
W
OCF0B: Timer/Counter
W 00Y
W.1 0YOutput OM Compare B Match
W .100
WFlag OM
.T
W .C W .C W W Y .C W
WW .100The Y OCF0B
M .TW bit is set when W a Compare
W .100 Match O M T
.occurs W
between theWTimer/Counter .100 O M.T and the data in
W O Y.C W Y .C W the cor-
WW .10OCR0B 0Y.C –M .TW Compare
Output WW Register0
. 100 B. OCF0B M
Wcleared by
.Tis Whardware .100whenOexecuting M.T
W O W . C
W
WW .responding .CO interrupt .TW handling WWvector. Y.C
Alternatively, .TWOCF0B is
W
Wcleared 0YwritingMa.Tlogic
.10by
W one to
1 00Y M W .100 O M W C O
W the flag. O Y.C(Timer/Counter WW B.1Match .
WW and Y.CWhen.Tthe
00OCF0B W I-bit in SREG, WW OCIE0B . 100Compare M .TW
Compare
00Y Interrupt M.T
W Enable),
. 1 O Mare set, the Timer/Counter W O Match Interrupt is W
executed. .C O
W
W
W O W O W W .C O
WW • Bit –.C W WW 0 Output Y.C .TWA Match W .100
Y
M.T
W
. 1 010Y OCF0A:
M .TTimer/Counter W .100 Compare O M Flag
W C O
W O Y.C W .
Y and the W
WWThe OCF0A .C
00Y bit is set
.TWwhen a Compare WW .Match 100 occurs M .T W
between theW Timer/Counter0.100 M.T data
in OCR0A
WW .100Y.C M.TW
– Output Compare Register0. WW OCF0A Y.Cis cleared .TWby hardware W when .100
Y
executing the W
M.T
cor-
responding interrupt handling vector. W . 100
Alternatively, O MOCF0A is cleared by W writing a C O
logic one to
WW 00Y.C O W .
W .T W WW .100Y.C M.TW W . 1 00Y M .TW
the flag. W. 1When theOM I-bit in SREG, OCIE0A W (Timer/Counter0O Compare Match W Interrupt O Enable),
WWOCF0A
and 0 Y.Cset, the
are .T WTimer/Counter0 WW Compare 0 0Y.CMatch .T W
Interrupt is
WW .100Y.C M.TW
executed.
1 0 . 1 M W O
W. OM W O
WW .100Y.C M.TW
• BitW 0W CO
– TOV0:Y.Timer/Counter0 W Overflow WWFlag Y .CO .TW W WW 00Y.CO .TW
W 0
W
The bitW TOV0
0
W.1 is set
0 .T
OM an overflow occurs
when W.in 1 0
C
Timer/Counter0.
. OM TOV0 isW W
cleared W.1 by hardware
Y.C
OM
W
.C W Y W 0
W
when executing
0 Y
.10 the corresponding M. T W W
interrupt .1 0
handling
W
0
O
vector.
.T
M Alternatively, TOV0 W 1 0
.is clearedOby M.T
W .C O W Y. C W Y.C
W
writingWa logic.1one 00Yto the M .TW
flag. When the W SREGWI-bit, .100 TOIE0 M .TW
(Timer/Counter0
W
Overflow
W .100Interrupt
W O C O W
W TOV0 Y.C .TW WW Overflow Y. W W
Enable), Wand
W .100 are set, O Mthe Timer/Counter0
W .100 interrupt O M.T is executed.
W Y. C
The setting WWof this .10flag 0Y.Cis dependent M.T
W of the W WGM0[2:0] .100 bit setting.
W
M.TRefer to Table 15-8, “Wave-
W O W C O
WW Mode Y.C W on page WW104. .100Y.
form Generation
W .100 Bit Description” O M.T W
WW .100Y.C M.TW WW
W O
WW .100Y.C M.TW
W O
WW .100Y.C 107
W W
7799D–AVR–11/10 W
.C OM
00Y .TW
W W.1 Y.COM W
W 100 .T
16. 16-bit Timer/Counter 1 withWPWM WWW. 00Y.COM .TW
.T .1 M
.C OM WW 00Y.CO .TW
00 Y .T W W .1 M
16.1 Features W W.1 Y.COM W WW 00Y.CO .TW
00 Design
W • True.116-bit .T W .1 M
W W .C OM (i.e., Allows 16-bit PWM)
WW 00Y.CO .TW
.T W 00 Y
W• Three.1independent T W
.Output W
Compare Units.1 M
C OM • W W Buffered .C OM WW 00Y.CO .TW
Y. W W Double 0 Y Output W Compare WRegisters
00
W.1 Y.COM W
.T .10 M.T .1
WW 00Y.CO .TW
M
W • One
W WW Input Capture
0 Y .CO Unit W W
W 00
W.1 Y.COM W
.T • Input W .10 Noise M.T .1
WW 00Y.CO .TW
M
W W W Capture 0 Y .CO CancelerT W W
W 00
W.1 Y.COM W
.T • Clear Timer 0
W.1 onYCompare M. Match (Auto Reload) .1
WW 00Y.CO .TW
M
W W W 0 .CO .TW W
W 00 .T • Glitch-free,.1Phase 0 Correct
M Pulse Width Modulator .1 (PWM) M
W W.1 Y.COM W • Variable WW PWM Y .CO .TW
Period W WW 00Y.CO .TW
W 00 .T W .10 0 M .1 M
W W.1 Y.COM W • Frequency WWGenerator Y .CO .TW W WW 00Y.CO .TW
W 00 .T W 0 0 .1 M
W.1 Y.COM W • ExternalW W.1 Counter
Event
Y
M
.CO .TW WW 00Y.CO .TW
W W 0 W .1
W 00 .T
W.1 Y.COM W• Five independent .10 interruptMsources (TOV1, OCF1A, WW OCF1B, OM ICF1)
OCF1C,
W W
. 1 00 M .T W
W . 1 O M W .1 0
O M.T
W .CO .TW WW .100Y. C
WW Overview
16.2 00Y WW .100Y.C M.TW M.T
W
. 1 M W O W C O
W
WW .100Y.C M.TThe
O
WW .100Y.1CunitM
W 16-bit Timer/Counter .TW accurateWprogram
allows
W 0Y.
.10execution .TW (event management),
Mtiming
O W O W .C O
W
WW .100Y.C M.wave TW generation, WW and.1signal .C
00Y timing W
.Tmeasurement. WWMost.1register 00Y and TWreferences in this sec-
M.bit
W O M W C O
W O tion are written inWgeneral Y .C A lower
form.
.TW case “n”Wreplaces
W Y. Timer/Counter
the W number (for this
WW .100Y.C M.TW W . 100 M W .100 O M.T
product, only n=1 is W
available), O
and a lower case “x” replaces the COutput Compare unit channel.
W
WW .100Y.C However,
O
OM when usingW the register O or bit defines in a program, W the O
precise form must be used,
W 0Y.C M.TWcounter value
WW .1Timer/Counter1 WW and.1so Y.C .TW
WW .100Y.C i.e., .T W for accessing
TCNT1 0 W
00on.
O M
W OM W O
WW .100Y.C M.TW
WW .100Y.C A simplified .T W WW .100Y.C M.TW
W OM block diagram W of the 16-bit
O Timer/Counter isWshown W .CO 16-1.
in Figure For the actual
WW .100Y.Cplacement .T W of I/O pins, WW see 0 0Y.C on M
“Pinout”
.1 page .TW2. CPU accessible W . 1 00YRegisters,
I/O M .TW including I/O bits
W W .C OM
W WinWbold. Y.COdevice-specificW W WW 00Y.CO .TW
Yand I/O pins, are shownW 0The .T I/O Register and bit locations are listed in
W
W .100 O M.T W .10
.C Oon M W W.1 Y.COM W
C W .TW
WW .100Y. the “16-bit
M.T
Timer/Counter
W W 1 with PWM”
00Y page 108. W 00
W.1 Y.COM W
.T
W . C O W W.1 Y.COM W W
WW .100The Y Power.TReduction W W
Timer/Counter1 00 bit, PRTIM1, M.T in “PRR0 W – Power 00Reduction.TRegister 0” on
W O M W.1to enable.C OTimer/Counter1 W W.1 Y.COM W
page . C 46 must be written to Wzero 00Y W module.
W 00 .T
WW .100Y M.T
W W .T W.1 Y.COM W
W . C O W W.1 Y.COM W W
WW .100Y W W 00 .T W 00 .T
. C W W 00 .T
WW .100Y M.T
WW .100Y W W 00 .T W 0 .T
.C W W 0 .T
WW .100Y M.T
W W 00 .T 0
W.1 Y.COM W
WW .100Y .TW W .10 M.T
M
W
W . 100 O M .T W C O
W O W .
Y
M.T
W
W O W O W W .C O
Y
M.T
W
W O W O W W .C O
Y
M.T
W
W O W O W W .C O
Y .TW
W O W C O W W .C OM
W W .100
Y .TW
W O W C O W W .C OM
W W .100
Y .TW
W O W C O W W .C OM
W W .100
Y
W O W C O W W
W W
W O W C O
W
W O W C O
W O W
WW .100Y.C M.TW WW
W O
WW .100Y.C M.TW
W O
WW .100Y.C 108
W W
7799D–AVR–11/10 W
.C OM
00Y .TW
W W.1 Y.COM W
Figure 16-1. 16-bit Timer/Counter
W .100 Diagram
WBlock OM (1)
.T
W . C
M .TW W . 100
Y
M .TW
O W Count O
Y.C
TOVn
0 0 Y.C .T W WW Clear . 1 0 0Control M .TW (Int.Req.)
W .1 O M W W .C O TCLK
Logic
Clock Select
WW .100Y .C T W W
Direction
0 0Y .T W
. . 1 M
W W .C OM WW 00Y.CO .TW
Edge
Detector
Tn
.T W W 0 0 Y .T W W . 1 M
W. 1 OM W O
OM
TOP BOTTOM

0
( From Prescaler )
W W WW 00Y.CO .TW Timer/Counter

W
W 00 .T .1 M TCNTn .1 M
W W.1 Y.COM W WW 00Y.CO .TW W WW =00Y.CO= 0 .TW
W 00 .T W .1 M .1 M OCFnA
W W.1 Y.COM W WW 00Y.CO .TW W WW 00Y.CO .TW(Int.Req.)

W 00 .T W .1 M .1 M
W.1 Y.COM W WW 00Y.CO .TWGeneration
Waveform
W W WW 00Y.CO .T=W W 1
OCnA
W 0 0 .T 1 . M
W.1 OM W. OM W O
WW .100Y.C M.TW WW .100Y.C MOCRnA .TW WW .100Y.C M.TW
W O W O
WW Fixed
W .CO .OCFnB
WW .100Y.C M.TW WW .100Y.C M.TW . 1 00Y TW
M (Int.Req.)
W O W TOP
C O
W
WW .100Y.C M.TW
O
WW .100Y.C M = .T
W WW Values.100Y. TW
M.Generation
Waveform
OCnB
W O W O W W .C O
W Y .C W W W 0 Y .C T W W 0 0 Y .T W
W 00 .T .10 M. .1 M
DATABUS

OCRnB
W WW 00Y.CO .TW
W 00 .T W .1 M .1 M
W.1 Y.COM W WW 00Y.CO .TW WW 00Y.CO
OCFnC
W W
W M.T
(Int.Req.)
W 00 .T W . 1 M .1
. 1 M W O W C O
W O
WW .100Y.=C M.TW WW .100Y. Generation
Waveform
W
WW .100Y.C M.TW M.T
OCnC
W O W C O
W
WW .100Y.C M.TW
O
WW .100OCRnC Y.C .TW WW .100Y. W
M.T ( From Analog
W O M W C O
W
WW .100Y.C M.TW
O
WW .100Y.C M.TW WW
ICFn (Int.Req.) .10
0Y. M.T
W Ouput )
Comparator
W O W C O
W O
WW .1ICRn .C W Y.Noise W
WW .100Y.C M.TW 00Y M .TW W Edge
W .100 Canceler O M.T
W O C
W O
Detector
W ICPn
W O C
W
WW .100Y.C M.TW
O
WW TCCRnA Y.C .TWTCCRnB WW .10TCCRnC 0Y. M.T
W
W . 100 O M W C O
W
WW .100Y.C M.TW
O
W
O W O W .C O
W
W
O W O W .C O
W
W
O W O W .C O
W Note:
WW .100Y.C M
1. Refer
.TW
to Figure 1-1
W Won page 2, Table
.C
00Yand description.
12-3
.TW
on page 74,
WW .100Y
and Table 12-6 on page
M
77
.TW
for
Timer/Counter1 pin placement
W .1 O M W O
W
WW .100Y.C M.TW
O
16.2.1 Registers WW .C O
W 0 Y W 1
W
The.10Timer/CounterO M.T (TCNTn), Output W
1
W.Compare .C
M
ORegisters (OCRnA/B/C), W W.and Input OM
Y.C Capture WReg-
.C Y W W 0
W 0 0
W ister.1(ICRn) Y
are Mall
W W
.T16-bit registers. Special W . 0 0
1 procedures O M .T
must be followed W .
when
1 0
O
accessing M.Tthe 16-
W .C O W Y.C W WW .100Y .C W
WWbit registers.
.1 00Y These M .TW procedures Ware
W . 100
described inOM the.Tsection “Accessing W 16-bit Registers”O M.T on
WW 110. O Y.C(TCCRnA/B/C) W .C
Wpage .C
00YThe Timer/Counter .TW WW Registers
Control 100 M .TW areW 8-bit registers
Y
.100 and M .TWno
have
. 1 O M W . O W W .C O
WWaccess
CPU .C
00Y restrictions. .TW InterruptWrequests
W Y.C
(shorten W
as Int.Req.) W
signals are 0YvisibleMin.Tthe
.10all
W
W
W . 1 O M W .100 O M.T W W .C O
Timer Interrupt Flag Register (TIFRn). WW All interrupts .Care individually masked
W with theYTimer Inter- W
WW .100Y.C M.TW 00Y
.1TIMSKn
W
M.Tnot shown in the W .100 O M.T
rupt MaskW Register O (TIMSKn). TIFRn andW O are W figure C
since
. these
WW are Y.C TW timer units. WW .100Y.C M.TW W .100
Y .TW
registers W .100sharedOby M.other W C O W W .C OM
M.T or by an external
W .100
Y .TW
The Timer/Counter
W canO be clocked internally, W via the O
prescaler,
C W W clock C
source
. OMon
WW Y.C W WW .1which .
00Y clockMsource .TW and edge W .100
Y .TW
the Tn pin.W The.100Clock Select O M.T logic block controls W C O the
W W Timer/Counter .C OM
W Y.C W its value. WW Y. W W no clock Y
.100 source
uses to Wincrement
W .100 (or decrement)
O M.T .100
The Timer/Counter
W O M.Tis inactive whenW W
.C WW 0Y. C
WW The.1output
is selected. 00Y from M.T
theWclock select logic is .10referred to .TW
Mas the timer clock W (clkTn).
W O W C O
WW buffered Y.C W WW .10(OCRnA/B/C) 0Y. W
M.T are compared with the
The double
W .100 Output O M.TCompare Registers W C O
WW value C time. T
atY.all W result ofW Wcompare Y.
Timer/Counter
W .100 O M.
The the
W .100 can be used by the Waveform Gener-
ator to generate C variable
Y.or W on the Output Compare pin (OCnA/B/C).
WW a PWM .100 M.T
WfrequencyWoutput
W O
WW .100Y.C M.TW
W O
WW .100Y.C 109
W W
7799D–AVR–11/10 W
.C OM
00Y .TW
W W.1 Y.COM W
W 00 .T
See “Output Compare Units” on W W.1117..Y.The
page C OM compare match event will also set the Compare
Match Flag (OCFnA/B/C) M .TW which
W can be . 0 to generate
10used M .TW an Output Compare interrupt request.
W O
. 1 00Y Capture M O
The W Input O
Y.C on either
Register can WW the
capture Timer/Counter
0Y.C
value at a given external (edge trig-
TWon the Analog Comparator pins (See
WW gered) 1 0 0
event .T W
the Input
WCapture . 1 0 pin (ICPn) M .or
.
WW Comparator” OM W .CO .TW
.T W W“Analog 0 0 Y.C .T onWpage 223.) WW The Input
. 1 0 0YCapture M unit includes a digital filtering unit (Noise
1
W. forYreducing OM
.COM W
Canceler) .C W
the chance W
of W W
capturing 0 Y .CO spikes.
noise .TW
00 Y .TW W . 1 0 0 M .T . 1 0 M
.1 O M W O W .C O
W
WW .100Y.C M.TW WW
The TOP .value,
.C
00Y or maximum .TW Timer/Counter WW .1value, 00Y canM in.T
W
some modes of operation be defined
1 O M W O
W O WW the00OCRnA Y.C W Register, Y.C or by.T aW
WW .100Y.C M.TW byW either
. 1 M .TW
Register, the W ICRn
W . 100 O M set of fixed values. When using
W O OCRnA W
as TOP C
value O in a PWM mode, W
the OCRnA .CRegister
WW .100Y.C M.TW W W 0Y . .TW W 100
Y Tcan
W not be used for generating a
M.double
PWM output.W . 10However, O M the TOP value will W
in
.this case O be buffered allowing the TOP
W O
WW .100Y.C M.TW valueW
to be W . 1
changed inO runM time. If a fixed TOP value is .required, O the ICRn Register can be used
W O Y.C the.TOCRnA WW 0Y C output. TW
WW .100Y.C M.TW as an alternative, WW .100freeing W to be Wused as
. 1 0
PWM M .
W OM W O
W
WW .100Y.C M.TW
O
W O W O
16.2.2W Definitions
WW .100Y.C M.TW
O
W CO usedTextensively WW 00the O
W O The followingW definitions Y.are throughout Y.Cdocument: W
WW .100Y.C M.TW W . 1 0 0 M . W W
W . 1 O M.T
W O W O W Y. C
WW .100Y.C M.TW BOTTOM WW Y.C WBOTTOM W .100 0x0000. M.T
W
The counter
W . 100 reaches O M .Tthe when it becomes
W C O
W
WW .100Y.C M.TMAX
O
W W Y.C W WW .100Y. M.T
W
WThe
W .
counter 100 reaches O M .TMAXimum
its when it becomesW 0xFFFF
C O (decimal 65535).
W
WW .100Y.C M.TW
O
W
O W O W C O
. the highest
W
WW .100Y.C M.TW
TheW
W
counter reaches .C the .TOP
00YTOP value W when it becomes
Tcan WW equal to
00Yof the fixed Wvalue in the count
M.Tvalues: 0x00FF,
sequence. W .1The O M be assigned to W be.1one C O
W O TOP
WW or .0x03FF, Y.C or to the W Y. TW
WW .100Y.C M.TW 0x01FF,
100 M .TW value storedWin the OCRnA
W .100 or ICRn O M.Register. The
W CO assignment W W is dependent
. C O of the mode of W
operation. Y.C W
WW .100Y. M.T
W W .100
Y .TW W 00
W.1 Y.COM W
.T
W C O W W .C OM W
WW .100Y. M.T
W W .100
Y .TW W 00
W.1 Y.COM W
.T
16.3 Accessing W 16-bit
C O Registers W W .C OM W
WW .100Y. W
M.T OCRnA/B/C,
W 0Y
.10ICRn .TW W 00
W.1be accessed
.T
OM by the AVR CPU
W TheC O TCNTn, W W
and .Care OM 16-bit registers that W can Y .C W
WW .100Y .
M .TWdata bus. W . 0Y
10register M .TW W
W 100 twoOread
.using M.T or write opera-
via theO 8-bit The 16-bit
W O must be byte accessed .C
W Y.C Each.T16-bit
WW .100tions. W timer W W Y.C .TWfor temporary WW .100Y W
M.Tbyte of the 16-
M has a W .100 8-bit register
single O M storing
W of theC O high
W .CO The .C W Y . .TW each 16-
WW .10bit0Yaccess. .TWsame Temporary WW .1Register 00Y isM .TW between
shared Wall .100registers
16-bit Mwithin
O M W O W .C O
W
WW .bit Y.C Accessing W triggers Y.C .TW WW Y
.100 When .TW
1 00timer. M .TW the lowWbyteW .100 theO16-bit M
read or write operation.
W .C O Mthe low byte of
W a 16-bit .C O
register is written by the
W CPU, the .C high byte W stored in theW Temporary Y Register, Wand the
WW .100Y M .TW W
W . 10the0Y
O M .T W
W .100 O M.T
W low byte written
O are both copied into 16-bit register in the same
WW .100Y clock cycle.
.C When the low
WW byte 0 0 Y.C .T W WW . 1 0 0Y.C M.TW M .TW
W. 1 of a 16-bit
OM register is read by the CPU, the high byte of the 16-bit register
WW 00Y.C is O
copied into the
W Y .C W W WW 00Y.CO .TW W 1 .T W
W Temporary 0 0 Register .T in the same clock .cycle
1 as the Mlow byte is read. WW. OM
W.1 Y.COM W WW 00Y.CO .TW W 0 Y.C W
WWNot all .1 0
016-bit accesses M .T uses the
W
Temporary W . 1 Register O M for the high byte. W
Reading. 1 0
the O M.T
OCRnA/B/C
WW registers O .C W Y .C W
W16-bit .C
00Y does .Tnot W involve using WW the.1Temporary 00Y M .TW
Register. W .100 M.T
WW 00Y.C .TWhigh byte W
W .C
00Y before W W Y
.100 read, .TW
WTo doW a.116-bit write, O Mthe must be W .1written O M.Tthe low byte. For W aW 16-bit .C O Mthe low
.C W Y .C W W 0 Y W
W W
byte must .1be 0 Y
0 read before T W
M. the high byte.WW.1
W 0 0
O M .T
W . 1 0
O MT .
W O Y.C W .C
WW Y.C W .TW W .100
Y .TW
The following
W .100 codeOexamples M.T
W
show how toWaccess .100 theOM 16-bit timer registers W Wassuming . C OMno
that
Y.C WWThe .same Y. C W W 00Yaccessing .TW
WW updates
interrupts .100 theOtemporary M.T
W register. 100 principle M.Tcan be used directly W .1for OM
W W C O W . C
WW .100and
the OCRnA/B/C Y.C ICRn.TRegisters. W WWthat .when
Note Y.
100 using .TWthe compiler
M“C”,
W handles Y
.100the 16-bit .TW
W O M W C O W W .C OM
access. WW .100Y.C M.TW WW .100Y. M.T
W W .100
Y
W O W C O W W
W W
W O W C O
W
W O W C O
W O W
WW .100Y.C M.TW WW
W O
WW .100Y.C M.TW
W O
WW .100Y.C 110
W W
7799D–AVR–11/10 W
.C OM
00Y .TW
W W.1 Y.COM W
W
(1) WW
.100 OM
.T
.C
Assembly Code.TExamples
M
W W . 100
Y
M .TW
O W O
Y.C
00... .TW WW .100Y.C M.TW
W . 1 O M W O
WW .10;0Y .C TCNTn
Set
.T W to 0x01FF WW .100Y.C M.TW
W ldi r17,0x01 OM W O
OM W ldi r16,0xFF O W O
0 O
W.1 OM Wout TCNTnH,r17
Y.C
O W
WW .100Y.C M.TW
WW .100Y.C M.TW WW out 1 0 0 M .T W
W. TCNTnL,r16
.CO .TW W O
W
WW .100Y.C M.TW
O
WW ; Read 0 0 YTCNTn WW .100Y.C M.TW
W. 1 OM into r17:r16 W O
W
WW .100Y.C M.TW
O
WWin r16,TCNTnL 0 0 Y.C .T W WW .100Y.C M.TW
. 1 OM W O
W O WWr17,TCNTnH Y.C WW .100Y.C M.TW
WW .100Y.C M.TW Win . 1 0 0 M .T W
W O
WW .100Y.C M.TW W ...
1
WW 00(1)
. OM W O
W O
WW .100Y.C M.TW C Code WExamples Y.C .T W WW .100Y.C M.TW
W. 1 M W O
W O
WW .1int .CO WW .100Y.C M.TW
WW .100Y.C M.TW unsigned 00Y i; M.TW W O
W O
W
WW .100Y.C M.TW
O ...WW 0 0 Y.C .T W WW .100Y.C M.TW
W. 1 O M W O
W
WW .100Y.C M.TW
O /* SetWWTCNTn 00Y
to.C0x01FF
.T*/W WW .100Y.C M.TW
. 1 M W O
W O TCNTn =W0x1FF; W .CO .TW WW .100Y.C M.TW
WW .100Y.C M.TW W . 1 00Y M W O
W O /* Read W W into
TCNTn .CO i */
WW .100Y.C M.TW
WW .100Y.C M.TW i = TCNTn; W . 1 00Y M .TW W O
W O
W O
WW .100Y.C M.TW ... WW .100Y.C M.TW WW .100Y.C M.TW
W O W O
W
WW .100Y.C Note:
O
OM 1. See “Code Examples” W on O page 6. W O
W
WW .100Y.C TheMassembly .TW WW .100Y.C M.TW WW .100Y.C M.TW
W O code example W returnsOthe TCNTn value in W the Wr17:r16 CO
.register pair.
WW .100Y.C M.TW WW .100Y.C M.TW W . 1 00Y M .TW
W ItCisO important to noticeWthat W accessing O 16-bit registers are W
WW atomic .CO .TWIf an interrupt
operations.
WW .100Y.occurs T W W 0 0Y.C M.TW 1 00Y
.
OM between the twoWinstructions . 1
WW
. OMthe interrupt code
W .C W Y .COaccessing W
the 16-bit
W
register,.C
0 Y
and
W
W W
. 1
Y
00 updates M
W
.T temporary register
the W
W .1by 0
0 accessing
O M .T the same or any W other 0
.1 of theO16-bit M.T Timer Regis-
W O Y.C W Y .C W
WW .100ters, Y.C then the .TWresult of the WWaccess .100outsideOthe M
W
.Tinterrupt .100 Therefore,
willWbe corrupted. M.T when both
M W W .C O
W
WW .10the .CO code
0Ymain .TW
and the interrupt WW code Y .C
update the W
.Ttemporary WW .the
register, Y code.Tmust
100main O
W disable
M W . 100 O M W C
M
W the interrupts O during the 16-bit Y.C WW .100Y .
WW .100Y.C M.TW WWaccess. .100 M .TW M.T
W
O W O W .C O
W .C WW .Cdo an.Tatomic
W ofW Y W
WW The . 1 00Y
following
M
code
.TW examples show how
W . 100
Yto
O M
read W
W .100 Register
the TCNTn
O M.T contents.
O
WReading any of the OCRnA/B/CWor ICRn0Registers Y.C can be doneW byW using the .C
Ysame principle. W
O W O .C
W
W
O W O W .C O
W
W
W O W O W W .C O
Y
M.T
W
W O W O W W .C O
Y
M.T
W
W O W O W W .C O
Y
M.T
W
W O W O W W .C O
Y .TW
W O W C O W W .C OM
W W .100
Y .TW
W O W CO W W .C OM
W W .100
Y .TW
W O W C O W W .C OM
W W .100
Y
W O W C O W W
W W
W O W C O
W
W O W CO
W O W
WW .100Y.C M.TW WW
W O
WW .100Y.C M.TW
W O
WW .100Y.C 111
W W
7799D–AVR–11/10 W
.C OM
00Y .TW
W W.1 Y.COM W
W 00 .T
W W.1 Y.COM W
W W 00 .T
O M.T W W.1 Y.COM W
Assembly .C
Y Code .Example W (1)
W 00 .T
W .100 O MT W W.1 Y.COM W
WW TIM16_ReadTCNTn:Y .C W W 00 .T
W WW .1;00Save .C
Y global Winterrupt W flag.100 .T
O M.T W O M.T W W .C OM
.C WW .100Y in .C
r18,SREG Y .TW
100Y M .TW M .TW W
W . 100 O M
. O
W; Disable interrupts
W O
W O W O
WW .100Y.C M.TW
W O cli
WW .100Y.C M.TW WW ; Read 0 0 Y.C .T W
W. 1 TCNTn OMinto r17:r16 WW O
W
WW .100Y.C M.TW
O
WWin r16,TCNTnL 0 0 Y.C .T W W . 1 0 0Y.C M.TW
. 1 OM W O
W O WWr17,TCNTnH Y.C WW .100Y.C M.TW
WW .100Y.C M.TW Win 1 0 0 M .T W
W. .CO .interrupt W O
W
WW .100Y.C M.TW
O
W ;W Restore 0 0 Yglobal T W WW .100Y.C M.TW
flag
W. 1 OM W O
W
WW .100Y.C M.TW
O
WWSREG,r18
out 0 0 Y.C .T W WW .100Y.C M.TW
W. 1 OM W O
W
WW .100Y.C M.TW
O
WW .100Y.C M.TW
ret WW .100Y.C M.TW
W (1) O W O
W O
WW .100Y.C M.TWC Code Example WW .100Y.C M.TW WW .100Y.C M.TW
W O W .CO .TW WW 00Y.CO .TW
WW .100Y.C M.TW unsigned WWint.1TIM16_ReadTCNTn(
00Y M
voidW) .1 M
W W .C O
W { WW 00Y.CO .TW W WW 00Y.CO .TW
W 00 Y .T W .1 M
W.1 Y.COM W unsignedWchar W.1 sreg; Y .CO .TW
M WW 00Y.CO .TW
W W 0 0 W .1
W 00 .T W.1i; Y.COM W M
W W.1 Y.COM W unsigned W int
W WW 00Y.CO .TW
W 00 .T W .10 0 M .T .1 M
W W.1 Y.COM W/* Save global WW interrupt Y .CO flag W
*/
W WW 00Y.CO .TW
W 00 .T sreg = SREG; W.10 W 0 M .T .1 M
W 00 W
.T /* Disable interrupts 0 0 .1 M
W.1 Y.COM W W W.1 Y.C */OM
W WW 00Y.CO .TW
W W 0 0 .T W .1
W 00 .T__disable_interrupt(); W.1 Y.COM W M
W W.1 Y.COM /*WRead TCNTnWinto W WW 00Y.CO .TW
W 00 .T W .10i 0*/
M .T .1 M
W W.1 Y.COMi = W TCNTn; WW 00Y.CO .TW W WW 00Y.CO .TW
W 00 .T W .1 M .1 M
W W.1 Y.COM /* Restore
W global WWinterrupt Y .COflag W*/ W WW 00Y.CO .TW
W 00 W .10 0 .T .1
W.1 Y.COSREG M.T = sreg; WW 00Y.CO .TW
M WW 00Y.CO .TW
M
W W W W .1
W 00 .T i; .1 M M
W W.1 Y.Creturn OM
W 00 } .T W .1 M . 1 M
W W.1 Y .C OM
W 1
W .100
WNote: OSeeM.T W W.1 Y.COM W .
WW 00Y.CO .TW
M
W W 0 Y .C
1. “Code
W Examples” W on page 6.
0 0 .T W 1
.10assembly .T .1 M W. OM
W
The .C OMcode example returns WWthe0TCNTn Y .CO value Win the r17:r16 W Wregister 0 Y.C
pair. W
W W
. 1 0 0 Y
M .T W W
W .1 0
O M .T
W . 1 0
O M.T
W O WW .100Y .C
W
W O W O W W .C O
Y
M.T
W
W O W O W W .C O
Y
M.T
W
W O W O W W .C O
Y
M.T
W
W O W O W W .C O
Y .TW
W O W C O W W .C OM
W W .100
Y .TW
W O W C O W W .C OM
W W .100
Y .TW
W O W C O W W .C OM
W W .100
Y
W O W C O W W
W W
W O W C O
W
W O W C O
W O W
WW .100Y.C M.TW WW
W O
WW .100Y.C M.TW
W O
WW .100Y.C 112
W W
7799D–AVR–11/10 W
.C OM
00Y .TW
W W.1 Y.COM W
The following code examples show
W .100 to doOan
Whow
T
M.atomic write of the TCNTn Register contents.
W W 0Y
Wor ICRn.1Registers .C TW
Writing any of the .T OCRnA/B/C 0 M
can. be done by using the same principle.
.C OM WW 00Y.CO .TW
00 Y .T W W .1 M
W W.1 Y.Code
Assembly C OM Example(1)
W WW 00Y.CO .TW
W
W .100
WTIM16_WriteTCNTn: OM
.T .1
WW 00Y.CO .TW
M
W W Y .C W W
.T W 00 .T .1 M
.C OM W W.1; Save Y .C OM
global
W
interrupt flag WW 00Y.CO .TW
Y W W 0 W
00
W.1 Y.COM W
.T in.10 r18,SREG M.T .1
WW 00Y.CO .TW
M
W W WW 00Y.CO .TW W
W 00 .T 1
; .Disable M
interrupts .1 M
W W.1 Y.COM W WW Y . CO W W WW 00Y.CO .TW
W 00 .T W cli.10 0 M. T .1 M
W W.1 Y.COM W W;WSet 0TCNTn Y .CO to .r17:r16 W W WW 00Y.CO .TW
W 00 .T W .1 0 M T .1 M
W W.1 Y.COM W WWTCNTnH,r17
out Y .CO .TW W WW 00Y.CO .TW
W 00 .T W .10 0 M .1 M
W W.1 Y.COM W outWW TCNTnL,r16 Y .CO .TW W WW 00Y.CO .TW
W 00 .T W .10 0 M .1 M
W W.1 Y.COM W WW 00global
; Restore Y .CO interrupt W flagWW
W 0Y .CO .TW
W 00 .T W .1 M. T .1 0 M
out SREG,r18
W WW 00Y.CO .TW
W 00 .T W .1 M .1 M
W W.1 Y.COM W ret
W 00 .T C Code Example W .1 M .1 M
(1)
W W WW 00Y.CO .TW W
W 00 .T .1 M .1 M
W W.1 Y.COM W void TIM16_WriteTCNTn( WW 00Y.CO unsigned W int iW)W
W 0 Y .CO .TW
W 00 .T W .1 M. T .1 0 M
W W.1 Y.COM W{ WW 00Y.CO .TW W WW 00Y.CO .TW
W 00 .T W .1 M
W.1 Y.COM W unsigned W charW.1 sreg; Y .CO .TW
M WW 00Y.CO .TW
W W 0 W .1
W 00
W.1 Y.COM W
.T unsigned intWi; .10 M WW 00Y.CO .TW
M
W W W 0 Y .CO T W W
W 00 .T /* Save global 0
.1interrupt .
Mflag */ .1 M
W 00 .T sreg = SREG;W .1 .1 M
W.1 Y.COM /*W Disable interrupts WW 00Y.C OM WW 00Y.CO .TW
W W */ .T W W .1
W 00 .T .1 M M
W W.1 Y.COM __disable_interrupt();
W 00 .T W .1 M .1 M
W W.1 Y.COM/* Set W
TCNTn to WW i */ Y.CO W W WW 00Y.CO .TW
W 00 .T = i; W .10 0 M .T .1 M
W W.1 Y.COM TCNTn
W 00 W .1
W.1 Y.CO/* M.T Restore global interrupt .1
WW 00Y.CO .TW
M */
flag WW 00Y.CO .TW
M
W W W W .1
W 00 SREG.T= sreg;
W.1 Y.COM W M
W 00 } .T W .10 0 M .T . 1 M
W 1
W .100 1. OSee
WNote: M.T“Code Examples”W onW .1 6. OM
page .C
.
WW 00Y.CO .TW
M
W
W The 0 Y .C W W 0 0 Y .T W W 1
0 .T .1 M . OM to be writ-
W.1 assembly .C OMcode example requires WW that Y
the.CO r17:r16
W W WW 0the
register pair contains
0 Y.Cvalue W
W
W ten .to 1 0 Y
0TCNTn. M.T W W
W .1 0 0
O M .T
W . 1 O M.T
W O WW .100Y .C
W
W O W O W W .C O
16.3.1 Reusing the Temporary
WW .100High Y.C Byte.TRegister W WW .100Y.C M.TW W .100
Y
M.T
W
O M
W to more than one 16-bit register W O W W .C O
If writing
WW where .C high.byte
0Ythe W is the same W for all registers
Y written,
.TW
WW .100Y.C M.TW .10once. M T note that the W .100 rule of O M
then W the high byte O only needs to be W
written O
However, W same .C atomic
WW .1described
operation 00Y
.C .TW
previously
WW .in
also applies
0Y.Ccase.M.TW
10this
W .100
Y
M.T
W
W O M W O W W .C O
Y .TW
W O W C O W W .C OM
16.4 Timer/Counter Clock WW Sources Y.C W WW .100Y. M.T
W W .100
Y .TW
The W W
Timer/Counter Y.Ccan be.Tclocked W by an WW internal 0Yan . external W
M.T clock source.W
W The.1clock 00Y source .TW
W .100 O M W .10or O W .C OM
.C WW is .controlled Y. C W Clock Select Y bits
is selected
WW by.1the 00Y
Clock SelectW logic which
M.T control Register W 100 O
by the
M.T
W
W .100
(CSn2:0)
located inWthe W Timer/Counter O B (TCCRnB). C For details on W
clock sources and
W 0 0 Y.C .T W WW .100Y. M .TW W
prescaler, see .1
W“Timer/Counter0 O M and Timer/Counter1 W Prescalers” O on page 88.
W O W O
W O W
WW .100Y.C M.TW WW
W O
WW .100Y.C M.TW
W O
WW .100Y.C 113
W W
7799D–AVR–11/10 W
.C OM
00Y .TW
W W.1 Y.COM W
W 00 .T
16.5 Counter Unit W W.1 Y.COM W
.TW W 00
W.1 isYthe M.T
The main part
. C OM of the 16-bit Timer/Counter W .C Oprogrammable
W 16-bit bi-directional counter unit.
0 0 Y shows.TaWblock diagram W of the . 1 0 0counter M . Tits
W.1
Figure 16-2 OM W O and surroundings.
WW 16-2. O
Y.CCounter WW 00Y.CO .TW
.T W WFigure 1 0 0 M . T WUnit BlockW Diagram
.1 M
.C OM W W. Y .C ODATA
W WW 00Y.CO .TW
Y W W 0 BUS W
M.T
(8-bit)
00 .T .10 .1 M
W W.1 Y.COM W WW 00Y.CO .TW W WW 00Y.CO TOVn .TW
W 00 .T W . 1 M . 1 M(Int.Req.)
.1 M W O W O
W
WW .100Y.C M.TW
O
WW .1TEMP .C
00Y(8-bit) M.TW WW .100Y.C M.TW
W O W O
WW
W .CO .TW Clock Select
WW .100Y.C M.TW WW .100Y.C M.TW Count . 1 00Y M
WW 00Y.COclk .TW Detector
Edge
W W Y.C O
W W WW 0 Y
TCNTnH (8-bit) .CO TCNTnL . T W (8-bit) W Clear
Tn
W 00 .T 1 0 M . 1 Tn
M
W.
Control Logic
W.1 OM W O
WW .1TCNTn .COCounter) WW .100Y.C M.TW
Direction
WW .100Y.C M.TW 00Y W
(16-bit
.T
W OM W O
W O
( From Prescaler )
WW .100Y.C M.TW
W O W BOTTOMO
W O
TOP
WW .100Y.C M.TW W O
WW .100Y.C M.TW Signal description W . 1 M
W(internal signals):
O W O
W
WW .100Y.C M.TW
O
W TCNTn by O 1.
W O Count WW .COIncrement or decrement
WW .100Y.C M.TW
WW .100Y.C M.TW W . 1 00Y M .TW
W O W O
WW and
W .CO .TW
WW .100Y.C M.TW
Direction WW .100Y.CSelect between increment
.TW 1 00Ydecrement.
O M WW
. OM
W .C O WW 00Y.C W W 0 Y.C W
W W
. 1 00 Y
M .T W Clear W
W .1 Clear
O M
TCNTn
.T (set all bits to
W
zero).
.1 0
O M.T
W O .C W .C
WW .100Y.C M.TW clkTn WW .100YTimer/Counter M .TW clock. W W.100Y OM.TW
W O
W
WW .100Y.C M.TTOP
O
W WW .100Signalize Y.C TW TCNTn has
.that WW .100Y.C M.TW
M reached maximum value.
WW 00Y.CO .TW
W W Y .C O
W W WW 00Y.CO .TW W
W 00 .T .1 M TCNTn has reached .1 OM
W W.1 Y.COMBOTTOM W WW Signalize 0 Y .CO that W W WW 0minimum 0 Y.C value .TW
(zero).
W 0 0 .T W . 1 0 M .T . 1 M
W.1 M
.CO16-bit.Tcounter
The is mapped W O
Y.C 8-bit I/O
W
WW .1Counter .CO .T(TCNTnH)
WW .100Y W WW into .1 0 0two M .TWmemory locations: 00Y High W
M the lower eight
con-
W taining O Mthe upper eight bits of W the counter, O and Counter Low W
(TCNTnL)
W O
containing
.C
WW .100bits. Y.CThe TCNTnH .TW Register WWcan .only Y.C .TWaccessedWby theWCPU. Y
.100 When .TW
M W 100 be indirectly
O M C O M the CPU does an
W W .C O W Y .C W W W 0Y . .T W
W 0 Y
0access toM the W
.TTCNTnH I/O location, W . 0
10the CPU M .T
accesses the high byte 1 0
.temporary register (TEMP).
M
. 1 W O W .C O
W
WW .The .CO .TWregister isWupdated W 0Y.Cthe M .TW valueWwhenWthe
W Y
.100TCNTnL
W
M.isT read, and
1 00Ytemporary M W .10with O
TCNTnH
.C O
O
W TCNTnH is updated with the temporary .C WW is Y W
WW .100Y.C M.TW WW .100Yregister M
value
.TW when TCNTnL written.
.100
This.Tallows
M
the
CPU to read O or write the entire W
16-bit counter Ovalue within one clock W
cycle via .C
the O 8-bit data bus.
W
WW It is 0Y.C Mto.Tnotice W WW .100Y.C M.TW WW .100Y W
M.Twhen the
. 1 0important that there are
W special cases
O of writing to the W
TCNTn Register
.C O
W O Y.C results. WWcases 0Y described W
WW counter .C
00Yis counting .TW that will give WWunpredictable.100 M .TWThe special .10are M.T in the
. 1 O M W O W .C O
WWsections
W .C they .TW WW .100Y.C M.TW WW .100Y M.T
W
.1 00Y where
M
are of importance.
W O W . C O
WW 00Yon O C W W
WDepending .C
theMmode .TW of operation WWused, . 10the 0Y.counter M .TisW W
cleared, incremented,
Y
.100or decremented M.T
W . 1 O W O W W .C O
Y.C W .C .TWan external Y .TW
W atW each timer
.100
clock (clk
M.TTn
W). The clkW Tn can be
W
00Y
.1generated O Mfrom
W or internal
W .100 clock O Msource,
W O .C W .C
Y = 0).T W
selected
WW .by 00Y
the.CClock Select
.TW bits (CSn2:0). WW .1When 00Y no clock M.T
Wsource is selected W 100
.(CSn2:0 M the
timer W 1
is stopped. O M W O
can.Cbe accessed W W .C O
WW .100Y .C However, W the TCNTn WWvalue 00Y .TW
by the WCPU, .independent
100
Y .of
TW
whetherWclk Tn is present O M.Tor not. A CPU W writeW .1overrides
C O M
(has priority over) W allW counter .C OM or
clear
WW Y.C W Y. W W .100
Y .TW
count operations.
W .100 O M.T
W
WW .100Y. C Y W
WW .100Y.C M.TW M.T
W W
W .100mode O M.T
The counting W sequence O is determined by the W setting .CofO the Waveform Generation
W .C bits
WW located Y.C .TW
W
WControl 00Y A.T
W W 00Y
.1TCCRnB).
(WGMn3:0)
W .100 in the O MTimer/Counter W .1Registers
C O M and B (TCCRnA and
W W
WWclose.1connections .C W WW counter Y. W W
There are
W
00Y
O M.Tbetween how the W .100 behaves O M.T (counts) and how waveforms
.C WWOCnx. C
0Y.moreM
are generated WW on.1the 00YOutputMCompare .TW outputs
.10For .TW about advanced counting
details
W O W .C O
sequences and
WW .100Y.C M.TW
waveform generation, see “Modes WW of.1Operation” 00Y on page 120.
W O W
WW .100Y.C M.TW WW
W O
WW .100Y.C M.TW
W O
WW .100Y.C 114
W W
7799D–AVR–11/10 W
.C OM
00Y .TW
W W.1 Y.COM W
The Timer/Counter Overflow Flag
W
W .100 is set
(TOVn) OM
.T
according to the mode of operation selected by
W .C
the WGMn3:0 M .TW
bits. TOVn can
Wbe used . 00Y
1for generating M .TW a CPU interrupt.
C O W W .C O
Y . W W 0 Y .T W
. 1 00 M .T W . 10 O M
W O
16.6 Input Capture WWUnit .100Y.C M.TW WW .100Y.C M.TW
O W O
W WWTimer/Counter
WThe 0 0 Y.C .T W
incorporates WW
an input capture 1 0 0Y.C unitMthat .TWcan capture external events and give
M .T . 1 O M W . O
.CO .TW WW
them a time-stamp
00Y
.C indicating .TW time of
W
Woccurrence. 100
Y.TheC external
.TW signal indicating an event, or mul-
.100Y M
W
W . 1 O M W . O M
W O tipleWevents, can .Cbe applied via the ICPn
WWpin .or Y.C
alternatively,
.TW
for the Timer/Counter1 only, via the
WW .100Y.C M.TW W
Analog . 1 00Y
Comparator M
unit. .TW The time-stamps W can100then be O M
used to calculate frequency, duty-cycle,
WW 00Y.C O
W
WW .100Y.C M.TW
O
andWother features of the .T W applied.
signal WW .
Alternatively1 0 0Y.Cthe time-stamps
M .TW can be used for creating a
W. 1 M
W W .C O
W W Y .CO .TW W WW 00Y.CO .TW
W 00 Y .T log W
of the events.
.10 0 M .1 M
W 00 .T W
The Input Capture 1
.diagram M in Figure 16-3. The elements of
W.1 Y.COM W W W.1 unit Y .CO
isM illustrated by the block
W WW 00Y.CO .TW
shown
W the W
block diagram 0that are not T directly a W
part of the input capture unit are gray shaded. The small
W
W .100 O M.T W .10 O M. W W.1 Y.COM W
W .C
WW .100Y.C M.TW “n” in register W and0bit
.1 0
Ynames indicates .TW the Timer/Counter
W 00 number..T
W.1 Y.COM W
W CO W W .C OM W
WW .100Y. W W
M.T Figure 16-3.WInput
Y
.100Capture .TW
Unit Block DiagramWW.1
W 00
OM
.T
W C O W . C OM Y . C W
WW .100Y. M .TW W . 100
Y
M .TW W
W .100 O M.T
W O C
W
WW .100Y.C M.TW
O
WW .100Y.C M.TW DATAWWBUS.10(8-bit) 0Y. M.T
W
W O W C O
W
WW .100Y.C M.TW
O
W
W O W C O
W
WW .100Y.C M.TW
O
WW Y.C .TW WW .100Y. M.T
W
W 100
TEMP .(8-bit) O M W C O
W
WW .100Y.C M.TW
O
W
W O W C O
W
WW .100Y.C M.TW
O
W
W O W C O
W
WW .100Y.C M.TW
O
W
W O W C O
W O ICRnHW (8-bit)
Y.CICRnL (8-bit) WWTCNTnH Y.
(8-bit) W (8-bit)
TCNTnL
WW .100Y.C M.TW W .100 M .TW W .100 O M.T
O W O C
Y. (16-bit Counter)
W
WW .100Y.C M.TW WRITE W
W Y.C
ICRn (16-bit Register)
.TW WW .TCNTn 100 M.T
W
W . 100 O M W C O
W
WW .100Y.C M.TW
O
W
O W O W .C O
W
W
O W O W .C O
W
W
O W O W .C O
W
W
O ACO* W ACIC* O ICNC W ICES .C O
W
W
O W O W .C O
W
WW .100Y.C M.TWComparator Analog WW Y.C .TW WW .100Y M.T
W
W . 100 O M W C O
W O .
WEdge 00Y ICFn .(Int.Req.)
WW .100Y.C M.TW WW .100Y.C Canceler M
NoiseW
.T WDetector .1 MT
W
O W O W .C O
W
WW .100ICPn Y.C .TW WW .100Y.C M.TW WW .100Y M.T
W
W O M W O W W .C O
Y
M.T
W
O W O W W .C O
WW The Y.C Comparator W WW .C
00Yonly trigger W W Y
.10–0 not OM.T
W
W
Note:
W .100 Analog O M.T Output (ACO).1can
W O M.Tthe Timer/Counter1 W W ICP
.C
WW Timer/Counter3, Y.C .T4W or 5. WW .100Y.C M.TW W .100
Y
M.T
W
W . 100 O M W O
C the Input W W .C O
W occurs 0Y.on Y W
WW .100Y.C M.TW
When a change of the logic level (an W event) W CaptureW Pin (ICPn), alternatively
W .10this O M.Tconfirms to theWsetting W .100 M.T
Oedge
on theWanalogW ComparatorO output (ACO), and change
C of .C
the
Y.C W WW .100Y. M.T
W W Y
.1of00the counter .TW
W
detector, W 100
a .capture will
O M be.Ttriggered. When aW capture is C triggered,
O the 16-bit value W W .C OM
WW is written Y.C .TW CaptureW
W 00Y The
. TW CaptureWFlag (ICFn) Y
.100 is set at.
TW
(TCNTn)
W .100 to the O MInput Register W .1(ICRn). O M.Input W W .C OM
Y.C as the WWis copied Y. C W W 0Y
the sameWWsystem .100
clock
M.T
WTCNTn value .100 intoOICRn M.T Register. If enabled W .10(TICIEn =
1), the W input W .C O W W Y .C W W
W capture 0Y flag generates
.TW an input
W capture 00 interrupt. The
.T ICFn flagW is automatically
cleared when W .10interrupt
the C OM is executed. Alternatively
W W.1 the YICFn .C OM flag can be cleared by software by
W W
1 0 0Y .
M .T W W . 1 00 M .TW
writing a logical .
Wone to its O I/O bit location. W O
W O W
WW .100Y.C M.TW WW
W O
WW .100Y.C M.TW
W O
WW .100Y.C 115
W W
7799D–AVR–11/10 W
.C OM
00Y .TW
W W.1 Y.COM W
W 00 M.T
Reading the 16-bit value in the W W.1Capture
Input .C ORegister
W (ICRn) is done by first reading the low
byte (ICRnL)Oand .T W
then the high
Wbyte (ICRnH). . 1 0 0Y When M .Tthe low byte is read the high byte is copied
M WW 00Y.CO .TW
Y .C W W
100high byte
into .the
OM
.TTemporary Register .(TEMP). 1 WhenM the CPU reads the ICRnH I/O location it
Wwill
Waccess Y .C
the TEMP W Register. W WW 00Y.CO .TW
W 00 .T .1 M
.T W WThe ICRn 00RegisterMcan .T only be written W W when.1 usingOaMWaveform Generation mode that utilizes
OM W.1 Register C O W 0Y.Cvalue.
Y.C W Wthe W ICRn 0 0 Y . for W
defining
.T the Wcounter’s 10TOP TW
.In these cases the Waveform Genera-
.100 M .T W . 1 O M W .
. C O M
W O tion mode .C
(WGMn3:0) bits must be W
set before Y the TOP .TW value can be written to the ICRn
WW .100Y.C M.TW WW .100Y M .TW W . 100 M
O W O
W O WW 00Y.C
Register. When writing the ICRn Register the
WW .100Y.C M.TW
high byte must be written to the ICRnH I/O location
WW .100Y.C M.TW W 1 .T W
before the W.low byte is OM written to ICRnL. W O
W
WW .100Y.C M.TW
O
W O For more information O
W on how to access theW16-bit W registers .CO refer to “Accessing 16-bit Registers”
WW .100Y.C M.TW on page WW110. .100Y.C M.TW W . 1 00Y M .TW
W O W O
W
WW .100Y.C M.TW
O
W O
WW 0Input
16.6.1 O
Y.C Capture W Trigger W WW 00Y.CO .TW
Source WW .100Y.C M.TW
W 0 .T 1
W.1 OM W. source OM W O
WW .100Y.C M.TW
The main WW trigger
0 0 Y.C for.Tthe W input capture WW .1unit 0 0Y.C is the .Input
MT
W Capture Pin (ICPn).
W . 1 O M W C O
W
WW .100Y.C M.TW
O Timer/Counter1 can alternatively use the analog
WW .100Y.C M.TW WW comparator .10as 0Y. output .TW
Msource
as trigger source for the
O input capture unit.W The Analog O Comparator is selectedW O
trigger
.C by setting the analog
W
WW .100Y.C M.TComparator W W
WInput .C
00Y (ACIC) .TW WW Comparator . 100Y M .TW and Status Register
. 1
Capture M bit in the Analog Control
W O WWthat00changing Y.C
O WW 00Y.CO .TW
WW .100Y.C M.(ACSR). TW Be W aware . 1 M TW source
.trigger Wcan trigger a capture. The input capture flag
W.1 Y.COM W
W C O W W . C O W
WW .100Y. must
M.T
WthereforeW be cleared
.100
Y the change.
after .TW W 00
W.1 Y.COM W
.T
W CO W W .C OM W
WW .100Y. W Y W W 00 M.T inputs are sampled
W O
Both
M.T
the Input Capture W
W .100(ICPn)Oand
Pin M.Tthe Analog Comparator W W.1 output .C O(ACO)
C W . C W (Figure 14-1 Y W
WW .100Y. using M .TWthe same technique W .
as Y
100
for the Tn.Tpin
M
W on page
W .100 88).OThe M.Tedge detector is also
W O C
W
WW .100Y.C M.TW
Oidentical. However, when
WW the Y.C canceler
noise
.TW
is enabled, WW additional 0Y. logicMis.Tinserted
.10cycles.
W before the
edge detector, which W
increases . 100 the delay O M by four system W
clock C O
Note that the input of the
W O
WW .100Y.CnoiseMcanceler .TW W W .C
00Y is always .TW WW .100Y. M .TW
and edge .1
detector M enabled unless the Timer/Counter is set in a Wave-
W CO Generation W O
Y.C to define WW 00Y.CO .TW
WW .100Y.form .T W mode WW that uses
. 1 0 0ICRn M .TW TOP. W .1 M
W W .C OM
W Y
00 input .T W .1 by software M by controlling the .1 of the O M pin.
W.1 An .C OMcapture can be triggered WW 00Y.CO .TW W WW port
0 Y.C
ICPn
W
W W
. 1 00 Y
M .T W W
W .1 O M W .1 0
O M.T
WW 00Y.CO .TW WW .100Y .C
16.6.2 NoiseW Canceler WW .100Y.C M.TW M.T
W
. 1 M W O W .C O
W
WW .The .CO canceler
noise
.TW
improves WW noise Y.C
immunity by
.TW using a simple WW digital .100
Yfiltering scheme.
M.T
W The
1 00Y canceler M W . 100 O M W C O
W noise O input is monitored over four samples, and all four must
WW .100Y be equal . for changing the
WW output 0 0 Y.C .T W WW .100Y.C M.TW M .TW
W. 1 thatOinMturn is used by the edge W detector. O W O
byWsettingY.the CO InputTW WW O
W WThe noise
Y .C O
canceler
W
is enabled W
W 0 .
Capture Noise W Canceler
00 Y.C(ICNCn) .TWbit in
W Timer/Counter1 0 0 M . T .1 0 M W . 1 O M
W. .CO .TW
Control Register B (TCCRnB).
WW 00Y.When CO enabled the noise canceler
WW .100Y.C M.TW
introduces addi-
WWtional.1four 00Ysystem clock cycles W
of delay . 1
from a change M .TW applied to the input, to the update of the
WW Register.
M
.COThe.Tnoise W
Wuses .CO clock
Ysystem W and is therefore
W
WW .1not .CO .TW
0Yaffected
WICRn 0 Y W canceler W the
0 0 .T 0 M by the
0
W
prescaler. W 00 .T W .1
W 00 .T W.1 Y.COM W M
W 0 T W 0 0 .T 1
16.6.3 Using the Input Capture 0
.1Unit M. .1 M W. OM
W
The main .challenge1 when
M using the Input .1
Capture unit is Mto assign enoughWprocessor W capacity
O
WW the Y .CO .Tevents. W W WW 00Y.CO .TW W If the .processor
1 0 0Y.C has .TW
for W handling .10 0 incoming M The time between
.1 two Mevents is critical. W OM
W O W C O W .C
WWthe .captured
not read Y.C value Win the ICRnWRegister W 0Y. theMnext .TWevent occurs, W the.1ICRn 00Y will be .TW
W 100 O M.T W .10before O W W .C OM
overwritten .C value. W result0of C
. capture Y
WW with .100
aY new
M.T
In this caseWthe
W .1 0
Ythe
M.T
Wwill be incorrect.
W
W .100
W O W C O W
WW the.1Input .C W WW Y. should W W
When using
W
00Y Capture
O M.T
interrupt, the
W .100
ICRn Register
O M.T be read as early in the inter-
rupt handler .Cpossible. WW the.1Input . C
WW routine 00Y
as WEven though
M.Tresponse time W 00Y Capture .TW
Mthe
interrupt has relatively high
priority, the W W.1 Yinterrupt
maximum .C O is Wdependent .C O on maximum number of clock
cycles it takes W to handle . 1 00 any of M TWother interrupt
.the W .1
requests. 00Y
W O W
WW .100Y.C M.TW WW
W O
WW .100Y.C M.TW
W O
WW .100Y.C 116
W W
7799D–AVR–11/10 W
.C OM
00Y .TW
W W.1 Y.COM W
W 00 .T
Using the Input Capture unit inWany W.1mode .C ofOM operation when the TOP value (resolution) is
actively changed M
W
.Tduring W is not
operation, .
Y
100recommended. M .TW
W O
. 1 00Y
Measurement M
of an external signal’s W duty cycle O
WW
W
0
O
Y.C Changing .T W WWsensing 0 Y.C requires
0must .
that the trigger edge is changed after
TW as early as possible after the ICRn
each 1 0
capture. the edge . 1 be M done
WW 0has
. OM WW 00Y.CO .TW
W WRegister 0 Y.Cbeen read. .T W After a W change of the edge, the Input Capture Flag (ICFn) must be
OM
.T 1
W. by software .C OM W W.1 Y.COM W
Y .C W W W
cleared 0 Y W
(writing a logical W one to 00 I/O bitM
the .T
location). For measuring frequency only,
W .100 OM.T W .10 O M.T W W.1(if anYinterrupt
.C O
the clearing
WW .100Y of .C
the ICFn Flag is not required handler
W is used).
W . 100 O M .T
W O
W
WW 16.7 .CO .TW WW .100Y.C M.TW WW .100Y.C M.TW
.1 00YOutputM Compare Units W O W O
W
WW .100Y.C M.TW
O
The 16-bitWcomparator CO continuously compares W TCNTn O with the Output Compare Register
W O
WW .100Y.C M.TW (OCRnx). WW If TCNT 0 0 Y.equals .T
OCRnx
W the comparator WW .10signals 0Y.C aMmatch. .TW A match will set the Output
W . 1 O M W O
W O
WWFlag .(OCFnx) Y.C at the W Y.C W
WW .100Y.C M.TW Compare 100 M .TW next timer W clock cycle.
W .100If enabled O M.T(OCIEnx = 1), the Output Com-
W O
W O
WW .100Y.C M.TW pare Flag WW generates Y.an C Output
.TWCompare W
W
interrupt. 0Y.COCFnx
.10The
W
M.TFlag is automatically cleared
W . 100 O M W C O
W O
WW .100Y.C M.TW
when the interrupt is executed. Alternatively W the WOCFnx Y. can be
Flag Wcleared by software by writ-
WW .100Y.C M.TWing a logical W .100 GeneratorO M.T uses the match signal to
one
W to its I/O O bit location. The Waveform C
W
WW .100Y.C M.TW
O W 0Y.C M.T W WW .100Y. .TW
generate W an output W . 10according O to operating mode W set by the C O MWaveform Generation mode
W O W .C WW .100bits. Y. The TOP W
WW .100Y.C M.T(WGMn3:0)
W W bits and.1Compare 00Y .TW mode (COMnx1:0)
Output
M W OM.T and BOTTOM signals
O W O Y. C
W
WW .100Y.C M.are TWused by W theWWaveform Y.C .TWfor handling WWthe .special 100 cases
W
M.Tof the extreme values in
W . 100 Generator O M W C O
W O some modes of operation Y.C “Modes WWon page .
Y120.) W
WW .100Y.C M.TW WW .100(See M .TWof Operation” .100 M.T
W O W C O
W
WW .100Y.C A
O special feature of
WWOutput Y.C .TWA allows itWto define
W 0Y.Timer/Counter
M.T
W TOP value (i.e.,
M .TW W .100Compare O M
unit
W .10the
C O
W Ocounter resolution).W Y.toC the counter WW the.1TOP . .TW the period time
WW .100Y.C M.TW W In addition . 100the Waveform M .TW resolution, 00Y valueMdefines
for waveforms generated W by O Generator. W C O
W O
W
O W O W . C O
W Figure
WW .100Y.C M.TW
16-4 shows aWblock W diagram Y.Cof the.Output TW Compare WWunit..1The 00YsmallM Wthe register and
“n”.Tin
W .100number O M W C O
W bit
CO
WW .100Y.Compare
names
.T W
indicates the device
WW .100Y.C M.TW
(n = n for WW .100Y.
Timer/Counter n), and the
M
“x”
.TW
indicates Output
M unit (A/B/C). The W elementsCofOthe block diagram that Ware not directly O a part of the Out-
W
WW .100Y .CO .TWunit are gray
put Compare WWshaded. 0 0Y. .TW WW .100Y.C M.TW
.1 M W O
W OM W O
WW .100Y.C M.TW
W O
W FigureO16-4. Output Compare
WW Unit,
W .CO Diagram WW .100Y.C M.TW
WW .100Y.C M.TW
Block .TW
. 100Y M W O
W O
W
WW .100Y.C M.TW
O
WW .100Y.C DATA W (8-bit) WW .100Y.C M.TW
.TBUS
M WW 00Y.CO .TW
W W Y .C O
W W WW 00Y.CO .TW W
W
W .100 O M.T .1
W(8-bit) .C OM W W.1 Y.COM W
. C W W
WW .100Y Y W .100 .T
TEMP
M .TW W
W . 100 O M .T W C OM
W .C O W Y . C W W W 0 Y . W
WW .100Y M .TW W
W .100 O M .T W .10 O M.T
W O W .C WW .100Y .C W
WW .100Y.C M.TW OCRnxHW . 00Y Buf. (8-bit)
1OCRnxL M .TW
TCNTnH (8-bit) W TCNTnL .(8-bit) O M.T
W O W
Buf. (8-bit) O W C
WW .100Y.C M.TW WW (16-bit . 0Y.C M.TW
10Register)
W .100
Y
M.T
W
W O OCRnx BufferW O TCNTn (16-bit
W W Counter)
.C O
Y
M.T
W
W O W O W W .C O
Y
M.T
W
W O W O W W .C O
WW .100Y.C M.TWOCRnxH (8-bit)W OCRnxL
W 0Y.C M.TW
.10(8-bit)
W .100
Y .TW
W O W C O W W .C OM
WW .100Y.C M.TW OCRnx (16-bit WW .100Y. M.T
W W .100
Y .TW
W O W
Register)
C O W W .C OM
W W .100
Y .TW
W O W C O W W .C OM
WW .100Y.C M.TW WW .=10(16-bit 0Y.Comparator M.T
) W W .100
Y
W O W C O W W
WW .100Y.C M.TW WW .100Y. OCFnxW
M.T
(Int.Req.) W
W O W C O
WW .100Y.C M.T W WW Waveform Y. W
.100 Generator M.T
TOP
OCnx
W C O BOTTOM
W W .C O
W . .TW 00 Y
W 00Y W
W.1 COMnx1:0
W W.1 Y.COM W W
W 00 .T W WGMn3:0
W W.1 Y.COM W
W 00 .T
W W.1 Y.COM
W 00
W W.1 117
7799D–AVR–11/10 W
.C OM
00Y .TW
W W.1 Y.COM W
W 00 M.T any of the twelve Pulse Width Modulation
The OCRnx Register is double W W.1 when
buffered .C Ousing
(PWM) modes. M .TWthe Normal
For
W and Clear .
Y
100 Timer M on.TW Compare (CTC) modes of operation, the
C O W W .C O
Y . W W 0 Y .T W
double. 1 00bufferingMis.Tdisabled. The double W . 10buffering O synchronizes
M the update of the OCRnx Com-
W W Register .C O W Y .Cthe counting W
pare Y to either W TOP orW BOTTOM
.10 0 of .T sequence. The synchronization
W
W .100 O M.T W Wnon-symmetrical .C OM PWM pulses, thereby making the out-
W prevents
WW .100Y the .Coccurrence W of odd-length,
W 00Y .T W
O M.T put glitch-free.
Y.C WW .100Y .C W W 00
.100 M.T
W
W O M.T W.1 Ybut OthisM.T
W O The OCRnx C
Register access may seem W complex, .C is
WW .100Y.C M.TW WW .100Y .
M .TW W . 100 M .Tnot
W case. When the double buffering
O W O
W O is WW 00Y.C
enabled, the CPU has access to the OCRnx
WW .100Y.C M.TW
Buffer Register, and if double buffering is dis-
WW .100Y.C M.TW W
abled theWCPU . 1 will access .T W
M the OCRnx directly. W TheYcontent
W O .CO .TW WW (the .CO .of the OCR1x (Buffer or Compare)
TW does not update this register
WW .100Y.C M.TW WW is only
Register 1 0 0 Ychanged by a write operation . 1 0 0 Timer/Counter M
W. OM W O
W O
WW .100Y.C M.TW automatically WW .as 00theY.CTCNT1.Tand W ICR1 Register). WW .1Therefore 0 0Y.C M .TW is not read via the high byte
OCR1x
W 1 O M W O
W O
WWregister .C is W Y.C to .T W the low byte first as when
WW .100Y.C M.TW
temporary (TEMP). .THowever,
W it W a good0practice read
W . 1 00Y
O M W .1 0 O M
W O accessingW other 16-bit Y.C registers.W Writing theWOCRnx W Y.C must
Registers TWbe done via the TEMP Reg-
WW .100Y.C M.TW ister since W
the . 100
compare of M
all
.T
16 bits is done W .100
continuously. O
The M.high byte (OCRnxH) has to be
O W O Y. C
W
WW .100Y.C M.TWwritten first. WWWhen 0 0 C
Y.high .T W WisWwritten . 1 0 0by M .TWthe TEMP Register will be
. 1 the OM byte I/O location W the O CPU,
W O WW Y.C Then WWbyte .(OCRnxL) 0Y.C is .TW to the lower eight bits,
WW .100Y.C M.TW updated byWthe value . 1 0 0
written. M .T W when the low
W 1 0
O Mwritten
W O W O Weither0the Y. C
WW .100Y.C M.Tthe W high byte WwillW be copied Y.Cinto the .TW upper 8-bits Wof .1 0 OCRnx
W
M.Tbuffer or OCRnx Compare
W . 100 O M W C O
W
WW .100Y.C M.TW
O Register in the same
WW .system Y.Cclock .cycle. TW WW .100Y. M.T
W
W 100 O M W C O
W
WW .100Y.C MFor
O
.TW more information WW of.10how 0Y.Cto access .TWthe 16-bitW
W
registers 0Y. to “Accessing
.10refer M.T
W 16-bit Registers”
W O M W C O
W
WW .100Y.C M.TW
O on page 110.
W
W O W C O
WW Output .CO .TW WW .100Y.C M.TW WW .100Y. M.T
W
16.7.1 WForce.1 00Y Compare
M W O W C O
W O
WW .100Y.C In non-PWM .TW Waveform WW Generation Y.C modes, .TWthe matchWoutput
W 0Y.comparator
.10the
W
M.T can be forced by
M W . 100 O M W of
C O
W O
WW .100Y.Cwriting aW one to the W W Output
Force Y.C .TW WW 0Y. .TW will not set the
M .T W .100 Compare O M
(FOCnx) bit. Forcing
W .10compare
C OM match
W O
WW .the Y.C but.Tthe WW Y. as .ifTW
WW .100Y.C M.TW
OCFnx Flag or reload/clear timer, W OCnx pin will be updated a real compare
W 100 bitsOsettings M W .100 O M
W match
.CO .TW had occurred (the COMn1:0 define WW .100Y.
whether the OCnxC pin is set, cleared or
WW .100Y WW .100Y.C M.TW M .TW
OM
toggled). W O W O
W
W O W O
16.7.2 Compare
W
WWMatch 0 Y.C
O by TCNTn Write
Blocking .T W WW .100Y.C M.TW WW .100Y.C M.TW
0 O
W.1 CPU M
.COwrites W O
Y.Cblock any WWthat00occurs Y.C in the W
WW .All 00Y .T to
Wthe TCNTn WW Register
.1 0 0will M .TWcompare W match
. 1 M.T next timer
1 O M W O W .C O
W clockYcycle,
WW same .C even Wwhen theW timer
W is stopped. Y.C This.Tfeature W allows WWOCRnx toY be initialized
.100 clock .TW to the
. 1 00 value M as .TTCNTn without .
triggering
W 100 an interrupt O M when the W
Timer/Counter C O Mis enabled.
W O WW .100Y .
WW .100Y.C M.TW WW .100Y.C M.TW M .TW
W O W O
16.7.3
W
WW Compare
Using the Output 0
O
Y.C Unit.TW WW .100Y.C M.TW WW .100Y.C M.TW
1 0 CO
W. .CO
M W W Y
O
.Cwill W W WW 0for 0 Y.one W
WWSince.1writing
0 0 Y TCNTn
M .T W in any mode W of operation
W . 1 0 0
O
block
M .T all compare matches
W . 1 O M.T clock
timer
O
W there are risks involved when Y.C W Y .C W
cycle,
WW .100Y.C M.TW WWchanging . 100
TCNTn T
M . when
W using W any of the0Output
.1 0
Compare
M.T
channels, independentO of whether the W Timer/Counter O is running or not.
W WIf the value .C O written to
W WW 00Y.C .T W WW .100Y.C M.TW W . 1 00Y M .TW
TCNTn W. 1
equals the OM OCRnx value, the compare match will be missed, resultingW in incorrect O wave-
Y.C Do not WW 00Y.CO .TW WW with Y.C
00variable .TW
WW generation.
form . 1 0 0 M .T Wwrite theW TCNTn . equal
1 to TOP
M in PWM modes W . 1 O MTOP
W O W O W .C
WW The
values. Y.C match
compare W for the TOP WWwill be 0Y.C and
.10ignored
W
M.Tthe counter will W
W continue Y
.100 to 0xFFFF. .TW
W .100 O M.T W C O W .C OM
Similarly,
WW do.1not .C the.TTCNTn
write W value WequalW to0BOTTOM Y. when W the counter W is downcounting.
.100
Y .TW
W
00Y
O M W .1 0 O M.T W W .C OM
.C should WW before Y. C Y W
The W W of the
setup YOCnx W be performed .100 setting Mthe.TWData Direction W Register .100 forOthe M.T
W .100 O M.T W .C O W W Y .C
port pin WW to output.0YThe
0
.C easiest .TWway of setting WW the.1OCnx 00Y value M.T
isW to use theW Force Output
.100 Com-
pare (FOCnx) W .1strobe O
bitsMin Normal mode. W
The OCnx C O
Register keeps its W
value W even when
W W 0 0 Y.C .T W WW .100Y. M .TW W
changing between . 1
W Waveform M
O Generation modes. W O
Be aware that W the COMnx1:0 O bits are not double W
WW buffered .CO together with the compare value.
WW .100Y.C M.TW . 1 00Y
Changing the COMnx1:0 W bits
O will take effect immediately. W
WW .100Y.C M.TW WW
W O
WW .100Y.C M.TW
W O
WW .100Y.C 118
W W
7799D–AVR–11/10 W
.C OM
00Y .TW
W W.1 Y.COM W
W 00 .T
16.8 Compare Match Output Unit W W W.1 Y.COM W
.T W 00 .T
The Compare
.C OM Output mode (COMnx1:0) W W.1 bitsY.have C OMtwo functions. The Waveform Generator uses
W
the 1 00Y
COMnx1:0
. Mbits.TW for defining
Wthe Output
W . 100 Compare O M .T(OCnx) state at the next compare match.
W W .C O W Y .C W
W Secondly Y
00 the COMnx1:0 .T W W
bits control the .OCnx 0 .T
0 pin output source. Figure 16-5 shows a simplified
W.1 of .C OM W 1 Y.COM W
WCOMnx1:0
W W
schematic Y the logic W
affected byWthe 00 bit setting. .T The I/O Registers, I/O bits, and I/O
O M.T
W
W .100 O M.T W W.1 the Y .C OM
.C pins
WW .100Yin the figure
.C are shown in bold. Only parts of the
.TWgeneral I/O Port Control Registers
100Y M .TW M .TW W
W . 100 O M
. (DDR and
WW 00Y.C PORT) O that are affected by the COMnx1:0 bits are shown. When referring to the
W O
WW .100Y.C M.TW W .T W WW .100Y.C M.TW
OCnx state, 1
W. theY.reference M is for the internal WOCnx Register, O not the OCnx pin. If a system reset
W O
WWthe OCnx CO WW .100Y.C M.TW
WW .100Y.C M.TW occur, 1 0 0 Register .T Wreset to “0”.
is
W. OM W O
W
WW .100Y.C M.TW
O
W O
W O Figure W W
W 16-5. .1Compare .CO Match WOutput Unit, WWSchematic 0Y.C M.TW
WW .100Y.C M.TW 00Y .T . 1 0
W OM W O
W
WW .100Y.C M.TW
O
W O W O
W
WW .100Y.C M.TW
O
COMnx1 W W O
W O
WW .100YWaveform .CO .TW WW .100Y.C M.TW
WW .100Y.C M.TW COMnx0 M W O
W O
WW .100Y
W .CO .TW D Q
WW .100Y.C M.TW
WW .100Y.C M.TW FOCnx Generator
M W O
W O
W
WW .100Y.C M.TW
O
WW .100Y.C M.TW WW .100Y.C 1 M.TW
W O W O OCnx
W
WW .100Y.C M.TW
O
WW .100Y.C M.TW OCnx WW .100Y.C M.TW Pin
W O W .C O W W 0.CO W
C W .TW Y
WW .100Y. M.T
W W .100
Y W 00
W.1 Y.COM W
.T
W CO W W .C OM W
WW .100Y. M.T
W W .100
Y .TW D Q W W.100 OM
.T
W CO W W .C OM W Y.C W
WW .100Y. M .TW W . 100
Y
M .TW W
W .100 O M.T
W O C
W
WW .100Y.C M.TW
O
W
DATA BUS
W O W C O
W
WW .100Y.C M.TW
O
WW .100Y.C M.TPORT W WW .100Y. M.T
W
W O W C O
W O
W
W O D Q W C O
W
WW .100Y.C M.TW
O
W
O W O W .C O
W
W
O W O W .C O
W
WW .100Y.C M.TW WW .100Y.C DDR .TW WW .100Y M.T
W
O W O M W .C O
W
WW .100Y.CclkI/O M.TW WW .100Y.C M.TW WW .100Y M.T
W
O W O W .C O
W
W
O W O W .C O
W general
WW The .C I/O.Tport W functionWisWoverridden Y.C by the .Output
TW Compare WW(OCnx) .100
Yfrom the .Waveform
MT
W
. 1 00Y M W . 100 O M W C O
W O WW pin .direction .
WW .100Y.C M.TW
Generator.Cif either of the COMnx1:0 bits are set. However, the OCnx Y (input TWor out-
WW put).1is00still
Y
M
controlled .TW by the Data Direction Register (DDR) for the portW 100The Data
pin. O M.Direction
O W O .C
W
WWRegister .C W pin (DDR_OCnx) WW .100must Y.C .TW WW .100Y W
M.Tis visi-
. 1 00Y bit for the M .TOCnx W beMset
O as output beforeW the OCnxCvalue
. O
WWon the .C O W Y.C W Y Generation W
Wble 1 00Ypin. The M TW override W
.port function.1is00generally M .TW
independent Wthe Waveform
of
W .100 O M.T
. O W O W .C
WW but
mode, Y.C are.Tsome
00there W exceptions. WW Refer .C Table.T16-1,
Yto W TableW16-2 and Y
.100Table O16-3
W
M.Tfor
W
W . 1 O M W .100 O M W W .C
details.
Y
M.T
W
W O W C O W W .C O
WW
The design of0Y .COutput.TCompare
the W pin W allows
Wlogic Y.initialization W of the OCnx W state.1before 00Y theM .TW
out-
W . 10 O M W .100 O M.T W W .C O
put isWenabled.YNote .C that some COMnx1:0WW .bit Y. C
settings are
TWreservedW for certain modes of.TW
Y
W .100“16-bitOTimer/Counter
M.T
W
W 100 on page O M.108. W .100 OM
operation.WSee 1 with PWM”
WW .100Y. C W Y.C .TW
WW .100Y.C M.TW M .T W W
W . 1 0 0
OM
W O W C O W .C
The COMnx1:0
WW .100Y.C M.TW
bits have no effect on theWInput W Capture Y. unit. .TW W .100
Y
W O W .100 O M W W
W Y.C Generation W WW .100Y. C W W
16.8.1 Compare Output Mode Wand
W .100
Waveform O M.T W O M.T
Y.C uses.Tthe WWbits differently C
Y. in normal, W CTC, and PWM modes.
The Waveform WW Generator .100 M
W COMnx1:0 .100 M.T
W O W C O
WW setting .C COMnx1:0 W = 0 tells WWthe Waveform Y.
For all modes,
W .100
Ythe
O M.T W .100 Generator that no action on the
OCnx Register W is to be Y .C
performed on
W the next W
compare
W match. For compare output actions in the
W
W .100 O M.T
WW .100Y.C M.TW
W O
WW .100Y.C 119
W W
7799D–AVR–11/10 W
.C OM
00Y .TW
W W.1 Y.COM W
W 00 M.T For fast PWM mode refer to Table 16-2 on
non-PWM modes refer to TableW W.1on page
16-1 .C O130.
page 130, and M .TW
for phase correct
W and phase . 100 and
Y
M .TW
frequency correct PWM refer to Table 16-3 on
C O W W .C O
Y . W W 0 Y .T W
page.1131. 00
OM
.T .10 M
W W Y .C W W WW 00Y.CO .TW
W A change 00 M.T .1have effectMat the first compare match after the bits are
W W.1 ofY.the C OCOMnx1:0
W
bits state will
WW 00Y.CO .TW
.T W Wwritten..1For 00 non-PWM .T modes, the action W .1can be forced M to have immediate effect by using the
C OM W W strobe .C OM WW 00Y.CO .TW
Y. W FOCnx
W 0 Y bits. W W
00
W.1 Y.COM W
.T .10 M.T .1
WW 00Y.CO .TW
M
W W WW 00Y.CO .TW W
W .100 Modes .T .1 M .1 M
W W16.9 .COM of Operation
W 00 Y .T W .1 M .1 M
W W.1 Y.COM W The mode WWof operation, Y .CO i.e., Wthe behavior W
W ofW the Timer/Counter
0 Y .CO .TW and the Output Compare pins, is
W 00 .T W . 0
10combination M T
. of the Waveform Generation .1 0 M (WGMn3:0) and Compare Output
.1 M defined by W the O W O
mode
W O W Y.C The WW mode Y.C .TWaffect the counting sequence,
WW .100Y.C M.TW modeW(COMnx1:0) . 100 bits.OM .TW Compare Output W .100 bits O doMnot
W O W Y.C W .C
WW .100Y.C M.TW while the WW Waveform 100 Generation M .TWmode bitsWdo. The 00Y
.1COMnx1:0 .TW
Mbits control whether the PWM out-
W O W . O W W .C O
W .C Y W
WW .100Y.C M.TW put generated W should
. 100
Y be inverted
M .TW or not (inverted W
W
or10non-inverted
. 0 O M.TPWM). For non-PWM modes
O W O C
Y. set, cleared
W
WW .100Y.C M.TWmatch (See
the COMnx1:0
WW .100Y.C M.TW
bits control whether the output WWshould .100
be
M.T
W or toggle at a compare
“Compare
W Match O Output Unit” on page W 119.) C O
W
WW .100Y.C M.TW
O
W
W O W C O
W O For detailed timing
WW information Y.C refer to “Timer/Counter WW Timing Y. Diagrams” W on page 127.
WW .100Y.C M.TW . 100 M .TW W .100 O M.T
W O C
W
WW Normal .CO WW .100Y.C M.TW WW .100Y. M.T
W
16.9.1 . 1 00Y ModeM.TW W O W C O
W O
WW of operation Y.C is the WW(WGMn3:0 Y. W
WW .100Y.C MThe .TWsimplest mode . 100 M .TW Normal mode W .100 = O .Tthis
0).MIn mode the counting
W C O direction is alwaysWup (incrementing), W .C O W clear0is .C
Yperformed. WThe counter simply
W Y . W W 0 Y .T W
and no counterW .1 0 .T
W 00
W.1 Y.COoverruns M.T .10 M WW= 0xFFFF) OM
when itW WW its00maximum
passes Y .CO .16-bit W value (MAX W 0 Y.C and .then W restarts from the
W W
. 1 00 M .T W
W . 1 O M T
W .1 0
O MT
W BOTTOM
O (0x0000). In normal operation the Timer/Counter
WW .100Y. Overflow C Flag (TOVn) will be set in
WW .100Y.C theMsame .TW timer clock WW .100Y.C M.TW M .TW
W O cycle W as the TCNTn
O becomes zero.WThe W TOVn O in this case behaves
.CFlag
WW .100Y.Clike aM17th .TWbit, except WW that it .is1 0Y.Cset,M
0only not.TW cleared. W
However, . 1 00Y
combined with
W
M.Tthe timer overflow
W O W C O
W CO WW clears Y.C W the timer WWresolution Y. TW
WW .100Y.interrupt M
W automatically
.Tthat . 100 the TOVn M .TFlag, W .100 canObe M.increased by soft-
W C O W W . C O W Y.C W
WW .100Y. ware. There
M .TW
are no special
W cases
.100
to
Y consider
M .TW in the Normal W mode,
W
a
.100 new counter
O M.T value can be
O anytime. W O . C
W written
W
O Capture unit is easy W O W .C O
W
WW .10The 0Y.C Input
.TW WW to.10use 0Y.C in Normal .TWmode. However, WW .observe 100
Y that .the W
M T maximum
M W O M W .C O
W interval
WW .between .CO between the externalW
.TWare too long, W events must .Cnot exceed
00Y overflow .TW WW of.1the
the resolution
00Ycounter. If the
W interval
M.Tbe used to
1 00Y M
events the
W .1timer O M interrupt or the W prescaler .C O
must
W .C O W .C WW .100Y W
WW extend 1 00Y the resolution M .TW for theWcapture . 00Y
1unit. M .TW W O M.T
. O W O .C
WW The
W
0Y.C M.TW WW .100Y.C M.TW WW .100Y TW
M.Using
. 1 0Output Compare units can be W used to O
generate interrupts at W
some given .C O
time. the
W .C O W Y.C W WW .100Y .TW
WW Output 1 0 0 Y
Compare .Tto
Wgenerate W waveforms .1 0 0in Normal M .Tmode is not recommended,
W M
since
O this will
W. OM W O
WW .100Y.C M.TW
WWoccupy 0 0 Y.Cmuch of
too .T W CPU time.
the WW .100Y.C M.TW
W. 1 OM W O W O
W O W O
16.9.2 Clear Timer on Compare W
WW .100Y.C M.TW
Match O (CTC) Mode
WW or00ICRn O
In Clear
WW Timer Y .ConOCompare or CTC mode
W W WW (WGMn[3:0] 0 Y .CO = .4TW or 12), the W OCRnA Y.C Register .TW
W
are used 0
.1to0 manipulate T
M. the counter resolution. 0
.1 In CTCOmode M the counter isW W .
cleared 1 to zeroO Mwhen
W O W Y.C .C
WW Y.C W matches WWeither W W
M.T (WGMn[3:0]W=W4).10or the
0Y ICRn .TW
the counter
W .100valueO(TCNTn) M.T W .100the OCRnA O .C OM
Y.CThe OCRnA WW . C W Y W
WW .1=0012).
(WGMn[3:0]
M.T
W or ICRn define.1the
W
00Ytop value
O M.Tfor the counter,W
W hence
W .100also itsOres-M.T
W O C .C
olution.WWThis.1mode 00Y
.C allows TWgreater control WW of .the 100
.
compare
Y
M.T
W
match outputW frequency. Y
.100 It also .TW
simplifies W
the operation O M.counting
of external W
events. C O W W .C OM
W W .100
Y
W O W C O W W
The timing WW diagram 0Y.forC the CTC
.TW mode isWshown
W in FigureY. 16-6. WThe counter W value (TCNTn)
W .10compare O M W .100 O M.T
increases until a match occurs with either
WW .100Y. OCRnA C or ICRn, and then counter (TCNTn)
W W
. 1 0 0Y.C M.TW M .TW
is cleared. W O W O
W O W
WW .100Y.C M.TW WW
W O
WW .100Y.C M.TW
W O
WW .100Y.C 120
W W
7799D–AVR–11/10 W
.C OM
00Y .TW
W W.1 Y.COM W
Figure 16-6. CTC Mode, Timing
W
W .100
Diagram OM
.T
W .C
M .TW W . 100
Y
M .TW
W O
.CO .TW WW .100Y.C M.TW OCnA Interrupt Flag Set
. 1 00Y M W O or ICFn Interrupt Flag Set
W W .C O W Y .C W (Interrupt on TOP)
W 00 Y .T W W . 10 0 M .T
W . 1 O M W O
M W O W O
0 Y.C
O
0 O
W.1 OM W Y.C
O W
WW .100Y.C M.TW
WW .100Y.C M.TW WWTCNTn 1 0 0 .T W
W. OM W O
W
WW .100Y.C M.TW
O
W O
WW .100Y.C M.TW WOCnA . 1 M (COMnA1:0 = 1)
W W .C O
W
(Toggle)
W 00 Y .T W .1 4 OM
W.1 Y.COM W Period W.1 M 3 W
W .C1O .TW 2 W Y.C W
WW
. 1 00 M .T W
W . 10 0 Y
O M
W
W .100 O M.T
W O
WWcan.1be Y.C W Y.C .TW the TOP value by either
WW .100Y.C M.TW An interrupt 00generated M .TatWeach timeWthe .100 value
counter
W O M reaches
W O W O W register Y. C
WW .100Y.C M.TWusing theWOCFnA.1or
W 00ICFnY.C Flag.Taccording W Wthe
to .100 used M
W the TOP value. If the
to.Tdefine
W O M W C O
W O W C
theY.interrupt WWcan be Y. for updating W the TOP value. How-
WW .100Y.C M.TW interrupt isW enabled,
. 100 M .Thandler
W routine
W .100
used
O M.T
O ever, changingWthe TOP Y W O
to.Ca value close C
. counter
W
WW .100Y.C M.Tlow W W to BOTTOM WW when Ythe
.100modeOdoes
Wis running with none or a
M.T not have the double buff-
prescaler
W
value W . 100 be done
must O M .T
with care since the WCTC C
W O W Y.C WWor ICRn Y. TW the current value of
WW .100Y.C M.ering TW feature.WIf the new . 100 valueOM .TW to OCRnA
written W .100 is lower O M.than
W O W .C W Y. C
WW .100Y.C MTCNTn, .TW the counter WW will.1miss 00Y the compare .TW match.W The counter .100 will then TW to count to its max-
M.have
W O M W C O
W O
WW and Y.C around WW before Y. W match can occur.
WW .100Y.C imum M .TWvalue (0xFFFF) .100
wrap
M .TW starting at 0x0000
W .100 theOcompare M.T
OIn many cases this feature W O .C
W
WW .100Y.C M.TW WW .1is 00Y
not.Cdesirable. .TW
An alternative WW will.1then 00Y be toM use
.TW the fast PWM mode
using OCRnA for defining W TOP O
(WGMn3:0 M = 15) since the W OCRnA O
then
C will be double buffered.
W
WW .100Y.C M.TW
O
W inOCTC T W O
W O generating a waveform
For WW output .C mode, the OCnA WW output 00canY.Cbe set.TtoWtoggle its logical
WW .100Y.C M.TW .1 00Y M . W W . 1 OM
W level
C O on each compare WW match by.Csetting O the CompareWOutput Y.C bits.Tto
mode W toggle mode
W W 0 Y. .T W W 0 0 Y .T W W . 1 0 0 M
0 . 1 M
W
(COMnA1:0
W.1 Y.COM W = 1). The OCnA value
WW 00Y.CO .TW
will not be visible on the
W WW 00Y.CO .TW direction for
port pin unless the data
W 00 the pinM is.Tset to output (DDR_OCnA W = 1). The waveform generated .1 will have M a maximum fre-
W.1 quency .C O of f W W.1 Y.COM W WW The 0 Y .CO .TW
W Y W = f W /2 when OCRnA
0 is set
.T to zero W
(0x0000). 0 waveform frequency is
W
W .100 O M.TOCnA clk_I/O WW.10 .C OM W W.1 Y.COM W
WW .100Y defined.C by the W following equation:
W 00Y .T W W 00 .T
W O M.T W.1 Y.COM fW W W.1 Y.COM W
.C W W 00 .T
WW .100Y M.T
W W 100 = ---------------------------------------------------
.T clk_I/O W.1 Y.COM W
W C O W Wf .OCnA . C2 O M N   1 + OCRnA  W
WW .100Y . W W 00Y .T W W 00 .T
. C W .T64, 256, or W 0 .T
WW The Y
.10N0 variable .TW W 00 0
W.1 Y.COM W
W .C O Mrepresents the prescaler
W W.1 factor Y .C O(1,M8,
W
1024).W 0
WW .100Y W W .10 .T
AsW for the Normal O M.Tmode of operation,
W
Wthe.100TOVn O FlagM.Tis set in the same W W
timer clock .C OM that the
cycle
.C W Y . C W W 0 Y W
WWcounter .1
Y
00counts from
M .TW MAX to
W
0x0000. W . 100 O M .T W .10 O M.T
W O W .C
Y
M.T
W
W O W O W W .C O
16.9.3 Fast PWM Mode WW .100Y.C M.TW WW .100Y.C M.TW W .100
Y
M.T
W
W O W O W W .C O
The
WWfast .Pulse 00Y
.CWidth Modulation TW orW fastW PWM0mode 0Y.C (WGMn[3:0] TW
M.fast
= 5, 6,W7, 14, .or Y
10015) provides M.T a
W
W 1 Y.PWM O M.waveform W .1option. O W W .C O
WW .100Y.C M.TW
highW frequency C generation The PWM differs from the Yother PWM
.TW
W
options W by.1its00 single-slope W
M.T operation. The Wcounter O
counts from BOTTOM
W
to W
TOP.100then restarts OM
O C W .C
W Y.C W Compare WW Output Y. W W Y
.100 is set .TW
from WBOTTOM.
W .100 In non-invertingO M.T W .100 mode, O the.TOutput Compare W
M W
(OCnx)
.C OMon
.C WWOCRnx, Y.C W Y .TW
WW .1match
the compare 00Y between W
M.T TCNTn and W W .100 and cleared O M.T at TOP. In inverting
W
W .100Compare OM
W O .C W Y .C
Output WmodeW output Y.C is cleared .TWon compare W match.1and 00Yset atM TOP..TWDue to the Wsingle-slope .100 oper-
W . 100 O M W C O W W
ation, theW operatingYfrequency .C of the fast PWM
.TW PWM W
W mode Y. be twice
can Was high asWthe phase correct
and phase and
W
W
00
.1frequency O Mcorrect modes W .100 use dual-slope
that O M.T operation. This high fre-
Y.C WW for.10power 0Y. C
W W .TW rectification, and DAC
quency W makesWthe .100fast PWM M .Tmode well suited W .CO
M
regulation,
WWHigh.1frequency .CO allows .TW physically WW 00Y external components (coils, capaci-
applications. 00Y M small.1sized
W
WW 0total O
tors), henceWreduces 0Y.Csystem W
.Tcost. WW
W . 1 O M
WW .100Y.C M.TW
W O
WW .100Y.C 121
W W
7799D–AVR–11/10 W
.C OM
00Y .TW
W W.1 Y.COM W
The PWM resolution for fast PWM
W
W .100be fixed
can OM
.T
to 8-, 9-, or 10-bit, or defined by either ICRn or
W .C
OCRnA. TheOminimum M.T
W W
resolution allowed
Y
.100 is 2-bit M .TW or OCRnA set to 0x0003), and the max-
(ICRn
W O
0Y.C Mis .TW WW Y.C .TW The PWM resolution in bits can be
imum . 1 0resolution 16-bit (ICRn or OCRnA
W . 100 setOtoMMAX).
W .C O W Y.C
WWcalculated
1 00Yby using M .T theWfollowingW equation:
. 100 M .TW
W . O W O
.C  TOP.T
.TW WW .100Y.C M.TW WRW .10=0Ylog M +W 1 -
----------------------------------
O M W C O FPWM
W W .C logO  2 
00Y
.C .TW WW .100Y .
M .TW W . 100
Y
M .TW
.1 M O W O
W O WW Y.C the .counter WW .10until 0Y.Cthe M .TW value matches either one of the
WW .100Y.C M.TW InWfast PWM
. 1 00mode M TW is incremented
W O
counter
O W O .C
W
WW .100Y.C M.TW WWvalues
fixed Y.C
000x00FF, .0x01FF,
TW WW .1(WGMn[3:0]
or 0x03FF 00Y M .T=W5, 6, or 7), the value in ICRn
. 1 O M
W = 14), or the value in OCRnAW(WGMn[3:0] W O
W O (WGMn[3:0] .C = 15)..TThe W counter is then cleared at the
WW .100Y.C M.TW WW .100Y.C M.TW W .1for00Y M
following timer
W clock cycle.
O The timing diagram W the fast O PWM mode is shown in Figure 16-7.
W O
WW .100Y.C M.TW The figure WW shows 0 0 .C
Yfast .T W W
WOCRnA . 1 0 0Y.C M.TW
W. 1 PWM M mode when or ICRn is used to define TOP. The TCNTn
W W .C O
W 00 Y .T W
value is in the .timing 10 0 diagram T
. shown as a histogram .1 for illustrating M the single-slope operation.
W.1 Y.COM W The diagram WW .C OM WWPWM Y .CO The W
W W includes 0 Y non-inverted .T W and W
inverted 0 0 outputs. .T small horizontal line marks
W
W .100 O M.T on the TCNTn W .10
slopes .C OM
represent compare W
matches W.1 between Y .C OM OCRnx W and TCNTn. The OCnx
C W .TW
WW .100Y. M .TWInterrupt W .
Y
100set when M
W
W .100 O M.T
Flag W
will be O a compare match occurs. C
W
WW .100Y.C M.TW
O
W
W O W C O
W O
WW .100Y.C M.TFigure W 16-7.WW Y.C .TW Diagram WW .100Y. M.T
W
Fast PWM
W . 100 Mode, O M Timing
W C O
W
WW .100Y.C M.TW
O
M.T OCRnx / TOP Update
W O W C O
W
WW .100Y.C M.TW
O
WW .100Y.C M.TW WW .100Y. M
and
.TSetW TOVn Interrupt Flag
and OCnA Interrupt
W W .C O
W WW 00Y.CO .TW W WW 00Y.CO .T FlagWSet or ICFn
W 00 Y .T W .1 M .1 M Interrupt Flag Set
W.1 Y.COM W WW 00Y.CO .TW W WW 00Y.CO (Interrupt W on TOP)
W W
. 1 00 M .T W
W . 1 O M W .1 O M.T
W O WW .100Y. C
W
W O W C O
W
WW .100Y.C MTCNTn
O
W
W O W C O
W
WW .100Y.C M.TW
O
W
W O W C O
W
WW .100Y.C OCnx
O
.TW WW .100Y.C M.TW WW .100Y. (COMnx1:0 M.T= 2)
W
O M W O W .C O
W
W
O W O W .C O
W
WW .100Y.C M.TW
OCnx
WW .100Y.C M.TW WW .100Y (COMnx1:0 =
M.T
3) W
W O W .C O
W
WW .100Y.Period CO WW .100Y.C M.TW WW .100Y W
M .TW 1 W 4 O5 6 8 W O M.T
W O 2 3 7
WW .100Y .C
W
O W O W .C O
W
WW The 0Y.C M.TWOverflow W
W Y.C each .TWtime the counter WW reaches .100 TOP.
Y .TW
. 1 0Timer/Counter Flag (TOVn)
W . 100 is set O M W C O MIn addition
W .C O W Y .C W W
W is set 0 Y . W
WW the .OCnA
1 00Y or ICFn M .TFlag
W is set W at the same
W .100 timerOclock M .T cycle as TOVn W .10when either O M.TOCRnA
O
orWICRn is used for defining the W TOPW value.00IfYone .C of the interrupts are WW enabled, Y .C
the interrupt W
han-
WW .100Y.C M.TW . 1TOP and M .TW W .100 O M.T
dlerW routine can O be used for updating W
the O compare values. W .C
Y
M.T
W
O
W changing the TOP value the W W O W W .C O
When
WW .100Y.C M.TW Wprogram Y.C ensure
must
.TWthat the new W TOP.1value 00Y is higher M.T
Wor
equalWto the value O of all of the Compare W .100
Registers. O M
If the TOP value is W W
lower than .C O
any of the
WW .1Registers, 00Y
.C W WW .100Y.C M.TW W Y
100 the OCRnx. M.T
W
Compare W O Ma.Tcompare matchWwill W never occur
.C O between the TCNTn W W .and
.C O
WWthat .when Y.C .TW TOP values W the .1unused 00Y bits .TWmasked to Wzero when Y
.100 anyOofMthe .TW
Note
W 100 using O Mfixed W C O Mare W W .C
OCRnxWW Registers Y.Care written. W WW .100Y. M.T
W W .100
Y .TW
W C
0Y.updating W WW updating Y. W W defining Y
.100 the TOP .TW
The W procedure
W .10for O M.TICRn differs from W .100 OCRnA O M.T when used forW W .C OM
Y.C W C
0Y. means W Y
value.WThe W ICRn00Register
.1 M.T
W double W
is not buffered.
W .10This O
W
M.Tthat if ICRn is changed W .100to a low
W O Y. C W
value when WW the.counter 00Y
.C is running TW with none WW or a low0prescaler
.1 0
W there isW
value,
M.T
a risk that the new
ICRn valueWwritten W 1 isY.lower O M.than the current W
value of TCNTn. C O The result will then be that the
W 0 0 C M.TW WW .100Y. M .TW
counter will miss . 1
the compare match at the TOPWvalue. W The O
counter will then have to count to the
WW 00Y.CO .TW
W(0xFFFF) W at 0x0000 1
.C
00Ybefore the compare match can occur.
MAX value . 1 and wrap O M around starting W .
The OCRnA WW 00however,
WRegister Y.C W
.Tdouble
is WW This feature allows the OCRnA I/O location
buffered.
W . 1 O M
WW .100Y.C M.TW
W O
WW .100Y.C 122
W W
7799D–AVR–11/10 W
. C OM
00Y .TW
W W.1 Y.COM W
W 00 .T
to be written anytime. When theW W.1 I/O
OCRnA .C OM
location is written the value written will be put into
the OCRnA O Buffer .T W
Register.
W OCRnA
The . 1 0 Y
0Compare M .TW
Register will then be updated with the value
M WW 00Y.CO .TW
0 Y . C W W
in the .10Buffer Register .T at the next timerWclock .1 cycleOthe M TCNTn matches TOP. The update is done
W W .C OM WTCNTn Y .C W the TOVn Flag is set.
W at the same
00 Y timer clock
.T W cycle as Wthe
. 10 0 is cleared
M .Tand
. 1 O M W O
WW the00ICRn Y.C Register .TW for defining WWTOP.10works 0Y.C well .TW using fixed TOP values. By using
M .TW WUsing . 1 O M W O M when
.CO .TW WWthe 0OCRnA
ICRn, 0Y.C Register .TW is free to WW be used 10for
C
0Y.generating .TWa PWM output on OCnA. However,
.100Y M
W
W . 1 O M W . O M
W O if the
WWbase.1PWM .Cfrequency is actively WW changed 0(by Y.Cchanging .TWthe TOP value), using the OCRnA
WW .100Y.C M.TW 00Y M .TW W . 10 O M
as TOP W is clearly a Obetter choice due to its double buffer feature.
W
WW .100Y.C M.TW
O
W O WWgeneration O
W
WW .100Y.C M.TW
O In fastW
W PWM.1mode, 00Y
.C the compare .T W unitsW allow
. 1 0 0Y.C ofMPWM .TW waveforms on the OCnx pins.
Setting the W COMnx1:0 O M
bits to two will produce W a non-inverted O PWM and an inverted PWM output
W O
WW .100Y.C M.TW can be
W
Wgenerated 0 0 Y.C . T W WW .100Y.C M.TW
. 1 by setting M the COMnx1:0 W to W three (see Table
O on page 130). The actual OCnx
W O WW 00Y.CO .TW Y.C TWthe port pin is set as output
WW .100Y.C M.TW value W will only.1be visible M on the port pinW if theW data
. 100direction O M .for
W O
W O
WW .100Y.C M.TW (DDR_OCnx). WW The 0 0 Y.C waveform
PWM .T W is generated WW by . 1 0 0Y.C (or
setting TW
M.clearing) the OCnx Register at
W . 1 O M W C O
W CO the compare W match .
betweenC OCRnx and TCNTn, W and Y
clearing . (or W
setting) the OCnx Register at
WW .100Y. M .TW W . 1 00Y M .TW W
W .100 O M.T
O the timer clock W O
cycle the counter is cleared (changes . C
W
WW .100Y.C M.TW WW .100Y.C M.TW WW from .100
YTOP to BOTTOM).
M.T
W
O W O W . C O
W
WW .100Y.C M.TThe W PWM frequency WW .1for 00Y the.C output.Tcan W be calculated WW by.1the 00Yfollowing M.T
W
equation:
W O M W C O
W O
WW .100Y.C M.TW WWf clk_I/O Y. W
WW .100Y.C M.TW f = W .100
----------------------------------- O M.T
W O W O NW W Y. C
WW .100Y.C M.TW  1 + TOP
.100
W
OCnxPWM
W O C
W
WW .100Y.C The
O
.TN W WW .100Y.C M.TW WW .100Y. M.T
W
M variable represents W the prescaler
O divider (1, 8, 64, W 256, or O
1024).
C
W
WW .100Y.C M.TW
O
W
W O W C O
W OThe extreme values W for the OCRnx .C Register represents WW special cases Y. when generating
W a PWM
WW .100Y.C waveform M .TW output inWthe fast . 00Y mode.
1PWM M .IfTW the OCRnx is set W .100 to BOTTOM
equal O M.T (0x0000) the out-
W O C
W O
WW .100Y.Cput will Wa narrowWspike W 0Y.CTOP+1 .TW WW .100Y. the M .TW equal to TOP
M .Tbe W for
. 10each O M timer clock cycle.WSetting
CO OCRnx
W COresult WWhigh .or Y.C W W Y. W
WW .100Y.will M .TW in a constant 100low output M .T(depending Won the polarity
W .100 ofOthe M.T output set by the
W O C
W
WW .100Y .CO .TW
COMnx1:0 bits.) WW .100Y.C M.TW WW .100Y. M.T
W
M W O W .C O
W .CO .TW
WW .100AYfrequency (with 50% W duty W cycle)00waveform Y.C TW in fastW
.output
W
PWM mode Y be achieved
.100 can O M.T
W by set-
M W .1 O M W C
W .C O W .C W W Y . W
WW .10ting 0Y OCnAMto .Ttoggle
W its logical
W level .100
on Y each compare
M.T
matchW(COMnA1:0 00 = 1). This .T applies only
W if OCR1A O is used to define the WTOP value C O (WGM13:0 = 15). The W W.1 Y.Cgenerated
waveform
OM
WW .100Y .C
.TW W W Y
100 /2 when
.
M .T W W 00
.1(0x0000). M .TWwill have
a maximum O M frequency of f =W f . O OCRnA is set to W
zero .C O This feature is
W
WW similar 0 Y.C .T W toggleOC W
nWA clk_I/O Y.C
0 0 except . TtheW WW .100Y M .TW
1 0 to the OCnA in CTC . 1
mode, M double buffer feature of the
O Output Com-
W W. .C OM
W pare 0 Y
0unit is enabled .T in the fast PWM W .mode.
1 M . 1 M
W 0 W 1
0
W.1 Mode M.T .1
WW 00Y.CO .TW
M W. OM
16.9.4 Phase CorrectW
W
PWM
0 Y .CO .TW W WW .100Y.C M.TW
.10 correct M .1 M WW(WGMn[3:0] O
The
WWphase Y .CO Pulse W
Width Modulation
W WW 00orY.phase CO correct T W PWM mode W 0 0 Y.C = 1, .TW
2, 3,
W10, 1 0 0 .T . 1 M . W . 1 O M
or. 11) provides
WW 00Y.CPWM OM a high resolution Wphase correct CO PWM waveform W generation option. The
0Y.C onM TW
Wphase correct .T
mode W is, like the WW phase .1 0
and0Y.frequency M .TW correct PWM
W mode, . 1 0based a .dual-
WW operation. Y.C The counter W countsWrepeatedly W Y.C W (0x0000) W to TOP Y
.100and then .TW
slope
W .100 O M.T W .100 fromOBOTTOM M.T W W . C O Mfrom
TOP WWto BOTTOM. .C In non-inverting
.TW
W
Compare Y.C mode,
Output W the Output W Compare Y
.100 (OCnx) M.TisW
W . 1 00Y
O M
W
W .100 O M.T W W .C O
cleared on the compare match betweenW
W TCNTn and C
Y. OCRnx while upcounting, and0Y set on the .TW
WW .100Y.C M.TW .100 Output
W
M.TCompare mode,
W
W .10operation OMis
compareW match while O downcounting. In W
inverting C O W the .C
WW The.1dual-slope .C .TW
W Y. W W 00Y slope .TW
inverted.
W
00Y
O Moperation hasW lowerWmaximum .100 O M.T
operation frequency than
W W .1single
.C OM
Y.C to.T WW .10of0Y .C W PWM modes, Y
operation. WW However, .100 due
W
M the symmetric feature W
the dual-slope
O M.T
W
W .100 modes
these
W O C W
are preferred WW for.1motor .C
00Y control W
applications. WW .100Y. M.T
W W
W O M.T W C O
W Y.C phase W WW .100can Y. be fixed W
The PWM Wresolution
W .100 for the O M.T correct PWMWmode W O M.T to 8-, 9-, or 10-bit, or defined
Y.C The.Tminimum . C
by either W ICRn W or OCRnA.
.100 M
W resolution
W 00Y
.1allowed is 2-bit (ICRn or OCRnA set to
W .C O W W
W W 00Y .TW W
W W.1 Y.COM W
W 00 .T
W W.1 Y.COM
W 00
W W.1 123
7799D–AVR–11/10 W
.C OM
00Y .TW
W W.1 Y.COM W
W 00 M.T or OCRnA set to MAX). The PWM resolu-
0x0003), and the maximum resolution W W.1 is 16-bit .C O(ICRn
tion in bits can be
W
.Tcalculated W using .the
by
Y
100following M TW
.equation:
M W O
. 1 00Y M W O
W O
W O
WRW
W .CO TOP.T+W 1
.T W WW .100Y.C M.TW . 1 00=Ylog
----------------------------------
M -
O M W W .C O PCPWM
W W Y .C O
log  2  W
Y .C W W 0 Y .T W W 0 0 . T
00 .T 0
W.1 Y.COM W .1 M
W
In phase .correct 0 PWM M.modeT the counter is .incremented
W 00
W.1 Y.COM W
.T 0
W 1fixedYvalues .CO 0x00FF, Wor W 1 Y.COMuntilWthe counter value matches either
Wthe W W 00 (WGMn[3:0]
WW
.100 M.T
one W of
W .10 0
O M. T 0x01FF, 0x03FF
W.1 Y.C=O11). M.T = 1, 2, or 3), the value in ICRn
W O (WGMn[3:0]W = 10), .C or the value in OCRnA W (WGMn3:0 T counter has then reached the
The
W
WW .100Y.C M.TW W .
Y
100 theOcount M .TW W
W .100value O M.be
TOP and W
changes direction. The TCNTn will equal to TOP for one timer clock
W O
WW .100Y.C M.TW cycle.WThe timing
1
. diagramMfor the phase correct
W O WW 00Y.CO .TW WWPWM mode
Y.C
O is shown on Figure 16-8. The figure
.TWto define TOP. The TCNTn
WW .100Y.C M.TW showsW phase correct . 1 PWM M mode when WOCRnA W . 1
or 0 0ICRn isM
O used
O W O .C
W
WW .100Y.C M.TW value isW in Wthe timing Y.C TW as a histogram WW .1for 00Yillustrating W
M.Tthe dual-slope operation. The
W . 100 diagram O M .shown W C O
W O W .C W outputs. Y. The small W horizontal line marks on
WW .100Y.C M.TW
diagram W includes non-inverted .Tand
W invertedWPWM
W . 1 00Y
O M W .100 O M.T
W O the TCNTn slopes represent compare matches WW between0Y .
OCRnxC andWTCNTn. The OCnx Inter-
WW .100Y.C M.TW WW .100Y.C M.TW .10 M.T
rupt Flag will be set
W when a compare
O match occurs. W C O
W
WW .100Y.C M.TW
O
W
W O W C O
W O W Y.C PWM.TMode, WW Y. W
WW .100Y.C M.Figure TW 16-8. WPhase .Correct 100 M
W Timing Diagram
W .100 O M.T
W O C
W
WW .100Y.C M.TW
O
M.TOCRnx/TOP Update and
W O W C O
W
WW .100Y.C M.TW
O
W Interrupt Flag Set
OCnA
W O W C O or ICFn Interrupt Flag Set
W
WW .100Y.C M.TW
O
W on TOP)
(Interrupt
W O W C O
W
WW .100Y.C M.TW
O
W
W O W C O
W
WW .100Y.C M.TW
O
WW .100Y.C M.TW WW .100Y. TOVn
M .TW
Interrupt
(Interrupt
Flag Set
on Bottom)
W O W O
W
WW .100Y.C M.TW
O
W O W O
W
WW .100Y.C M.TW
O
W O W O
W
WW .100Y.C M.TW
O
W O W O
W
WW .100Y.C M.TW
O
TCNTn
W O W O
W
WW .100Y.C M.TW
O
W .C
OCnx O WW 00Y.CO .TW W WW 00Y.CO (COMnx1:0 W= 2)
WW
. 1 00 Y
M .T W W
W . 1 O M W .1 O M.T
W O WW .100Y (COMnx1:0 .C
WW .100OCnx Y.C .TW WW .100Y.C M.TW M.T = 3)
W
O M W O W .C O
W
W
O W O W .C O
W
WW .1Period .C .TW 1 WW 2 Y.
C
.3TW WW .100
Y
M.T
W
00Y 100
4
W O M W . O M W W .C O
Y
M.T
W
O W O W W .C O
TheW Timer/Counter Overflow Flag W W is 0set
(TOVn) C time
Y.each the counterWreaches 0 Y
BOTTOM. W
When
WW .100Y.C M.TW 1 0 TOP O
.the
W
M.T the OCnA or ICFn W .1 0 O M.T
eitherW OCRnA .or OICRn is used for defining W value, W Flag is .C
set accord-
WW at the YC W WW .100Y.C M.TW W Y
100double .TW
ingly W .100same O M.Tclock cycle as the
timer W OCRnx Registers O are updated with
W W .the
.C O Mbuffer
WW(at TOP). Y.C W Flags can WWbe used Y.C W W Y
.100 the counter .TW
value
W .100 TheOInterrupt M.T W .100 to generate O M.T an interrupt each W W time
.C OM
.C W value. WW .100Y. C W Y .TW
WW the.1TOP
reaches 00Y or BOTTOM M.T W O M.T
W
W .100 OM
W O Y. C W Y .C TW
WW Y.C TW the program WW must .100ensure .TW W .10is0higher or.
When changing
W .100the TOP O M.value W C O Mthat the new TOP value
W W .C OM
toW .C all of .the WCompareWRegisters. W Y. W W than.1any 00Y of the
equalW the value
W .100
Yof
O MT W .100 If theOTOP M.T value is lowerW W
Compare Registers, .aC compare WW C
Y. between W
WW 00Y
.1using .TWmatch will
MTOP
never occur
W .100 O M.T
the TCNTn Wand the OCRnx.
Note that when W O
fixed values, the unused bits C are masked to zero when any of the
W W 0 0Y.C M.TW WW .100Y. M .TW
OCRnx Registers .
W are Y1 written.
O As the third period Wshown in.C O
Figure 16-8 illustrates, changing the
TOP actively WWwhile 0 .C
0the .TW
Timer/Counter is WW in.1the
running 00Yphase correct mode can result in an
. 1 M
W O
Y.Creason WW
unsymmetrical WWoutput. . 1 00The M
W this canW
.Tfor be found in the time of update of the OCRnx Reg-
W O
WW .100Y.C M.TW
W O
WW .100Y.C 124
W W
7799D–AVR–11/10 W
.C OM
00Y .TW
W W.1 Y.COM W
W 00 .T
ister. Since the OCRnx update W W.1 at YTOP,
occurs .C OM the PWM period starts and ends at TOP. This
W
implies that O the TW of the W
M.length fallingW .100 is determined
slope O M.T by the previous TOP value, while the
Y .C W W W 0 Y .C .T W
length 10of 0 the rising .Tslope is determined by0 the new TOP value. When these two values differ the
W.slopes .C OM W W.1 Y.COM W
W
two Y of the periodW will differ
W in length. 00 The difference .T in length gives the unsymmetrical
W
W result
WW .100Y on the .C
output. W W 00 .T
Y.C W Wrecommended
It is Y .C to useW the phase W and frequency 00 correct .T mode instead of the phase correct
W .100 O M.T
W
W .100 O M.T W W.1the Timer/Counter
.C OM
mode
WW .100Y when .C
changing the TOP value while Y .TW is running. When using a static
W . 100 O M
TOP valueW there are O practically no differences between the two modes of operation.
W
WW .100Y.C M.TW
O
W O
W O In phase
WW correct
W .CO mode,
YPWM W the compare WW units Y.C generation
0allow .TW of PWM waveforms on the
WW .100Y.C M.TW . 1 0 0 M . T
W . 1 0
O M
OCnx pins. W Setting the O COMnx[1:0] bits to two will produce a non-inverted PWM and an inverted
W O
WW .100Y.C M.TW PWMWoutput .can
W .C
00Ybe generated .T W WW .100Y.C M.TW
W 1 OM by setting theWCOMnx[1:0] O to three (See Table 16-3 on page
W O
WW .100Y.C M.TW 131). The WWactual 0 0 Y.C value.Twill
OCnx W only beW W
visible on
. 1 0 0Y.C
the port pin
W
M.Tif the data direction for the port
W . 1 O M W O
W O W output Y.C WW Y.C W
WW .100Y.C M.TW pin is set Was . 100(DDR_OCnx). M .TW The PWM waveform
W .100 is generated O M.T by setting (or clearing) the
O W O .C
W
WW .100Y.C M.TW
OCnx Register WW at.1the .C
00Ycompare .Tmatch
W betweenWW OCRnx .100
Yand TCNTn
M.T
W when the counter incre-
W O M W C O
W O ments, and clearing
WW .100Y.C M.TW
(or setting) the OCnx Register WW .at Y.
compare match
.TW
between OCRnx and
WW .100Y.C M.TW TCNTn when the counter decrements. The PWM W 100
frequency O
for Mthe output when using phase
W O W .C O W .C
WW .100Y.C M.Tcorrect W PWM Wcan W
be 1 00Y
calculated by
M
W
.Tthe following
Wequation: . 1 00Y M .TW
W . O W O
W
WW .100Y.C M.TW
O
W O W O WfW clk_I/O Y.CO
WW .100Y.C M.TW WW .100Y.C M .TW
f OCnxPCPWM =
2   100 -
W----------------------------
.TOP M.T
W
W O N W C O
W
WW .100Y.C M.TW
O
W
W O W C O
W O
WW .1the .C W Y. W
WW .100Y.C The M
NW
.T variable represents 00Yprescaler M
W
.Tdivider (1, 8,W64, 256,
W .10or0 1024). O M.T
W O C
W O
WW .100Y.C TheMextreme .TW values WW 00Y
for the.1OCRnx
.C .TW represent
Register WW special 0Y. when
.10cases
W
M.Tgenerating a PWM
W O M W C O
W O Wphase00correctY.C PWM W Y. W
WW .100Y.Cwaveform M .TWoutput inW the
.1 M .TWmode. If W the OCRnx
W .100is setOequal M.T to BOTTOM the
W CO will W O Woutput00will C
Y. be continuously
WW .100Y.output .TW
be continuously WW low andY.Cif set equal .TW to TOPW the
M.T
W high for
M W . 100 O M W .1
C O
W .CO .TWPWM mode.
non-inverted For inverted PWM the outputW
WW .100Y.C M.TW
Whave 0the
will Y.opposite .Tlogic
W values. If
WW .100Y OCR1A M is used to define the W TOP value O (WGM13:0 = 11) and W .1 0
COM1A[1:0] O M
= 1, the OC1A out-
W O WW .100Y .C
WW .100put Y.Cwill toggle .T Wwith a 50% WW duty 1 0
cycle.
. 0Y.C M.TW M .TW
OM W O W O
W
W O W O
16.9.5 Phase W WW
and Frequency
0
O
Y.C Correct .T WPWM Mode WW .100Y.C M.TW WW .100Y.C M.TW
1 0 O correct PWM
W W.The phase .C OM and frequency
W correctWWPulse Y .CO Modulation,
Width W or phase
W WW Y.C
and frequency
0 0 .TW
W Y
00 (WGMn[3:0] .T = 8 or 9) provides W . 0 0
1a high resolution M .T . 1 MPWM
W . 1
mode O M W O phase and W
frequency
W C O
correct
. wave-
WW form 0 Y.C .T W W W 0 Y.C
0frequency .TW PWMW . 1 0Y
0like M .TW
1 0 generation option. The phase and. 1 M correct mode W is, the O phase correct
W. OM W O
WWrepeatedly .C
WW PWM 0 0 Y.C based
mode, .T Won a dual-slope WW operation. .1 0 0Y.C The M . W
Tcounter counts . 1 00Y fromMBOTTOM .TW
WW(0x0000) .C .TWthen fromWTOP W
W to BOTTOM. Y.C W WCompare Y
.100OutputOmode, M.T the
W
.1 00Yto TOPMand . 100 O MIn.T non-inverting
W C
WW Compare O Y.C W .
0Y OCRnx W
WOutput 00Y
.C (OCnx) .TW
is cleared WWon the .
compare
100 M
match
.TW between WTCNTn.10and M.T
while
upcounting, . 1 and O M
set on the compare W
match while Odowncounting. In W
invertingW Compare .C O Output
W WW 00Y.C W
.Tinverted. WW .100Y.C M.TW W Y
.100 operation M.Tfre-
W
mode, W .1 operation
the O Mis The dual-slopeW operation
C O gives a lower maximum
W W .C O
WW compared Y.C to the WW .100Y.However, W W Y
.100feature TW
quency .100
W
M.T single-slope operation. W O M.T due to the symmetric W C O Mof. the
W .C O W preferred Y.C W W Y . .TW
WW .1PWM
dual-slope 00Y modes, M.T
W modes
these Ware
W .100 forOmotor M.T control applications.
W
W .100 OM
W O C W .C
W Y.C between W the phase WWcorrect, Y. .TW and frequency W 00Y PWM .TW
TheWmain difference
W .100 O M.T W .100 and the O Mphase W W .1correct
.C OM
.C OCRnx WW .1by .C W Y W
mode WisWthe time .100
Ythe W
M.T Register is updated W
00Ythe OCRnx
O M.T Buffer Register,
W
W(see.100FigureO16- M.T
W O C W .C
8 andW W 16-9).
Figure Y.C W WW .100Y. M.T
W W .100
Y
W .100 O M.T W .C O W W
The PWM WWresolution Y.C the phase W and frequency WW .1correct 00Y PWM W W
M.Tmode can be defined by either
W .100 for O M.T W C O
ICRn or W W
OCRnA. C
TheY.minimum resolution
W WW is.102-bit
allowed 0Y. (ICRn M.T
orW OCRnA set to 0x0003), and
W .100 O M.T W C O
W O W
WW .100Y.C M.TW WW
W O
WW .100Y.C M.TW
W O
WW .100Y.C 125
W W
7799D–AVR–11/10 W
.C OM
00Y .TW
W W.1 Y.COM W
W 00 .T
the maximum resolution is 16-bitW(ICRn W.1 orYOCRnA .C OM set to MAX). The PWM resolution in bits can
W
W W equation: .100 M.T
be calculatedOusing M.T the following W W O
.C .TW Y.C .TW
. 1 00Y M
W
W . 100 O M
O Y.Clog  TOP .TW+ 1 -
W
WW .100Y.C M.TW WRWPFCPWM . 100 = ----------------------------------
M
W O W O log 2
OM W CO WWmode
W CO
0Y.counter
00 Y.C .T W W
In
W
phase 1 0
and 0 Y.frequency
M .T Wcorrect PWM . 1 0
the M .TisWincremented until the counter value
.1 M W . O W O
W O
WW either .C WW .1=008), Y.C .TW in OCRnA (WGMn[3:0] = 9). The
WW .100Y.C M.TW matches
. 1 00Ythe value M
WICRn (WGMn[3:0]
.Tin W
or the
O M value
O W then O .C count.Tdirection.
W
WW .100Y.C M.TW
counter
WW has 00Y
.Creached .TW the TOP and WW changes
. 100
Ythe
M
W The TCNTn value will be
to W . 1 O M W O
W O equal W TOP for one
0Y.C M.TW
timer clock cycle. The
WW timing Y.C
diagram for Wthe phase correct and frequency
WW .100Y.C M.TW W PWM
correct . 10mode is shown on Figure 16-9. W 100 figure
.The O M .T
shows phase and frequency correct
O W O .C
W
WW .100Y.C M.TW PWMW
W
mode when 0 0 .C
YOCRnA .T
or
WICRn is usedWW to define. 1 0 0YTOP. TheM . W
TTCNTn value is in the timing dia-
. 1 M
W W . C O
W WWas a00histogram Y .CO .for W W WW 00Y.CO .TW
Y gram W
shown T illustrating the dual-slope operation. The diagram includes non-
W
W .100 OM.T W .1
. C O M W W.1 Y.COM W
W
WW .100Y.C M.TW invertedW and inverted YPWM outputs.
.100 between .TW The small W horizontal 00 line marks
W.1 TheYOCnx
.T on the TCNTn slopes repre-
OMInterrupt Flag will be set when a
W C O sent compare W Wmatches .C OM OCRnx and TCNTn. W .C W
WW .100Y. M .TWcompare W . 100
Y
M .TW W
W .100 O M.T
match W occurs. O C
W
WW .100Y.C M.TW
O
W
W O W C O
W O
16-9.WW .C WW Mode, Y. W
WW .100Y.C M.TFigure W Phase . 00Y Frequency
1and M .TWCorrect PWM W .100TimingODiagram M.T
W O C
W
WW .100Y.C M.TW
O
M.T OCnA Interrupt Flag Set
W O W C O
W
WW .100Y.C M.TW
O
M.T (Interrupt on TOP)
or ICFn Interrupt Flag Set
W O W C O
W
WW .100Y.C M.TW
O
W
W O W C O
W
WW .100Y.C M.TW
O
WW .100Y.C M.TW WW .100Y. TW
M.OCRnx/TOP Updateand
W O W C O W W .C O TOVn Interrupt Flag Set
C W . .TW Y W
WW .100Y. M.T
W W .100
Y W 00
W.1 Y.COM W
.T on Bottom)
(Interrupt
W C O W W .C OM W
WW .100Y. M.T
W W .100
Y .TW W 00
W.1 Y.COM W
.T
W C O W W .C OM W
WW .100Y. M.T
W W .100
Y .TW W 00
W.1 Y.COM W
.T
W C O W W .C OM W
WW .100Y. M.T
TCNTn W W 00Y .TW W 00
W.1 Y.COM W
.T
WW .100Y W W 00 .T W 00 .T
.C W W 00 .T
WW .100Y OCnxM.TW W 00 .T W.1 (COMnx1:0 OM= 2)
WW .100Y .C
.TW W W
100 M .T W Y
.100(COMnx1:0 M .TW
OCnx O M W . O W .C O
W
= 3)
W
O W O .C
W
WW .100Period Y.C .TW 1 WW .2100Y.C 3 M.TW WW .100Y M.T
W
O M W O 4 W .C O
W
W
O W O W . C O
W
WWThe Timer/Counter .C W WW(TOVn) Y.C .TWsame timer WW 100 as O
Y TW
M.OCRnx
.1 00Y M .TOverflow Flag
W . 100is setOatMthe clockW .cycle
C
the
WW 00are O Y.C W Y . W
WRegisters Y.C updated .TWwith the double WW buffer . 100 valueO(at M TW
.BOTTOM). W either
When .100OCRnA M or.TICRn
. 1 O M
W for defining the TOP value, the W W W .C O
is used
WW .100Y.C M.TW WW OCnA Y.C
or ICFn Flag Wset when W TCNTn has
.100
Yreached TOP.
M.T
W
The Interrupt
W Flags O can then be used to W .100 anOinterrupt
generate M.T each time the W W counter C O
reaches
. the
WW or BOTTOM Y.C W WW .100Y.C M.TW W .100
Y
M.T
W
TOP W .100 O M.T
value. W O W W .C O
Y .TW
When changingW the O TOP value the program W must ensure
C O that the new TOP W Wvalue is .C OM or
higher
WW 0Y.C of all TW WW .100Y. .TW value isW Y
.100 any of .TW
equal to W the.10 value O M.of the Compare Registers. W IfCOtheMTOP lower W W than .C OMthe
WW Registers, Y.C a compare W WW .1occur .
00Y between W
M.T the TCNTn and
W 0Y
.10OCRnx. .TW
Compare
W .100 O M.T match will never W C O W Wthe
.C OM
WW16-9.1shows .C
00Y theMoutput .TW generated WW .100Y. .TW W 0Y
.10symmetri-
As Figure W O is, Win contrast C toM
O the phase correct mode, W W
W 0Y.C theMOCRnx .TW Registers WWare .updated Y. at BOTTOM, W W
cal in all Wperiods. .10Since W 100 O M.T the length of the rising
W O C
WW slopes
and the falling .C always
Ywill Wbe equal. This WWgives 0Y.
.10symmetrical
W
M.Toutput pulses and is therefore
W .100 O M.T W C O
frequencyW correct.
W Y.C W WW .100Y.
W .100 O M.T W
WW .100Y.C M.TW WW
W O
WW .100Y.C M.TW
W O
WW .100Y.C 126
W W
7799D–AVR–11/10 W
.C OM
00Y .TW
W W.1 Y.COM W
W 00 .T
Using the ICRn Register for defining W W.1TOPY.works C OM well when using fixed TOP values. By using
ICRn, the OCRnA M .TW Register is
W
free to .
be
0
10used for M .TW
generating a PWM output on OCnA. However,
C O W W .C O
Y . W W 0 0 Y .T W
if the.1base00 PWMMfrequency .T is actively changed
W.1 Y.COM W
by changing the TOP value, using the OCRnA as
W W is clearly .C O W
TOP Y a betterW choice dueW to its double
0 0 buffer .feature.
T
W
W WInWphase .C
0Y frequency W W mode, 00the compare .T units allow generation of PWM wave-
O M.T W .10and O M.T correct PWMW W.1 Y.COM W
Y.C W W on the
forms .C
YOCnx pins. WSetting the W COMnx[1:0] 00 bits M to.T two will produce a non-inverted PWM
W .100 O M.T
W
W .100 O M.T W W.1 byY.setting C O the COMnx1:0 to three (See Table 16-
and an
WW .100Y inverted . C
PWM output can be generated .TW
W . 100 O M
3 on WW 00Y.C
page 131). The O actual OCnx value will only be visible on the port pin if the data direction for
W
WW .100Y.C M.TW
O
the port pin 1
. is set as output M (DDR_OCnx).WThe W PWMY.waveform O is generated by setting (or clear-
W O WW 00Y.CO .TW 0 C OCRnx TW and TCNTn when the counter
WW .100Y.C M.TW ing)W the OCnx 1 Register at the compare Wmatch .1between 0 M .
W. OM WWRegister O
W O
WW .100Y.C M.TW increments, WW and 0 0 Y.C
clearing (or.T W
setting) theW OCnx . 1 0 0Y.Cat compare M.T
W match between OCRnx and
W . 1 O M W O
W
WW .100Y.C M.TW
O TCNTnWwhen W the00counter Y.C decrements.
.TW WWPWM.10frequency
The 0Y.C Mfor .TW the output when using phase
W . 1 O M W O
W O and frequency
WW .100Y.C M.TW
correct PWM can be calculated WWby the Y.C
following equation:
W
WW .100Y.C M.TW W .100 O M.T
W O C
W
WW .100Y.C M.TW
O
WW .100Y.C M.TW WW .f100Y. .TW
W O W clk_I/O OM
W O f W
WW Y. - C
= ----------------------------
WW .100Y.C M.TW WW .100Y.C M.TOCnxPFCPWM 2  .N10 0TOP M.T
W
W O W C O
W
WW .100Y.C M.TW
O
W
W O W C O
W O The N variable W representsYthe .C prescaler divider (1, WW 8, 64, 256, Y.or 1024). W
O W O Y. C
W
WW .100Y.C MThe .TW
extreme values WW for.1the 00YOCRnx
.C .TW
Register representsWW special .100 cases .TW generating a PWM
Mwhen
W O M W C O
W O waveform output in
WW .100Y.C output .TW will be continuously WW .100Y.C M.TW
the phase correct PWM mode. WIfWthe OCRnx 0Y. is set
.10output M.be
equal
T W to BOTTOM the
M W low O
and if set equal to TOP W the C Owill set to high for non-
W O
WW .100Y.C inverted .T W PWM mode. WWFor .inverted 0 0Y.C PWM . W
Tthe WW .100Y. M .TW values. If OCR1A
1 M output will have the opposite logic
W OM W .CO .TW WW 00Y.CO .TW
WW .100Y.C is used .T W
to define the WW TOP value . 1 0 0Y(WGM1[3:0] M = 9) and W COM1A[1:0] .1 = 1, the MOC1A output will tog-
W W .C OM
gle with aW 50% duty WW 00Y.CO .TW
cycle. W WW 00Y.CO .TW
W 00 Y .T W .1 M .1 M
W 00 .T W 1 M .1 M
16.10 Timer/Counter
W W.1 YTiming .C OM Diagrams WW. Y .CO .TW W WW 00Y.CO .TW
W 00 .T W W .10 0 .1
W.1 The OM CO and
M WW(clk0Tn0)Yis OM
.C Timer/Counter WW 00Y.design
is a synchronous W the timerW clock .Ctherefore Wshown as a
W W
. 1
Y
00clock enable M
W W
.T signal in the following W .1 figures. O M .T
The figures include W .1
information O M.T
on when Interrupt
W O .C WW .100Y .C
WW .10Flags 0Y.CareM .TW
set, and when W
W
the OCRnx 1 00Y Register M .isTW updated with the OCRnx buffer M .TW (only for
value
. WW 00Y.CO .TW
W .CO .TW WW Figure
W CO
0Y.16-10 TW a timingWdiagram.1for
WW .modes 1 00Y utilizing M double buffering). .1 0 M .
shows
W the setting
OM of OCFnx.
WW .100Y . .TW Y W W .100 M.T
M
W
W . 100 O M .T W C O
O
WFigure 16-10. Timer/Counter Timing W Prescaling .
WW .100Y.C M.TW
Diagram, Setting of OCFnx, Wno Y W
WW .100Y.C M.TW W .100 O M.T
O W O .C
W
W
O W O W .C O
W
WW .100Y.C
clkI/O
W
W O M W O W W .C O
WW .10clk 0Y.C M.TW WW .100Y.C M.TW W .100
Y
M.T
W
W O W O W W .C O
/1).C WW .100Y.C M.TW Y W
Tn
WW .(clk 10I/O0Y M.T
W
W O
W
W .100 O M.T
W O W .C
Y
M.T
W
W O W O W W .C O
TCNTn
WW .100Y.C M.TW
OCRnx - 1
WW OCRnx Y.C OCRnx
W + 1 W OCRnx0+
.10
Y2 .TW
WW .100Y. C Y W
WW .100Y.C M.TW M.T
W W
W .100 OM.T
W O W C O W .C
OCRnx
WW .100Y.C M.TW WW OCRnx .
YValue W W .100
Y .TW
WW .100Y. C Y
WW .100Y.C M.TW M.T
W W
W .100
W O W C O W
OCFnx
W W
W O W C O
W
W O W C O
WW .10the 0Y.C .TW data, but WW .100Y.
Figure 16-11 shows W same O Mtiming withW the prescaler enabled.
WW .100Y.C M.TW WW
W O
WW .100Y.C M.TW
W O
WW .100Y.C 127
W W
7799D–AVR–11/10 W
.C OM
00Y .TW
W W.1 Y.COM W
W 00 M.T of OCFnx, with Prescaler (f
Figure 16-11. Timer/Counter Timing W W.1Diagram, .C OSetting clk_I/O/8)
. T W W . 1 0 0Y M .TW
OM W O
0 0 Y.C .T W WW .100Y.C M.TW
W.1 clkI/O OM W O
W O
W
W
WW .10clk 0Y .CO .TW WW .100Y.C M.TW
.T OM W O
OM W Tn
Y.C WW .100Y.C M.TW
00 Y.C .T W WW (clk 1 0 0
I/O /8)
.T W
W.1 OM W. OM W O
TCNTn
W O OCRnx - 1 W
OCRnx O OCRnx + 1 OCRnx + 2
W
WW .100Y.C M.TW
O
W O W O
W
WW .100Y.C M.TW
O
OCRnxW O WOCRnx Value O
W
WW .100Y.C M.TW
O
W O W O
W
WW .100Y.C M.TW
O
OCFnx W O W O
W
WW .100Y.C M.TW
O
W O W O
W
WW .100Y.C M.TW
O
W O
W O
WW
W .CO .TW Y.C
WtoWTOP.1in00various W
WW .100Y.C M.TW Figure 16-12 shows . 1 0 0
the
Ycount sequence
M close W O M.T When using phase and
modes.
O W O C
Y. BOTTOM.
W
WW .100Y.C M.Tfrequency W WW PWM Y.C W WWis updated
.100 at O M.T
W The timing diagrams
correct
W . 100modeOthe M .T
OCRnx Register
W C
W O
WW but .TOP C
Y.should WW Y. .TW
WW .100Y.C M.will TWbe the same, 100 M .TW
be replaced by BOTTOM,
W .100 TOP-1 O Mby BOTTOM+1 and so on.
W CO The same renaming W W applies .C O
for modes that set the W
TOVn Flag Y.C
at BOTTOM. W
WW .100Y. M .TW W . 100
Y
M .TW W
W .100 OM.T
W O C
W O
WW .100Y.C Figure .TW 16-12. Timer/CounterWW .100Y.Timing C
.TW WW .100Y. M.T
W
M W O MDiagram, no PrescalingW C O
W
WW .100Y.C M.TW
O
W
W O W C O
W O
WW .100Y.C M.TW clkI/O W
W
W . 100 O M W CO
W O
WW .100Y.C M.TW clk WW .100Y.C M.TW WW .100Y. M.T
W
W O W C O
W
WW .100Y.C M.TW
O Tn
(clkI/O /1) WW .100Y.C M.TW WW .100Y. M.T
W
W O W C O
W O
W
O W O W .C O
W
WW .100Y.C (CTC .Tand WFPWM) WW TOP.1-010Y.C M.TW
TCNTn
TOP WWBOTTOM .100
Y
M.T + 1
BOTTOM W
O M W O W .C O
W
W
W O TCNTn W O W .C
W - 1 00Y TOP.-T2WO
WW TOP - 1 0Y.C
WW .100Y.C(PC and .TW
TOP WTOP
M .TWPWM)
PFC
W .10 O M W.1 Y.COM W
W .C O W .C W W
WW .100Y TOVnM(FPWM) .TW W 00Y .T W 00 .T
and
.C ICFn (if used W W 0 .T
WW .100Y as TOP) M.T
W W 00 .T 0
W.1 Y.COM W
WW .100Y OCRnx W W 00 .T W 0 .T
W O M.T Old W.1 Value
OCRnx .C OM New
W W.1 Value
OCRnx Y .C OM
W
. C W Y W W 0
WW .100Y .TW M.T
(Update at TOP)
M
W
W . 100 O M .T W .10 O
W O W .C
Y
M.T
W
O W O W W .C O
WW 16-13 Y.C .TWsame timing WW Y.C
100 with the .TW W
enabled. W.10
0Y M.T
W
WFigure
W .100 shows O Mthe data,.but
W O Mprescaler W .C O
Y
M.T
W
W O W O W W .C O
Y .TW
W O W C O W W .C OM
W W .100
Y .TW
W O W C O W W .C OM
W W .100
Y .TW
W O W C O W W .C OM
W W .100
Y
W O W C O W W
W W
W O W C O
W
W O W CO
W O W
WW .100Y.C M.TW WW
W O
WW .100Y.C M.TW
W O
WW .100Y.C 128
W W
7799D–AVR–11/10 W
.C OM
00Y .TW
W W.1 Y.COM W
W 00 .T
W W.1 Y.COM W
.TW W .100 .T
OM Prescaler (fclk_I/O/8)
Figure 16-13. C OM Timer/Counter Timing W WDiagram, .C with
1 00Y
.
M .TW W . 100
Y
M .TW
W . O W O
WW .1clk 00Y
W O M W O
I/O
.T W
OM W O W O
0 Y.C .T W WW clk.Tn100Y.C M.TW WW .100Y.C M.TW
0 O
W.1 OM WI/O/8)
(clk O W
WW .100Y.C M.TW
W O W O
W
WW .100Y.C M.TW
O
W WTCNTn 0Y.C
0 .T
TOP W- 1 WWTOP.100Y.C BOTTOM M .TW BOTTOM + 1
(CTC and . 1
FPWM) O M W O
W W Y .C O
W W WW 00Y.C T W W W 0 0 Y .C .T W
W 00
W.1 Y.COM W
.T .1 M. .1
WW 00Y.COTOP -.T
M
W W WW 00Y.CO TOP.T- W
TCNTn 1 W TOP W
W .1 00 M .T (PC and PFC PWM)
W . 1 O M W .1 O M1 TOP - 2
W O W .C W Y .C W
WW .100Y.C M.TW TOVn W(FPWM) .100Y M.T
W W 00
W.1 Y.COM W
.T
W O W W .C O W
WW .100Y.C M.TW and ICF Wn (if used
as TOP) W.1
00Y .TW W 00
W.1 Y.COM W
.T
W C O W .C OM W
WW .100Y. M.T
W W .100
Y .TW W 00
W.1 Y.CNew
.T
OMOCRnx Value
W C O OCRnx
W W . C OMOCRnx Value
Old W W
WW .100Y. M .TW (Update atWTOP) W.100Y OM.TW W
W .100
C O M.T
W
WW .100Y.C M.TW
O
W
W O W C O
W
WW .100Y.C M.TW
O
W
W O W C O
W
WW .100Y.C M.TW
O
W
16.11 Register Description W O W C O
W
WW .100Y.C M.TW
O
W
W O W C O
.CO .TW
WW 00–YTimer/Counter1 WW Register Y.C W WW .100Y. M.T
W
16.11.1 WTCCR1A . 1 M Control
W . 100 A OM.T W C O
W
WW .100Y.C M.TW
O
W
W O W C O
W O
WW 6 .100Y.C5 M.TW
W Y. 1 .TW 0
WW .100Y.C Bit M.TW 7 4 3W .2100 M
W .C O W W Y .C O
W W
W
WCOM1C000Y.WGM11 CO W
W W
. 1
Y (0x80)
00 Read/Write M .T W COM1A1 WCOM1A0
W .
COM1B1
0
10 R/W OM R/W
COM1B0
.T COM1C1
W .1 O M.TWGM10 TCCR1A
W .CO .TW .C WW .100Y. C
.TW
R/W R/W R/W R/W R/W R/W
WW .100YInitial WW .1 0 0Y M .TW M
W W . C OM
Value
W
0 0
WW 00Y.CO .TW
0 0 0
W WW 00Y.CO .T0 W
0 0
W 00 Y .T W .1 M .1 M
W W.1 • Bit .C 7:6OM – COMnA1:0: Compare
W WWOutput Y CO forTChannel
.Mode W A
W WW 00Y.CO .TW
W 00 Y .T W 0
.10 Mode M . .1 M
W W.1• BitY.5:4 C O–MCOMnB1:0: Compare
W
Output
WW 00Y.CO .TW
for Channel B
W WW 00Y.CO .TW
W 0 3:2 – COMnC1:0:
• 0Bit .T W
Compare Output .1 Mode for M Channel C . 1 M
W 1
W .100COMnA[1:0],
The
WOCnB, OM
.T COMnB[1:0], W and
.1 COMnC[1:0]
Wbehavior. .C OM control the output . compare
WW 00Y.bits CO
M pins (OCnA,
W
. C Y W W
W W
. 1 0 0 Y and OCnC
M .T W respectively) W
W . 1 0 0 If one
O M or
.T both of the COMnA[1:0]
W . 1 O M.Twritten to
are
W O Y.portC functionality WW it Y .C Wto. If
WW one,.1the 00Y
.C
OCnA output
.TW
overrides WW the normal
. 100 M .TW of the I/O pin
.100
is connected
M.T
O M W O W .C O
oneW or both
WWport functionality .C of the COMnB[1:0]
W bits are
WW .100Y.C M.TW
written to one, the OCnB WW .100Y
output overrides the normal
.TW
.1 00Y M of.Tthe I/O pin it is connected
W to. If
O one or both of the W
COMnC[1:0] .C O Mare
bits writ-
WW 00Y.C O W
Wten to .one, the OCnC .T Woutput WW the
overrides . 1 0 0Y.C port
normal M .TW
functionality
W
of the .
I/O 1 0Y
0pin it is M .TW
connected
1 M W O W .C O
W
W
to.WHowever, 0 CO thatTthe
Y.note W Data Direction WW Register 0 0Y.C (DDR) . W corresponding
Tbit WW to.1the 00YOCnA,MOCnB .TW
. 1 0 M . W .1 O M W C O
W O
.C be set W the Y.C driver. W W Y . W
or
WOCnCW pin Y
.100
must
M.T
Win order toWenable
W .100
output
O M.T
W
W .100 O M.T
W O .C W Y .C W
WhenWW the .OCnA, Y.C W WW .10to 0Ythe TWfunction of
M.the
Wthe COMnx[1:0].100 M.Tis
W 100 OCnB O M.Tor OCnC is connected W C
pin,
O W W .C Obits
Y.CWGMn[3:0] WW Table Y. shows W W 0Y W
WW .of
dependent
1 00the M .TW bits setting. W .100
16-1
O M.T
the COMnx[1:0]
W
bit.10functionalityO M.T
W O C W .C
when the WGMn[3:0] bits are set to a normal
WW .100Y.C M.TW WW or.1a0CTC 0Y. mode M.T
(non-PWM).
W W .100
Y .TW
W O W C O W W .C OM
W W .100
Y
W O W C O W W
W W
W O W C O
W
W O W C O
W O W
WW .100Y.C M.TW WW
W O
WW .100Y.C M.TW
W O
WW .100Y.C 129
W W
7799D–AVR–11/10 W
.C OM
00Y .TW
W W.1 Y.COM W
W 00 .T
.
W W.1 Y.COM W
Table 16-1. OM .TW Output
Compare
W
Mode, 00
W.1non-PWM OM
.T
C W .C
1 00Y
.
M .TW W . 100
Y
M .TW
W .
COMnA1/COMnB1/ O W
COMnA0/COMnB0/ O
WW .10COMnC1 0Y.C M.TW W W
COMnC0.100
Y.C Description .TW
W O W O M
.TW WW .100Y.C M.TW WW .100Y.C Normal M .TW port operation, OCnA/OCnB/OCnC
O M W 0 C O 0 W W O
.Cdisconnected.
Y.C W W W 0 Y. .T W W 0 0 Y .T W
.100 M .T . 1 0 M W . 1 O M
O W O Y.C
W
WW .100Y.C M.TW WW .1000Y.C M.TW 1 W
W 100 Toggle .TW
OCnA/OCnB/OCnC on compare match.
W O W . O M
W O .C W Y .C W
W W 00 Clear OCnA/OCnB/OCnC
.T on compare match
W O W .C O 0
W W.1 (set Y .C OM to low level).
output W
W
WW .100Y.C M.TW W .100
Y
M.T
W W 00
W.1 SetY.OCnA/OCnB/OCnC
OM
.T
W O W W .C O W C W
WW .100Y.C M.TW
on compare match (set
W 1 .100Y M .TW 1 W
W
0
.10output to O M.Tlevel).
high
W O
W
WW .100Y.C M.TW
O
W O W O
W O
WW .100Y.C M.TW Table 16-2 WWshows 0 0
theY.C COMnx[1:0].T WW .when
W bit functionality 1 0 0Y.C the M.T
W
WGMn[3:0] bits are set to the fast
W . 1 O M W C O
W C O W .C W Y . W
WW .100Y. M.T
WPWM mode. W .100
Y .TW W 00
W.1 Y.COM W
.T
W C O W W .C OM W
WW .100Y. W
M.T Table 16-2. W
W Compare Y
.100 Output .TW W 100 OM
.T
W CO W .C OMMode, Fast PWMWW. Y .C W
WW .100Y. M .TWCOMnA1/COMnB1/ W .
Y .TW
100 COMnA0/COMnB0/
M
W
W .100 O M.T
O W O Y. C
W
WW .100Y.C M.TW COMnC0 WW .100Y.C COMnC0 .TW WW .100
Description M.T
W
W O M W C O
W O
WW .100Y.C M.TW
W Y. TW
WW .100Y.C M.TW WNormal
W 100operation,
.port O M.OCnA/OCnB/OCnC
0 W O 0 C
W
WW .100Y.C M.TW
O
disconnected.
M.T
W
W O W C O
W
WW .100Y.C M.TW
O
WW .100Y.C M.TW WW .1=014
WGM1[3:0] 0Y.or 15: M .TW OC1A on
Toggle
O W O Compare W Match, C
OC1B
. O and OC1C disconnected
W
WW .100Y.C M.TW 0 WW .100Y.C 1 M.TW WWport.operation).
(normal 1 00Y M
For .TallWother WGM1
W O W O
W
WW .100Y.C M.TW
O
WW .100Y.C M.TW WWnormal
settings, . 1 0Y.C
0port operation,M.T
W
W O W C O
W
WW .100Y.C M.TW
O
OC1A/OC1B/OC1C disconnected.
M.T
W
W O W C O
W
WW .100Y.C M.TW
O
1 WW .100Y.0C M.TW Clear WW .100Y. onM
OCnA/OCnB/OCnC
.TW match,
compare
O W O set OCnA/OCnB/OCnC W at
.C O
TOP
W
WW .100Y.C M.TW WW .100Y.C M.TW WW .100Y M.T match,
W
O 1 W O Set OCnA/OCnB/OCnC W on .C O
compare
W
WW .100Y.C M.TW WW .1001Y.C M.TWclear OCnA/OCnB/OCnC WW .100Yat TOPM.TW
W O W O
W
WW .Note: .CO .TW WW .100Y.C M.TW WW .100Y.C M.TW
1 00Y A special O
W W .C OM
W
case occurs when OCRnA/OCRnB/OCRnC
WW is set. Y
O
.Cthis W
equals TOP
W WW and
0 0 Y.C but the.Tset Wor clear
W 00 Y .T
COMnA1/COMnB1/COMnC1 W . 10 0 In case
M .T the compare match is . 1
ignored, M
WWPWM.1Mode” .Con page.T97. Y W
WW .100Y.C M.TW
is done at TOP. See “Fast W for more W details.
W
00Y
O M W .100 O M.T
W O
Table 16-3 shows the COMnx[1:0] Y.C WW bits .C
WW .100Y.C M.TW WWbit functionality
.100 M
when
.TW
the WGMn[3:0]
.100
areY set to the
M.T
phase
W
correct and frequency
O correct PWM W
mode. O W .C O
W
W
W O W O W W .C O
Y
M.T
W
W O W O W W .C O
Y
M.T
W
W O W O W W .C O
Y
M.T
W
W O W O W W .C O
Y .TW
W O W C O W W .C OM
W W .100
Y .TW
W O W C O W W .C OM
W W .100
Y .TW
W O W C O W W .C OM
W W .100
Y
W O W C O W W
W W
W O W C O
W
W O W C O
W O W
WW .100Y.C M.TW WW
W O
WW .100Y.C M.TW
W O
WW .100Y.C 130
W W
7799D–AVR–11/10 W
.C OM
00Y .TW
W W.1 Y.COM W
W 00 .T
W W.1 Y.COM W
Table 16-3. OM .TW Output
Compare
W
Mode,W.1Phase
00 .T
OM and Phase and Frequency Correct PWM
Correct
C W .C
1 00Y
.
M .TW W . 100
Y
M .TW
W .
COMnA1/COMnB/ O COMnA0/COMnB0/W O
WW .10COMnC1 0Y.C M.TW W W
COMnC0.100
Y.C Description .TW
W O W O M
.TW WW .100Y.C M.TW WW .100Y.C Normal M .TW port operation, OCnA/OCnB/OCnC
O M W 0 C O 0W W O
.Cdisconnected.
Y.C W W W 0 Y . .T W W 0 0 Y .T W
.100 M .T . 1 0 M W . 1 O M
W O C
W
WW .100Y.C M.TW
O
WW .100Y.C M.TW WW .100Y.WGM1[3:0] M .TW= 8, 9 10 or 11: Toggle OC1A on
O W O W .C O
W
WW .100Y.C M.TW WW .1000Y.C M.TW WW .100YCompare M
Match, OC1B and OC1C disconnected
.TW
O 1 W (normalO port operation). For all other WGM1
W W Y.C O
W W WW 00Y.C .T W W W 0 0 Y .C
settings, .T
normal W port operation,
W .1 00 M .T W . 1 O M W .1 O M
W
WW .100Y.C M.TW
O
WW .100Y.C M.TW WW .10OC1A/OC1B/OC1C 0Y.C M.TW disconnected.
W O W O W
WW .1Clear .CO .TW
WW .100Y.C M.TW WW .100Y.C M.TW 00Y OCnA/OCnB/OCnC
M
on compare match
O 1W O 0 W when .C O
up-counting. Set OCnA/OCnB/OCnC on
W
WW .100Y.C M.TW WW .100Y.C M.TW WW compare . 100Y match M .T W
when downcounting.
W O W O W
WW Set.1OCnA/OCnB/OCnC .CO .TW
WW .100Y.C M.TW WW .100Y.C M.TW 00Y
WW OM on compare match when
W W Y.C O
W W 1 WW 00Y.CO .TW1 W 0
up-counting.
0 Y.C Clear.T W
OCnA/OCnB/OCnC on
W
W .100 O M.T W .1
. C OM W W.1 match
compare Y . C OM when downcounting.
W
C W .TW
WW .100Y. W
M.TNote: A specialWcase
W 0Y
.10occurs
W 00
W.1 equals OMand
.T
W C O W .C OM OCRnA/OCRnB/OCRnC
when W Y .C TOP W
WW .100Y. M .TW COMnA1/COMnB1//COMnC1
W . 100
Y
M .TisW W
set. See “Phase Correct W .100PWM O M.T on page 99. for more
Mode”
W O C
W O
WW .100Y.C M.TW details.W
W
W . 100 O M W C O
W
WW .100Y.C •MBit
O
.TW1:0 – WGMn1:0: WW .100Y.C M.TW WW .100Y. M.T
W
W Waveform O Generation Mode W C O
W
WW .100Y.C Combined
O
.TW with the WW Y.C .TWin the TCCRnB WW .100Y. TW
M.bits
M WGMn[3:2]
W . 100 bitsOfound M WRegister, these
C O control the count-
W W Y .C O
W W W 0 Y .C .T W W W 0 0Y. .T W
W 00 ingM .T
sequence of the counter, 0 the source for maximum (TOP)
W.1 Y.COM W .1counterOvalue,M and what type of
W.1 Y.Cwaveform O Wto W WW of00operation Y.C W
W W
. 1 00 M .T W generation W
W
be
.10 used,
0 see
O M .Table
T 16-4. Modes
W .1 O M.Tsupported by the
W O Y.C (counter), WW on.1Compare .C W (CTC) mode,
WW .100Y.C M.TW
Timer/Counter WWNormal
unit are:
. 0mode
10Modulation M .TW Clear Timer 00Y match
M.T
W O W C O
W
WW .100Y
and three
.CO .TW types of Pulse Width
WW .100Y.C M.TW
(PWM) modes. WW .100Y.
(See “Modes of Operation”
M .TW
on page
96.). OM W O W O
W
W O W O
W
WW .100Y.C M.TW
O
W O W O
W
WW .100Y.C M.TW
O
W W .C O
Y W
W
.C W
WW .100Y M .TW W
W . 100 O M .T W
W .100 OM
.T
WW .100Y M .TW W
W .100 O M .T W .10 O M.T
W O WW .100Y .C
W
W O W O W W .C O
Y
M.T
W
W O W O W W .C O
Y
M.T
W
W O W O W W .C O
Y
M.T
W
W O W O W W .C O
Y .TW
W O W C O W W .C OM
W W .100
Y .TW
W O W C O W W .C OM
W W .100
Y .TW
W O W C O W W .C OM
W W .100
Y
W O W C O W W
W W
W O W C O
W
W O W C O
W O W
WW .100Y.C M.TW WW
W O
WW .100Y.C M.TW
W O
WW .100Y.C 131
W W
7799D–AVR–11/10 W
.C OM
00Y .TW
W W.1 Y.COM W
W 00 .T
W W.1 Y.COM W
.TW W(1) 100 OM
.T
Table 16-4. Waveform Generation Mode
.C OM Bit Description WW. Y .C W
0Y
WGMn2W.10WGMn1OM WGMn0
.TW W
W
Timer/Counter .100 ModeOof M.T Update of TOVn Flag
Mode WGMn3 WW .1(PWMn1)
(CTCn) 00Y
.C .T W
(PWMn0) WW .100Y.C M.TW TOP
Operation OCRn x at Set on
W W .C OM WW 00Y.CO .TW
0 .T0 W W
0 000 Y .T0 W W
Normal .1 M 0xFFFF Immediate MAX
.COM W W.1 Y.COM W WW 00Y.CO .TW
Y W 0W 0 W
001
W.1 Y.COM W
.0T .100 M.1T PWM, PhaseW .1
Correct, 8-bit OM 0x00FF TOP BOTTOM
W W WW 00Y.CO .TW W W 0 0Y.C .T W
W 020 0.T 0 .1 M0 PWM, Phase Correct, .1 9-bit M 0x01FF TOP BOTTOM
W 0 0 .T W 1 . 1 M
W.13 O0M 0 W1. O1M PWM, Phase Correct, W 10-bit O 0x03FF TOP BOTTOM
WW 4.100Y.C 0 M.TW 1 WW .100Y.C M.TW WW .100Y.C M.TW
0
W O0 CTC W O OCRnA Immediate MAX
W O
WW 5 .100Y.C 0 M.TW 1 WW .100Y.C M.TW WW .100Y.C M.TW
W O 0W 1O Fast PWM, 8-bitWW .CO0x00FF TOP TOP
6W 0 O 1 1 W 0 O Fast PWM, 9-bit WW .CO 0x01FF W TOP TOP
WW .100Y.C M.TW WW .100Y.C M.TW W . 100Y M.T
W O W C O
7W
WW .100Y.C M.TW
0 O 1
WW .100Y.C M.TW
1 1 Fast PWM, 10-bit WW .100Y. 0x03FF M.T
W TOP TOP
W O W C O
W O
0WW Y.C PWM, Phase andW W
Frequency Y. W
W8W .1001Y.C M.T0W . 100 M .TW
Correct W .100 ICRnOM.T BOTTOM BOTTOM
WW .100Y. W Y W W 00 .T
M.T
W .100 O M.TPhase and Frequency
PWM, W.1 Y.COM W
9 WW 1 Y.CO 0 W 0 WWW 1 0Y.C W
W 1 00 M .T . 10 Correct
M .TW W
W .100
OCRnA
O M.T
BOTTOM BOTTOM
. W O .C
10 W
WW 1 00Y.CO 0 .TW 1 W
W Y.C
0.100 PWM, .TW Correct W W.1ICRn
Phase
W 00Y TW
M.TOP BOTTOM
. 1 M W O M C O
W W Y .C O
W W W 0 Y .C .T W W W 0 0 Y. .T W
11 W 1 00 0 .T 1 1 .10 PWM,M Phase Correct 1
.OCRnA MTOP BOTTOM
W 1 .100 1 M.T
W 0 .1 CTC M .1 M
12
W W .C O
W
0
WW 00Y.CO .TW W WWICRn00Y.COImmediate .TW
MAX
W 0 0 Y .T W . 1 M . 1 M
13 1 W.1 1 OM 0 1 W (Reserved) O W
– O
– –
W W 0 Y.C .T W WW .100Y.C M.TW WW .100Y.C M.TW
1 W.1 0 1 OM 0 W Fast PWM O W O
WW .100Y.C M.TW
14 1 ICRn TOP TOP
15 1 1
WW 00Y.CO .TW
1 1 WW Fast PWM O WW 00YTOP
WOCRnA .CO .TW TOP
W W 0 0Y.C M.TW 1
Note: 1. The CTCnWand .1 PWMn1:0 OMbit definition namesW are .1
Wobsolete. O the WGMn2:0 definitions. .
WW However, OM
W Y .C W W 0 Y .CUse .T W W 00 Y.C the functionality
.TW
and
W
location of these 0 0bits are T
compatible
. with previous 0
versions
.1 of the M timer. . 1 O M
W.1 OM W O W
WW .100Y.C M.TW
W O W O
W
WW .100Y.C M.TW
O
W W . C O
Y W
W
.C W
WW .100Y M.TW W
W . 100 O M .T W
W .100 OM
.T
W .C O W Y . C W W W 0 Y .C W
WW .100Y M .TW W
W .100 O M .T W .10 O M.T
W O WW .100Y .C
W
W O W O W W .C O
Y
M.T
W
W O W O W W .C O
Y
M.T
W
W O W O W W .C O
Y
M.T
W
W O W O W W .C O
Y .TW
W O W C O W W .C OM
W W .100
Y .TW
W O W C O W W .C OM
W W .100
Y .TW
W O W C O W W .C OM
W W .100
Y
W O W C O W W
W W
W O W C O
W
W O W C O
W O W
WW .100Y.C M.TW WW
W O
WW .100Y.C M.TW
W O
WW .100Y.C 132
W W
7799D–AVR–11/10 W
.C OM
00Y .TW
W W.1 Y.COM W
W 00 .T
16.11.2 TCCR1B – Timer/Counter1 Control Register B W W.1 Y.COM W
.TW W
5W.
100 4 OM.T3
Bit OM 7 6 2 1 0
0 0 Y .C
.T W ICES1 W – .10WGM13 W 0Y.C M .TW CS12
W.1 Y.COM
(0x81) ICNC1 WGM12 CS11 CS10 TCCR1B
W W W W W
0 Y .CO R/W .T W
W .100
Read/Write
OM
R/W
.T R/W R
.10 R/W
OM0
R/W R/W R/W
WValue C 0WW 0 Y.C
.TW W WInitial
1 00 Y . 0
M .T W 0
W . 1 0 0 M .TW 0 0 0
M . O W O
.CO .TW WW 00Y.C .TW WW Canceler 100
Y.C .TW
.100Y M
W
• Bit 7 –.1ICNCn:
W O Input
M Capture Noise W . O M
W O
WW this .C one) .activates W Y.C .TW
WW .100Y.C M.TW Setting . 1 0Y(to
0bit M TW theW Input Capture
W . 100 Noise O M Canceler. When the Noise Canceler is
W C O WW the00input O
.C from.T W Pin (ICPn) Y.C is filtered. W The filter function requires four
W Y . W activated,
W Y theW Input W
Capture 0 0 .T
W 00
W.1 Y.COM W
.T .1 M
CO samples W.1pin Y OM
W successive
W WW equal 0 Y .valued .T W of the W W ICPn 0 0 .Cchanging
for .TWits output. The input capture is
W .1 00 M .T therefore W .
delayed 10 by four O M Oscillator cycles when W .1 the noise O Mcanceler is enabled.
W
WW .100Y.C M.TW
O
O W O
W O WW 00Input Y.C Capture WW .100Y.C M.TW
WW .100Y.C M.TW • Bit 6W– ICESn: 1 .T W Edge Select
O WW which
. OM W .CO that
W
WW .100Y.C M.TW This bitW selects 0 0 Y.Cedge on .T W the Input Capture WW .Pin 1 0 0Y (ICPn)M .TW is used to trigger a capture
W . 1 O M W C O
W C O event. When W the ICESn .C bit is written to zero, Wa falling Y .
(negative) W is used as trigger, and
edge
WW .100Y. M .TW W . 1 00Y M .TW W
W .100 O M.T
O when the ICESn W O
bit is written to one, a rising (positive) C
. will trigger
W
WW .100Y.C M.TW WW .100Y.C M.TW WW .1edge 00Y M.T
Wthe capture.
W O W C O
W O
WW is triggered Y.C according WW setting, Y.the counter Wvalue is copied into the
WW .100Y.C M.TWhen W a capture . 100 M .TW to the ICESn W .100 O M.T
O Input Capture Register W (ICRn). O C
Y. Capture
W
WW .100Y.C M.can TWbe used W
W Y.C The
00Input
event will alsoWset the 0Input
.TW Interrupt,Wif thisWinterrupt .10 M.T
W Flag (ICFn), and this
to cause W . 1an O M
Capture CisOenabled.
W
WW .100Y.C M.TW
O
W
O When the ICRn isWused as Y W O W C O
.WGMn[3:0]
W
WW .100Y.C TCCRnA .TW and the
TOP.C value .TW
(see description WW of.1the 00Y M.T
W bits located in the
M
W
TCCRnB W .100Register), O M the ICPn is disconnected W and C O
consequently the input cap-
W
WW .100Y.C ture
O
function is disabled. W O
W OM W O
WW .100Y.C M.TW
W O W O
W O 5 – Reserved Bit
WW .100Y.C• Bit .T W WW .100Y.C M.TW WW .100Y.C M.TW
W ThisOM bit is reserved for WW use. .COensuring W
WW with.1future .CO .TW
WW .100Y.C M.TW Wfuture . 1 00Y
For
M .TW
compatibility 00Y devices, M
this bit must be
written to zero when TCCRnB W is written. O W C O
W
WW .100Y.C M.TW
O
W
W O W .C O
W
WW .100• YBit .CO4:3 –.TWGMn[3:2]: W W Y.C .TWMode W W.100Y OM.TW
W
M
WWaveform
W .100 Generation O M
W
WW .10See 0Y.C
O
TCCRnA .T WRegister description. WW .100Y.C M.TW WW .100Y.C M.TW
OM W O W O
W
W W • BitY2:0 . C O– CSn[2:0]: Clock Select
W .1
W
W .100three O
The M.Tselect bits select
clock
W Wthe .1 clock source
.C OM to be used by the W WTimer/Counter,
Y.C
OM see Figure
W
.C Y W W 0
W
W 15-1 . 1 0 Y
0and Figure M
W
.T15-2. W
W . 1 0 0
O M .T
W . 10
O M.T
W O WW .100Y .C
W
O W O W .C O
W
W
O W O W W .C O
WW 16-5.
WTable 00Y
.C Clock.TSelect W Bit Description WW .100Y.C M.TW W .100
Y
M.T
W
WW CSn2 .C
YCSn1 W
CSn0 WW .100Y.C M.TW
Description W .100
Y
M.T
W
WW0 .100Y.0C M.TW WWsource. Y.C W W .100
Y
M.T
W
W O
0 No clock
W .100(Timer/Counter
O M.T stopped) W W .C O
WW 0 .C 1W W prescaling Y.C W W .100
Y .TW
0
W .100
Y
O M.T
clkI/O/1 W(No
W Y. C Y .TW
W0W .1001Y.C M0.TW clkI/O/8 W (From prescaler).100 M.T
W W
W .100 OM
W O W C O W .C
0 W Y.C 1 .TW clkI/O/64 W
W Y. W W .100
Y .TW
W
W .1010 O M (From prescaler)
Y.C 0 .TWclk /256 (From WW prescaler) Y. C W Y
1W
W
.0100 M I/O W .100 O M.T
W
W .100
W O Y. C W
1 W
W
0.100
Y.C 1 .TW WW prescaler) .100 M.T
W W
W O M clkI/O/1024 (From W C O
W Y.C W WW .100Y. W
M.Ton falling edge
1 W 1 .100
W 0 OM.TExternal clock source W on Tn pin. O Clock
WW .100Y. C
1
WW 1 .100Y.C TW
1 OM.External clock sourceW on Tn pin. Clock on rising edge
W
WW .100Y.C M.TW WW
W O
WW .100Y.C M.TW
W O
WW .100Y.C 133
W W
7799D–AVR–11/10 W
.C OM
00Y .TW
W W.1 Y.COM W
If external pin modes are used W
W
forWthe .100Timer/Countern,OM
.T
.T W W 0 Y
0an .C
. W transitions on the Tn pin will clock the
TThis
counter even if the pin is configured .
as1 output. M feature allows software control of the
.C OM WW 00Y.CO .TW
counting. 00 Y .T W W .1 M
W 00 .T W 1 M
16.11.3 TCCR1C – Timer/Counter1 W W.1 Y.C OM Register C WW.
Control Y .CO .TW
W W W 0 0
OM
.T W
Bit W
.100 O7M
.T
5 WW
.1
4 Y.CO 3
M
Y.C W W
W(0x82) .10 0 Y .C W 6
W 0 0 .TW –
2 1 0
100 M .T M .T FOC1B FOC1C W.1– O –M
. WW
FOC1AO – – TCCR1C
W O
WW .100Y.C M.TW Read/Write 100Y W
W .C .T W W WW
W
.
R 1 0 0Y.C R M.TWR R R
W O W. OM 0 0 WW 0 00Y. 0
W CO
WW .100Y.C M.TW WW
Initial Value
0 0 Y.C 0
.T W . 1 M .TW0 0 0
W . 1 O M W C O
W O W . C W Y . W
WW .100Y.C M.TW • BitW7 – FOCnA: Y
.100 ForceOOutput
W
M.T Compare forW
W Channel 00 A
W.1 Y.COM W
.T
W O W W .C
WW .100Y.C M.TW
• Bit W 6 – FOCnB:0Force Y Output WCompare for W Channel 00B .T
W O • W .10 Force O M.T Compare for Channel W W.1 C Y.COM W
Bit 5 – FOCnC:
W .C Output
WW .100Y.C M.TW W .100
Y W
M.Tbits are only active
W
W .100 OM
.T
W O The FOCnA/FOCnB/FOCnC
W W .C O W when the
Y .C WGMn[3:0] W bits specifies a non-PWM
WW .100Y.C M.TW mode. When W .
writing
Y
100 a logical M
W
.Tone to the
W
W
FOCnA/FOCnB/FOCnC .100 O M.T bit, an immediate compare
O W O Y. C
W
WW .100Y.C M.TWmatch is W
W 0Y.C .TWgeneration WW .100OCnA/OCnB/OCnC M.T
W
forcedWon . 10the waveform
O M unit.WThe
C O output is changed
W W Y .C O
W
according Wto Wits COMnx[1:0] 0 Y .C bits.Tsetting. W Note W W
that the 0 0 Y.
FOCnA/FOCnB/FOCnC.T W bits are imple-
W
W .100 O M.T W .10
.C OM W W.1 Y.COM W
C W .TW
WW .100Y. mented
W as strobes.
M.Teffect of the forced
W .100
Y
Therefore it is the value present W in 0the0 COMnx1:0
W.1 Y.COM W
.T bits that determine the
W CO W W compare. .C OM W
WW .100Y. M.T
W W .100
Y .TW W 00
W.1 Y.COM W
.T
W CO W W .C OM W
WW .100Y. AT
. FOCnA/FOCnB/FOCnC
W Y
strobe W generateWany interrupt
will.Tnot
.100 norOwill M.itTclear the timer in Clear
W O MTimer
W
W .100 M
Omode W WTOP. .C
C on Compare W Match (CTC) .C using OCRnA as Y W
WW .100Y. M .TW W .100
Y
M .TW W
W .100 O M.T
W O W O W Y. C
WW .100Y.C The FOCnA/FOCnB/FOCnB
.T W WW .100bits Y.Care always .TW read asW zero. .100 M.T
W
M W O M W CO
W
WW .100Y.C • Bit
O
TW– Res: Reserved WW Bits Y.C .TW WW .100Y. M.T
W
M .4:0 W . 100 O M W C O
W O
WW for .future Y.C For WW .100with Y. future.T W
WW .100Y.CThese M TW are reserved
.bits 100 use. M
W
.Tensuring compatibility
W O M devices, these bits
W O C
W
WW .100Y.must CO be Twritten
. W
to zero WW when TCCRnC Y.C is written. .TW WW .100Y. M.T
W
M W . 100 O M W C O
W
WW and 0Y.C M
O
TW
.Timer/Counter1 WW .100Y.C M.TW WW .100Y. M.T
W
16.11.4 TCNT1H . 1 0TCNT1L – W O W .C O
W
WW .100Y .CO .TW WW 0Y.C M4.TW 3 WW .100Y .TW
Bit M 7 6 W.10 5 O 2 W 1 COM 0
W O WW .100Y .
WW .100(0x85) Y.C .TW WW .100Y.C M .TW
TCNT1[15:8]
W
M.T TCNT1H
M W O W .C O
W
WW .1(0x84) .CO .TW WW .100Y.C TCNT1[7:0] .TW WW .100Y W
M.T TCNT1L
00Y M W O M W .C O
W O WW .100Y
WW 0.100Y.C 0 M.TW0 .TW
Read/Write R/W R/W R/W R/W R/W R/W R/W R/W
WW .Initial .C .TW
1 00Y Value M 0 0 W O 0 W 0
.C O0M
W O WW .100Y
W
The two Timer/Counter
O I/O locationsW (TCNTnH O and TCNTnL, W
combined TCNTn).C O give direct
W
WW access, 0 Y.C .T W WW .100Y.C M.TW WW .100Y M .TW
1 0 both for read and for write operations, to the Timer/Counter O
W. . CO
M WW 00Y.CO .TW W
unit
WW 00Y.C 16-bit counter.
T W
To
WWensure 0 Y
.10 that both T W
. high and low bytes
the W .1 are read Mand written simultaneously . 1 whenMthe CPU .
WW 00these OM WW .CO using WW 00Y.CO .TW
Waccesses Y.C registers, T W the W
access is 0
performed
0 Y .T W an 8-bit W
temporary High
1 Byte M Register
W.1 This OM
. W.1by all .C
M
Oother W W. Y .CO 16-bit W
(TEMP). .Ctemporary register is W
shared Y the W
16-bit registers.
W See “Accessing
0
W W Y
.100on page M110..TW W
W .100 O M.T W .10 O M.T
W O W .C
WW .100Y.C M.TW
Registers” Y W
WW .100Y.C M.TW W
W .100 O M.T
W O W O W .C
Modifying
WW .the .C
counter (TCNTn)W whileWthe W counter Yis.Crunning W
introduces a risk of 1missing
W . 00
Y a com- .TW
W
0Y
10between O M.T and one of W W .100 Registers. O M.T W W .C OM
pare match TCNTn the OCRnx Y. C Y .TW
WW .100Y.C M.TW W .100 M.T
W W
W .100 OM
W O W C O W . C
Writing WW to the TCNTn Y.C Register W blocks (removes) WW .1the .
00Ycompare M.T
W on theWfollowing
match 0Y clock
.10timer .TW
for all compare W .100units. OM.T W C O W W .C OM
W W .100
Y
W O W C O W W
W W
W O W C O
W
W O W C O
W O W
WW .100Y.C M.TW WW
W O
WW .100Y.C M.TW
W O
WW .100Y.C 134
W W
7799D–AVR–11/10 W
. C OM
00Y .TW
W W.1 Y.COM W
W 00 .T
16.11.5 OCR1AH and OCR1AL – Output Compare Register W W.1 1 AY.COM W
.TW W 00
W.1 Y4.COM 3 W
.T
Bit
.C OM 7 6
W 5 2 1 0
0 0 Y .T W W . 1 0 0 OCR1A[15:8] M .T
W.1 Y.COM W
(0x89) OCR1AH
W W WW 00Y .CO .TW
W .100 M.T
(0x88) OCR1A[7:0] OCR1AL
W .C O W W.1 R/WY.COM W
WW
Read/Write R/W R/W R/W R/W R/W R/W R/W
M.T
W .100
Y
0M
.TW 0 W 00
W.1 0 Y.COM
.T
O InitialW Value
C O 0
W 0 0 0 0
0 Y.C .T W WW .100Y . .T W W . 1 0 0 M .TW
0 OM .CO .TW
W.1 Y.COOCR1BHM W
0Y.C Compare WW
W
1 B .100Y
WW 16.11.6
0 0 .T W and OCR1BL WW –.1Output 0 M .T W Register M
W W.1 Y.COM W BitWW
W Y .C7 O .TW 5 W
WW4 00Y.C3O .TW
.10 0 6
.1 2 1 0
W
W .100 O M.T W W . C O M W W Y . C OM
W
WW .100Y.C M.TW
(0x8B) OCR1B[15:8] OCR1BH
W . 100
Y
M .TW W
W .100 O M.T
O (0x8A) W O OCR1B[7:0]
Y.C
OCR1BL
W
WW .100Y.C M.TW WW .100R/W
Read/Write
Y.C .T W R/W WW . 1 0 0R/W M . TW
OM
R/W R/W R/W R/W R/W
W O W
WW
W .CO 0.TW 0
WW .100Y.C M.TW Initial Value WW .1000Y.C M 0 .TW 0 0
1 000Y 0
W O W C O W W .
. C OM
W . Y W
W W 0Y.C Mand .TWOCR1CLW– Output 0Y
.10Compare .TW W 100 OM
.T
16.11.7 W.10OCR1CH
CO W W . C OMRegister 1 C WW. Y .C W
WW .100Y. M .TW Bit W . 100
Y
M .TW 5 W
W .1300 O M.T 1
W 7 O
6 4 C 2 0
W
WW .100Y.C M.TW(0x8D)
O
OCR1C[15:8] M .TW OCR1CH
W W .C O
Y (0x8C) W OCR1C[7:0] OCR1CL
W
W .100 O M.T Read/Write W .1
. C OM R/W W W.1 YR/W . C OM R/W
W
C W R/W R/W
.TW
R/W R/W R/W
WW .100Y. W
M.TInitial Value
W
0 W.1
00Y0 W .100 0 OM.T0
W O C OM 0 0
W 0W .C 0
WW .100Y. C
.T W W W
1 0 0Y .
M .TW W . 1 00Y M .TW
OMThe Output Compare .
WRegistersOcontain a 16-bit value W .CO .TWcompared with the
W
WW .100Y.C counter T W WW .100Y.C M.TW WW that.10is0Y continuously
OM
. value (TCNTn). WW an00Output OM
W W Y.C W W WW A 0match 0 Y .COcan be .T W
used to generate
W 1
Y.C Compare .TW
interrupt, or to
W 00 generate.T a waveform output . 1 on the OCnx
M pin. . O M
W.1 OM W O W
WW .100Y.C M.TW
WW .100Y.C TheMOutput .TW Compare WW .100Y.C M.TW
Registers are W O high and low bytes are
W O
WW
W .C16-bit
O in size. To ensure that both the
WW .100Y.C M.TW
WW .100Y.Cwritten .T W
simultaneously when .1 0
the 0YCPU writes
M .TW to these registers, the access is performed using an
W W .C OM
W WWRegister Y
O
.C(TEMP). W W WW 00Y.CO .TW
Y8-bit temporary High WByte 0 .T This temporary
W
W .100 O M.T W .10
. COM W W.1 Y.COM by
register is shared
W
all the other
. C W 0Y Registers” .TW on pageW110.W.100 .T
WW .100Y 16-bit registers.
M.T
W See “Accessing W 016-bit OM
W . C O W W.1 Y.COM W W Y .C W
WW .100Y – Input
16.11.8 ICR1H andWICR1L M
W
.TCapture W
Register W1 .100 O M .T W
W .100 O M.T
O WW .100Y .C
WW .100BitY.C M.TW 7 WW .100Y.C M.TW M0 .T
W
6 W 5 O 4 3 2 W 1 .C O
W
WW .1(0x87) .CO .TW WW .100Y.C ICR1[15:8] .TW WW .100Y W
M.T ICR1H
00Y M W O M W .C O
W O WW .100Y
WW .(0x86) 00Y
.C .TW WW .100Y.C ICR1[7:0] M .TW W
M.T ICR1L
1 O M W O W .C O
W Read/Write
WW Initial Y.C R/W
.T0W
R/W
WW R/W.100Y.C R/W
.TW
R/W R/W WW R/W .100
Y R/W .TW
. 1 00Value M W 0 OM W OM
W .C O 0
W 0
Y .C 0
W
0
W W 0
0 Y.C0 W
W W
. 1 0 0 Y
M .T W W
W .1 0 0
O M .T
W . 1 0
O M.T
W
IThe Input O
Capture is updated with the counter (TCNTn) value eachWW .100Y
time an event .C occurs
WWICPn.1pin 00Y
.C .T W WW .100Y.C M.TW M .TonWthe
(or optionallyM on the Analog Comparator W Ooutput for Timer/Counter1). W The Input Capture O
WW 00Y.CO .TW
Wcan WWTOP.1value. 0 0Y.C M.TW WW .100Y.C M.TW
be.1used for defining M the counter W O W O
The Input .1 Capture M Register is 16-bit in size. Wlow bytes O
WW 00Y.CO .TW W WW To 0 0
ensure
Y.C
O that both the high W
. T W W
and
1 0 0Y.C are read .TW
W
simultaneously .1 when Mthe CPU accesses these.1 registers, M the access is performed W . using O anM8-bit
W O W O W .C
WW .1High .C Register .TW (TEMP). WW Y.C register W W all .1the 00Y M.T
W
temporary 00Y Byte M W 100
This .temporary
O M.T is shared by W otherO16-bit
C
W O Y. C W Y . .TW
WW See
registers. Y.C
“Accessing 16-bit
W Registers” WW on .page 100 110.OM.T
W W .100
W .100 O M.T W C W W .C OM
WW Interrupt Y.C W WW .100Y. M.T
W W .100
Y .TW
16.11.9 TIMSK1 – Timer/Counter1 W .100 OMaskM.T Register W C O W W .C OM
WW .1007Y.C M6 .TW 5 WW .100Y. M.2T
W W .100
Y
Bit O 4 W 3 O 1 0W
W .C W
W Y.C – .TW ICIE1 WW 00Y OCIE1B W
M.T OCIE1A TOIE1
W
(0x6F) W
W .10–0 O M –
W W .1OCIE1C
.C O TIMSK1
W .C W Y W
00Y W .100 .T
Read/Write W R R R/W R R/W R/W R/W R/W
Initial Value W.10 Y.CO 0
M.T 0 0 WW 0 .C O0M 0 0
W .TW W 00 Y
W . 1 00 M W . 1
W O
WW .100Y.C M.TW WW
W O
WW .100Y.C M.TW
W O
WW .100Y.C 135
W W
7799D–AVR–11/10 W
. C OM
00Y .TW
W W.1 Y.COM W
• Bit 5 – ICIEn: Timer/Countern,
W
W .100 Capture
Input
.T
OM Interrupt Enable
W .C
When this bit M
is TW to one,
.written W
and .
the
Y
100I-flag in Mthe
.TW Status Register is set (interrupts globally
CO W O
enabled), 0 0 Y.the .T W
Timer/Countern W W
Input 1
Capture
. 0 0Y.Cinterrupt M .TW is enabled. The corresponding Interrupt
W W.1 Y.COM W WW 0 Y .COwhen.Tthe W ICFn Flag, located in TIFRn, is set.
W Vector (See
00 “Interrupts” .T on page W 64.) is executed
. 10 M
. 1 O M W O
WW 00Y
.C .TW
W
WOutput 0Y.C MC.TMatch W
M .TW WBit 3 –.1
W
OCIEnC:
O
Timer/Countern,
M W . 10Compare O Interrupt Enable
.CO W Y .C W W W 0 Y .C .T W
00 Y .T W WWhenW 0
.10bit is written
this M.T to one, and the I-flag 0
.1 in theOStatus M Register is set (interrupts globally
W W.1 Y.COM W W 0 Y .CO .TW W WW 0 0 Y.C .TW is enabled. The corresponding
W 0 0 .T W
enabled), the
1 0 Timer/Countern M Output Compare . 1 C Match Minterrupt
W.1 OM W. CO “Interrupts”
Y.(See WW64.)0is .CO .Twhen
0Yexecuted W the OCFnC Flag, located in
WW .100Y.C M.TW WW Vector
Interrupt
. 1 0 0 M . T W on W page . 1 M
W O W O
W
WW .100Y.C M.TW
O TIFRn, WWis set. Y.C .TW WW .100Y.C M.TW
W . 100 O M W O
W O
WW .100Y.C M.TW • BitW
W 0 0 Y.C . T W WW .100Y.C M.TW
2 – OCIEnB: . 1 M
Timer/Countern, Output Compare W BOMatch Interrupt Enable
W O WW 00Y.CO .TW WW in the Y.C .TW is set (interrupts globally
WW .100Y.C M.TW When W this bit is . 1 written toM one, and the I-flag W . 1 0 0Status
O M
Register
O W O Y.C
W
WW .100Y.C M.TW enabled),
W Timer/Countern Y.C W Compare WW B Match .100 interrupt
W
M.Tis enabled. The corresponding
Wthe
W . 100 O M .T
Output
W C O
W O W (See .C WWis executed Y. when.Tthe W OCFnB Flag, located in
WW .100Y.C M.TWInterrupt W Vector
. 100
Y“Interrupts”
M .TWon page 64.) W .100 O M
W O C
W
WW .100Y.C M.TW
O TIFRn, is set.W Y.C .TW WW .100Y. M.T
W
W
W . 100 O M W C O
W O
WW Timer/Countern, Y.C WW .1A Y. W
WW .100Y.C M.T•WBit 1 – OCIEnA: . 100 M .TWOutput Compare W
00Match
O M.T
Interrupt Enable
W Y . W W 0 Y T W W 0 0 .T
W 00
W.1 Y.COM enabled),
.When
T this bit is written .10 to one,Oand M. the I-flag in theWStatus W.1 Register OM is set (interrupts globally
WW 00Y.COutput W W 0 Y .Cis W
W W
. 1 00 M .T W the Timer/Countern
W
W . 1 O M .T Compare A Match
W
interrupt
.1 0
O M.T The corresponding
enabled.
W O Interrupt Vector (See Y.C on .page W C
Y. the OCFnA W Flag, located in
WW .100Y.C M.TW WW “Interrupts” .100 M TW 64.) is W executed
.100
when
M.T
TIFRn, is set. W O W CO
W
WW .100Y.C M.TW
O
W
W O W C O
W O
WW .100Y.C Overflow WW Y. W
WW .100Y.C • Bit M .T0W – TOIEn: Timer/Countern, M .TW Interrupt EnableW .100 O M.T
O W O Y.C
W
WW .100Y.CWhen TW bit is written WW to one, Y.C .TW in the Status WW Register .100 isOset TW
M.(interrupts
M .this W .100 and the O M I-flag
W C
globally
W C O W .C W Y . W
WW .100Y. enabled),
M .TW
the Timer/Countern W .
Overflow
100
Y
M .TW
interrupt is enabled. W The
W
corresponding
.100 O M.T Interrupt Vector
W O“Interrupts” on pageW64.) is executed W O W located C
Y. in TIFRn,
WW .100Y.C M.TW
(See Y.C when
.TW
the TOVn WFlag, .100 M.T
Wis set.
W
W .100 O M W C O
W .CO .TW W Y.C WW .100Y . W
16.11.10 TIFR1 WW 00Y
– Timer/Counter1
1 M Interrupt Flag WRegister .100 M .TW W O M.T
. O W O .C
W
WW .100BitY.C M.TW 7 W6W .1050Y.C M 4 .T
W 3 WW 2 .1001
Y
M0 .T
W
W O W .C O
W
WW .10x16 .CO – W Y.C – .TWOCF1C OCF1B WW OCF1A .100
Y TOV1.TW TIFR1
00Y(0x36) M.TW– W
W .100
ICF1
O M W OM
W Read/Write .C O R R W R/W Y .C R .TW R/W R/W W R/W 0Y.C R/W W
W Y W W 0 0 W 1 0 M.T
W . 1 00 Value M.T 0
Initial 0 W 0.1 0OM 0 0 W .0
.C O0
W O WW .100Y
W
O W O W .C O
W 5Y
WW • Bit .C .TW WWInput 0Y.C M .TW WW .100Y M.T
W
. 1 00 – ICFn:MTimer/Countern, W .10Capture O
Flag
W .C O
W O
is.Cset when W occurs .C the ICPn WW Y .TW
WWThis .flag 1 00Y M .TW a capture W event
. 100
Yon
M .TW pin. When the Input
W .100Capture O MRegister
O
W is set by the WGMn[3:0] toWbe used0Y
(ICRn) W O
as.Cthe TOPWvalue, theWICFn Flag W is .C
Y set when the
W
WW .100Y.C M.TW W . 10 M .T W .100 O M.T
counterW reaches O the TOP value. W O W .C
Y
M.T
W
W O W O W W .C O
ICFn is automatically cleared when W the WInput Capture .C Interrupt W Vector W is executed. YAlternatively, W
WW .100Y.C M.TW 00Y
.1its M.T W .100 O M.T
ICFn can W be cleared O by writing a logic one W to bit O
location. W .C
Y .TW
W O W C O W W .C OM
WW Y.C W WW Compare Y. C Match W W .100
Y .TW
• Bit 3 – OCFnC:
W .100 Timer/Countern, O M.T Output
W .100 O M.T Flag W W .C OM
C timerTW W the0counter Y. C 0Y Output .TW
ThisW flagW is set00inY.the
1 M.
clock cycleWafter
.1 0 M .TW valueW
(TCNTn) matches
W .10the OM
W . O W C O W .C
Compare
WWRegister YC.C(OCRnC). W WW .100Y. M.T
W W .100
Y
WW Y.C Compare W (FOCnC) WWstrobe Y. W W
Note that a Forced
W .100
Output
O M.T W .100will notOset M.Tthe OCFnC Flag.
Y.C cleared WW .Compare Y. C W
OCFnC W is Wautomatically.100
W
M.T when the Output 100 M.T C Interrupt Vector is exe-
Match
W O W C O
WW .10OCFnC
cuted. Alternatively, 0Y.C can beW cleared by WW writing1a00logic Y. one to its bit location.
W O M.T W .
WW .100Y.C M.TW WW
W O
WW .100Y.C M.TW
W O
WW .100Y.C 136
W W
7799D–AVR–11/10 W
.C OM
00Y .TW
W W.1 Y.COM W
W 00 .T
• Bit 2 – OCFnB: Timer/Counter1, W W.1Output .C OM
Compare B Match Flag
.T W W . 1 0 0Y M .TW
This flag is set Min the timer clockWcycle W after the
O counter (TCNTn) value matches the Output
0 CO
Y.Register T W(OCRnB).W 0 0Y.C M.TW
Compare 0 . B . 1
W.1 Y.COM W W O
WW 0 0 .T WW .100Y.C M.TW
Note 1
. a Forced
Wthat OM Output CompareW (FOCnB) strobe
W .CO will not set the OCFnB Flag.
.T W WW .100Y.C M.TW W . 1 00Y M .TW
OM OCFnB
WW is0automatically O cleared when Wthe OutputOCompare Match B Interrupt Vector is exe-
0 Y.C .T W W 0 Y.C .T W WW .100Y.C M.TW
0 cuted.W . 1
Alternatively, OMOCFnB can be cleared W by writingOa logic one to its bit location.
W.1 OM WW .100Y.C M.TW
W O W O
W
WW .100Y.C M.TW
O • WBitW 1 – OCF1A: 0 0 Y.C Timer/Counter1, .T W WW Compare
Output . 1 00Y.C AM .TW Flag
Match
. 1 O M W O
W O ThisW WW
flag is set in .C timer.Tclock
the W cycle after WWthe .counter Y.C (TCNTn Wvalue matches the Output Com-
WW .100Y.C M.TW . 1 00Y M W 100 O M.T
W O
W
WW .100Y.C M.TW
O pare Register
WW .100Y.C M.TW
A (OCRnA).
WW .100Y.C M.TW
W O W O
W O
WW .C WW strobe Y.Cnot set.Tthe W OCFnA Flag.
WW .100Y.C M.TW
Note that a Forced0Y Output Compare
. T W (FOCnA) 0 0will
. 1 0 M W . 1 O M
W O W O W .C Match
WW .100Y.C M.TW OCFnAW isWautomatically Y.C cleared .TWwhen theWOutput 00Y
.1Compare
W
M.T A Interrupt Vector is exe-
W . 100 O M W C O
W O
WW .100OCFnA Y.C can byW Y. one .to W
WW .100Y.C M.TW
cuted. Alternatively, .Tbe
W cleared W writing 0a0logic its bit location.
W O M W .1 O MT
W O Y.C WW .100Y. C W
WW .100Y.C M.TW WW Timer/Countern,
. 100 M .TW M.T
O • Bit 0 – TOVn: W O Overflow Flag W .C O
W
WW .100Y.C M.TThe W setting W W Y.C .TWof the WGMn[3:0] WW .1bits 00Ysetting.MIn W
.TNormal
of thisW flag
. 100is dependent O M W C O and CTC modes,
W W .C O W Y .C W W W 0 Y . .T W
Y theWTOVn Flag W is set when 0 the .
timerT overflows. Refer to 0
Table 16-4 on page 132 for the TOVn
W
W .100 O M.T W .10
.C OM W W.1 Y.COM W
C W .TW
WW .100Y. FlagWbehavior W
M.T
when using
.100
Y
another WGMn[3:0] bitWsetting. 100
W. OM
.T
W C O W W .C OM W Y .C W
WW .100Y. .TWis automatically
TOVn
M
W 100 when
cleared
.
Y
M .TW
the Timer/Countern W
W .100 Interrupt
Overflow O M.T Vector is executed.
W O W O W its0bit C
Y.location..TW
WW .100Y.C Alternatively, .TW
TOVn WW can be cleared Y.C by writing.TW a logicWone to .1 0
M W . 100 O M W OM
W .C O W Y .C W W W 0 Y.C W
W W
. 1 00 Y
M .T W W
W . 10 0
O M .T
W .1 0
O M.T
W O WW .100Y. C
W
W O W CO
W
WW .100Y.C M.TW
O
W
W O W C O
W
WW .100Y.C M.TW
O
W
O W O W .C O
W
W
O W O W .C O
W
W
O W O W .C O
W
W
O W O W .C O
W
W
O W O W .C O
W
W
O W O W .C O
W
W
O W O W .C O
W
W
W O W O W W .C O
Y
M.T
W
W O W O W W .C O
Y
M.T
W
W O W O W W .C O
Y
M.T
W
W O W O W W .C O
Y .TW
W O W C O W W .C OM
W W .100
Y .TW
W O W C O W W .C OM
W W .100
Y .TW
W O W C O W W .C OM
W W .100
Y
W O W C O W W
W W
W O W C O
W
W O W C O
W O W
WW .100Y.C M.TW WW
W O
WW .100Y.C M.TW
W O
WW .100Y.C 137
W W
7799D–AVR–11/10 W
.C OM
00Y .TW
W W.1 Y.COM W
W 00 .T
17. SPI – Serial Peripheral Interface W W.1 Y.COM W
.TW W 00
W.1 Y.COM W
.T
.C OM W
Y W W 00 .T
WW .C W
.100
• Full-duplex,
W
Y Three-wire
O M.T Synchronous
W .100Transfer
Data
W OM
.T
C W .C
.TW W• WMaster 1 0or
.
M .TW
0YSlave Operation W . 100
Y
M .TW
M . O W O
.CO .TW WWFirst00or
• LSB C First
Y.MSB .TW Data TransferWW .100Y.C M.TW
.100Y M
W . 1 O M
W Programmable Bit Rates W O
W O
• Seven WW .100Y.C M.TW
• End of O Interrupt Flag WW O
W O WWTransmission Y.C 0Y.C M.TW
WW .100Y.C M.TW W
• Write Collision1 0 0 M .T W W . 1 0
W. FlagOProtection W O
W
WW .100Y.C M.TW
O
WW from
• Wake-up 0 0 Y.C Mode.TW
Idle WW .100Y.C M.TW
W. 1 OM W O
W O
WW .100Y.C M.TW • Double WWSpeed 0 Y.C Master
(CK/2)
0 .T WSPI Mode WW . 1 0 0Y.C M.TW
W. 1 OM W O
W
WW .100Y.C M.TW
O
W O W O
17.2W Overview
WW .100Y.C M.TW
O
W O WW 00synchronous O
W O
WW .100Y.C M.TW
The Serial Peripheral Interface (SPI) allows W high-speed Y.C Wdata transfer between the
WW .100Y.C M.TWATmega8U2/16U2/32U2 W . 1 O M.T AVR devices.
W O
and peripheral devices or between Cseveral
W
WW .100Y.C M.TW
O
W
W O W C O
W O USART can also
WW be.used Y.in C Master SPI mode,W see W “USART Y.in SPI Mode”
W on page 176.
WW .100Y.C M.TW 100 M .TW W .100 O M.T
O W O Y. C
W
WW .100Y.C M.The TW Power Reduction WW .1SPI .C
00Ybit, PRSPI, .TWin “Minimizing WW Power .100 Consumption”
W
M.T on page 44 on page
W O M W CO
W O 50 must be written
WW to zero Y.C
to enable SPI module. WW Y. W
WW .100Y.C M.TW . 100 M.TW W .100 O M.T
W O C
W O
WW .100Y.C Figure .TW 17-1. SPI WW 00Y
.C (1) .TW WW .100Y. M.T
W
M BlockW .1Diagram O M W C O
W
WW .100Y.C M.TW
O
W
W O W C O
W
WW .100Y.C M.TW
O
W
W O W C O
W
WW .100Y.C M.TW
O
W
W O W CO
W O
W
W O W C O
W O
WW .100Y.C M.TWDIVIDER W
W
W .100 O M W C O
W O WW .100Y .
WW .100Y.C M .TW
/2/4/8/16/32/64/128 WW .100Y.C M.TW M.T
W
O W O W .C O
W
W
O W O W .C O
W
W
O W O W .C O
W
W
O W O W .C O
W
W
SPI2X
O W O W .C O
W
W
O W O W .C O
W
W
W O W O W W .C O
Y
M.T
W
W O W O W W .C O
Y
M.T
W
W O W O W W .C O
Y
M.T
W
W O W .C O
SPI2X
W O W
Y .TW
W O W C O W W .C OM
W W .100
Y .TW
W O W C O W W .C OM
W W .100
Y .TW
W O W C O W W .C OM
W W .100
Y
W O W C O W W
W W
W O W C O
W
W O W C O
W O W
Note: 1. W W to Figure
Refer .C
00Y 1-1 onMpage .TW2, and Table WW 12-6 on page 77 for SPI pin placement.
W . 1 O
WW .100Y.C M.TW
W O
WW .100Y.C 138
W W
7799D–AVR–11/10 W
.C OM
00Y .TW
W W.1 Y.COM W
The interconnection between Master
W
W.and 100 SlaveOCPUs M.T with SPI is shown in Figure 17-2. The sys-
W .C
tem consistsOof Mtwo .TWshift Registers, W and
Y
.10a0 Master .TW generator. The SPI Master initiates the
Mclock
W O
.C cycle .TWwhen pulling WWlow the Y.C Select .TWSS pin of the desired Slave. Master and
communication
. 1 00Y M W . 100Slave O M
W O
WW Slave prepare 00Y the
.C .TW to be sent
data WW 0Y.C Mshift
in their10respective
. .TW Registers, and the Master generates
. 1 O M W O
WW
Wthe requiredY.clock C pulses
.TW
on the SCK WWline .to 100
Y.C
interchange .Tdata.
W Data is always shifted from Mas-
M .TW ter to .
Slave1 00
on theO MMaster Out – Slave W
In, MOSI, O
line, Mand from Slave to Master on the Master In
Y.C
O
00 .T – Slave . 1 M
W.1 OM WOut, MISO,
.CO .TW
line. After each data packet, W the Master
O will synchronize the Slave by pulling
WW .100Y.C M.TW WWthe Slave
high 0 0 YSelect, SS, line. WW .100Y.C M.TW
. 1 M W O
WW .100Y.C M.TW W
When configured . 1 as aMMaster, the SPI interface W has.Cno O automatic control of the SS line. This
W O WW 00Y.CO .TW WW 0Y W
WW .100Y.C M.TW must Wbe handled. 1 by user M software before 1 0
communication
W . O M.Tstart. When this is done, writing a
can
W O W O W clock0generator, Y.C
WW .100Y.C M.TW byte to WW the SPI
. 0Y.CRegister
10Data M .TWstarts theW SPI .1 0 TW the hardware shifts the eight
M.and
W O W O
W O
WW .C shifting WWthe SPI Y.C generator W stops, setting the end of
WW .100Y.C M.TW
bits into the Slave. After .TW one byte, clock
W . 1 00Y
O M W .100 O M.T
W O Transmission W Flag00(SPIF). Y.C If the SPI Interrupt WWEnable bit C
Y.(SPIE) in
TW the SPCR Register is set, an
WW .100Y.C M.TW interruptWis requested. . 1 The M .TW may continue
Master W
to 100 the next
.shift O M.byte by writing it into SPDR, or
O W O .C
W
WW .100Y.C M.TWsignal theWend of .packet
W .C
00Y by pulling .T W WW Select, . 1 0 0YSS M .TW last incoming byte will be
1 OM high the Slave W line.
O The
W O WW Register Y.C for later WW .100Y.C M.TW
WW .100Y.C M.TW kept in theW Buffer 1 0 0 M .T W use.
W O W. O WW 00Y.CO .TW
WW .100Y.C M.TWhen W configured WW as.1a0Slave, 0Y.C the M TWinterfaceW
.SPI will remain .1 sleepingMwith MISO tri-stated as long
W W .C O
W
W
Wdriven Y .COIn this W W WW 00Y.CO .TW
Y as the SS pin W is 0
high. .T state, software may update the contents of the SPI Data
W
W .100 O M.T W .10
.C OM W W.1 Y.COM W
C W W
WW .100Y. Register,
.TW
Muntil
SPDR, W but the .100
Y will not
data
M.T
be shifted W out by incoming 00
W.1 Yshifted,
clock.Tpulses on the SCK pin
OM the end of Transmission
W C O the SS pin is W
driven
W low. C
As
. Oone byte has been W
completely .C W
W Y. W W 0 Y .T W W 0 0
.1 SPCR O M.T is set, an interrupt
W . 1 00 M .T SPIF is set. If the
Flag, W .10 Interrupt
SPI O M Enable bit, SPIE, inW the C Register
W
WW .100Y.C isM
O
.TW
W Y.C W WW .100Y. TW
M.SPDR
requested. The WSlave
W . 100 continue
may O M .Tto place new data Wto be sent C into
O before reading
W W Y.C O
W W W 0 Y .C .T W W W 0 0 Y. .T W
W 00 .T
the incoming data. The last.1incoming 0 byte
M will be kept in the .1
Buffer Register M for later use.
W 00 .T W .1 M .1 M
W W.1 Y.FigureC OM 17-2. SPI Master-slave
W WW 00Interconnection Y .CO .TW W WW 00Y.CO .TW
W 00 .T W .1 M .1 M
W 00 .T W .1 M .1 M
W 00 .T W .1 M .1 M
W 00 .T W .1 M .1 M
W 00 .T W 1
W.1 Y.COM W .1 M .
WW 00SHIFT OM
WW 00Y.CO .TW W Y.C W
W W
. 1 00 M .T W
W . 1 O M W . 1 ENABLE
O M.T
W O WW .100Y .C
W
O W O W .C O
W
W
O W O W .C O
W
W
O W O W W .C O
WWsystem
WThe .C
00Y is single W
.Tbuffered in W
W
the transmit Y.C
100 direction TW double buffered
.and W .in10the0Y receive M.T
W
direc-
. 1 O M W . O M W W .C O
WWThis0means
tion. Y.C that.Tbytes W to be transmitted WW .100cannot Y.C be.T W W Data Y
.100Register .TW
W
W .1 0 O M W O M written to the SPI W W .C O Mbefore
theW C WW receiving .C Y must.Tbe W
W entire.1shift 00Y
.cycle is completed.
W
M.TRegister beforeWthe
When
00Y data,Mhowever,
.1next .TW a received
W
W
character
.100 O M
readW from
W the Y SPI OData W characterO has been W
completely shifted .C in. Oth-
.C .TW Y.C W W .100
Y .TW
W the.1first
erwise, W
00 byte isMlost.
O
W
WW .100Y. C Y .TW
WW .100Y.C M.TW W
M.T signal of the SCK
W
W .100 OM
In SPI W SlaveW mode, O
the control logic will W
sample the O
incoming
C W pin. To .Censure W
Y.C W WW .100Y. TW
M.clock
W .100 f O
Y
M.T
correct W sampling
W .100 of theOclock M.T signal, the frequency W of the C OSPI should never W W exceed .C /4.
WW .100Y. Y osc
WW .100Y.C M.TW W
M.TSCK, and SS pins
W
W .100
When theW SPIW is enabled, O the data direction of W
the MOSI, C O
MISO, W is overridden
Y.C W WW .100Y. .TW W
according to W
W .100 17-1.OFor
Table M.Tmore details onW automatic
W port
.C O Moverrides, refer to “Alternate Port
WW .100Y.C M.TW W . 1 00Y M .TW
W O W O
W O W
WW .100Y.C M.TW WW
W O
WW .100Y.C M.TW
W O
WW .100Y.C 139
W W
7799D–AVR–11/10 W
.C OM
00Y .TW
W W.1 Y.COM W
W 00 .T
Functions” on page 72. W W.1 Y.COM W
W W 00 .T
O M.T W W.1 Y.COM W
Table 17-1.Y .C SPI.TPin W Overrides W
(1)
00 .T
W .100 O M W W.1 Y.COM W
WW .Pin Y .C Direction,W MasterW SPI 00 .T Direction, Slave SPI
W 100 O M.T W.1 Y.COM W
.C W
W WW MOSI .100
Y User .Defined
MT
W W 00 .TInput
Y.C W WWMISO Y
.100 Input M.T
W W 00 .TUser Defined
W .100 O M.T W .C O W W.1 Y.COM W
WW .100Y.C M.TW WWSCK .100Y User Defined M.T
W W 00 .T
W O W .C O W W.1 Y.COMInputW
WW .100Y.C M.TW WW SS .100YUser Defined M.T
W W 00 .T
W O W C O W W.1 Y.COM Input
WW .100Y.C M.TW W W Y .
100“Alternate M .TW W .100 74 forOaM .TW
Note: 1. W .
See O Functions of Port B” onW page detailed description of how to define the
W
WW .100Y.C M.TW
O
WW direction 0 0 Y.ofC
the .T
user Wdefined SPI W W
pins. . 1 0 0Y.C M.TW
W. 1 M
W O .CO .TW WW 00Y.CO .TW
WW .100Y.C M.TW The following WW code 0 Yexamples show how W
to initialize the SPI as a Master and how to perform a
W O W . 1 0
W
WW .100Y.C M.TW simple transmission.W YDDR_SPI
.100the SPI .TWin the examplesW must
W.1 Y
00be replaced M.T by the actual Data Direction
W O Register W
controlling C OMpins. DD_MOSI, DD_MISO W .
andC ODD_SCK
WW .100Y. C
.TWactual data W W Y .
100bits for M .TW W .10is0 placed M .TW must be replaced by the
M direction
W . O these pins. E.g. if W
MOSI C O on pin PB5, replace DD_MOSI
W
WW .100Y.C M.TW
O W 0 Y.C W WW .100Y. .TW
with DDB5W and DDR_SPIW. 1 0 with
O M .T
DDRB. W O M
W
WW .100Y.C M.TW
O
W O W O
W
WW .100Y.C M.TW
O
W O W O
W
WW .100Y.C M.TW
O
W O W O
W
WW .100Y.C M.TW
O
W O W O
W
WW .100Y.C M.TW
O
W O W O
W
WW .100Y.C M.TW
O
W O W O
W
WW .100Y.C M.TW
O
W O W O
W
WW .100Y.C M.TW
O
W O W O
W O
W O W O
W
WW .100Y.C M.TW
O
W O W O
W
WW .100Y.C M.TW
O
W O W O
W
WW .100Y.C M.TW
O
W W .C O
Y W
W
.C W
WW .100Y M .TW W
W . 100 O M .T W
W .100 OM
.T
WW .100Y M .TW W
W .100 O M .T W .10 O M.T
W O WW .100Y .C
W
W O W O W W .C O
Y
M.T
W
W O W O W W .C O
Y
M.T
W
W O W O W W .C O
Y
M.T
W
W O W O W W .C O
Y .TW
W O W C O W W .C OM
W W .100
Y .TW
W O W C O W W .C OM
W W .100
Y .TW
W O W C O W W .C OM
W W .100
Y
W O W C O W W
W W
W O W C O
W
W O W C O
W O W
WW .100Y.C M.TW WW
W O
WW .100Y.C M.TW
W O
WW .100Y.C 140
W W
7799D–AVR–11/10 W
.C OM
00Y .TW
W W.1 Y.COM W
W 00 .T
(1) W W.1 Y.COM W
Assembly Code.TExampleW W 00 .T
.C OM W W.1 Y.COM W
Y
SPI_MasterInit: W W 00 .T
W .100 O M.T W W.1all Yothers .C OM
WW .100Y .C TW
; Set MOSI
M .TWand SCK output,
W
W . 100 O M .input
O
W ldi r17,(1<<DD_MOSI)|(1<<DD_SCK)
M W O W O
O WW .100Y.C M.TW
out DDR_SPI,r17
W.1 OM W; Enable OSPI, Master, set W W rate
clock Ofck/16
WW .100Y.C M.TW WW ldi 0 0 Y.C .T W W . 10 0Y.C M.TW
1 OM
W. r17,(1<<SPE)|(1<<MSTR)|(1<<SPR0) W O
W
WW .100Y.C M.TW
O
0Y.C M.TW
WW out.10SPCR,r17 WW .100Y.C M.TW
W O W O
W
WW .100Y.C M.TW
O
WWret .100Y.C M.TW WW .100Y.C M.TW
W O W O
W
WW .100Y.C M.TW
O
W O W O
W
WW .100Y.C M.TW
O
WW .100Y.C M.TW
SPI_MasterTransmit: WW .100Y.C M.TW
W O W .CO .TWof data W WW 00Y.CO .TW
WW .100Y.C M.TW WW .1transmission
; Start
00Y M
(r16)
.1 M
W W .C O
W
W
out WSPDR,r16
Y .CO .TW W WW 00Y.CO .TW
W 00 Y .T W .10 0 M .1 M
W W.1 Y.COM W Wait_Transmit: WW 00Y.CO .TW W WW 00Y.CO .TW
W 00 .T W .1 transmission M .1 M
W W.1 Y.COM W ; Wait for
WW 00Y.CO .TW
complete
W WW 00Y.CO .TW
W 00 .T W .1 M
W.1 Y.COM W
sbis SPSR,SPIF
W W 0 T W
W 00
W.1 Y.COM W ret
.T rjmp Wait_Transmit .10 M. .1
WW 00Y.CO .TW
M
W W WW 00Y.CO .TW W
W 00 .T W.1 Y.COM W .1 M
W W.1 Y.COM W W(1) W WW 00Y.CO .TW
W 00 C Code
.T Example W .10 0 M .T .1 M
W 00 W
.Tvoid SPI_MasterInit(void) .1 M .1 M
W 00 .T
{ W .1 M
W.1 Y.COM /*W Set MOSI W W.1 Y.COM W WW */00Y.CO .TW
W W and SCK 0output, .T
all others W input .1
W 00
W.1 Y.COM DDR_SPI
M
W W WW 00Y.CO .TW
= (1<<DD_MOSI)|(1<<DD_SCK);
W W
W 00 .T W.1 Yset M .1 OM
W.1 Y.COM/* Enable SPI,W Master, .CO clock W rate fck/16 W WW */ 0Y.C W
W W
. 1 00 M
W W 10
.T = (1<<SPE)|(1<<MSTR)|(1<<SPR0);
W . 0
O M .T
W .10
O M.T
W O WW .100Y .C
WW .100Y.C M.TW
SPCR W
WW .100Y.C } M.TW W O M.T
O W O .C
W
W
W O W .C O
W
WW .100Y.void CO WW .100Y.C .TW WW .100Y W
M .TW
SPI_MasterTransmit(char
W cData)
O M W O M.T
W O WW .100Y .C
WW .100Y {.C .TW WW .100Y.C M.TW M.T
W
O M W O W .C O
W
WW .100Y/* .C Start .TW transmission WW */ .100Y.C M.TW WW .100Y M.T
W
O M W O W .C O
W
WW .100SPDR Y.C = cData;.TW WW .100Y.C M.TW WW .100Y M.T
W
O M W O W .C O
W /* Wait for transmission
WW .100Y.C M.TW WW complete Y.C */ .TW WW .100Y M.T
W
W . 100 O M W C O
W O W .
WW .100Y.C M.TW
while(!(SPSR & (1<<SPIF))) Y W
WW .100;Y.C M.TW W
W .100 O M.T
W O W O W .C
WW } .100Y.C M.TW WW .100Y.C M.TW W .100
Y
M.T
W
W O W O W W .C O
Y
M.T
W
Note: W1. See “CodeO Examples” on page 6. W O W W .C O
Y .TW
W O W C O W W .C OM
W W .100
Y .TW
W O W C O W W .C OM
W W .100
Y .TW
W O W C O W W .C OM
W W .100
Y
W O W C O W W
W W
W O W C O
W
W O W C O
W O W
WW .100Y.C M.TW WW
W O
WW .100Y.C M.TW
W O
WW .100Y.C 141
W W
7799D–AVR–11/10 W
.C OM
00Y .TW
W W.1 Y.COM W
The following code examples show
W 100 to initialize
W.how
.T
OM the SPI as a Slave and how to perform a
W .C
simple reception. M .TW W . 100
Y
M .TW
W O
. 1 00Y Code M (1) W O
Assembly
W O Example
WSPI_SlaveInit: O W O
OM W ; SetY.C O output, all others W input O
WW .100Y.C M.TW
MISO
00 Y.C .T W WW ldi 1 0 0 .T W
W.1 OM W. OM
r17,(1<<DD_MISO) W O
WW .100Y.C M.TW WW out 0 0 Y.C .T W WW .100Y.C M.TW
W. 1 DDR_SPI,r17
OM W O
W
WW .100Y.C M.TW
O
WW ; Enable 0 0 Y.CSPI .TW WW .100Y.C M.TW
W. 1 M W O
W O
WWldi .1r17,(1<<SPE) .CO .TW WW .100Y.C M.TW
WW .100Y.C M.TW 00Y
WW SPCR,r17 OM W O
W
WW .100Y.C M.TW
O
Wout 0 0 Y.C .T W WW .100Y.C M.TW
. 1 M W O
WW .100Y.C M.TW
ret
W 1
W. OM W O
W
WW .100Y.C M.TW
O
W O
W O WW 00Y.CO .TW
SPI_SlaveReceive:
WW .100Y.C M.TW
WW .100Y.C M.TW W 1
; Wait W for. reception OM complete W O
W
WW .100Y.C M.TW
O
sbis SPSR,SPIF . 1 M W O
WW .100Y.C M.TW rjmpWSPI_SlaveReceive . 1 M
W O W .CO and WW 00Y.CO .TW
WW .100Y.C M.TW ; Read WW received
. 1 00Ydata M .TW return W .1 M
W W .C O
W 00 Y .T in r16,SPDR
W .1 M .1 M
W 00 .T W .1 M .1 M
W 00 .T W .1 M .1 M
W W.1 Y.COC MCode
W ExampleW (1)
W 00 .T .1 M .1 M
W W.1 Y.COM void W SPI_SlaveInit(void) WW 00Y.CO .TW W WW 00Y.CO .TW
W 00 .T W .1 M .1 M
W W.1 Y.COM{ W WW 00Y.CO .TW W WW 00Y.CO .TW
W 00 .T W .1 .1 M
W.1 Y.COM/* Set MISO output, WW all .C OM input */
others WW 00Y.CO .TW
W W W 0 Y .T W W .1
W 00
W.1 Y.COM
M
W
DDR_SPI
W
= (1<<DD_MISO);
W WW 00Y.CO .TW W
W 00 M.T Enable SPI */ W.1 M .1 M
W W.1 Y.CO/* W W Y .CO .TW W WW 00Y.CO .TW
W 00 SPCR.T= (1<<SPE); W 0 0 .1 M
W W 0 .T W 1
W 00 }
W.1 Y.COM W
.T .10 M .
WW 00Y.CO .TW
M
W 00 M.T .1 M . M
W W.1 char .C OSPI_SlaveReceive(void)
W 0 0 Y .T W .1 M . 1 M
W W.1 { Y.COM W WW 00Y.CO .TW W WW 00Y.CO .TW
W 0 .T W 1
0
W.1 /* Wait OM for reception W W.1 Y.*/ CO
M W. OM
WW .100Y.C M.TW W
complete
0 0 .T W WW .100Y.C M.TW
W.1 OM W O
W while(!(SPSR O WW .100Y.C M.TW
& (1<<SPIF)))
WW .100;Y.C M.TW WW .100Y.C M.TW
W O
W .CO .TW WW 00Y.CO .TW WW .100Y.C M.TW
WW ./* 0 Y
0 Return Data Register */ W.1 W M
W 1 Y.COM W W Y .CO .TW W WW 00Y.CO .TW
WW return 0 SPDR;. T W 0 0 .1 M
0
W
W } .100 T W 0 0 .T W 1
M. W.1 OM W. OM
Note: 1 “CodeOExamples”
1.W.See M on page 6. W O W O
W O W O
17.3 SS Pin Functionality
W
WW .100Y.C M.TW
O
O W O W
W
W O W O
17.3.1 Slave Mode
When the SPI W WSelect (SS) O pin is always input. When SS is
W is configured Y.C
00activated,
O as a Slave, the Slave
TW MISO becomes WW .100Y.C
held low, W the SPI . 1
is M .and an output if configured so by the user. All
W .COSS is.Tdriven WW
other pins are WWinputs. 0 0 Y
When W high, W all pins are inputs, and the SPI is passive, which
W W.1 Y.COM W
W 00 .T
W W.1 Y.COM
W 00
W W.1 142
7799D–AVR–11/10 W
.C OM
00Y .TW
W W.1 Y.COM W
W 00 .T
means that it will not receive incoming W W.1 data. .C OMthat the SPI logic will be reset once the SS pin
Note
is driven high. M .TW W . 100
Y
M .TW
O W O
00pinY.C .TWfor packet/byte WW .100Y.C M.TW
. 1 M O to keep the slave bit counter synchronous
The W SS isO useful
Y.C clock WW synchronization
Y.C .TW high, the SPI slave will immediately
WW withWthe . 1 0 0
master M .T W
generator.
W When .
the 1 0 0SS pin isMdriven
O W .C O
.TW
W the0send
Wreset 0Y.C andMreceive .TW logic, and WWdrop.1any 00Ypartially M TW
.received data in the Shift Register.
M W . 1 O W O
.C O W Y .C W W W 0 Y .C .T W
Y W W .10 0 M.T .1 0
100
W.17.3.2 M.T Mode WW 00Y.CO .TW
M
W Y .C OMaster
W W WW 00Y.CO .TW W
W 00 .T W.1SPI Y OM .1 OM is set), the user can determine the
W W.1 Y.COM W When Wthe 0
is.Cconfigured
W
as a Master
W WW (MSTR Y
00
in.CSPCR
.TW
W 00 .T W
direction of. 1 0 SS pin.M.
the T . 1 M
.1 M W O W O
W
WW .100Y.C M.TW
O
If SS is W
configured as O an output, the pin is aWgeneral output O pin which does not affect the SPI
W O
WW .100Y.C M.TW system. WW 0 0 Y.C .T W WW .100Y.C M.TW
W. 1
Typically, the pin OMwill be driving the W SSWpin of the
W O .CSPIO Slave.
W O W O
WW .100Y.C M.TW
W O If SS is configured
W as an
.C input, it must be held high to ensure Master SPI operation. If the SS pin
WW .100Y.C M.TW is drivenWlow by.1peripheral 00Y .T W
W O W OMcircuitry when theWSPI W is configuredY.C
O as a Master with the SS pin
WW .100Y.C M.TWdefined as WW an input, 0 0 Y.C SPI system
the . T W interprets W this.1as 0 0another M .TW selecting the SPI as a
master
W. 1 OM O
W O Y.Cdata to.Tit. WW 00Y.Cthe .TW
WW .100Y.C M.TW slave and starting WW to . 1 0send
0 M
WTo avoid W bus contention,. 1 MSPI system takes the following
W O W C O W W .C O
C actions: W . .TW Y W
WW .100Y. M .TW W . 100
Y
M
W
W .100 O M.T
W O W .C O W Y. C W
WW .100Y.C M.T1. W The MSTR WWbit in.1SPCR 00Y is cleared M .TW and the W SPI system .100becomes M.aTSlave. As a result of
W O W C O
W O the SPI becoming WW .1a00Slave, Y.C the.T MOSIW and SCK WWpins .become Y. inputs. W
WW .100Y.C M.TW M W 100 O M.T
O 2. The SPIF Flag W O Y. C
W
WW .100Y.C M.TW WW in SPSR C set, and
.is
00Y willMbe .TW
if the SPI interruptWW .is 100
enabled, andW
M.T
the I-bit in SREG
is set, the interrupt W .1routine O executed. W C O
W O
WW .100Y.C Thus, .TW WW .100Y.C M.TW WW .100Y. W
M.Tthere exists a possi-
M when interrupt-driven W SPI transmission
O is used in W
Master mode,C O and
W O
WWlow,.1the .C W Y. W
WW .100Y.C bility M TWSS is driven
.that 00Y interrupt M TW always
.should Wcheck
W 100 the MSTR
.that O M.Tbit is still set. If the
W O W O
.C select, W Y. C
WW .100Y.CMSTR bitWhas been W
.T
W by00aYslave
cleared 1 M .TW it must be Wset 100user to
by .the M .TW SPI Master
re-enable
M W . O W C O
W CO
WW .100Y.mode. .TW WW .100Y.C M.TW WW .100Y. M.T
W
M W O W C O
W
WW .100Y.C M.TW
O
W
17.4 Data Modes O W O W .C O
W
WW .100Y.C M.TW WW .100Y.C M.TW WW .100Y Mdata,.TW
There Oare four combinations Wof SCK phase O and polarity with W
respect to C O
serial
. which are
W
0Y.C M.by
WW .10determined TWcontrol bitsWCPHA .and
W .C
00YCPOL.MThe .TWSPI data transfer WW .100Y M .TW
1
W W .C O
W WW 00Y.CO .TW W WW 00Y.CO .TWin Figure
formats are shown
Y W
W
W 100 andOFigure
.17-3 M.T 17-4. Data bits are.1shifted outMand latched in on opposite
W . C O W W.1 edges OM of the SCK sig-
Y.C by summarizing W
.C W Y W W 0
WW nal,
. 1 00 Y
ensuring
M .T W
sufficient time W for data
W . 1 0 0
signals
O
to
M stabilize.
.T This is clearly
W . 1 0 seen
O M.T
W O
.C and .Table W below: Y.C WW .100Y .C W
WW Table . 1 00Y
17-3
M TW 17-4, as Wdone . 100 M .TW W O M.T
O W O .C
W
W
O W O W .C O
W
W
W O W O W W .C O
Y
M.T
W
W O W O W W .C O
Y
M.T
W
W O W O W W .C O
Y
M.T
W
W O W O W W .C O
Y .TW
W O W C O W W .C OM
W W .100
Y .TW
W O W C O W W .C OM
W W .100
Y .TW
W O W C O W W .C OM
W W .100
Y
W O W C O W W
W W
W O W C O
W
W O W C O
W O W
WW .100Y.C M.TW WW
W O
WW .100Y.C M.TW
W O
WW .100Y.C 143
W W
7799D–AVR–11/10 W
.C OM
00Y .TW
W W.1 Y.COM W
W 00 .T
W W.1 Y.COM W
Table 17-2. OM CPOL.TW Functionality W 00
W.1 Y.COM W
.T
Y.C W W W 00 .T
W .100 O M.T W W.1 Edge
Leading .C OM Trailing Edge SPI Mode
WW .100Y .C T W W 0 0Y . TW
. . 1 M
WCPOL=0, CPHA=0 OM Sample W (Rising) O Setup (Falling) 0
OM WCPOL=0, CPHA=1 O Setup W (Rising) O Sample (Falling) 1
0 O
W.1 OM CPOL=1,
W CPHA=0 O Sample W
(Falling)
WW .100Y.C M.TW
Setup (Rising) 2
W O W
CPOL=1, CPHA=1 O Setup W W
(Falling) .CO Sample (Rising) 3
WW .100Y.C M.TW WW17-3..10SPI
Figure 0Y.CTransfer .T W
Format with WCPHA =0
W O W . C O M W W.1 Y.COM W
W
WW .100Y.C M.TW W SCK.1(CPOL 00Y = 0) M.TW W 00
W.1 Y.COM W
.T
W O W W .C O W
WW .100Y.C M.TW W mode.10 00Y M.T
W W 00
W.1 Y.COM W
.T
W O W W .C O W
WW .100Y.C M.TW
SCK (CPOL = 1)
W mode 2.100Y .TW W 00
W.1 Y.COM W
.T
W C O W W .C OM W
WW .100Y. M.T
W W .1I 00
Y .TW W 00
W.1 Y.COM W
.T
W CO SAMPLE
W W .C OM W
WW .100Y. M.T
W W .100
Y .TW W 00
W.1 Y.COM W
.T
W CO
MOSI/MISO
W W . C OM W
WW .100Y. M.T
W W 0 .10
0Y .TW W 00
W.1 Y.COM W
.T
W CO CHANGEW
W .C OM W
WW .100Y. M.T
W MOSI WPIN .100Y .TW W 00
W.1 Y.COM W
.T
W CO CHANGE W 0 W .C OM W
WW .100Y. M.T
W W
MISO PIN W.10
0Y .TW W 00
W.1 Y.COM W
.T
W CO W .C OM W
WW .100Y. M.T
W W .100
Y .TW W 00
W.1 Y.COM W
.T
W C O W W .C OM W
WW .100Y. M.T
W SS W .100
Y .TW W 00
W.1 Y.COM W
.T
W C O W W .C OM W
WW .100Y. W Y W W 00 .T
W O M.T
W
=W
.100 BitO
M.TBit 5 W W.1 Bit 2Y.COBitM
C MSB first (DORD W 0) MSB .C 6 Bit 4
W Bit 3 WBit 4 .1Bit005Bit 3 1 W
LSB
WW .100Y. M .TW LSB first (DORD W = 1) LSB .
Y
100 Bit 1OM.T Bit 2
W Bit 6M.T MSB
O
W C
W
WW .100Y.C M.TW
O
W
W O W C O
W O 17-4. SPI Transfer
WW .100Y.C M.TW
Figure WW Format .C CPHA
Ywith .TW= 1 WW .100Y. M.T
W
W .100 O M W C O
WW .100Y.C M.SCK TW(CPOL = 0)W .100 M .TW W O M.T
O mode 1 W O .C
W
WW .100Y.C M .TW WW .100Y.C M.TW WW .100Y M.T
W
O SCK (CPOL = 1) W O W .C O
W
WW .100Y.C mode .TW3 WW .100Y.C M.TW WW .100Y M.T
W
O M W O W .C O
W
WW .100Y.C SAMPLE .TWI WW .100Y.C M.TW WW .100Y M.T
W
O M W O W .C O
W
WW .100Y.C MOSI/MISO .TW WW .100Y.C M.TW WW .100Y M.T
W
O M W O W .C O
W
WW .100Y.CCHANGE .T0W WW .100Y.C M.TW WW .100Y M.T
W
O M W O W .C O
W
WW .100Y.C M.TW
MOSI PIN
W
W CHANGEO 0 W O W W .C O
WW .100Y .C PIN .TW
MISO WW .100Y.C M.TW W .100
Y
M.T
W
W O M W O W W .C O
Y
M.T
W
W SS CO W O W W .C O
WW .100Y. W WW .100Y.C M.TW W .100
Y
M.T
W
WW .10MSB .C
0Yfirst W WW .100Y.C M.TW W .10LSB0Y .TW
W (DORD
O M.=T0) MSB Bit 6 W Bit 5
CBitO
4 Bit 3 Bit 2 Bit 1W
W .C OM
WW .1LSB 00Y
first.C(DORD = 1) W LSB Bit W
W 1 Bit 2 0Y. Bit 3
M.T
BitW4 Bit 5 WBit 6 .1MSB 00Y .TW
W O M.T W .10 O W W .C OM
WW .100Y. C Y .TW
WW .100Y.C M.TW M.T
W W
W .100 OM
W O W C O W .C
W W .100
Y
W O W C O W W
W W
W O W C O
W
W O W C O
W O W
WW .100Y.C M.TW WW
W O
WW .100Y.C M.TW
W O
WW .100Y.C 144
W W
7799D–AVR–11/10 W
.C OM
00Y .TW
W W.1 Y.COM W
W 00 .T
.TW W 00
W.1 Y.COM W
.T
.C OM W
00Y W W 00 .T
17.5.1 SPCR – SPI Control.1Register
WWBit .100Y .C 7 .TW W5 004 3.T
W.1 MSTRY.COM
6 2 1 0
W O M W
WW .100Y .C W
M .TW
0x2C (0x4C) SPIE
M .TW SPE W
DORD
W . 100 O
CPOL
M .T CPHA SPR1 SPR0 SPCR
WW 00Y.C O Y.C
.CO .TW W
Read/Write R/W R/W R/W R/W R/W R/W R/W R/W
00Y WInitial 1 0 M.
TW 0 W . 1000 0M
.TW 0
.1 M Value. O 0 W O 0 0
W W Y .CO
W 00
W.1 Y.COM W
.T .1 M.T .1
WW 00Y.CO .TW
M
W • W BitW 7W – SPIE: 0 Y .COInterrupt
SPI .T W Enable W
W 00 .T W.1 the
0
OMinterrupt to be executed .1 M
W.1 Y.COM W This bit Wcauses Y .CSPI W W WW if0SPIF 0 Y .CObit in .the WSPSR Register is set and the if
W W
.1 00 M .T the
W
Global W . 10 0
Interrupt O M
Enable
.T
bit in SREG is set. W .1 O MT
W
WW .100Y.C M.TW
O
W O W O
W O
WW .100Y.C M.TW • Bit 6W– SPE:.1SPI
W .C
00YEnable .T W WW .100Y.C M.TW
M W CO
W O
WW
W .CO to.Tone, Wenabled. 0Y.This TW be set to enable any SPI
WW .100Y.C M.TW When the SPE bit
. 1 0 is
0 Ywritten
M
W the SPI Wis
W . 1 0
O M.must
bit
W O C
W
WW .100Y.C M.TW
O operations. WW .100Y.C M.TW WW .100Y. M.T
W
W O W C O
W
WW .100Y.C M.TW
O
WW Data Y.C .TW WW .100Y. M.T
W
• Bit 5 – DORD: W . 100 Order O M W C O
W
WW .100Y.C M.TWhen
O
W the DORD WW bit.1is0written 0Y.C toMone, .TWthe LSB of WW the W data.10word0Y. is transmitted
M.T
W
first.
W O W O W .C O
W Y .C W W W 0 Y .C .T W W 0 0 Y .T W
W 00 .T the DORD bitWis.1written 0
OM .1 word isOtransmitted
M
W W.1 Y.COM When W W 0 Y .Cto zero, the MSB of the
W W WW data
0 0 Y .C .TW
first.
W 00 .T W . 1 0 M .T . 1 M
W.1 OM W O
WW 00Y.CO WW .100Y.C M.TW
WW .100Y.C •MBit .TW4 – MSTR: WMaster/Slave .1 Select
M .TW
W O W O W
WWand .Slave .CO .TWwhen written logic
WW .100Y.C This T bit
Wselects Master WW SPI 0 0Y.C when
mode . W
Twritten to one, 1 00Y SPI mode
.
M If SS is configured . 1 M WWMSTR OM
W .C O
zero. WWas an Y .CO and.TisWdriven lowWwhile
input 0Y.isCset, MSTR W will be cleared,
W W
. 1 00 Y
and M SPIF
W
.T in SPSR will become W
W . 0
10 set. O TheM user will then have W to
0
.1set MSTR O Mto.Tre-enable SPI Mas-
W O WW .100Y. C
WW .100Y.Cter mode. .TW WW .100Y.C M.TW M.T
W
M W O W C O
W
WW .100Y.C M.TW
O
W
W O W C O
W
WW .100Y • .C O 3 – CPOL: Clock Polarity
Bit .TW WW .100Y.C M.TW WW .100Y. M.T
W
M W O W .C O
W WhenOthis bit is written to W SCK is.C W Y W SCK is low
WW .100Y.C M.TW Wone, high when .TWidle. When WCPOL is written to zero,
W .
Y
100 Figure O M W .100 O M.T
W when O
idle. Refer to Figure 17-3 and 17-4 for an example. WW .100Y The CPOL .C functionality is sum-
WW .10marized 0Y.C below: .T W WW .100Y.C M.TW M .TW
OM W O W O
W
W W TableY.17-3. C O CPOLW Functionality WW 00Y.CO .TW W WW 00Y.CO .TW
W
W
W .100 O M.T W .1
.C OM W W.1 Y.COM W
.C W Y W W 100 Edge .T
WW .100Y CPOL
M .TW W . 100
Leading Edge
M .T W .Trailing OM
W W 0 Y . 0 .T W W 0 0 YRising .T W W . 1 0 0
Falling M.T
. 1 0 M W .1 O M W C O
W O Y.C WW .1Rising . W
WW .100Y.C 1M.TW WW .100Falling M .TW 00Y M.T
W O W O W W .C O
Y
M.T
W
• Bit 2 – CPHA: O Clock Phase W O W W .C O
WW 00Y.C .TW Phase bitW(CPHA)
W 0Y.C M.TW W 0Y
.10leading M.T or
W
WThe settings
W .1 of the O M Clock W .10determine O if data is sampled W on W the .C O (first)
Y.C W .C .TW 17-4 forW Y W
WW (last)
trailing .100 edgeOof TW Refer to
M.SCK.
WFigure
W
00Y and M
.117-3 O Figure an example.W .100 TheOCPOL M.T
W W .C
WW .10is0Ysummarized
functionality .C W WW .100Y.C M.TW W .100
Y .TW
W O M.T below: W C O W W .C OM
WW .100CPHA Y.C W WW .100Y. M.T
W W .100
Y .TW
Table 17-4. W O M.T
Functionality W C O W W .C OM
W W .100
Y .TW
W CPHA CO Leading W Edge C O Trailing W W
Edge .C OM
WW .100Y. W WW .100Y. M.T
W W .100
Y
W 0 O M.T Sample W C O Setup W W
W W
W 1 O Setup W C O Sample
W
W O W C O
W O W
WW .100Y.C M.TW WW
W O
WW .100Y.C M.TW
W O
WW .100Y.C 145
W W
7799D–AVR–11/10 W
.C OM
00Y .TW
W W.1 Y.COM W
W 00 .T
• Bits 1, 0 – SPR1, SPR0: SPI W W.1 Rate
Clock .C OM 1 and 0
Select
These two bits M .TW the SCK
control
W
rate of . 00Y
1the device M .TW
configured as a Master. SPR1 and SPR0 have
W O
0 Yon .CO .TW WW .1between 0 0Y.C SCK .TW
no effect0 the Slave. The relationship M and the Oscillator Clock frequency fosc is
W shown in
00 the following.T table: W .1 M
.T W WTable 17-5. 00 Relationship .T W .1 the Oscillator M
.COM W W.1 Y.C OM
W
Between SCK
WW and 0 Y .CO .TWFrequency
Y W W 0 W 0
00
W.1 Y.COM W
.T .10
SPI2X M.T SPR1 WW SPR0
.1 OM SCK Frequency
10 0 Y.C .TW
W .100 M .T . 1 M W . O M f
W 0 O 0 osc/4W
W
WW .100Y.C M.TW
O
WW .100Y.C M.TW WW .100Y.C M .T
W O W0 C O 0 W W1 . C O fosc/16
WW .100Y.C M.TW
W Y . .TW W .100
Y
M/.64TW
W
0 W . 100 O M 1 W Of
WW .100Y.C oscM.TW
W O 0
W O W fO /128
WW .100Y.C osc M.TW
W O 0 1 1
1 W O 0 0W f O/2
W
WW .100Y.C M.TW
O
WW .100Y.C M.TW WW .100Y.Cosc M.TW
O 1 W O0 1 W f .CO /8
W
WW .100Y.C M.TW WW .100Y.C M.TW WW .100Yosc M.T
W
O 1 W O 1 0 W f .C/ O
32
W
WW .100Y.C M.TW WW .100Y.C M.TW WW .100Y osc
M.T
W
1 W O
1 1 W f / C
64 O
W
WW .100Y.C M.TW
O
WW .100Y.C M.TW WW .100oscY. M.T
W
W O W C O
W
WW SPSR –.C
O
.TW RegisterW W.100Y OM.TW
W .C WW .100Y. M.T
W
17.5.2
. 1 00Y SPI Status
M W C O
W
WW .100Y.C M.Bit
O
TW WW Y.C 5.TW WW3 .100Y2. M.1T
W
7
W . 1006 O M 4
W C O
0
W C O W .C W Y . W
WW .100Y. M
0x2D
.TW
(0x4D)
W SPIF
.
WCOL
10R0
Y –
M .TW – W –
W .100R
–
O MR.T
– SPI2X SPSR
W O C
W O WW .100Y.
Read/Write R R R R R/W
WW .100Y.C Initial W W Y.C TW 0 .TW 0
M .TValue W
0
W . 1000 O0M. 0 W 0
C O M
0
W
WW .100Y.C M.TW
O
W
W O W C O
W
WW .100Y.C• Bit
O 7 – SPIF: SPI Interrupt
.TW WW .10Flag 0Y.C M.TW WW .100Y. M.T
W
M W O W C O
W O a serial transfer W
When W is complete, Y.Cthe SPIF Flag is set. WWAn interrupt Y. is generated.TW if SPIE in
WW .100Y.C M.TW . 100 are enabled. M .TW W .100is driven O Mlow
SPCR is set and global W
interrupts O If SS is an input and C when the SPI is
W
WW .100Y .CO .TW WalsoW 0
C
0Y.SPIF .TWSPIF is cleared WW .100Y. M .TW
in Master mode, this will set.1 the MFlag.
W W .C OM
by hardware when executing the
Y W
W 00corresponding
W.1 SPI
.T interrupt handling
OM Register with SPIF .1vector. Alternatively,
OM the SPIF bit W.is1 cleared byMfirst reading the
.CO .TW
W Y .C
Status W W WWset, 0then 0 Y .Caccessing .T W the SPI W
Data
WRegister 0 0 Y(SPDR).
W 00 .T .1 M .1 M
W 00 W 1
W.•1 BitY6.C–OWCOL: M.T Write COLlision WW Flag
.1
.CO .TW
M .
WW 00Y.CO .TW
M
W W W 0 0 Y W 1
W .100WCOL
WThe OM bit.Tis set if the SPI Data .1
WW Register
M
.CO (SPDR) is writtenWduring W. aYdata M
.CO transfer. The
W
W WCOL 0 0 Y .C
bit (and .T
the W SPIF bit) W
are cleared 1 0 0by
Y
first .T
reading
M
W
the SPI
WStatus . 10 0
Register withM .TW set,
WCOL
W. 1 M W . O W O
WW and.1then .CO .TW WWRegister. 0Y.C M.TW WW .100Y.C M.TW
00Y accessing the SPI Data . 1 0 W O
W OM W O
WW .100Y.C M.TW
O Reserved Bits WW O W O
W 5:1 – Res:
• Bit
These W bits are reserved W.1
bits in the ATmega8U2/16U2/32U2 OM and will always Wread as zero.O
WW .100Y.C M.TW
O
WW .CODouble W W W Y .CO .TW W WW 00Y.CO .TW
•WBit 0 –1SPI2X: Y SPI Speed W Bit 0
W . 0 0
O M. T 0
W . C W W 0 .T
When
W this.1bit 00is Y written .logic
M TW one the W SPI speed
.100(SCK O Frequency)
M.T will be doubled
W .10when theMSPI
O
W O W C
Y. the minimum W .C
Ytwo CPU.TW
WW .100Y.C M.TW
is in Master mode (see Table 17-5). This WWmeans that
.100 theOSPI
W SCK W
M.Tis only guaranteed
period will0be
.1 0 M
clock periods.
W W When .C O
the SPI is configured W as W Slave, Y .C W W W W to work0 CO
Y.at fosc/4 TW
W
or lower. W.10 0 Y .T W W 0 0
W.1 Y.COM W
.T
W. 1 0 M.
W .C OM W W W 0 Y.CO
W 00Y the .TW W 00
W.1 Yis.Calso
.T
OM used for program .10
The SPI W W.1 Yon
interface .C OM ATmega8U2/16U2/32U2
W W W W W Wmemory and
W downloading 00 M.T
W 00 .T
EEPROM W.1 Y.CorOuploading. See page 259
W W.1 for serialY .C OM programming and verification.
W
W W
W
W .100 O M.T
W
W .100 O M.T
WW .100Y. C
WW .100Y.C M.TW
W O W
WW .100Y.C M.TW WW
W O
WW .100Y.C M.TW
W O
WW .100Y.C 146
W W
7799D–AVR–11/10 W
.C OM
00Y .TW
W W.1 Y.COM W
W 00 .T
17.5.3 SPDR – SPI Data Register W W.1 Y.COM W
.TW W
5W.
100 4 OM.T3
Bit OM 7 6 2 1 0
00Y
0x2E.1(0x4E)
.C
.
MSBT W – W – .100Y–.C M.–TW
W
– – LSB SPDR
W W .C OM W W Y .CO R.TW R
Y W W .10 0
W .100 .T
Read/Write R/W R R R R R/W
WValue C OM XWW X Y.C
OMX
.T W W WInitial
1 00 Y . X
M .T W X
W . 1 0 0 M .TW X X X Undefined
M . O W O
.CO .TW The WW SPI Data .C
00Y Register .Tis WWregister
Wa read/write Y.C for data
100used O .TW transfer between the Register File
.100Y M
W . 1
WSPI Shift O M W .
.C
M
W O andW the .C Register. Writing toWtheW register 0Yinitiates .data
TW transmission. Reading the regis-
WW .100Y.C M.TW W
ter causes . 1the M .TW
00YShift Register Receive buffer W .
to10be O
read. M
W O
W
WW .100Y.C M.TW
O
W O W O
W
WW .100Y.C M.TW
O
W O W O
W
WW .100Y.C M.TW
O
W O W O
W
WW .100Y.C M.TW
O
W O W O
W
WW .100Y.C M.TW
O
W O W O
W
WW .100Y.C M.TW
O
W O W O
W
WW .100Y.C M.TW
O
W O W O
W
WW .100Y.C M.TW
O
W O W O
W
WW .100Y.C M.TW
O
W O W O
W
WW .100Y.C M.TW
O
W O W O
W
WW .100Y.C M.TW
O
W O W O
W
WW .100Y.C M.TW
O
W O W O
W
WW .100Y.C M.TW
O
W O W O
W O
W O W O
W
WW .100Y.C M.TW
O
W O W O
W
WW .100Y.C M.TW
O
W O W O
W
WW .100Y.C M.TW
O
W O W O
W
WW .100Y.C M.TW
O
W O W O
W
WW .100Y.C M.TW
O
W W .C O
Y W
W
.C W
WW .100Y M .TW W
W . 100 O M .T W
W .100 OM
.T
WW .100Y M .TW W
W .100 O M .T W .10 O M.T
W O WW .100Y .C
W
W O W O W W .C O
Y
M.T
W
W O W O W W .C O
Y
M.T
W
W O W O W W .C O
Y
M.T
W
W O W O W W .C O
Y .TW
W O W C O W W .C OM
W W .100
Y .TW
W O W C O W W .C OM
W W .100
Y .TW
W O W C O W W .C OM
W W .100
Y
W O W C O W W
W W
W O W C O
W
W O W CO
W O W
WW .100Y.C M.TW WW
W O
WW .100Y.C M.TW
W O
WW .100Y.C 147
W W
7799D–AVR–11/10 W
.C OM
00Y .TW
W W.1 Y.COM W
W 00 .T
18. USART W W.1 Y.COM W
.TW W 00
W.1 Y.COM W
.T
.C OM W
Y W W 00 .T
WW .C W 00
00Y Operation
• Full.1Duplex M.T (IndependentWSerial
W
W.1 Receive OandM.TTransmit Registers)
W C O .C
.TW W• WAsynchronous
1 00Y
. .TW
or Synchronous
M
W
Operation . 100
Y
M .TW
M . O W O
.CO .TW WW control
• Flow .C
00Y CTS/RTS .TWsignals hardwareWW management 100
Y.C .TW
.100Y M
W . 1 O M
W or Slave Clocked SynchronousWOperation W . O M
W O
WW .100Y.C M.TW
• Master Y.C .TW
WW .100Y.C M.TW •
W
W . 100 O M
High W
Resolution O
Baud Rate Generator
W
WW .100Y.C M.TW
O
WW .1Serial .C
00Y Frames W
.Twith WW .100Y.C M.TW
• Supports W O M 5, 6, 7, 8, or 9 W Data Bits and O 1 or 2 Stop Bits
W
WW .100Y.C M.TW
O
WW
• Odd or Even 0 0 Y.C Generation
Parity .T W and Parity WWCheck . 1 0 0Y.C Mby
Supported .TW Hardware
W . 1 O M W O
W W .C O • W Y .C W W W 0 Y .C .T W
W 00 Y .TW Data
W OverRun
. 10Detection
0 M .T .1 0 M
.1 M W O W O
W
WW .100Y.C M.TW
O • Framing
WWError.1Detection00Y
W O M W O
W O • Noise Filtering
W Includes
Y.C False Start Bit Detection
WW and Y.C Low.TPass
0Digital W Filter
WW .100Y.C M.TW • Three W Separate . 1 0 0
Interrupts M
on .TTX
W
Complete, TX W
Data . 10
Register O M and RX Complete
Empty
W O C
W O
WW .100Y.C M.TW• Multi-processor WW .Communication Y.C .TW WW .100Y. M.T
W
W 100 O M Mode W C O
W O
WW Asynchronous Y.C W Y. W
WW .100Y.C M.TW • Double Speed
. 100 M .TW
Communication WMode
W .100 O M.T
W O C
W
WW .100Y.C M.TW
O
W
W O W CO
W
18.2WWOverview .CO .TW WW .100Y.C M.TW WW .100Y. M.T
W
. 1 00Y M W O W C O
W O The Universal Synchronous
WW .100Y.C and Asynchronous WW Receiver
serial Y. and Transmitter
W (USART) is a
highly flexible serial W
communication O device. C
W
WW .100Y.C M.TW
O
W
OA simplified block diagram W O W .C O
W
WW .1of the .CUSART TransmitterWisWshown0in YFigure 18-1Won page 149. CPU
WW .100Y.C M.TW 00Y M .TW W .1 0 O M.T
accessible I/O Registers W and I/O O
pins are shown in bold. C
W
WW .100Y.C M.TW
O
W
W O W CO
W
WW .100Y.C M.TW
O
W
W O W C O
W
WW .100Y.C M.TW
O
W
W O W C O
W
WW .100Y.C M.TW
O
W
O W O W .C O
W
W
O W O W .C O
W
W
O W O W .C O
W
W
O W O W .C O
W
W
O W O W .C O
W
W
O W O W .C O
W
W
O W O W .C O
W
W
W O W O W W .C O
Y
M.T
W
W O W O W W .C O
Y
M.T
W
W O W O W W .C O
Y
M.T
W
W O W O W W .C O
Y .TW
W O W C O W W .C OM
W W .100
Y .TW
W O W C O W W .C OM
W W .100
Y .TW
W O W C O W W .C OM
W W .100
Y
W O W C O W W
W W
W O W C O
W
W O W C O
W O W
WW .100Y.C M.TW WW
W O
WW .100Y.C M.TW
W O
WW .100Y.C 148
W W
7799D–AVR–11/10 W
.C OM
00Y .TW
W W.1 Y.COM W
W 00 .T
Figure 18-1. USART Block Diagram W W.1(1) Y.COM W
.TW W 00
W.1 Y.COM W
.T
.C OM W
Y W W 00 .T
W .100 O M.T W W.1 Y.COM W Clock Generator
WW .100Y .C T W W 0 0 .T
. . 1 M
W OM W
UBRR[H:L] O
.T W WW .100Y.C M.TW WW .100Y.C MOSC .TW
M W O W O
W Y.C .TW
.100Y M
BAUD W RATE GENERATOR
W . 100 O M
W O
W O
W O W O LOGIC
W O
SYNC
WW .100Y.C M.TW
PIN
XCK
CONTROL
W O W O
W
WW .100Y.C M.TW
O
WW 00Y.CO .TW
Transmitter
W C O W W .C O
W Y. W W 0 Y T W W
W .100 M.T .10 M. W.1 Y.COM W CONTROL
TX
UDR (Transmit)
W O W W .C O W
WW .100Y.C M.TW W .100
Y
M.T
W W 00 .T
PARITY
W.1 GENERATOR OM
DATA BUS
W O W W .C O W Y .C W PIN
WW .100Y.C M.TW W . 100
Y
M .T W SHIFT REGISTER
TRANSMIT W
W .100 O M.T CONTROL TxD
WW .100Y. M.T
W W .100
Y .TW W 00
W.1 Y.COM WReceiver
.T
W CO W W .C OM W
WW .100Y. M.T
W W .100
Y .TW W 00
.1CLOCK .T RX
OM CONTROL
W CO W W .C OM W WRECOVERY Y .C W
WW .100Y. M .TW W . 100
Y
M .TW W
W .100 O M.T
O W O DATA 0Y.
C
W
WW .100Y.C M.TW WW .100Y.C RECEIVE W REGISTER WW RECOVERY
.TSHIFT .10
PINW
.T
MCONTROL RxD
W O W O M W W .C O
C W .C Y W
WW .100Y. M.T
W W .100
Y .TW W 00
W.1 Y.COM W
.T
W C O W W .C OM W PARITY
WW .100Y. Y .TW W CHECKER.100 .T

UDR (Receive)
W W .100
W O M.T W W .C OM W W Y .C OM
W
WW .100Y. C .TW
M .TW W
W . 100
Y
O M
W
W .100 O M.T
W O WW .100Y. C
W
W O W C O
W
WW .100Y.C M.TW
O
WW .100Y.C M.TW
UCSRA UCSRB
WW .100Y. UCSRC
M.T
W
W O W C O
W
WW .100Y.C M.TW
O
W
W O W C O
W
WW .100Y.C M.TW
O
W
O W O W .C O
W
WW .100Note:Y.C 1. .TSee W Figure 1-1 Won W Y.C
00Table .T W WW .100Y M.T
W
M page
W .12, O M
12-9 on page 79 and for USART W pin C O
placement.
W O W Y.C WW .10of0Ythe USART . W
WW .10The 0Y.C dashed M .T W in theW
boxes block W 100 separate
diagram
. M .TW the three main parts W O M.T (listed from
O .C
W
WW .the .COClock .TW
W Y.C Receiver. .TW ControlWRegisters
W Y
.100are shared
W
M.Tby all units.
1 00Y top):
M
Generator,W Transmitter
W .100 and O M W C O
W O
.C Generation W .C Wexternal Y . .TWused by
WW The 1 00Y
Clock
M .TW logicWconsists
. 100
ofYsynchronization
M .TW logicW for
W .100 clockOM input
. O W O .C
Wsynchronous
WW only 0Y.C M.TW
slave operation, and
WW the Y.C rate generator.
baud
.TW
TheWW XCKn (Transfer 0Y
.1a0single
Clock) W pin is
M.Tbuffer, a
. 1 0used by synchronous transfer W . 100 TheOM
mode. Transmitter consists Wof C O
write
W O .C WW .100Y . .TW
WW serial 0Y.C Register,
0Shift .TWParity Generator WW .1and 00YControl M TW for handling
.logic different serial Mframe for-
C buffer
.write W Y .C W W 0 Y T W
WWmats..1The 0 0 Y
M. T W allows a W continuous .1 0 0 transfer M .
ofT data without any 1
delay
W.
0 between M .
frames.
WWReceiver .CO WWof the .CO module Wclock CO
Y.data
WThe 0 0 Y is the .Tmost
W complex W part 1 0 0 YUSART
M . T W due toW its . 1 and
0 0 M .TW
recovery
. 1 O M
WThe recovery units are used for W . O W W .C O
units.
WW .100Y.C M.TW WWasynchronous Y.C data W reception. W In addition00to Y the recovery
M.T
W
units,W the Receiver O includes a Parity W .100 Control
Checker, O M.Tlogic, a Shift Register W W .1
and .C
a O
two level
WW buffer Y.C W WW .100Y.C M.TW W 00Y
.1Transmitter, .TW
receive W .100 (UDRn). O M.TThe Receiver supports W the C same O frame formats asWthe W .C OM and
WW .C W WW Parity Y. W W .100
Y .TW
can detect.1Frame
W
00Y Error,
O M.TData OverRun and W .100 Errors. O M.T W W .C OM
WW .100Y. C Y .TW
WW .100Y.C M.TW M.T
W W
W .100 OM
W O W C O W . C
18.3 Clock Generation WW Y.C W WW .100Y. M.T
W W .100
Y .TW
W .100 O M.T W .C O W W .C
Y The
OM
The Clock WW Generation Y.C logic.Tgenerates W WWbase.1clock
the 00Y for the M.T
W
Transmitter Wand Receiver. .100
W . 100 O M W C O W W
USARTn W supports four Y.C modes of clock operation:WW .1Normal . asynchronous, W Double
W Speed asyn-
W .100synchronous
W
M.T and Slave synchronous 00Y M.T The UMSELn bit in USART
chronous, Master W O W .C O
mode.
W Y.C W WW .1between 00Y M.T
W
Control W and Status W .100Register O M.CT (UCSRnC) selects W W .C O asynchronous and synchronous
operation.WDouble W 0
SpeedY .C (asynchronous
.T W W
mode only) 0 0
is Y controlled by the U2Xn found in the
W .10
.C OM W W.1
UCSRnA Register. W W 00Y using synchronous
When .TW W
mode (UMSELn = 1), the Data Direction Register
W W.1 Y.COM W
W 00 .T
W W.1 Y.COM
W 00
W W.1 149
7799D–AVR–11/10 W
.C OM
00Y .TW
W W.1 Y.COM W
W 00 .T
for the XCKn pin (DDR_XCKn) W W.1 whether
controls .C OMthe clock source is internal (Master mode) or
external (Slave .TW The XCKn
mode).
W pin .is 10only0Y active M TW using synchronous mode.
.when
O M W O
0Y.C M.TW
018-2 WW .100Y.C M.TW
Figure
W . 1 shows
O a block diagram ofWthe clock generation O logic.
O W O
W WW 18-2.
WFigure 0 0 Y.CClock.T W
Generation WW Block
Logic, 1 0 Y.C
0Diagram .TW
M .T . 1 O M W . O M
W
.CO .TW WW .100Y.C M.TWUBRR WW .100Y.C M.TW
.100Y M W O W O
WfoscW .100Y.C M.TW
U2X
W O
WW .100Y.C M.TW WW .100Y.C M.TPrescaling W
W O Down-Counter UBRR+1
W /2 O
W O
WW .100Y.C M WW .100Y.C M.TW
/4 /2
WW .100Y.C M.TW .TW W O
0
W O W W .C O W Y .C W 1
WW .100Y.C M.TW W . 1 0 0 Y
OSCM
.T W W
W . 1 0 0
O M .T 0
txclk
WW .100Y.C M.TW
1
W 0 0 Y .T W W . 1 0 0 M .T DDR_XCK
W. 1 OM W O
W
WW .100Y.C M.TW
O
WW .100Y.C Register Sync TW
. EdgeWW .100Y.C M.TW
M W O
WW xcko00Y.CO .TW
Detector
O WW .100Y.C M.TW
xcki 0
W
WW .100Y.C M.TW
UMSEL
WXCK . 1 M 1
Pin
W O W C O
W
WW .100Y.C M.TW
O
W
W O W C O
W O
WW .100Y.C M.TW UCPOL W
W Y. W
WW .100Y.C M.TW .100 M.T
DDR_XCK 1
rxclk
W O W O W W . C O 0
W Y.C W W W 0 Y .C T W W 0 0Y .T W
W 00
W.1 Y.COM W
.T .10 M. .1
WW 00Y.CO .TW
M
W W WW 00Y.CO .TW W
W 00 .T .1 M .1 M
W W.1 Y.COM Signal W
description: WW 00Y.CO .TW W WW 00Y.CO .TW
W 00 .T W .1 M .1 M
W W.1 Y.COM txclk W Transmitter WWclock Y .CO Signal).
(Internal W W WW 00Y.CO .TW
W 00 .T W 0 0 .T .1 M
W rxclk Receiver W base clock
0 0 (Internal .TSignal). W .1
W 00 xcki .T Input from XCKWpin W 0
.10(internal M .T
Signal). Used for synchronous .1 slaveM operation.
W 00 xcko.T Clock output to XCK W 0
.10pin (Internal M Signal). Used for .1
synchronous Mmaster operation.
W 00 W .1
W.1 Y.CO
fOSC M.TXTAL pin frequency .1(System Clock).
WW 00Y.CO .TW
M WW 00Y.CO .TW
M
W W W W .1
W 00 .T .1 M M
18.3.1 InternalW W.1 Generation
Clock .C OM – The Baud Rate
W WWGenerator Y .CO .TW W WW 00Y.CO .TW
W 00 Y .T W 0 0 .1
W.1 Internal OM W.1 for Y M WW OM
.C clock W generationW isW used the.CO asynchronous W andWthe synchronous0Y.C master W modes of
W W
. 1 0 Y
0operation. M .T description in this W . 10 0
O M . T
W .1 0
O M.T
W O The section refers to Figure 18-2.
WW .100Y .C
W
O W O W .C O
W The USART Baud Rate Register
WW .100Y.C M.TW WW (UBRRn) Y.C and the .TW down-counter WWconnected .100
Y to it function
M.T
W as a
programmable prescaler or baud W . 100generator.
rate O M The down-counter, W running C O
at system clock
W O WW .100Y .
WW (f .1), 0
C
0isY.loaded .T W WWvalue.1each 0 0Y.C M.TW M .TW
Wosc Y.COM W with the UBRRn time the counter has counted
WW 00Y.C down to O zero or when
WW
W .CO .TW
0Ygenerated W .TW This
WW the .UBRRLn 1 00 M .T
Register is written. A clock .1 0 is M each time the .1 reaches
counter
W O Mzero.
W O W O W Transmitter .C
WWclock.1is00the Y.Cbaud rate .TW generator
W output Y.C fosc/(UBRRn+1)).
.TW WThe .100
Y
M.T the
W
M
Wclock
W . 100 (= O M W C O
divides
WW rate O .C W . W
Wbaud 00Y
.C
generator clock output W
.TW
byW 2, 8 or 016
. 1 0
Ydepending
M .TW on mode. The W baud.1rate 00Ygenerator M.T
out-
W WW 00Y.C
put is used directly by the
W Receiver’s clock
WW .100Y.C M.TW
and data recovery units. However,
W the
.10the0Y recovery units
.TW
use aWstate .1 machine O M.Tthat uses 2, 8 or W16 states.Cdepending O on mode W setWby Y state
.C OMof the
W
WW .1U2Xn
UMSELn,
.C
00Y andMDDR_XCKn .TW WW .100Y
bits. M.T
W W .100 M.T
W O W O W W .C O
Y .TW
W O W C O W W .C OM
W W .100
Y .TW
W O W C O W W .C OM
W W .100
Y .TW
W O W C O W W .C OM
W W .100
Y
W O W C O W W
W W
W O W C O
W
W O W C O
W O W
WW .100Y.C M.TW WW
W O
WW .100Y.C M.TW
W O
WW .100Y.C 150
W W
7799D–AVR–11/10 W
.C OM
00Y .TW
W W.1 Y.COM W
Table 18-1 contains equations for
W
W .100
calculating the
.T
OMbaud rate (in bits per second) and for calculat-
W .C
ing the UBRRn M .TW for eachWmodeWof.1operation
value 00Y M .TWan internally generated clock source.
using
O
. 1 00Y M
Table 18-1. Equations for W O
Calculating Baud Rate Register WW 00Y.CO .TW
WSetting
WW .100Y.C M.TW
W C O W W.1 Y (1).CO
M
Operating Mode
.TW W W 00 Y .
Equation for
.T W Calculating W Baud Rate
. 1 0 0 M TW
.Equation for Calculating UBRR Value
M W . 1 O M W O
.CO .TW WW .100Y.C M.TW WW .100Y.C M.TW UBRRn = ----------------------- f OSC
.100Y M O W O -–1
W W Y.C O
W W WW 00Y.C W W W 0 0 Y .C .T W 16BAUD
W 00
W.1 Y.COM W
.T .1 M.T .1
WW 00Y.CO .TW
M
W W WW 00Y.CO .TW f W
W .100
Asynchronous .T
Normal mode .1 M .1 M
W W(U2Xn C
=Y.0) OM WW 00Y BAUD W
OSC
.CO = .T-----------------------------------------
W W-W 0 Y .CO .TW
W 00
W.1 Y.COM W
.TW W .1 M 16  UBRRn + 1 WW.1 0
OM
W W
.1 00 M .T W
W . 1 O M W .1 0
O M.T
W
WW .100Y.C M.TW
O
W O W O
W
WW .100Y.C M.TW
O
W O W O f OSC
W
WW .100Y.C M.TW
O
WW .100Y.C M.TW WW .100Y.C UBRRn M .TW = -------------------- –1
W O W C O W W .C O 8BAUD
C W . .TW Y W
WW .100Y. .TW W .100
Y W 00
W.1 Y.COM W
.T
W
Asynchronous Double
C O M
Speed W W .C OM f W
WW(U2Xn.10=01)Y. W Y W W 00 .T
W BAUD .100 = --------------------------------------
OSC
mode W O M.T W 8 O M.T + 1 -
UBRRn W W.1 Y.COM W
C W .C
WW .100Y. M.T
W W .100
Y .TW W 00
W.1 Y.COM W
.T
W C O W W . C OM W
WW .100Y. M.T
W W .100
Y .TW W 00
W.1 Y.COM W
.T
W CO W W .C OM W
WW .100Y. M.T
W W .100
Y .TW W 00
W.1 Y.COM fW
.T
W C O W W .C OM W
WW .100Y. M.T
W W .100
Y .TW W 00
W.1 UBRRn
.T OSC – 1
O=M --------------------
W CO W W .C OM W Y.C 2BAUD W
WW .100Y. M .TW W . 100
Y
M .TW W
W .100 O M.T
W O C
W
WW .100Y.C M.TW
O
WW .100Y .C
f OSCOM.T
W WW .100Y. M.T
W
W W C O
Synchronous Master W mode
WW .100Y.C M.TW
O BAUD Y.C + 1 - .TW
WW= -------------------------------------- WW .100Y. M.T
W
W 100
2 .UBRRn
O M W C O
W
WW .100Y.C M.TW
O
W
O W O W .C O
W
W
O W O W .C O
W
W
W Note: O1. The baud rate is defined W O W
W (bps) .C O
WW to .Ctransfer Y W
WW .100Y.C M.TW
be Y the
. 100 M .Trate
W in bit perWsecond
W .100 O M.T
O W O .C
W
WW .100Y.C M.TW
BAUD Baud rate
WW (in .bits per
Y .C second, .TW
bps) WW .100Y M.T
W
W 100 O M W C O
W .C O W Y.C frequency WW .100Y . W
WW .100fYOSC M .TW System WOscillator . 100
clock
M .TW W O M.T
O W O . C
W
WW .10UBRRn 0Y.C M.TW Contents
Wthe UBRRHn Y.C and.TUBRRLn W WW (0-4095).100
Y
M.T
W
Wof
W . 100 O M Registers,
W C O
W O Y.C WW .100Y . TW
WWSome.1examples
00Y
.C
of.T W
UBRRn values WW for W some . 100system M .TWfrequencies
clock areW found in Table M.18-9 on
O M O W .C O
WW 172.
Wpage 0 Y .C T W W W 0 0 Y .C .T W W 1 0 0 Y .T W
W.1
0
OM
. W.1 OM W. OM
W O W O
18.3.2 Double Speed Operation W (U2Xn)
WW .100Y.C M.TW
O
WW this O has
The transfer
WW 00rate Y .Ccan
O be doubled by setting
W W WW the 0 Y .CO bit .in
U2Xn
T WUCSRnA. Setting
W 0 0Ybit.Conly
.TW
W
effect forWthe .1 asynchronous M. T operation. Set W this 0
.1 bit to zero Mwhen using synchronous W 1
. operation. OM
O C O W .C
WW .100Y.C M.TW WW .100Y. W W
M.T from 16 to 8, effectively .100
Y .TW
Setting this W bit will.C reduce
O the divisor of the Wbaud rate C O
divider W W C OM
doubling
.
WW .100Y. W Y W
WW rate
the transfer
Y
.100 for asynchronousM.T
W
communication. W Note O M.T
however
W
that the Receiver W .100will in O M.T
this
W O . C W . C
0Y clock
WW use.1half .C
00Ythe number W WW .100Yfrom .TW8) for dataW .10and
case only
W O M.T of samples (reduced W .C O16Mto sampling
W W
recovery, WW and therefore Y.C a more Waccurate baud WW rate.1setting 00Y and TW clockW
M.system are required when
W .100 O M.T W W .C O
this mode is
W used. For .Cthe Transmitter, there are no downsides.
Y W
W 00Y .TW W 00
W.1 Y.COM
.T
W W.1 Y.COM W W
W 00 .T W 00
W.1 Y.COM W W W.1
W W 00 .T W
W W.1 Y.COM W
W 00 .T
W W.1 Y.COM
W 00
W W.1 151
7799D–AVR–11/10 W
.C OM
00Y .TW
W W.1 Y.COM W
W 00 .T
18.3.3 External Clock W W.1 Y.COM W
.TW W 00
W.1 Y.Cslave
.T
OM modes of operation. The description in this
External clocking
C OM is used by the synchronous W
section 1
Y
00refers
. .TW 18-2 forWdetails.
toMFigure . 100 M .TW
W . O W O
WW Y.C
00clock W
.Tfrom WW .100Y.C M.TW
External . 1 M
input the XCKn pinWis sampled
WW of Y.C
O
W The output WWfrom.1the .COby a.T
0Ysynchronization
synchronization register to minimize the
W
.T W Wchance . 1 0 0 meta-stability.
M .T 0 M register must then pass through
O M W C O W
W by the .C O
Y.C W an
W Wedge Y .
detector
0 before W it can be Wused 0 0 Y Transmitter .T W and Receiver. This process intro-
W .100 O M.T W .10 O M.T W W .1
. C OM
WW .100Y
duces a two CPU .C clock period delay and therefore Y the maximum W external XCKn clock frequency
W . 100 O M .T
O
Wby the following equation:
W
WW .100Y.C M.TW
O is limited
W O W O
W O
WW .100Y.C M.TW WW .10f0OSC Y.C .TW
WW .100Y.C M.TW f W  -------------
- O M
W O
W O
XCK
WW .100Y.C M.TW W O
W O
W
WW .100Y.C M.TW
O
Note that fW Wdepends.C onOthe stability of the system W clock source. O It is therefore recommended to
W O
WW .100Y.C M.TW add some W osc 0 0 Y .T W WW .100Y.C M.TW
margin 1
W. to avoidOpossible M loss of data due W to frequency O variations.
W
WW .100Y.C M.TW
O
W O W O
18.3.4 W
WW .Synchronous
0 Y.C
O
.TClock
W OperationWW .100Y.C M.TW WW .100Y.C M.TW
0 .CO .Tused
W1 OM When synchronous W .CO .(UMSELn WW
W
00Ypin willMbe W as either clock input
WW .100Y.C M.TW WW .mode 1 00Y is used M TW = 1), the XCKn
. 1
O (Slave) or clockWoutput (Master). W O TheW dependencyW W
between0Y CO
. clock .edges
the
W .C W and data sampling
WW .100Y.C M.or TW data change
W
is the . 00Y TheMbasic
1same. .T principleWis that W 10 inputO(on
.data M TRxDn) is sampled at the
W O C
W O
WW .100Y.C Mopposite .TW XCKnWclockWedge
W Y.C .TW WW .100Yis. changed. M.T
W
. 100 of theOedge M the data output (TxDn) W C O
W
WW .100Y.C M.TW
O
W
W O W C O
W O
WW .100Mode Y.C XCKn Timing. WW Y. W
WW .100Y.C Figure M .TW
18-3. Synchronous
M .TW W .100 O M.T
W O C
W
WW .100Y.C M.TW
O
W
W O W C O
O WW .100Y.
W UCPOL = 1 XCK
W
W O W C O
W
WW .100Y.C M.TW
O
WW Y.C .TW WW .100Y. M.T
W
RxD / TxD W . 100 O M W C O
W
WW .100Y.C M.TW
O
W
O W O W .C O
W
WW .100Y.C M.TW WW .100Y.C M.TW WW .100YSample
M.T
W
O W O W .C O
W
WW .100Y.C UCPOL .TW =0 XCK WW .100Y.C M.TW WW .100Y M.T
W
O M W O W .C O
W
W
O W O W .C O
W
WW .100Y.C M.TW RxD / TxDW
W Y.C .TW WW .100Y M.T
W
W . 100 O M W C O
W O W .
WW .100Y.C M.TW WW .100Y.C M.TW WSample .100
Y
M.T
W
O W O W .C O
W
W
O W O W .C O
W
WWThe UCPOLn .C .TW selects
W XCKn Y.C .TWis used for WW .100
Y and which
M.T
W is
.1 00Y bitMUCRSC Wwhich
W . 100 clock O M edge data sampling
W C O
WW for0data O W shows, .C UCPOLn W .
0Ybe changed W
Wused . 1 0Y.Cchange. M .TW As Figure W 18-3
. 100
Ywhen
M .TW is zeroWthe data W .10will O M.T at
O
WXCKn edge and sampled at falling
rising W O
.C If UCPOLn W .C
WW .100Y.C M.TW WW XCKn 00Y
.1XCKn
edge.
M.T
W is set,
W the data .100
will
Y be changed
M.T
W
at falling
W XCKnCedge O and sampled at rising W edge.O W W .C O
WW .100Y. W WW .100Y.C M.TW W .100
Y
M.T
W
18.4 Frame Formats W W.100Y OM.TW
W .C WW .100Y.C M.TW W .100
Y .TW
W C O W W .C OM
Y.C WW of.1data . W Y W
WW frame
A serial .100is defined Mto .TW be one character 00Y bits with M.TsynchronizationW
W bits .(start
W 100 andOstop M.T
W O W C O .C
bits),Wand W optionally Y.Ca parity W
bit for error W
Wchecking. Y.
.100The USART
W W
M.T accepts all 30Wcombinations .100
Y of.TW
W .100 O M.T W C O W .C OM
the following
WW as Y.Cframe .formats:
valid W WW .100Y. M.T
W W .100
Y
W .100 O MT W C O W W
• 1 startWW bit Y.C W WW .100Y. M.T
W W
W .100 O M.T W C O
• 5, 6, W 7, W 8, or 9 data Y.C bits W WW .100Y. M.T
W
W .100 O M.T W C O
• no, even WW or odd parity Y.Cbit .TW WW .100Y.
W .100 OM W
• 1 or 2 stop WWbits .100Y.C M.TW WW
W O
WW .100Y.C M.TW
W O
WW .100Y.C 152
W W
7799D–AVR–11/10 W
.C OM
00Y .TW
W W.1 Y.COM W
W 00 M.T significant data bit. Then the next data bits,
A frame starts with the start bit followed W W.1 byYthe .C Oleast
W
up to a total O ofM .TWare succeeding,
nine,
W
W .100 withOthe
ending M.Tmost significant bit. If enabled, the parity bit
is inserted .C
00Y afterM .TW
the data bits, before WW the.10stop 0Y.Cbits. M When.TW a complete frame is transmitted, it can
W . 1 O W O
WWbe directly .C
00Yfollowed byWa new frame,
.T WWor the . 0Y.C M.TW line can be set to an idle (high) state.
10communication
. 1 O M W O
W WW 18-4
WFigure 0 0 .C
Yillustrates .T Wthe possible WW combinations
1 0 0Y.C of the .Tframe
W formats. Bits inside brackets are
M .T optional. . 1 O M W . O M
W
.100Y M W O W O
W
WW .100Y.C M.TW
O
WW 18-4.
Figure 0 0 .C
YFrame .T
FormatsW WW .100Y.C M.TW
W. 1 OM
W O WW FRAME
W .CO .TW
W W .C O
W 00 Y .T W .1 M .1 M
W 00 .T W .1 St M .1 M
W W.1 Y.COM W (IDLE)
WW 00Y.CO .TW
0 1 2 3
W
4 W
W [5] [6]00Y[7] .CO[8] .[P] TW
Sp1 [Sp2] (St / IDLE)
W 00 .T W 1 . 1 M
W.1 OM W. OM W O
W O
W O St WW .CO bit,.T
YStart W low. WW .100Y.C M.TW
always
WW .100Y.C M.TW W 1 0 0
W. OM to 8). W O
W
WW .100Y.C M.TW
O (n) WW 0 0 Y.C bits (0
Data .T W WW .100Y.C M.TW
W. 1 M
W O O WW .CO .TW
WW .100Y.C M.TW P WW .10Parity 0Y.C bit.MCan .TWbe odd orW even. .100Y M
W W .C O
W 00 Y .T Sp W .1Stop bit, always M high. .1 M
W 00 .T W .1 M .1 M TxDn). An IDLE line
W.1 Y.COM WIDLE WWNo 0transfers Y.CO on.Tthe W
communication
W WW line 0 .CO or
Y(RxDn W
W W
. 1 00 must
M .T be W
W .1 0
O M W .1 0
O M.T
W O Y.C WW .100Y. C W
WW .100Y.C M.TW WW high. . 100 M .TW M.T
W O W C O
W O
WW .100Y.C TheMframe .TW format W
W .C
00YUSART TW
.is WW .100Y. W
M.Tand USBSn bits in
used W by.1the O M set by the UCSZn2:0, W UPMn1:0
C O
W O
WW The.1Receiver .C and.TTransmitter W Y. W
WW .100Y.CUCSRnB M .TWand UCSRnC. 00Y M
W W
use the .same
W 100 setting.
O M.T Note that changing
W O C
W
WW .100Y.the COsetting
.TWof any of these WW bits.10will C
0Y.corrupt .TW
all WW .100Y.for both
ongoing communication W
M.Tthe Receiver and
M W O M W C O
W
WW .100Y.C M.TW
O
Transmitter. WW .100Y.C M.TW WW .100Y. M.T
W
O W O W .C O
W
WW .100The Y.CUSART .TW Character W SiZeW (UCSZn2:0) Y.C bits.Tselect W the number WW of 0Y bits M
.10data TWframe. The
in .the
M W .100 O M W C O
W USART O Parity mode (UPMn1:0) Y.C and ofWparity bit. . W between
WW .100Y.C M.TW WW bits . 0enable
10USART M .TW
set the typeW 0YThe selection
.10bit. M.T
one or two stop bits is done by W the O Stop Bit Select (USBSn)W The
.C O Receiver ignores
W
WW .the .CO .TW W 0Y.Cwill M TW only be WW .100Y .TW
1 00Y second stop bit. An FE
W(Frame .1 0
Error) .
therefore detected in the O M
cases where the
W W .C OM
W Y
first00stop bit is .zero. T W .1 M . 1 M
W 0 0 .T W .1 M . 1 M
18.4.1 W.1 Y.COM W
Parity Bit Calculation
W 0 W 1
0
W.1parity .bit M.T WW
1
an. exclusive-or
M
.CO of.Tall WW
. OM
Y.C is used,
The
WWresult.10of0Y COis calculated
T W
by doing
W 0 0 Y W the data W bits. If odd 0parity
1 0 .TWthe
M
the exclusive . .
or is inverted.WThe relation 1 M
O between the parity W . O M
bit and data bits is as
WW 00Y.CO .TW
Wfollows:: WW .100Y.C M.TW WW .100Y.C M.TW
W. 1 OM W O W O
P even = d n – 1WW  dY  d 0  0 WWW O
W O 3 .
CO d 2  d 1W Y.C .TW
WW .100Y.C M.TW W
P odd = d n – 1  W 0 0
.1 d 3 .CdO
.T
 d1  d0  1
M W. 1 0 0
OM
W O W .C
2
M.T
W W .100
Y .TW
W O W C O W W .C OM
WW Peven.100Y
.C W WW .100Y. M.T
W W .100
Y .TW
W O M.T bit using evenWparity
Parity W C O W W . C OM
WPW Y.C W Y. W W .100
Y .TW
odd
W .100 M.T bit using odd parity
Parity
O
W
WW .100Y. C Y
WW .100Y.C M.TW M.T
W W
W .100
dn WW O
Data bit n of the character W C O W
Y.C W WW .100Y. M.T
W W
W
W .100 O M.T W
W data 0bit C O
. first .stop
If used, theW is.C
W parity.1bit 00Y
located between
M.T
W theW last
.1 0
Yand
MT
W bit of a serial frame.
W O W C O
W O W
WW .100Y.C M.TW WW
W O
WW .100Y.C M.TW
W O
WW .100Y.C 153
W W
7799D–AVR–11/10 W
.C OM
00Y .TW
W W.1 Y.COM W
W 00 .T
18.5 USART Initialization W W.1 Y.COM W
M.to TW W 00 .T
The USART
.C O has be initialized before W W.1any Y .C OM
communication
W can take place. The initialization pro-
0 0 Y .T W W . 1 0 0 M . Tsetting
W W.1 Y.COM W
cess normally consists of setting the
WW 00Y.CO .TW
baud rate, frame format and enabling the
W Transmitter00 or theMReceiver .T W
depending on .1 the usage.
W.1 Interrupt C O WW (and OMFor interrupt driven USART operation, the
.Cinterrupts
.T W W W
Global
1 00 Y . Flag
M .T W
should be Wcleared
. 1 0 0 Y
M .TWglobally disabled) when doing the
M . O W O
.CO .TW WW 00Y.C
initialization.
.TW WW .100Y.C M.TW
.100Y M
W
W . 1 O M W .CO or frame
W O C
aY.re-initialization WW baud 0Yrate .TW format, be sure that there are no
WW .100Y.C M.TW WW doing
Before
. 1 0 0 M .T W with changed . 1 0 M
W O W O
W O ongoing
WW transmissions .C during WW
the period the registers Y.C are changed. .TW The TXCn Flag can be used
WW .100Y.C M.TW . 1 00Y M .TW W . 100 O M
to WW 00Y.C
check that the O
Transmitter has completed all transfers, and the RXC Flag can be used to
W
WW .100Y.C M.TW
O
check thatWthere . 1 are O noMunread data in the W
W O .C W receive buffer.
O Note that the TXCn Flag must be
0Y.C ifMit.T W
WW .100Y.C M.TW cleared WW before.1each 00Y transmission M .T W (beforeWUDRn . 1
is 0written) is used for this purpose.
W O W O
W O
WW .100Y.C M.TW The following WW simple Y.C W WW .100Y.C M.TW
W . 100 USART O M .Tinitialization codeW examples show
O one assembly and one C func-
W O
WW .100Y.C M.TW tion thatW
W
are equal 0 0
in
.C
Yfunctionality. .T W The examples WW assume . 10 0Y.Casynchronous
M.T
W
operation using polling
W . 1 O M W C O
W W .C O Wenabled) Y C a fixed
.and W W W The baud 0 Y . .T W
Y W(no interruptsW 0 .T frame format. 0 rate is given as a function parameter.
W
W .100 OM.T For the assembly W .10
.C OMbaud rate parameter W W.1 Y.COM W
C W code, the .TW is assumed to be stored in the r17:r16
WW .100Y. M .TW W . 1 00Y M
W
W .100 O M.T
W O C
W
WW .100Y.C M.TW
O Registers.
W
W O W C O
W O
WW .100Y.C M.TAssembly W WW Example
Code Y(1).C .TW WW .100Y. M.T
W
W . 100 O M W C O
W O
WW .100Y.C M.TWUSART_Init: WW .100Y.C M.TW WW .100Y. M.T
W
W O W C O
W O
WW .100Y.C M.TW ; Set baud WW rate Y.C .TW WW .100Y. M.T
W
W .100 O M W C O
W
WW .100Y.C M.TW
O out UBRRHn,
WW r17 00Y
W
W . 1 O M W C O
W
WW .100Y.C M.TW
O out UBRRLn,
WW .100Y.C M.TW
r16
WW .100Y. M.T
W
; Enable receiver W and O
transmitter W C O
W O
WW .100Y.C M.Tldi W W Y.C .TW WW .100Y. M.T
W
r16,
W .100
(1<<RXENn)|(1<<TXENn)
W O M W C O
W
WW .100Y.C Mout
O
.TW UCSRnB,r16 WW .100Y.C M.TW WW .100Y. M.T
W
W O W C O
W
WW .100Y.C M
O
; .T SetW frame W W
format:.18data, 00Y
.C
2stop .TWbit WW .100Y. M.T
W
O W O M W .C O
W
WW .100Y.C ldi .TW WW .100Y.C M.TW
r16, (1<<USBSn)|(3<<UCSZn0) WW .100Y M.T
W
O M W O W .C O
W
WW .100Y.C out W
.TUCSRnC,r16 WW .100Y.C M.TW WW .100Y M.T
W
O M W O W .C O
W
WW .100Y.C M.TW
ret WW .100Y.C M.TW WW .100Y M.T
W
O W O W .C O
W
WW .C Code.C Example .TW
(1)
W
1 00Y M W O W .C O
W O Y.C ) .TW WW .100Y W
WW .100void Y.C USART_Init( .TW WW .int
unsigned
100 baudOM M.T
O M W W .C O
W
WW .10{0Y.C M.TW WW .100Y.C M.TW WW .100Y M.T
W
O W O W .C O
W /* Set baud rate */ W
WW .100Y.C M.TW Y.C .TW WW .100Y M.T
W
W
W . 100 O M W C O
W O W .
WW .100Y.C M.TW
UBRRHn .C = (unsigned char)(baud>>8); Y W
WW .1UBRRLn 00Y M .TW W O
W
W .100 O M.T
W O= (unsigned char)baud; W .C
WW ./* Y.C .TW WW .100Y.C*/ M.TW W .100
Y
M.T
W
W 100Enable O Mreceiver and transmitter
W O W W .C O
WW UCSRnB Y.C (1<<RXENn)|(1<<TXENn);
W WW .100Y.C M.TW W .100
Y
M.T
W
W .100 = O M.T W O W W .C O
WW /*.1Set .C .TW WW 2stop Y.C W W .100
Y .TW
W
00Y frameMformat:
O
8data,
W .100bit */ O M.T W W .C OM
Y=.C(1<<USBSn)|(3<<UCSZn0); WW .100Y. C W Y .TW
WWUCSRnC .100 M.T
W
W O M.T
W
W .100 OM
W O C W .C
W}W .100Y.C M.TW WW .100Y. M.T
W W .100
Y .TW
W O W C O W W .C OM
W .C
00Y Examples” W WW 0Y. M.T
W W .100
Y
Note: W 1. See
W .1“Code O M.T on page 6. WW.10 .C O W W
WW .1initialization .C .TW 00YincludeMframe .TW format as W parameters, dis-
More advanced 00Y Mroutines can be W made.1that
W O
W O W Y. C
WW and
able interrupts Y.Con. However,
so W many Wapplications .100 use TW setting of the baud and
a .fixed
W .100 O M.T W C O M
control registers,
WW and Y.Cthese types
for W of applications WW the Y.
initialization code can be placed directly
.10or0 be combined M.T with initialization W 100
.code
in the main routine, W O for other I/O modules.
WW .100Y.C M.TW WW
W O
WW .100Y.C M.TW
W O
WW .100Y.C 154
W W
7799D–AVR–11/10 W
.C OM
00Y .TW
W W.1 Y.COM W
W 00 .T
18.6 Data Transmission – The USART TransmitterW W.1 Y.COM W
W W 0
.10setting .T
The USART M.T
OTransmitter is enabled W Wby .C Othe MTransmit Enable (TXEN) bit in the UCSRnB
0 .C
YWhen the T W Wis enabled, 00Ythe normal .TW
0 . . 1 M
W W.1 Y.COM W
Register. Transmitter
WW 00Y.CO .TW
port operation of the TxDn pin is overrid-
W den by 0 USART
0the W
.Tand given the function as the Transmitter’s serial output. The baud rate,
W.1of operation.C OM W W.1 Y.COM W
W W
mode Y and W frame format W must be 0 0set up once .Tbefore doing any transmissions. If syn-
O M.T
W
W .100 O M.T W W.1on the .C OM pin will be overridden and used as
.C chronous
WW .100Y .C
operation is used, the clock Y XCKn .TW
100Y M .TW M .TW W
W . 100 O M
. transmission
W clock. O
W
WW .100Y.C M.TW
O
W O W O
W
WW 18.6.1 0
O
Y.C Sending
.T WW 5 to.1800Data
WFrames with Y.C Bit .TW WW .100Y.C M.TW
0 OM O
W.1 OM W Y.C is initiated WW
W
0Y.Cbuffer TW the data to be transmitted. The
WW .100Y.C M.TW WW
A data transmission
. 1 0 0 M .T W by loading the transmit
. 1 0 M.with
W O W O
W O CPU W canWload the .C
transmit buffer
W by writing WWto the Y.C I/O .location.
UDRn W The buffered data in the
WW .100Y.C M.TW . 1 00Y M .T W .100 O MT
transmit buffer W
W will O
be moved to the Shift Register C ShiftTRegister
Y.the
W O
WW .100Y.C M.TW frame.W 0Y.C M.TW WW when .if1it00is in idle . W
is ready to send a new
The Shift
W . 10Register Ois loaded with new data W O Mstate (no ongoing transmission) or
W O .C WW frame 0Y .C TW When the Shift Register is
WW .100Y.C M.TW immediately WW after.1the 00Ylast stop .T W
bit of the previous . 1 0 is M .
transmitted.
W OM W O
W O
WW .100Y.C M.TWloaded with WW new data, 0 0 Yit.Cwill transfer
.T W one complete WW frame . 1 0 0Yat.Cthe rate W
M.Tgiven by the Baud Register,
W . 1 O M W C O
W
WW .100Y.C M.TW
O U2Xn bit orWby WXCKn0depending Y.C onWmode of operation. WW .100Y. M.T
W
W . 1 0 O M .T W C O
W O
WW Y.C show WW transmit Y. function W
WW .100Y.C M.TThe W following 100
code .examples M .TW a simple USART
W .100 O M.T based on polling of the
W O W O W .C
WW .100Y.C M.Data TW RegisterWEmpty .(UDREn)
W Y.C Flag. .TW When using Wframes 00Y less than
.1with
W
M.T eight bits, the most sig-
W 100 O M W C O
W O nificant bits written Y.C are ignored. W has to. be initialized
WW .100Y.C Mcan .TW WWto the .
UDRn
100 M .TW
The W USART
00Y
.1is M.T
W before the function
be used. For the W assembly O code, the data to be W
sent assumed
CO to be stored in Register
W
WW .100Y.C R16
O
OM W O
W
WW .1(1)
WW .100Y.C M.TW 00Y M W O
W O
W
WW .100Y.C M.TW
OAssembly Code Example
W O W O
W
WW .100Y.C M.TW
O USART_Transmit:
W transmitO buffer W O
W O ; Wait for empty
WW .100Y.C Msbis .TW UCSRnA,UDREn WW .100Y.C M.TW WW .100Y.C M.TW
W O W O
W
WW .100Y.C M
O
.TWUSART_Transmit WW .100Y.C M.TW WW .100Y.C M.TW
rjmp W O W O
W O
WW .100Y.C ;MPut .TWdata (r16) WWinto 0Y.C Msends
0buffer, .TW the data WW .100Y.C M.TW
W .1 O W O
W
WW .100Y.C out
O
.T W
UDRn,r16 WW .100Y.C M.TW WW .100Y.C M.TW
OM W O W O
W
WW .100Y.CretM.TW WW .100Y.C M.TW WW .100Y.C M.TW
W W .C O
W (1) WW 00Y.CO .TW W WW 00Y.CO .TW
C Y
Code Example W
W
.C W
WW .100void Y USART_Transmit(
M .TW Wunsigned
W . 100 charOM data .T ) W
W .100 OM
.T
WW .10{0Y M .TW W
W .100 O M .T W .10 O M.T
W O .C WW .100Y .C W
WW .10/* 0Y.C Wait for
.TWempty transmit WW .1buffer 00Y */M.TW M.T
O M
W while ( !( UCSRnA & (1<<UDREn)) W O W W .C O
WW .100Y.C M.TW WW .100Y).C M.TW W .100
Y
M.T
W
W O W O W W .C O
WW .100Y.C M.TW 00Y .TW
;
WW .100Y.C M.TW W
W.1 Y.COM W
W /* Put Cdata O into buffer, W sendsW the .C O */
data W
WW UDRn Y. W Y W W .100 M.T
W .100 = data; O M.T
W
W .100 O M.T W W .C O
WW} .100Y.C M.TW WW .100Y.C M.TW W .100
Y .TW
W O W C O W W .C OM
WW .100Y. Y W
WW .100Y.C M.TW M.T
W W
W .100 O M.T
W O W C O W .C
Note: W1. See “Code .C Examples” W on pageW 6.W Y. W W .100
Y .TW
W
The function W
00Y waits
.1simply O M.Tfor the transmitWbuffer W .100to be O M.T by checking W
empty the W UDREn .C OM
Flag,
0Y. C Y
W
beforeWloading 0Y.CnewMdata
.1it0with .TWto be transmitted. W .1If0the Data M .TW W
Register Empty interrupt W .10is0 utilized,
W O W C O W
WW routine Y.C the.Tdata W into theWbuffer. W Y. W W
the interrupt
W .100 writes O M W .100 O M.T
WW .100Y. C
WW .100Y.C M.TW M.T
W
W O W C O
18.6.2 Sending Frames with 9 Data
WW Bit.100Y.C M.TW WW .100Y.
If 9-bit characters W are used O (UCSZn = 7), the WWbit must be written to the TXB8 bit in UCS-
ninth
WW .100Y.C M.TW W
RnB before the low W byte of the O character is written to UDRn. The following code examples show
WW .100Y.C M.TW
W O
WW .100Y.C 155
W W
7799D–AVR–11/10 W
.C OM
00Y .TW
W W.1 Y.COM W
W 00 .T
a transmit function that handlesW W.1characters.
9-bit
Y .C OMFor the assembly code, the data to be sent is
W
assumed to O .TW in registers
beMstored
W R17:R16.
W .100 O M.T
.C
00Y Code .TW WW .100Y.C M.TW
. 1
Assembly
W O M Example (1)(2) W O
WUSART_Transmit: O W O
OM W ; Wait O empty transmitWbuffer W O
0Y.C M.TW
for
0 Y.C .T W WW sbis 0 0 Y.C .T W W . 1 0
0 W. 1 OM O
W.1 OM UCSRnA,UDREn
Y.C
W
WW .100Y.C M.TW
WW .100Y.C M.TW WW rjmp 1 0 0 M .T W
O W. USART_Transmit
.CO bit.Tfrom W
0Y.C M.TW
O
W
WW .100Y.C M.TW WW ; Copy 0 0 Y9th W r17 to WW TXB8 . 1 0
W. 1 M W O
W O
WWcbi .1UCSRnB,TXB8 .CO .TW WW .100Y.C M.TW
WW .100Y.C M.TW 00Y
WW r17,0 OM W O
W
WW .100Y.C M.TW
O
Wsbrc 0 0 Y.C .T W WW .100Y.C M.TW
. 1 OM W O
W O WWUCSRnB,TXB8 Y.C WW .100Y.C M.TW
WW .100Y.C M.TW
sbi 0 W
W 1 0 M .T
O W.LSB dataO(r16) W .CO data
W
; Put into buffer,
WW sends . 100Y
the
M.T
W
W O W C O
WW .100Y.
W O out UDRn,r16
W
ret W O W C O
W O
WW .100Y.C M.TWC Code Example WW (1)(2) Y.C .TW WW .100Y. M.T
W
W . 100 O M W C O
W
WW .100Y.C M.TW
O
W
W O W C O
W
WW .100Y.C M.TW {
O
WW .100Y.C M.TW
void USART_Transmit( unsigned int data
WW ) .100Y. M.T
W
W O W C O
W O
WW .100Y.C M.TW /* Wait WW Y.C .TWbuffer */ WW .100Y. M.T
W
.
forWempty 100 transmit O M W C O
W O
WW .100Y.C M.TW while (W!( UCSRnA
W
W .100 & (1<<UDREn)))
O M ) W CO
W
WW .100Y.C M.TW
O W Y.C .TW WW .100Y. M.T
W
; W
W . 100 O M W C O
W
WW .100Y.C M.TW
O
WWbit .to Y.C .TW WW .100Y. M.T
W
/* Copy 9th
W 100TXB8 O*/ M W C O
W O
WW .100Y.C M.TUCSRnB W &= W W
~(1<<TXB8); Y.C .TW WW .100Y. M.T
W
W .100 O M W C O
W
WW .100Y.C M.TW
O if ( data & 0x0100
WW .1)00Y.C M.TW WW .100Y. M.T
W
W O W C O
W
WW .100Y.C M
O UCSRnB |= (1<<TXB8);
W
.TPut WW .100Y.C M.TW WW .100Y. M.T
W
O /* data into W
buffer, O
sends the data */ W .C O
W
WW .100Y.C UDRn .TW WW .100Y.C M.TW WW .100Y M.T
W
O M = data; W O W .C O
W
WW .100Y.C} M.TW WW .100Y.C M.TW WW .100Y M.T
W
O W O W .C O
W
W
O W O W .C O
W Notes: 1. TheseW
WW .100Y.C tents
transmit functions
WW
are written C to be general
0Y.example, W functions.
.Tonly WWThey .can00Y
be optimized if the con-
W
M.T is used
M .Tof the UCSRnB .
is static.
W 10For O M the TXB8 bit of W the1UCSRnB C O Register
W O WW .100Y .
WW .100Y.C after TW
.initialization. WW .100Y.C M.TW M.T
W
O M W O W .C O
W
WW .100Y2..CSeeM “Code
.TW Examples” Won Wpage 6. Y.C .TW WW .100Y M.T
W
W .100 O M W C O
W O Y.C frame WWmulti.1processor . W
WWThe ninth 00Y
.C can be
bit
.TW
used for indicating WW an . 100
address
M .TW when using 00Y communi-
M.T
W
cation .1 mode or O M
for other protocol W
handling as for O
example W
synchronization.W .C O
Y
M.T
W
W O W O W W .C O
WWand.1Interrupts
00Y
.C W WW .100Y.C M.TW W .100
Y
M.T
W
18.6.3 Transmitter Flags
WWUSART
The .C
YTransmitter W WW that 0Y.C M W USART
its.Tstate: W Data.1Register 00Y M.T
W
W .100 O M.T has two flags W .10indicate O W W .C O Empty
WW and
(UDREn) .C
Transmit Complete
W WW Both
(TXCn). Y.C can be
flags W W
used for generating 00Y
.1interrupts. .TW
W .100
Y
O M.T W .100 O M.T W W .C OM
Y.C WW .100whether Y. C Y .TW
TheWData W Register W .TW W is ready .100 to receive
W .100 Empty O M.T(UDREn) Flag indicates W C O Mthe transmit buffer
W W .C OM
W
new W W This0bit
data. 0Y.isCset M when.TWthe transmit WWbuffer.10is0empty, Y. and Wcleared when W the transmit Y
.100 buffer M.T
W . 1 O W O M.T W W .C O
containsW data to beY.transmitted that has not WW yet been0Y .C
moved into W
the Shift Register. For compat-
Y
W 0 C M.TW
.10devices, .10 whenOwriting M.T the UCSRnAW
W
W .100
ibility with future
W O always write this bit toW zero C Register.
W W
W O W C O
When the Data Register Empty Interrupt Enable
WW .100Y.C M.TW WW (UDRIEn) Y. bit in .UCSRnB
W is written to one, the
USART Data Register W Empty O Interrupt will be W
executed.100 as long O MasT UDREn is set (provided that
Y.C WW .100Y. C
WW are
global interrupts .100enabled). TW
M.UDREn is cleared by writing UDRn. When interrupt-driven data
W O
.CData Register WW
transmission WW is used, 0 0 Y
the .T W Empty W interrupt routine must either write new data to
W W.1 Y.COM W
W 00 .T
W W.1 Y.COM
W 00
W W.1 156
7799D–AVR–11/10 W
.C OM
00Y .TW
W W.1 Y.COM W
UDRn in order to clear UDREn W
W
orW .100 theOData
disable M.T Register Empty interrupt, otherwise a new
W Y .C W
interrupt will O M.T once the interrupt
occur
W
W .100 terminates.
routine O M.T
00Y
.C .TW (TXCn) WW .100Y.C M.TW
. 1 M O
TheW Transmit O Complete
Y.Cbeen shifted
FlagWWbit is00set Y.Cone when TW
the entire frame in the Transmit Shift
WW Register 1 0 0
has .T W
out and
Wthere . 1
are no new M .
data currently present in the transmit buffer.
W W. .C OM WW 00Y.CO .TW
W Y W W
.T WThe TXCn 100Flag bit
W.cleared OM
is.Tautomatically cleared .1when a O transmit
M complete interrupt is executed, or it
.COM
W canW be Y .C by writing W a one to W
its WW
bit location. 0 0 Y C TXCn
.The .T W Flag is useful in half-duplex commu-
Y W 0 M.T
W .100 O M.T nication W .10
interfaces .C O (like the RS-485 W W.1 Ywhere
standard), .C OM a transmitting application must enter
W
WW .100Y.C M.TW WW .100Y M.the TW W 0
.10immediately .T
W O receive Wmode and C O
free communication W Wbus .C OM after completing the transmission.
WW .100Y.C M.TW WW .100Y .
M .TW W . 100
Y
M .TW
W O W O
W O WhenW
W the Transmit Y.C Compete Interrupt WW Enable0(TXCIEn) Y.C bitW in UCSRnB is set, the USART
WW .100Y.C M.TW . 100 Interrupt M .TW W .1 0 the O M.T Flag becomes set (provided that
Transmit W
Complete O will be executed when TXCn
W O
WW .100Y.C M.TW globalWinterrupts
W Y.C .TWWhen theWtransmit
W 0Y.C M.TW
.10complete
W . 100are enabled). O M W O interrupt is used, the interrupt han-
W O
WW .100Y.C M.TW dling routine WW does 0 0 Y.Chave to
not .T W the TXCn
clear WWFlag, . 1 0 0Y.C
this is done M.T
W
automatically when the interrupt
W . 1 O M W O
W O
WW .100Y.C M.TW is executed. WW .100Y.C M.TW WW .100Y.C M.TW
W O W O
W
WW .100Y.C M.TW
O
W O W O
WW .100Y.C M.TW
18.6.4 W ParityCGenerator
O
WW .100Y. .T W WW .100Y.C M.TW
W OM The Parity Generator W calculates O the parity bit for the
Y.C control WW
W serial frame .COdata..TWhen W parity bit is enabled
WW .100Y.C M.T(UPMn1 W = 1),WW the W 100
transmitter
. M .TWlogic inserts the . 1
parity00Ybit between M the last data bit and the
W W .C O
W W frame00that Y .CO W W WW 00Y.CO .TW
W 00 Y first
.T stop bit ofW the .1 is M.
sent. T .1 M
W 00 .T W .1 M .1 M
18.6.5 W W.1 Y.the
Disabling C OM Transmitter
W 00 W .1
W.1 Y.COThe M.Tdisabling of theWTransmitter W.1 Y.C(setting OM the TXEN to zero) WW will00not OM
Y.Cbecome effective until ongo-
W W 0 0 .T W W 1 0 0 M .T W W . 1 M .TW
W.1 Y.COM W ing and pending transmissions . are completed, i.e.,
WW 00Y.CO .TShift
when the Transmit Register and
W 00 Transmit .T Buffer RegisterWdo .1 not contain M data to be transmitted. .1 When disabled,
M the Transmitter
W W.1 Y.Cwill OM no W
longer override W the TxDn Y .CO .TW
pin. W WW 00Y.CO .TW
W 00 .T W .10 0 M .1 M
W 00 W .1
18.7 Data Reception W.1 Y.C –OThe M.T USART Receiver .1
WW 00Y.CO .TW
M WW 00Y.CO .TW
M
W W W W .1
W 00 .T .1 M Receive Enable OM
W.1 The .C OM Receiver is enabled
USART WW by Y .CO the
writing W W WW (RXENn) 0 Y.Cbit in the W
W W
. 1
Y
00UCSRnBMRegister .T W
to
W
one. When W . 0
0 Receiver
1the O M .T
is enabled, the W
normal
0
.1 pin operation
O M.T of the RxDn
W .CO .TW Y.C WW .100Y .C
WW .10pin 0Yis WW and 100givenOthe M TW
.function M .TW
overridden
M by the USART W . as the Receiver’s W serial
.C O input. The baud
W
WW .rate, .CO of.Toperation W WW .C
00Y must TWset up once WW 0Y serialMreception
.10any .TW
1 00YmodeM and frame.1format
W O M .be before
W .C O can
W . C O W .C W W Y W
WW be done.
Y If synchronous W operation
W 0Y the clock
is0used, .T on the XCKn W pin.1will 00 be used .Tas transfer
W .100
clock. O M.T W W.1 Y.COM W W W Y .C OM
W
.C W 0
WW .100Y M .TW W
W . 100 O M .T W .10 O M.T
WW 00Y.C O WW .100Y .C
18.7.1 Receiving W Frames.1with 5 toO8MData .TWBits WW .100Y.C M.TW M.T
W
W W O W W .C O
WWThe Receiver .C W reception WWwhen.1it00detects Y.C a valid .TW start bit.W 00YfollowsMthe .TWstart
. 1 00Y starts M .Tdata W O M Each W bit.1that
.C O
WW O Y.C and W Y .TW
Wbit will be 00Y
.C
sampled TW
.at the baud rate WWor XCKn . 100 clock, M .TW shifted intoWthe Receive .100 Shift MRegister
WW
until the first C bit T
Y.stop of a frame isW
. W
W
received. .C
AYsecond stop Wbit will beWignored.10by 0Ythe Receiver. M.T
W
W
W .100first stop O Mbit W .100 O M.T frame is present W W .C O
WW .100Y.C M.TW
When the .C is received, i.e., a complete serial in the Receive
Y Shift
W
WW .1the
Register, 00Ycontents W
M.Tof the Shift Register W will be.Cmoved O into the receive
W
W .100 The O
buffer. M.T
receive
W O W .C
WWcan.1then .C
00Ybe read TWreading the WW 00Y M.T
W W .100
Y .TW
buffer
W O M.by UDRn W .1I/O location.
C O W W .C OM
WW .100code Y.C W WW .100Y. W
M.T function based
W 00Y
.1polling .TW
The following W O M.T shows a simple
example W USART C O
receive W W
on .C OM
of the
WWComplete Y.C W WW frames Y. W W Y
.100significant .TW
Receive
W .100 (RXCn) O M.TFlag. When using W .100 withO M.Tthan eight bits the
less
W
most
W .C OM
WW .100Y. C Y
WW .100Y.C M.TW M.T
W W
W .100
W O W C O W
W W
W O W C O
W
W O W C O
W O W
WW .100Y.C M.TW WW
W O
WW .100Y.C M.TW
W O
WW .100Y.C 157
W W
7799D–AVR–11/10 W
.C OM
00Y .TW
W W.1 Y.COM W
W 00 .T
bits of the data read from the UDRn W W.1will be .C OM
masked to zero. The USART has to be initialized
before the function .T W
can be
W
used. . 1 0 0Y M .TW
OM W O
0 0 Y.C .T W WW .100Y.C M.TW
W.1
Assembly OM Example
Code (1) W O
WUSART_Receive: O W O
OM W ; Wait O data to be received W O
WW .100Y.C M.TW
for
0 Y.C .T W WW sbis 0 0 Y.C .T W
0 W. 1 OM RXCn O
W.1 OM UCSRnA,
Y.C
W
WW .100Y.C M.TW
WW .100Y.C M.TW WW rjmp 1 0 0 .T W
W O W. OM
USART_Receive
WW 00Y.CO .TW
WW .100Y.C M.TW WW ; Get 0 0 Y.C return
and .T WreceivedWdata .1
from buffer M
W. 1 OM
W W .C O
W Win Y .CUDRn W W WW 00Y.CO .TW
W 00 Y .T W .10 0
r16,
M. T .1 M
ret W WW 00Y.CO .TW
W 00 .T W .1 M
W.1 Y.COM W C CodeW W.1 (1) Y .CO .TW
M WW 00Y.CO .TW
W W Example 0 0 W .1
W 00 .T W
unsigned .char 0
10 USART_Receive( M. T void ) .1 M
W 00 .T { W .1 M .1 M
W W.1 Y.COM W /* W WWfor00data
Wait Y .COto be W received W*/WW 00Y.CO .TW
W 00 .T .1 M. T .1 M
W W.1 Y.COM W while W (W !(UCSRnA Y .CO & (1<<RXCn))W ) WWW 0Y .CO .TW
W 00 .T W 10 0 M. T .10 M
W.1 Y.COM W ; WW. .CO .TW WW 00Y.CO .TW
W W 0 Y W
W 00 .T
W.1 Y.COM W /* Get and .10 OM W.1 */ .CO .TW
M
W W WWreturn 0 Y .Creceived T W
data fromW
W
buffer
0 0 Y
W 00 .T
W.1 Y.COM W return UDRn; .10 M. .1
WW 00Y.CO .TW
M
W W WW 00Y.CO .TW W
W 00 .T } .1 M .1 M
W 00 W .1
W.1 Y.CO M.T 1. See “CodeW
Note: W.1 Yon
Examples” .CO
M 6.
page WW 00Y.CO .TW
M
W W W 0 .T W W .1
W 00
W.1 Y.CThe
.T
OMfunction simply waits .10 Mpresent in the receive WWbuffer .CO
M
W W W WWfor data 0 Y CO
.to be
T W W 00 Yby checking
.TW
the RXCn Flag,
W 0 0 before .Treading the buffer and.1 0
returning M
the . value. . 1 O M
W.1 OM W O W
WW .100Y.C M.TW
W O W O
18.7.2 W
WW Frames
Receiving 0
O
Y.C with .9TData W Bits WW .100Y.C M.TW WW .100Y.C M.TW
0 .CO .TWbit in UCS-
W.1 If 9-bit OM W .CO .TW bit mustW W
beWread from 00Y the RXB8n
WW .100Y.C M.TW
characters are used WW(UCSZn=7) .1 00Y theMninth . 1 M
W W RnB .C O
before reading the lowWbits W fromYthe .COUDRn. WThis rule applies
W WWto the 0 .CO DORn
YFEn, .TW
and UPEn
W 0 0 Y .T W W . 1 0 0 M .T . 1 0 M
W.1Status .CO .TW
M as well. Read status
Flags W fromYUCSRnA, .CO .TW then data from
WW
W
UDRn. .CO the
Reading UDRn I/O
.TW FEn,
WW .location 00Y will change the WW of the
state .1 0 0receive Mbuffer FIFO and .
consequently100Y theMTXB8n,
1 M W O W O
WW DORn
W
0 Y.andCO UPEn
.T Wbits, whichWall Ware stored
0 0Y.Cin the .TW will change.
FIFO, WW .100Y.C M.TW
0 . 1 M
W W. 1
.C OM
W The 0 Y W
.T example showsWa.1simple USART .1 handles
.10following Mcode OM receive function Wthat OM both nine bit
W W characters
. 1 0 0 Y and
M
the
.T W
status bits.W
W .1 0 0
O M .T
W . 1 0
O M.T
W O WW .100Y .C
W
W O W O W W .C O
Y
M.T
W
W O W O W W .C O
Y
M.T
W
W O W O W W .C O
Y
M.T
W
W O W O W W .C O
Y .TW
W O W C O W W .C OM
W W .100
Y .TW
W O W C O W W .C OM
W W .100
Y .TW
W O W C O W W .C OM
W W .100
Y
W O W C O W W
W W
W O W C O
W
W O W C O
W O W
WW .100Y.C M.TW WW
W O
WW .100Y.C M.TW
W O
WW .100Y.C 158
W W
7799D–AVR–11/10 W
.C OM
00Y .TW
W W.1 Y.COM W
W 00 .T
(1) W W.1 Y.COM W
.C OM W W.1 Y.COM W
Y
USART_Receive: W W 00 .T
WW .100Y ; .C
Wait for W
data to be W received 00 .T
W O M.T RXCn W W.1 Y.COM W
W WW .100Y
sbis .CUCSRnA, W W 00 .T
O M.T W rjmp O M.T
USART_Receive W W.1 Y.COM W
Y.C W WW .100Y .C W W 00 .T
W .100 O M.T W ; Get status O M.Tand 9th bit, W W.1 data
then .C OM buffer
from
WW in.100r18, .C Y .TW
WW .100Y.C M.TW Y
M
UCSRnA .TW W
W . 100 O M
W O
W
WW .100Y.C M.TW
O
WW in .10r17, 0Y.C UCSRnB .TW WW .100Y.C M.TW
W O M W O
W
WW .100Y.C M.TW
O
WWin .1r16, .C
00Y UDRn .T W WW .100Y.C M.TW
M W O
W O W
W;WIf .error, .CO .TW-1 WW .100Y.C M.TW
WW .100Y.C M.TW 1 00Y return
OM
WWr18,(1<<FEn)|(1<<DORn)|(1<<UPEn)
W O
W
WW .100Y.C M.TW
O
W andi
0 0 Y.C .T W WW .100Y.C M.TW
W. 1 OM W O
W
WW .100Y.C M.TW
O breq
0 0 Y.C
WW USART_ReceiveNoError .T W WW .100Y.C M.TW
1
W. HIGH(-1) OM W O
W
WW .100Y.C M.TW
O ldi Wr17,
1
W. LOW(-1) OM W O
WW .100Y.C M.TW
W O ldi r16,
WW .100Y.C M.TW USART_ReceiveNoError: WW .100Y.C M.TW
W O W O
W
WW .100Y.C M.TW
O
WW the 009thY.C bit, .Tthen W return WW .100Y.C M.TW
; Filter . 1 M W O
WW .100Y.C M.TW lsr W r17 . 1 M W O
W O
WW 0x01
WW .100Y.C M.TW andi r17, . 1 00Y M W O
W O
W O
WW .100Y.C M.TW ret WW .100Y.C M.TW WW .100Y.C M.TW
O Code Example(1)WW O W O
W
WW .100Y.C C .T W W 0 0Y.C M.TW WW .100Y.C M.TW
. 1 W O
W OM W .CO void WW .100Y.C M.TW
WW .100Y.C M.unsigned TW intWW USART_Receive(
. 1 00Y M .TW )
W O W O
W O
WW .100Y.C M{.TW WW .100Y.C M.TW WW .100Y.C M.TW
W O
W O
WWstatus,
WW .100Y.C Munsigned .TW
char
. 100Yresh,Mresl; W O
W O /* Wait for data
WW to.1be
W .CO .TW
received */ WW .100Y.C M.TW
WW .100Y.C M.TW 00Y M W O
O while ( !(UCSRnAWW O )
W
WW .100Y.C M.TW W
& (1<<RXCn))
0 0Y.C M.TW WW .100Y.C M.TW
.1 W O
W O ; W
WW9th.1bit, .CO WW .100Y.C M.TW
WW .100Y.C /*MGet .TWstatus and 00Y thenM.data TW */
W O
W O
W
WW .100Y.C/* M
O
.TWbuffer */
from WW .100Y.C M.TW WW .100Y.C M.TW
W W .C O
Y W
W
W .100
status
O M.T
= UCSRnA;
.C W
WW .100Yresh M TW
= .UCSRnB; W
W . 100 O M .T W
W .100 OM
.T
WW .100Y resl =
M
UDRn;
.TW W
W .100 O M .T W .10 O M.T
O
W /* If error, return -1W*/ Y.C WW .100Y .C W
W O W O W .C
WW .100Y.C M.TW
if ( status & (1<<FEn)|(1<<DORn)|(1<<UPEn) ) Y W
WW .100return Y.C .TW W .100 M.T
W O M-1; W O W W .C O
WW ./* Y.C .TW9th bit,WthenWreturn
W Y.C W W .100
Y
M.T
W
W 100Filter O Mthe .100 */OM.T W W .C O
WW resh Y.C W WW 0Y.C M.TW W .100
Y
M.T
W
W .100 = (resh O M.T>> 1) & 0x01;WW.10 O W W .C O
WW return Y.C W Y.C W W .100
Y .TW
W .100 ((resh O M.T<< 8) | resl);
W
Y.C WW .100Y. C W Y .TW
WW }
.100 M.T
W
W O M.T
W
W .100 OM
W O C W .C
Note:WW1. See 0Y.C Examples” W WW 0Y. M.T
W W .100
Y .TW
W .10“Code O M.T on page 6. WW.10 C O W W .C OM
WW function Y.C W Y. into the W W before 0Y com-
.10any
The receive
W .100 example O M.T reads all the I/O
W
W .100
Registers
OM.T Register File W W
Y.Cgives an WW buffer Y. C W the buffer
Wlocation read will
putation WisWdone. .
This
100 M .TW optimal receive
.100
utilization since
M.T
W O W C O
be free to accept
WW .100Y.C M.TW
new data as early as possible. WW .100Y. M.T
W
W O W C O
W O W
WW .100Y.C M.TW WW
W O
WW .100Y.C M.TW
W O
WW .100Y.C 159
W W
7799D–AVR–11/10 W
.C OM
00Y .TW
W W.1 Y.COM W
W 00 .T
18.7.3 Receive Compete Flag and Interrupt W W.1 Y.COM W
W W 00 .T
The USARTO M.T has one flag
Receiver
W W.1 indicates
that
.C OM the Receiver state.
.C Y .TW
. 1 00Y Complete M .TW W
W . 100 if there O M
The W Receive O (RXCn) Flag indicates are unread data present in the receive buf-
fer.W This1
. flag isOone M when unread data Wexist Y in the O receive buffer, and zero when the receive
.T W W is 0empty
Wbuffer 0 Y.C (i.e., .does T W not contain WWany .unread 1 0 0 .Cdata). M .T W
If the Receiver is disabled (RXENn = 0),
M W . 1 O M W O
.CO .TW theWreceive Y.C will .be TWflushed and WW Y.C the RXCn .TW bit will become zero.
.100Y M
W . 1 00buffer M
consequently
W . 100 O M
W O
W
WW .100Y.C M.TW
O
WW the.1Receive
When
.C
00Y Complete .TW Interrupt WW Enable . 0Y.C Min.TUCSRnB
10(RXCIEn)
W
is set, the USART Receive
O M W O
W W Y.C O
W Complete
W WW interrupt 0 Y .C will be T W
executed asW W as 0the
long 0 Y C
.RXCn .T
Flag W is set (provided that global inter-
W
W .100 O M.T W .10 O M. W W.1 reception .C OM
rupts W
are enabled). . C When interrupt-driven data Y is W
used, the receive complete routine
WW .100Y.C M.TW W . 1 00Y M .TW W
W .100 O M.T
must read W O
the received data from UDRn inW Y.C the RXCn
W O
WW .100Y.C M.TW rupt will WW .100Y.C M.TW W order.1to00clear M.T
W Flag, otherwise a new inter-
occur W once the O interrupt routine terminates.W O
W
WW .100Y.C M.TW
O
W O W O
WW 0Receiver
18.7.4
W 0 Y.C
O Error Flags
W.1 OM W CO three W O
WW .100Y.C M.TWThe USART WWReceiver 0 0 Y.has .T W Error Flags: WW Frame10Error
. 0Y.C(FEn), W
M.TData OverRun (DORn) and
W . 1 O M W C O
W O Parity Error (UPEn).
WW .100Y.C M.TW
All can be accessed by W W
reading UCSRnA.Y. Common W for the Error Flags is
WW .100Y.C M.TW W .100 the frame O M.Tfor which they indicate the
that they are located
W in the Oreceive buffer together with C
W O
WW .100Y.C M.Terror W status.WDue W .C
00Ybuffering .TW WW .100Y. W
M.Tmust be read before the
W to.1the O M of the Error Flags, W the UCSRnA C O
W O W 0Y.C reading
W Y. W
WW .100Y.C M.receive TW bufferW(UDRn), . 10since M .TWthe UDRnWI/O location W .100 changes O M.Tthe buffer read location.
W O C
W O
WW .100Y.C MAnother .TW equality WW for the 0Error Y.C TW WWnot be 0Y. .TW
W . 1 0 Flags O M .is that they can
W .10altered
C O
byMsoftware doing a write to
W CO the flag location. W
However, all .Cflags must be set to zero W when Y
the . UCSRnA W is written for upward
WW .100Y. M .TW W .
Y
100 implementations. M .TW W
W .100 O M.T
compatibility of future WUSART O None of the Error C
Flags can generate interrupts.
W
WW .100Y.C M.TW
O
W O
W O
The Frame Error (FEn) WW Flag
W .CO the
indicates
.TWstate of the WW first stop 00bit Y.Cof the .next W readable frame
WW .100Y.C M.TW . 1 00Y M W . 1 O MT
stored in the receive buffer.W The FEn O Flag is zero when the stop bit C
was correctly read (as one),
W
WW .100Y.Cand M
O
. T W WW .100Y.C M.TW WW .100Y. M .TW
the FEn Flag will be W one whenCthe W(zero). O flag can be used for
W CO W . O stop TW
bit was incorrect
WW and Y.C
This
.TW
WW .100Y.detecting M .T Wout-of-sync Wconditions, . 1 0 0Ydetecting M . break conditions W . 1 00protocol
O Mhandling. The FEn
W C O W
W setting O
.Cthe USBSn W C
Y.the Receiver W ignores all,
W Y .
Flag is not W
affected by W the 0 Y
of .T W bit in W
UCSRnC 0
since
.1 0 .T
W 00
W.1 except OM
.T .10 M WW 0always OM
.C for the first, stop WWFor0compatibility
bits. .CO .TW with future devices, Y.C set.T W
W W
. 1 00 Y
M .T W W
W .1 0 Y
O M
W
W .1 0
O M this bit to zero
W when writing O to UCSRnA. W Y.C WW .100Y .C W
W O .C
W
WW .The .CO OverRun
Data
.TW (DORn) WW Flag indicates Y.C data.Tloss W due toW aW receiver Y
.100bufferOfull M.T
W
condition. A
1 00Y M W .100 O M W C
W Data Y OverRun O occurs when the .C is full WW it.1is00aYnew character .
WW ing 0 the
0in
.C .TW Shift Register, WW receive .
Y buffer
100a new Ostart M .TW
(two characters),
M.is TW wait-
W . 1 O M
Receive W and bit is detected. WIf W
the DORn .C O
Flag set there
WW was 0 0
oneY.Cor more .T W
serial frame WlostW
. 1
between 0 0Y.Cthe frame M .TWlast read W from UDRn,. 1 00Yand theMnext .TWframe
W. 1 M W O W .C O
WW read.1from .CO .TFor W compatibility WW with.1future 0Y.Cdevices, TWalways write WW 0to0Yzero when W
M.T writing
00Y UDRn. M W
0
O M . this W bit
. 1
.C O
W .C O W .C WWsuccessfully Y moved W
WWto UCSRnA. 1 00Y TheMDORn .TW Flag isW cleared
. 00Y the frame
1when M .TWreceived was W .100 O M.T from
theW
. O W O W .C
Shift Register to the receive buffer.
Y
M.T
W
O W O W W .C O
TheWW Parity Y.C (UPEn)
Error .TW Flag indicates WW that Y.Cnext frame
the W in the receive W Y
.100 hadOaMParity
buffer .TW
W
W . 100 O M W .100 O M.T W W .C
WW .C the UPEn Y zero. .For W
WW .100Y.C M.TW
Error when received. If Parity Check is not enabled .TW bit will W always be0read
W
00Y
.1this O M W .1 0 O MT
compatibility
W with future
O devices, always set bit to zero when writing toW UCSRnA. .CFor more
WW see.1“Parity .C
00Y BitM .TW WW .100Y.C M.TW W .100
Y .TW
details W O Calculation” on pageW 153 and “Parity C O Checker” on page W W160. .C OM
W W .100
Y .TW
W O W C O W W .C OM
18.7.5 Parity Checker WW .100Y.C M.TW WW .100Y. M.T
W W .100
Y .TW
W O W C O W W .C OM
The ParityWW Checker C activeTwhen
.is . W the high WW USART0Parity Y. mode W
(UPMn1) bitWis set. Type Y
.100 of Par-
00Y .1 0 M.T
ity CheckW toW be.1performed O M(odd or even) is selected W by theC OUPMn0 bit. When W
enabled, W the Parity
W 0 0 Y.C .T W WW .100Y. M .TW W
Checker calculates .1 M
the parity of the data bitsW inW incoming.Cframes O and compares the result with
WW 00Y.CO .TW Wof the .check 00Y is stored .TW
the parityWbit from.1the serial frame.
M The result W 1 O M in the receive buffer together
with the received WW data
W
0 Y .COstop.T
and W
bits. The ParityW W Error 0 0
(UPEn) Y.C Flag can then be read by software
0
W.1 Y.aCO M W.1
to check if the WWframe.10had 0 Parity.TError. W WW
W OM
WW .100Y.C M.TW
W O
WW .100Y.C 160
W W
7799D–AVR–11/10 W
.C OM
00Y .TW
W W.1 Y.COM W
W 00 M.T
The UPEn bit is set if the next character W W.1 that .C Ocan be read from the receive buffer had a Parity
Error when received M .T W
and the
W
Parity . 1
Checking0 0Y wasMenabled .TW at that point (UPMn1 = 1). This bit is
W O
.CO .TWbuffer (UDRn) WW is read. Y.C .TW
valid.1until00Ythe receive M W . 100 O M
W O
W O W O
18.7.6 Disabling the Receiver
OM In W contrast
W to .the O Transmitter, disabling Wof the Receiver O will be immediate. Data from ongoing
0 Y.C .T W W 0 0 YC .T W WW .100Y.C M.TW
0 receptions 1
. will therefore OM be lost. WhenW disabled (i.e.,Othe RXENn is set to zero) the Receiver will
W.1 OM WW override Y.C the .normal
W
0Y.C port .TWThe Receiver buffer FIFO will be
WW .100Y.C M.TW noWlonger . 1 0 0 M T W function W of the
W . 1 0RxDn O M pin.
W O W O W Y.C
WW .100Y.C M.TW WW when
flushed Y.CReceiver
00the .TW is disabled. WRemaining . 100 dataOinMthe .TW buffer will be lost
W . 1 O M W C
W O W .C W Y . W
WW .100Y.C M.TW W . 100
Y
M .TW W
W .100 O M.T
18.7.7 Flushing the Receive W
Buffer O
W O
WW .100Y.C M.TW The receiver WW .100Y.C M.TW WW .100Y.C M.TW
W buffer FIFO O will be flushed WWthe 0Receiver
when O is disabled, i.e., the buffer will be
W O
WW .100Y.C M.TW emptied WW 0
of its contents. 0 Y.C Unread .T W data willW be lost. . 1
If
0Y.Cbuffer
the M.hasTWto be flushed during normal
W . 1 O M W O
W O
WW .100Y.C M.TW operation, WW due to.1for .C
00Yinstance TWerror condition,
.an WW read .10the0Y.C UDRn MI/O.TWlocation until the RXCn Flag
W O M W C O
W O
WW .100Y.C M.TWis cleared. WThe W following Y.Ccode example .TW shows WW how to10 0Y. the receive
. flush
W
M.T buffer.
W . 100 O M W C O
W O
WW .100Y.C M.TWAssemblyWCode Example
W Y.C(1) .TW WW .100Y. M.T
W
W . 100 O M W C O
W O
WW .100Y.C M.TW USART_Flush: WW .100Y.C M.TW WW .100Y. M.T
W
W O W C O
W O
WW .100Y.C M.TW sbis W
W
UCSRnA,.10RXCn 0Y.C M.TW WW .100Y. M.T
W
W O W C O
W O
WW .100Y.C M.TW ret W
W
W . 100 O M W C O
W O
WW .100Y.C M.TW in r16, WWUDRn.100Y.C M.TW WW .100Y. M.T
W
W O W C O
W
WW .100Y.C M.TW
O rjmp USART_Flush
W
W O W C O
W
WW .100Y.C CM
O Code Example W
.TW
(1)
W
W
W . 100 O M W C O
W
WW .100Y.C Mvoid
O
.TW USART_Flush( WW void Y.C W WW .100Y. M.T
W
W .100 ) OM.T W CO
W
WW .100Y.C {M.TW
O
W
W O W C O
W
WW .100Y.C M.TW
O unsigned char W
Wdummy; Y.C .TW WW .100Y. M.T
W
W .100 O M W C O
W O WW .100Y .
WW .100Y.C M.TW
while ( UCSRnA & (1<<RXCn) ) dummy = UDRn; W
WW .100Y.C } M.TW W O M.T
O W O .C
W
W
W O W .C O
W
WW .Note: .CO1. See .TW
“Code Examples” WW on .page Y6..C .TW WW .100Y M.T
W
1 00Y M W 100 O M W C O
W O WW .100Y .
W
18.8 Asynchronous Data Reception
O W O W .C O
W
WW The 0Y.C includes .TW a clockW
W 0Y.C M.TW WW .100Y M.T data
W
. 1 0USART M recovery W . 10and a data
O recovery unit for W
handling O
asynchronous
C
W .C O W Y.C WW .100Y . .TW rate
WW reception.1 00Y The M .TWrecovery W
clock logic is 100 for synchronizing
used
. M .TW the internally
W generated O Mbaud
W . O W O W .C
WWclock.1to00the Y.Cincoming .TWasynchronous WW serial . 0Y.C atMthe
10frames .TW RxDn pin. W The data 00Y
.1recovery
W
M.T sam-
logic
O M W O W W .C O
WW and
Wples 00Y
low.C pass.T filters
W each W W
incoming
100
Y.Cthereby
bit, .TW improving W the noise Y
.100immunity TW
M.of the
W . 1 O M W . O M W W .C O
Receiver.
WW .100Y.C M.TW
The asynchronous reception
WW operational 0Y.C range
.10frames,
depends on
W Wthe accuracy
M.Tthe frame size inWnumber
Y of the .inter-
.100 of bits. MT
W
nal baud W rate clock, O the rate of the incoming W O and W .C O
Y
M.T
W
W O W O W W . C O
18.8.1 Asynchronous Clock WW Recovery Y.C W WW .100Y.C M.TW W .100
Y .TW
W .100 O M.T W W .C O W W Y .C OM
W
TheWclock W recovery Y.C logic .synchronizes
TW Winternal 00Y to the
.1clock TW
M.incoming
W frames.
serial .100FigureO18-5 M.T
W . 100 O M W C O W W .C
WWbit of.1an Y. Y16 times.TW
WW .100Y.C M.TW
illustrates the sampling process of the start
00incoming frame.
W The sample
M.Tfor Double Speed
W
W
rate0is
.1 0 OM
the baudWrate W for Normal O mode, and eight times
W W the baud .C O rate W mode. Y.Chor-
The
W 0 Y .C T W W 0 0 Y .T W W . 1 0 0
izontal arrows 0
W.1illustrate M. synchronizationWvariation
the W.1 Ydue M
.CO to the sampling process. WW Note the
W W 0 Y .CO .TW W 0 0 .T W W
larger time variation .10 when
.CO done
Musing the DoubleW W.1 mode
Speed O(U2Xn
M = 1) of operation. Samples
denotedW zeroWW are samples0 Y .T Wwhen the W
RxDn line is
0 0 Y
idle
.C(i.e., .
noT W
communication activity).
0
W W 00 .T W 00
W.1 Y.COM W W W.1
W W 00 .T W
W W.1 Y.COM W
W 00 .T
W W.1 Y.COM
W 00
W W.1 161
7799D–AVR–11/10 W
.C OM
00Y .TW
W W.1 Y.COM W
W 00 .T
Figure 18-5. Start Bit SamplingWW.1 .C OM
M .TW W . 100
Y
M .TW
O W O
00RxDY.C .TW
IDLE WW .100Y.C START M .TW BIT 0
W . 1 O M W C O
.C W . W
WW .100Y M.T
W W 00Y .T
W WW (U2X Sample
.10=00)
Y 0 0.TW W 5 6 .1070 8 9 M10.T 11 12 13 14 15 16 1 2 3
M.T W O M 1 2 3 4 W W O
0 Y.C
O
.T W WW Sample 0 0 Y .C
.T W W . 1 0 0Y.C M.TW
0 W. 1 M 1 O
W.1 OM 0 O
W
W3 W .4100Y.C5 M.T
WW .100Y.C M.TW WW (U2X .=11)00Y.C M .T W 2 6 W 7 8 1 2
W O W O
W
WW .100Y.C M.TW
O
Wclock recovery O WW(idle) O
W
WW .100Y.C M.TW
O When WW the Y.C logicW detects W a high 0Yto.Clow (start) W
W . 1 0 0
O M .T
W . 1 0
O M.T transition on the RxDn line, the
W O Wsample C
Y.denote
WW .100Y.C M.TW the figure.
start bitW
W
detectionYsequence
. 0 .C M.Tis
10clock
Winitiated. W Let
.100 8, O
1
Mand.the
TWfirst zero-sample as shown in
The
W O
recovery logic then uses W
samples 9, 10 for Normal mode, and sam-
W O
WW .100Y.C M.TW ples 4,W5, and .610for
W .C
0YDouble .T W WW .100Y.C M.TW
M Speed mode (indicated W with sample
O numbers inside boxes on the
W O
WW
W .CO .TW WWIf two.1or Y.C of these TW three samples have logical
WW .100Y.C M.TW figure), to decide.1if00aYvalid start bit is received. 0 0more M .
W OM WW 0as O
W O
WW .100Y.C M.TWhigh levels WW (the majority 0 0 Y.Cwins),.T Wstart bit is
the Wrejected . 1 0Y.aCnoise TW and the Receiver starts
M.spike
W . 1 O M W C O
W O C low-transition.
.to WW a.1valid . isW
WW .100Y.C M.TW
looking forW the Wnext high
. 1 00Y M .TW If however, 00Y start M bit.T detected, the clock recov-
ery logic is synchronized W O
and the data recovery W C O
W O
WW .100Y.C M.Trepeated W WW .100Y.C M.TW WWcan.1begin. 00Y
. The synchronization
M.T
W process is
for each W start bit. O W CO
W
WW .100Y.C M.TW
O
W
W O W C O
W
18.8.2WWAsynchronous .CO Data.TW Recovery WW .100Y.C M.TW WW .100Y. M.T
W
. 1 00Y M W O W C O
W O
WWclock.1is00synchronized Y.C WW Y. W
WW .100Y.C When M .TW
the receiver
M .TWto the start bit, the10data
W . 0 recovery O M.T can begin. The data
Orecovery unit uses W W O C
. in Normal
W
WW .100Y.C states .TW
a state machine Y.C thatW has 16 states WWfor each 0Ybit
.10the
W mode and eight
M.T of the data bits and
M for each bit
W
in Double
W . 100SpeedOmode. M .T
Figure 18-6 W
shows O
sampling
C
W O W Y.C W Y. .TW of the recovery
WW .100Y.C theMparity .TW bit. EachWof the . 100
samples is M .TWa numberWthat W
given 100 to O
is .equal theMstate
W O C
W
WW .100Y.Cunit.M.TW
O
W
W O W C O
W
WW .100Y.C M.TW
O
W
W O W C O
W
WW .100Y.C M.TW
O 18-6. Sampling W
Figure
W of Data andY.C Parity BitW WW .100Y. M.T
W
W .100 O M .T W C O
W O WW .100Y .
WW .100Y.C M .TW WW .100Y.C M.TW BIT n M.T
W
O
RxD
W O W .C O
W
W
O W O W . C O
W
WW .100Y.C(U2X Sample .TW WW .100Y.C M.TW WW .100Y M.T
W
O =M 3 W4 O 13 W .C O
W WW .100Y
1 2
WW .100Y.C M.TW
0) 5 6 7 8 9 10 11 12 14 15 16 1
W
WW .100Y.C M .TW W O M.T
O W O .C
W W7W .18 00Y 1 M.TW
Sample
WW .100Y(U2X .C = 1) .TW 1 W2W .3100Y.C4 M.T5 W 6
WW .C O M
W W W Y .C O
W W WW 00Y.CO .TW
Y W 0 .T
W
W .10 0
O M.T 0
.C W
WWThe decision
.1 00Y of M W level of
the.Tlogic Wthe received
W . 100 bit O isM .T by doing a majority
taken W
W .100votingOofMthe .T logic
WW to0the C O W of the Y.C W The center W Y .C W
Wvalue . 1 0Y.three M
samples
.TW in theW center
. 100 received M .Tbit. W samples
W .100are emphasized O M.T
O
W figure by having the sample number W O
.Cboxes..TThe W .C
Y is done W
on the
WW .100Y.C M.TW WW .1inside 00Y W majorityWvoting process
M received bit is registered .100 M.T
as
follows: W If two or all
O three samples have W
high levels, Othe W W to C
be
. Oa logic 1.
W 0 Y.C W WW .100Y.C M.TW W 1 00Y .TW
IfWtwo or W. 1
all0 three samples
M .T have low levels, the received bit is registered toW .
be a logic O M
0. This
CO
Y.process WW 00Y.CO .TW Won W .C
00Y pin.M .TW
WW voting
majority . 1 0 0 M .T W as a low
acts Wpass filter
.1 for the Mincoming signal the
W . 1RxDn O The
W O W C O W .C
WW process Y.C W WaWcomplete Y. TW W 0Y stop M
.10first .TW
recovery
W .100
is then .repeated
O MT
until
W .100 frame O Mis .received. Including
W W
the
.C O
bit.
NoteW that
W the Receiver Y.C only.Tuses W the first Wstop W bit 0of0Y C
a.frame. .TW Y .TW
.100 M W .1 O M
W
W .100 OM
W O C W .C
FigureW18-7 W shows .C sampling
Ythe W of the stop WW bit and .10the0Y.earliest TW
M.possible
W
beginning 00Ystart bit
of.1the
of the next WWframe. Y.C W WW .100Y. M.T
W W
W .100 O M.T W C O
W
W O W C O
W O W
WW .100Y.C M.TW WW
W O
WW .100Y.C M.TW
W O
WW .100Y.C 162
W W
7799D–AVR–11/10 W
.C OM
00Y .TW
W W.1 Y.COM W
W 00 .T
Figure 18-7. Stop Bit SamplingWand W.1NextYStart .C OM Bit Sampling
M .TW W . 100 M .TW
W O
.CO .TW WW .100Y.C STOP .T1 W (A)
. 1 00Y RxD
M W O M (B) (C)
W .C O W .C W
WW .100Y M.T
W W 00Y .T
W . C O W W.1 Y.COM W
W WW .(U2X Sample Y
100= 0) OM.T 1 2 3 4 5 W6.107 8 CO
W W 0 .T 0/1 0/1 0/1
O M.T W C W .
9 M10
00Y
.C .TW WW Sample 1 00Y
.
M .TW W . 100
Y
M .TW
.1 M .
W(U2X = 1) O W O
W O
1 2
W3 W .4100Y.C5 M.T 6 W 0/1
W O W O
W
WW .100Y.C M.TW
O
O WWbit as00done O
W O WWmajority Y.Cvoting .isTW Y.C for the W
WW .100Y.C M.TW TheW same
. 1 0 0 M
done to theW stop
W . 1 O M.T other bits in the frame. If the stop
O W O Y.C (FEn).TFlag
W
bit is registered to have a logic 0 value, the WWFrame .100
Error
M
W will be set.
W O W O W
W bit of0a0Ynew O
.C frame
WW .100Y.C M.TW A new W high W to low00transition Y.C .TW
indicating theW start
.1
W
M.T can come right after the last of
W . 1 O M W O
W O the bits used .C voting. WW .C
WW .100Y.C M.TW point marked WW for.1majority 00Y M .TW
For Normal Speed mode,
00Y theMfirst
.1mode .TWlow level sample can be at
(A)
W in Figure O 18-7. For Double Speed W C O
the first low level must be delayed to
W O
WW .100Y.C M.TW(B). (C) marks WW a .stop .C
00Ybit of full . T W WW .100Y. M .TW
W 1 OM length. The early Wstart bit detection O influences the operational
W
WW .100Y.C M.TW
O
range of the WW Receiver. 0 0 Y.C .T W WW .100Y.C M.TW
W. 1 O M W O
W
WW .100Y.C M.TW
O
W O
18.8.3 WW Asynchronous
Y.C
O Operational
W W WW 00Y.CO .TW
Range WW .100Y.C M.TW
W 00 . T . 1 M
W.1 OM The operational range W of the Receiver O is dependentWon W the mismatch .CO between the received bit
WW .100Y.C Mrate .TW WW .100Y.C M.TW W . 1 00Y W
M.Tframes at too fast or too
and the internally W generated O baud rate. If the Transmitter W is O
sending
C
W O W Y.C W Y. W
WW .100Y.C slow M .TW bit rates, orWthe internally .100 generated M .TWbaud rateWof theWReceiver .100 does
O M.T not have a similar (see
W O W O W . C
WW .100Y.C Table .TW
W Y.C .TWwill not beWable W 00Y M.the TWframes to the start
M
18-2) baseW frequency,
W . 100the Receiver
O M to.1synchronize
C O
W
WW .100Y.C bit.M.TW
O
W
W O W C O
W
WW .100Y.CThe M
O
.TW equations
following WW can.1be Y.C to calculate
00used .TW the ratio WWof the 0Y.
.10incoming Mdata.TW rate and internal
W O W O M W W .C O
C W .C Y W
WW .100Y.receiver M .Tbaud
W rate. W . 100
Y
M .TW W
W .100 O M.T
W O C
W
WW .100Y.C M.TW
O
W
W O W .C O
Y.C D + 1.S
W O W  D +002YS
WW R slow 1 TW -
=00------------------------------------------- WW .100Y.C M.TW R fastW= ------------------------------------
.11 S + S -OM.T
W
. S – 1 + O D M  S + S W O  D W + . C
W
WW .100Y.C M.TW
F
WW .100Y.C M.TW WW .100Y M M.TW
W .CO .TSum W O WW 00Y.CO .TW
WW .D 00Y W of character WW size 0 0Y.CparityMsize
and .TW(D = 5 to W 10 bit)W.1
1 M W .1 O OM
W W . C O W Y .C W W W 0 Y.C TW
W S.100
Y
M .T W
Samples
W
per bit. S = W .
16 0 0
1 for Normal O M .T
Speed mode and SW=. 8 for Double 1 0
O M.Speed
W O WW .100Y .C
WW .100Y.C M .TW
mode. WW .100Y.C M.TW M.T
W
O W O W .C O
W
WW S .100Y.C First .TW WW used C
0Y.majority W
.Tvoting. WW .100Y .TW
M sample number W .10for O M S = 8 for normal
W speed C O M and SF = 4
WF O W .C F W Y . W
WW .100Y.C forMDouble .T W W
Speed mode. .1 0 0 Y
M .T W W
W . 1 0 0
O M . T
O W O W .C
WW 00Y.C W WW .10for .C
0Ymajority W W Y
.100 speed .TW
WS
M W.1 Middle
O M.Tsample numberWused W O M.T voting. SM = 9 for W normal
W .C O Mand
WW .100Y.CSM =M5.T WDouble Speed Y.C W W .100
Y
M.T
W
W O
for W mode.
W .100 O M.T W W .C O
.C WW .100Ydata .C W W 00Y .TW
RWW .100Yis the .TW
ratio
M of the slowest incoming M.Tthat can be accepted
rate W .1in relation O Mto the
slow W
C O W W .C O W Y .C W
WW .100Y . T W W 0 0 Y .T W W 1 0 0 be.T
W
receiverMbaud
O
. rate. Rfast is the ratio
W .1 of theOfastest
C
M incoming data W
W
rate. that can
.C OM
WW .10accepted 0Y.C Min.Trelation W WW Y. W W .100
Y .TW
W O
to the receiver
W .100baud rate. O M.T W W .C OM
Y.C 18-3.Tlist WW receiver Y. C Y .TW
Table W18-2 W and00Table Wthe maximum .100 baud M .TW
rate error that can W be tolerated. .100 OM
Note
W .1 O M W .C O W W Y .C
that Normal WW Speed .C
Ymode has W higher toleration WW of.1baud 00Y rate variations.
M.T
W W .100
W W
W O W C O
W
W O W C O
W O W
WW .100Y.C M.TW WW
W O
WW .100Y.C M.TW
W O
WW .100Y.C 163
W W
7799D–AVR–11/10 W
.C OM
00Y .TW
W W.1 Y.COM W
W 00 .T
W W.1 Y.COM W
.TW BaudW 00
W.1 forYNormal
.T
OM Speed Mode (U2Xn = 0)
Table 18-2. Recommended Maximum
C OM Receiver Rate Error
W .C
1 00Y
.
M .TW W . 100 M .TW
D . O W O Recommended Max Receiver
# (Data+Parity Bit) W
WW R 00Y(%) .C .T W
R (%) WW Max 1 0 0Y.C Error
Total . TW
(%) Error (%)
W. 1 OM . M
WW 00Y.CO .TW
slow fast
W W Y .C W W
.T5 W 00
93.20 .T106.67 .1+6.67/-6.8 M ± 3.0
.C OM W W.1 Y.COM W WW 00Y.CO .TW
Y W W 0 T W
00
W.1 Y.COM W
.6T .10
94.12 M.105.79 .1
+5.79/-5.88
WW 00Y.CO .TW
M ± 2.5
W W WW 00Y.CO .TW W
W 00 7.T 94.81.1 M105.11 .1
+5.11/-5.19 M ± 2.0
W 00 .T W 1 . 1 M
W.1 OM 8 W.
95.36 OM 104.58 W
+4.58/-4.54 O ± 2.0
WW .100Y.C 9 M.TW WW .100Y.C M.TW WW .100Y.C M.TW
95.81 W O104.14 W
+4.14/-4.19 O ± 1.5
W
WW .100Y.C10 M.TW
O
W O W O
WW .100Y.C M.TW
W O 96.17 103.78 +3.78/-3.83 ± 1.5
W O W O
W
WW .100Y.C M.TW
O
W O WW Speed O
Table W
WW 18-3. 0 CO
Y.Recommended.T W Maximum WW Receiver 0 0 Y.CBaud Rate .T W Error forW Double
. 1 0 0Y.CMode TW = 1)
M.(U2Xn
. 1 0 M W . 1 O M W C O
W
WW .100DY.C M.TW
O
Recommended
M Max Receiver
W
#W(Data+Parity O
Bit) R (%) W R C
(%) O Max Total W
Error W (%) .C O Error (%)
.C W . .TW Y W
Y W .100 M.T
slow fast
W . 1 00Y M .TW W
W . 100 O M W C O
W 5
WW .100Y.C M.TW
O 94.12
WW .105.66 Y.C .TW
+5.66/-5.88 WW .100Y. M.T
W ± 2.5
W 100 O M W C O
W6
WW .100Y.C M.TW
O 94.92 WW 104.92 Y.C .TW +4.92/-5.08 WW .100Y. M.T
W ± 2.0
W . 100 O M W C O
W O
WW 7 .100Y.C M.TW95.52 W 104,35
W Y.C .TW+4.35/-4.48 WW .100Y. W
M.T ± 1.5
W .100 O M W C O
W O
WW103.90 Y.C +3.90/-4.00WW Y. W
WW 8 .100Y.C M.TW96.00 . 100 M .TW W .100 O M.T ± 1.5
W O C
W
WW9 .100Y.C M.T96.39
O
W WW103.53 Y.C W WW .100Y. W
M.T± 1.5
W . 100 O M .T+3.53/-3.61 W C O
WW 00Y.CO .T W W Y.C W WW .100Y. W
M.±T1.0
W10 . 1 M
96.70 W103.23
W .100 O M .T+3.23/-3.30
W C O
W
WW .100Y.C M.TW
O
Munder
The recommendations of W
the maximum O receiver baud rate W
error was C
made O the assump-
W
WW .100Y .CO .TW WWTransmitter 0 0Y.Cequally .TW WW .100Y. M .TW
tion that the Receiver and .1 M divides the maximumW total O
error.
W OM W O
WW .100Y.C M.TW
O WWThe00Receiver’s O
W There Oare two possible sources WW for00the Y.Creceivers Wbaud rateW error. Y.C system clock
.TW
WW .10(XTAL) 0Y.C will .T W W . 1 M .Tover . 1 M
W W .C OM always
W
have some minor
WW 00Y.CO .TW
instability the supply
W WW 00Y.CO .the
voltage range and
T W
tempera-
Y W 1
W 100 range.
ture
W.resonator OM
.T using a crystalW
When to.1generate the M system clock, this W OM
is.rarely a problem, but for a
W Y .C the W
system clock W
may W differ 0more
0 Y .CO than 2%
.T W depending W of
Wthe 0 0 Y.C tolerance.
resonators .T W The
W .100 .T .1 M . 1 OM
Wsecond .C OM for the error is more
source WW controllable. Y .CO The W baud rate W WW 0can
generator 0Y.Cnot always W do an
W W
. 1 0 0 Y
M .T W W
W . 1 0 0
O M .T
W . 1 O M.T
exact division O of the system frequency to get the baud rate wanted.WW .100Y
In this case .C an UBRR
W
WW that.1gives .C
00Y an acceptable .T W WW .100Y.C M.TW M .TWvalue
OM low error can W be used ifOpossible. W O
W
W W .CO .TW WW 00Y.CO .TW W WW 00Y.CO .TW
18.9 Multi-processor CommunicationW 0 Y Mode W .1 M
0
W W
Setting .the 0 Multi-processor T W
Communication 0 0
mode (MPCMn) .T bit in W
UCSRnA 1
enables a filtering
M
W 10 O M. W.1 Y.COM W W W. Y . CO W
.C W W 0
W W
function
.
of00incoming
1
Y
M TW received
.frames W by the
W .100
USART Receiver.
O M.T Frames that
W .10do not O M.T
contain
W O Y.Cthe receive W .C
WW .100Y.C M.TW
address information will be ignored and WWnot put into .TW buffer. W This effectively
.100
Y reduces .TW
the number W of incomingO frames that has W
to .100handled
be O Mby the CPU, in a W
system
W with .C OM
multiple
Y.C WW .100Y. C W W 0Y .TW
MCUs WWthat .communicate
100 M.T
W
via the same serialWbus. M.T
TheCTransmitter is unaffected W .10the
by MPCMnOM
W O O W .C
WWbut has Y.C used.Tdifferently W WW it is.1a00part Y. of a system
M.T
W .100
W Multi-processor Y .TW
setting,
W .100to be O M when W C O utilizing the W
W .C OM
WW .10mode.
Communication 0Y.C M.TW WW .100Y. M.T
W W .100
Y
W O W CO W W
WW is 0Y.up C
.TW frames W
W Y. W W
If the Receiver
W .10set to M
O
receive that contain W .100 5 to 8Odata M.Tbits, then the first stop bit indi-
Y.C data W Y. C W is set up for frames with
cates if the WW frame contains
.100 M.T
W
or addressW information. .100 If theOReceiver
M.T
W O W Y. C
nine data W W then 0the
bits, C bit T
Y.ninth (RXB8n)
W WW for identifying
is used
.100
address and data frames. When
the frame type W
bit 1 0 first stop
.(the O M.or the ninth bit) isWone, W the frame contains an address. When the
WW .100Y.C M.TW W
frame type bit is zero W the frame O is a data frame.
WW .100Y.C M.TW
W O
WW .100Y.C 164
W W
7799D–AVR–11/10 W
.C OM
00Y .TW
W W.1 Y.COM W
W 00 .T
The Multi-processor Communication W W.1modeY.enablesC OM several slave MCUs to receive data from a
master MCU. This
M .TW is done by
Wfirst . 100 anOaddress
decoding M .TW frame to find out which MCU has been
.CO .TW W Y.C
addressed.00Y If aMparticular slave WW MCU .has 100 beenOaddressed,M .TW it will receive the following data
. 1
W asYnormal, O W
W
frames .C W
while the other
W Wslave 0MCUs 0 Y .C will ignore .T W the received frames until another
W
W address
WW .100Y frame .C is received. W W 00 .T
Y.C Using W WW .100Y . C W W 00 .T
W 100
.18.9.1 OM.T MPCMn W O M.T W W.1 Y.COM W
WW .C
WW .100Y.C M.TW For an MCU Y as a.T
.100to act O
W
M master MCU, it can
W
Wuse.100a 9-bitOcharacter M.T frame format (UCSZn = 7). The
W .C O W W Y . C W W 0 Y .C W
W Y W ninthW bit (TXB8n) 0 must be T set when anW address frame
0 (TXB8n .T = 1) or cleared when a data frame
W
W .100 O M.T W .10 O M. W W.1 must .C OM
(TXB =W 0) is being .Ctransmitted. The slave MCUs Y in this W
case be set to use a 9-bit character
WW .100Y.C M.TW W . 1 00Y M .TW W
W .100 O M.T
W O
W
WW .100Y.C M.TW
O frame format.
W O W O
Y.C should toW
W CO in Multi-processor
0Y.data W
WW .100Y.C M.TW WW procedure
The following
. 1 0 0 M .T W be usedW exchange
. 1 0 M.T
Communication
W O W O
W
WW .100Y.C M.TW
O mode:
W O W O
.C in Multi-processor WW 00Y.COmode.T(MPCMn W
WW .100Y.C M.TW
1. All SlaveWW MCUs . 1 0 0 Yare
M .T W WCommunication
.1 M
in UCSRnA is
set). W O W C O
W O
WW .100Y.C M.TW2. The Master WW .100Y.C M.TW WW .100Y. W
M.T and read this frame.
O W MCU sends O an address frame, and W all slaves .C Oreceive
W
WW .100Y.C M.TW In the W
W Y.C RXCn .TW WW will .10be0Yset .TW
Slave W MCUs,
. 100 the O M Flag in UCSRnAW
C as
O Mnormal.
W O
WWMCU 0Y.C theMUDRn
W Y. .TWbeen selected. If
WW .100Y.C M.T3. W Each Slave . 10reads .TW RegisterWand determines W .100 if M
O it has
O W O Y. C
W
WW .100Y.C M.TWso, it clears WW the MPCMn Y.C .TW WW it waits .100 for the .TWaddress byte and
W . 100 bitOinMUCSRnA, otherwise
W C O Mnext
W
WW .100Y.C M.TW
O keeps the MPCMn
WW .1setting. 00Y
W
W O 4. The addressed W O M
MCU will receive all data frames W
W a new .C O
WW .100Y.C M.TThe W WW .100Y.C M.TW Wuntil 00Y
.1set,
address frame
W is received.
M.T the data frames.
other Slave MCUs,
W which O still have the MPCMn W
bit willC O
ignore
W
WW .100Y.C 5.M.T
O
W the last W Y.C .TW WW .100Y. M.T
W
When Wdata
W .
frame100 is received O M by the addressed W MCU, the C Oaddressed MCU sets
W W Y .C O
the W MPCMn bitW W waits
and 0 Y
for
.Ca new .address
T W frame W W
from 0 0
master.
Y. The process .T W then
W 00 .T .10 M .1 M
W W.1 Y.COMrepeats W from 2. WW 00Y.CO .TW W WW 00Y.CO .TW
W 00 .T W .1
W.1 Y OMany of the 5- to 8-bit .1 M WW 00but OM
.C
Using WW character Y .CO frame W formats is W possible, Y.C impractical W since the
W W
. 1 00 Receiver M .T W W
W . 0 .T
10 usingOnMand n+1 character frame W .1 O M.T
W O must change between WW .100Y .C
formats. This makes full-
WW .100duplex Y.C .T W WW .100Y.C M.TW M .TW
W M
Ooperation difficult sinceWthe Transmitter O
Y.Cused, .the
and Receiver uses W the same
WWmust.1be .COcharacter.TW
size set-
WW .10ting. 0Y.CIf 5- M to.T8-bitW character WWframes . 1 00are M TWTransmitter 00Yset to M use two stop bit
W W .C O
W WWbit is00used Y .COfor indicatingW W WW 00Y.CO .TW
W (USBSn
00 Y = 1) since
.T the firstW stop .1 M .T the frame type.. 1 M
W 0 use Read-Modify-Write
.T W 1
Do0not
W.1 Y.COM W W.1 Y.C(SBI
instructions OM and CBI) to set W orW . the MPCMn
clear OM bit. The
W MPCMn bit shares the same W W
I/O location0 as the .T W
TXCn Flag W
and this 0 0Y.Caccidentally
might .T W be
W .10 0 .T .1 0 M . 1 M
W W
cleared .C
when OM using WSBI or CBI WW 00Y.CO .TW
instructions. W WW 00Y.CO .TW
W 0 Y .T W 1
W.1
0
OM W.1 OM W. OM
W O
18.10 Hardware FlowWControl W Y .CO .TW W WW 00Y.CO .TW WW .100Y.C M.TW
W .10 0 .1 M
The
WW hardware .CflowOMcontrol can be enabled
W WW by00software. Y .CO .TW W WW 00Y.CO .TW
Y W
WCTS :W 0
.10 to Send)
(Clear OM
.T
.C W
W
W : (Request
RTS Y
.100 toOSend) M.T
W W
W .100 O M.T
W
W .100 O M.T
W W . C
WW .100Y.C M .TW WW .100Y.C M.TW W .100
Y .TW
W O HOST W C O W W
ATmega8U2/16U .C OM
WW .100Y.C M.TW TXDWW Y. W W .100
Y .TW
W O W .100 O M.T TXD W W .C OM
W Y. C Y .TW
WW .100Y.C M.TW RXD W .100 M.T
WRXD W
W .100 OM
W O W C O W .C
WW .100Y.C M.TW
CTS
WW .100Y. M.T RTS
W
CTS W .100
Y
W O W C O W W
WW .100Y.
RTS
WW .100Y.C M.TW M.T
W W
W O W C O
W
18.10.1 Receiver Flow Control W W .100 O M.T W C O
WW flow.1can .C W WW using Y.
The reception
W
00Ybe controlled
O M.T by hardware W .100the RTS pin. The aim of the flow control
Wexternal Y.C W WW
is to informW the
W .100 transmitter O M.T when the internal receive Fifo is full. Thus the transmitter can
WW .100Y.C M.TW
W O
WW .100Y.C 165
W W
7799D–AVR–11/10 W
.C OM
00Y .TW
W W.1 Y.COM W
W 00 .T
stop sending characters. RTS usage W W.1and so .C OM
associated flow control is enabled using RTSEN bit
in UCSRnD.OM.T
W W . 1 00Y M .TW
Y.C shows WreceptionW WW 00Y.CO .TW
Figure 0 0
18-8. . T a example. .1 M
W 00 .T W .1 M
W.1 18-8.
Figure C OM
Reception Flow Control WW Waveform .COExample
.T W W W
1 00 Y .
M .T W W . 1 0 0 Y
M .TW
M W . O W
FIFO O
.CO .TW WW .100Y.C M.TW WWIndex.100Y.C M.TW
0 1 2 1 0 1
.100Y M W O W O
W O
WW .100Y.C M.TW WW .100Y.C M.TW WW .100Y.C MCPU .TW Read
W O W C O W W .C O
WW .100Y.C M.TW WW .100Y . .TW WRXD .10C1 Y
0 C2 M.C3 TW
W O M W O
W
WW .100Y.C M.TW
O
W O W O
W
WW .100Y.C M.TW
O
RTS
W O W O
W
WW .100Y.C M.TW
O
WRTS behavior O W O
W
WW .100Y.C M.TW
O Figure 18-9.
W O W RXD O Stop W
WW .1Start CO Stop TW
.Byte1
WW .100Y.C M.TW WW .100Y.C M.TW 00Y
Start Byte0 Start Byte2
M .
W O W O
WW .100Y.C M.TW
1 additional byte may be sent
W O
if the transmitter misses the RTS trig
W O W C O
W
WW .100Y.C M.TW
O
WW .RTS Y.C .TW WW .100Y. M.T
W
W 100 O M W C O
W
WW .100Y.C M.TW
O
W
W O W C O
O WW .100Y.
W Read from CPU
W
W O W C O
W
WW .100Y.C RTS
O
W
M will rise at 2/3 of the
W last received
O stop bit if the receive W fifo is O
full.
C
W
WW .100Y.C M.TW
O
W
W O W C O
W O
To ensure reliable transmissions,
WW .100Y.C M.TW
even after a RTS rise, WWan extra-data Y. can.T still
W be received and
WW .100Y.C stored M .TinW
the Receive Shift Register. W .100 O M
W O C
W
WW .100Y.C M.TW
O
W
W O W C O
W
WW .100YFlow
18.10.2 Transmission .CO Control .TW WW .100Y.C M.TW WW .100Y. M.T
W
M W O W C O
W .COtransmission Wbe controlled Y.C by hardware .TW WW Y. W
WW .100Y The
M .TW flow W can
W .100 O M
using the CTS
W .100pin controlled O M.T by the exter-
W O
nal receiver. The aim ofW the
W flow control Y.C is to .stop WW when . C TW
WW .100Y.C M.TW .100 M TW transmission the
Y receiver
.100 CTSEN O M.bit
is full of data
(CTS =
O 1). CTS usage and soW associated O flow control is enabled W using .C in UCSRnD.
W
WW .10The 0Y.C .T W WW 0 0Y.C write . W
Tand WW .100Y M .TW
. 1 M
W W CTS
.C OM pin is
W
sampled at each
WW 00Y.CO .TW
CPU at the
W WW 00Y.CO .TW
middle of the last stop bit that is
W 00 Y
curently being.T sent. W .1 M . 1 M
W 1
W .100 18-10.
WFigure
.T
OM CTS behavior WW.
1
.CO .TW
M .
WW 00Y.CO .TW
M
W W 0 Y .C W W 0 0 Y W 1
0 .T .1 M . M
W W.1 Y.CWrite OM from CPU
W 0 .T W . 1 M
W.1
0
OM W.1 Y.COM W WW 00Y.CO .TW
WW .100Y.C M.TTXD W WWStart .Byte0 0 0 .T W 1
1 Stop M Start Byte1 Stop W. OM
WW 00Y.CO .TW
Start Byte2
W
WW .100Y.C M.TW
O
W WW .100Y.C M.TW
.1 sample M
WW 00Y.CO .TW
WW 00Y.CO .TW
sample sample
W O
WW .100Y.C MCTS .T W W W
W.1 Y.COM W
W W
.100
Y
M.T
W W
W .100 O M.T
W
W .100 O M.T
W O W .C
Y .TW
W W .100
Y .TW
W O W C O W W .C OM
W W .100
Y .TW
W O W C O W W .C OM
W W .100
Y
W O W C O W W
W W
W O W C O
W
W O W C O
W O W
WW .100Y.C M.TW WW
W O
WW .100Y.C M.TW
W O
WW .100Y.C 166
W W
7799D–AVR–11/10 W
.C OM
00Y .TW
W W.1 Y.COM W
W 00 .T
.TW W 00
W.1 Y.COM W
.T
.C OM W
00Y Register W W 00 .T
18.11.1 UDRn – USART I/O.1Data
W O M.T n W W.1 Y.COM W
WWBit .100Y .C 7 .TW 6 W5 040 3 .T
W.1 RXB[7:0]
2 1 0
W C O M W .C OM
WW .100Y . .TW Y W
W 100 .T UDRn (Read)
M .TW O M W . O M
Y.C
O
W WW 00Y.C
WRead/Write .T W WW R/W 1 0 0Y.C M.TW
TXB[7:0] UDRn (Write)
00 .T . 1 M .
W.1 WW0 00Y.C0O .TW
R/W R/W R/W R/W R/W R/W R/W
OM WW .CO .TW
WW .100Y.C M.TW Initial Value 00Y 0
W . 1 M 0 0 W
W.1 Y.COM W
0 0 0
W O W W .C O W
WW .100Y.C M.TW The WUSART 0Y
.10Transmit Data
M .TW Buffer Register W and.1USART
W
00 M.T Data Buffer Registers share the
OReceive
WW .100Y.C M.TW same WI/O address .
Y
100 referred M .TtoWas USART WData Register
W .100 M.T The Transmit Data Buffer Reg-
or UDRn.
O
O W O .C UDRn
W
WW .100Y.C M.TW ister W
W will 0be
(TXB) .C destination
Ythe .TW for data WWwritten .100
toYthe
M.T
WRegister location. Reading the
W . 1 0 O M W C O
W O UDRn Register
W location .C will return the contents W of the Y .
Receive DataW Buffer Register (RXB).
WW .100Y.C M.TW W . 100
Y
M .TW W
W .100 O M.T
O W O .C
W
WW .100Y.C M.TW For 5-, 6-, WW or 7-bit 0characters Y.C .TWupper unused
the WW bits.1will 00Ybe ignored W
M.T by the Transmitter and set to
W . 1 0 O M W C O
W
WW .100Y.C M.TW
O zero by the W Receiver. Y.C
.TW WW .100Y. M.T
W
W
W . 100 O M W C O
W O
WW C be T
Y.only W UDREn Y. .TWUCSRnA Register is set.
WW .100Y.C M.TW The transmit buffer can
. 100 M
W whenWthe
.written W .100 FlagOinMthe
W O W O W set, will .C
WW .100Y.C M.Tter.
Data written toWUDRn when
W Y.C the UDREn .TW
Flag isW not
00Ybe ignored TW
M.is
by the USART Transmit-
When
W
data is W . 100 to the
written O Mtransmit buffer, and W
the .1Transmitter
C O enabled, the Transmitter
W
WW .100Y.C M.will
O
TWload the W
W .C
00YTransmit W
.TShift WW .100Y. M .TW is empty. Then the
data into . 1the M Register when the Shift Register
W O W .CO .TW WW 00Y.CO .TW
WW .100Y.C Mdata .TWwill be serially WW transmitted . 1 00Y onM the TxDn pin. W .1 M
W W .C O
Y W
W 00
W.1 Y.COThe M.Treceive buffer W W.1 of
consists a two
.CO .TW
M level FIFO. The W W.1 will Y
FIFO change M state whenever the
.CO its
W W W 0 Y W 0 0
.1 buffer,Odo M.not TWuse Read-Modify-
W . 1 00 receive
M .T buffer is accessed. W . 10Due toOthis M behavior of the receive W C
W
WW .100Y.C Write
O
.Tinstructions (SBIW and 0CBI) Y.C this .TW
W
Wcareful 0Y. using W
M.Tbit test instructions
M
W W
W . 1 0 onOM location. Be
W .10when
C O
W O and SBIS), since
(SBIC WWthese Y.Cwill change
also
.TW the stateWof the
W FIFO. Y. W
WW .100Y.C M.TW .100 M W .100 O M.T
W O C
W
WW –.10USART
O
0Y.C Control .TW and Status WWRegister Y.C W WW .100Y. M.T
W
18.11.2 UCSRnA M W . 100 A OM.T W C O
W
WW .100YBit .CO .TW WW6 .100Y5.C M.T W WW .100Y. .TW
M 7 4 3 2W 1 OM 0
W O W O
.C FEn W .C
WW .100Y.C M.TW RXCn WTXCn .1UDREn
W 00Y M .TW DORn W UPEnW.100U2Xn Y
M .TW UCSRnA
MPCMn
O W O .C O
W
WW .100Y.C M.TW
Read/Write R R/W W R Y.C R
.TW R WW R
.1000
Y
R/W R/W W
M.T
W
W . 1010 O M W C O
W O WW .100Y .
WW .100Y.C M.TW
Initial Value 0 0 0 0 0 0
WW .100Y.C M.TW M .TW
O W O W .C O
W
WW •.1Bit .C .TW WW Complete Y.C .TW WW .100Y M.T
W
00Y7 – RXCn: M USART Receive
W . 100 O M W C O
W O Wunread Y.C the.Treceive WW Y . .TW
WW This . 1 0Y.Cbit isM
0flag set.TW when thereW are
. 100data in M
W buffer .100 when
and cleared
W O Mthe receive
W
buffer is C
emptyO (i.e., does not W
containW any . C
unread O data). If the W
Receiver is Y
disabled,.C the W
receive
WW .100Y . .TW Y W W .10 0 M.T
M
W
W .100 O M .T W C O
W
buffer will be Oflushed and consequently the RXCn bit will become WW .100Y
zero. The RXCn . Flag canW be
WWused.1to00generateY.C .T W WW .100Y.C M.TW M .T
W OMa Receive Complete Winterrupt (see O description of theW W
RXCIEn bit).
.C O
WW .100Y.C M.TW WW .100Y.C M.TW W . 1 00Y M.T
W
W O W O W W .C O
•W Y.C USART W TransmitWComplete W Y.C W W .100
Y
M.T
W
W Bit 6 –0TXCn:
W .1 0 O M.T W .100 O M.T W W .C O
WWflag.bit
This C whenTthe
is .set . W entire frame WW in the Y.C
Transmit Shift W RegisterW has been 0Y
.10shifted out TW
M.and
W 1 00Y
thereWare no new Y.Cdata currently W present WW in the transmit Y.C buffer (UDRn). The
W W TXCn.1Flag 00Ybit is auto- M.T
W
W
maticallyWcleared .100 when O M.aTtransmit complete W .100
interrupt isO M.T
executed, or it can be
W Wcleared C
by
. Owriting
.C WW .1generate .C TW Y W
a oneWWto its.1bit 00Ylocation. W
M.TThe TXCn FlagWcan 00Y Ma .Transmit Complete
W
W 100
.interrupt M.T
O(see
W O W C O W .C
WW of.1the .C TW Y. W W .100
Y .TW
description
W
00YTXCIEn
O M.bit).
W
WW .100Y. C Y
WW .100Y.C M.TW M.T
W W
W .100
W O W C O W
• Bit 5 – W UDREn: USART
0Y.C M.TW
Data RegisterW Empty
W Y. W W
The UDREn
W
Flag
W .10indicates O if the transmit buffer W .100 is ready
(UDRn) O M.Tto receive new data. If UDREn
Y.C WW .100Y. C W
is one, the WW buffer .1is00empty,Oand
W
M.Ttherefore readyWtoWbe written. M.TUDREn Flag can generate a
The
W .C O
WW Empty Y.C .TWdescription W of the.1UDRIEn 00Y bit).
Data Register
W .100interrupt O M(see W
WW 0Y.Cto indicate W WW
UDREn is set after W .a10reset O M.T that the Transmitter is ready.
WW .100Y.C M.TW
W O
WW .100Y.C 167
W W
7799D–AVR–11/10 W
. C OM
00Y .TW
W W.1 Y.COM W
W 00 .T
• Bit 4 – FEn: Frame Error WW.1 .C OM
This bit is set Mif .TWnext character
the
W
in .
the
Y
100receive M .TW had a Frame Error when received. I.e.,
buffer
W O
.CO .TW WW Y.C .TW buffer is zero. This bit is valid until the
when . 1 0the0Yfirst stopM bit of the next character
W . 100 in theOreceive M
W O WFEn bit Y.C
WW receive0buffer
. 1 0Y.C (UDRn) M .TWis read. W The . 100 is zero M .TW the stop bit of received data is one.
when
O W O
WW set
WAlways 00Y
.C bit to.T
this zero
W when writing WW to .UCSRnA. 100
Y.C .TW
M .TW . 1 O M W O M
.CO .TW WW 00Y.C W WW .100Y.C M.TW
.100Y M
W
• Bit W 3 –.1DORn: O DataM .TOverRun W O
W O
WW .100Y.C M.TW WWbit is.1set
This 00Y
.C
if a Data .T W
OverRun WW is .detected.
condition 1 0 0Y.C AM .TWOverRun occurs when the receive
Data
W O M W O
W O
WWis full.10(two 0Y.Ccharacters), WWcharacter Y.C TW
WW .100Y.C M.TW buffer M .TW it is a new W . 100 waiting O M .in the Receive Shift Register, and a
W O W W . C O W Y .C W(UDRn) is read. Always set this
WW .100Y.C M.TW newW start bit is00detected.
. 1
Y
M
This
.TW bit is valid Wuntil the
W .100
receive buffer
O M.T
W O
W
WW .100Y.C M.TW
O bit to zero when writing to UCSRnA.
W O W O
W O
WW .100Y.C M.TW • Bit 2W– UPEn:
W 0 0 Y.C Parity
USART .T WError WW .100Y.C M.TW
W. 1 OM W O
W O
is W Y.C character WW buffer Y.C a Parity W
WW .100Y.C M.TW This bit W set if the . 1 0 0next M .T W in the receive
W . 1 0 0had
O M.T Error when received and the
O W O .C
W
WW .100Y.C M.TWParity Checking WW was Y.C W point (UPMn1 WW =.101). 0YThis W until the receive buffer
.Tvalid
W . 100enabled O M
at
.Tthat W C O
bit
Mis
W O (UDRn) is W read.W Always .C this bit
Yset to zero when WW writing 0to .
YUCSRnA. W
WW .100Y.C M.TW . 100 M .TW W .1 0 O M.T
W O C
W O
WW .100Y.C M.T•WBit 1 – U2Xn: WW Double Y.C .TWTransmission WW .100Y. .TW
W . 100 the O M
USART WSpeed .COM
W O C WW .1Write W
WW .100Y.C M.This TW bit only W
W
has effect . 0Y.the
10for .TW
asynchronous
M operation. 00Y this M bit.Tto zero when using syn-
W O W C O
W O
WW .100Y.C Mchronous .TW WW .100Y.C M.TW
operation. WW .100Y. M.T
W
W O W C O
W O
WW .100Y.C Writing .TW this bit toWone W
W .C
00Y theMdivisor
will.1reduce .TW of the baud WW rate.10divider 0Y. from M.T
W
16 to 8 effectively dou-
M O W C O
W O
WW .100Y.C bling W transferW W for asynchronous Y.C W WW .100Y. M.T
W
M .Tthe rate
W . 100 O M .Tcommunication. W C O
W
WW .100Y.C M.TW
O
W
• Bit 0 – MPCMn: W
Multi-processor O Communication Mode W C O
W
WW .100Y.CThisM
O
W
.Tenables WW .100Y.C M.TW WW .100Y. W
M.T bit is written to
bit the Multi-processor
W OCommunication mode. WWhen the C O
MPCMn
W
WW .100Y.one,CO TWincomingW
W Y.C .TW WW .100Y. W
M.T address infor-
all
M .the frames W . 100
received by
O M the USART ReceiverW that do not C O contain
W .CO will W Transmitter Y.C is unaffected .TW
W Y. .TW
WW .100Y mation
M .TW be ignored.WThe
W .100 O M by W the MPCMn
W .100 setting. O MFor more detailed
W .C O W .C W W Y .C W
WW .100information
Y
M .Tsee
W “Multi-processor W
W . 00Y
1Communication O M .T Mode” onWpageW .100
164.
O M.T
W O WW .100Y .C
WW USART Y.C W WW .100Y.C M.TW M.T
W
18.11.3 UCSRnB – W .100 Control M .Tand Status Register W n B O W .C O
WW .1Bit .CO .TW WW .100Y.C M.TW WW .100Y .TW
00Y M 7 6 W 5 O 4 3 2 W 1 .C O M0
W O Y.C WW RXB8n Y W
WW .100Y.C MRXCIEn .TW TXCIEn WW UDRIEn . 100 RXENn M .TW TXENn UCSZn2 .100 TXB8n M.T UCSRnB
O W O W .C O
W
WW Read/Write .C .TW R/W WW R/W 00Y. R/W
C W WW .R100Y R/W M.TW
. 1 00Y M
R/W
W . 1 O M .TR/W R/W
W0 O
WInitial Value .C O 0 0 W0 Y .C
0 0W 0 WW 0 Y.C0 W
W W
. 1 0 0 Y
M .T W W
W .1 0 0
O M .T
W . 1 0
O M.T
W O Y.C WW .100Y .C W
WW• Bit.1700–YRXCIEn: .C .TRX W Complete WW Interrupt . 100 Enable M n.T
W M.T
O M W O W W .C O
WW this
WWriting .C
00Ybit to one W
.Tenables WW on.1the
interrupt
.C
00YRXCn M .TWA USARTW
Flag. Receive 00Y
.1Complete M .TW
interrupt
WW
will be generated Y.C only .TW if the RXCIEn WWbit is.1written 00Y to M
.C one, .TW the GlobalW Interrupt 0Y in SREG
.10Flag M.T is
W
W
W . 100 O M W O W W .C O
WW .100Y.C M.TW
written to one and the RXCn bit in UCSRnA WW .1is00set. Y.C W W .100
Y
M.T
W
W O W O M.T W W .C O
W Y.C TX Complete W WW Enable Y.C W W .100
Y .TW
•W Bit 6 – TXCIEn:
W .100 O M.T InterruptW .100 n OM.T W W .C OM
Y.C WWthe TXCn Y. C Y .TW
WWthis .bit
Writing 100to oneOenables
W
M.T interrupt on W .100 Flag. .TW Transmit
A USART
M
W Complete
W .100 interrupt OM
W W C O W .C
will be WW generated .C if the
Yonly W TXCIEn bitWis written Y.
.100to one,Othe
W
M.TGlobal InterruptWFlag
W Y
.10in0 SREG is.TW
W .100 O M.T W C W .C OM
writtenWto Wone and .C TXCn.Tbit
Ythe Win UCSRnA WWis set..100Y. M.T
W W .100
Y
W .100 O M W W .C O W W
W Y.C .TW RegisterWEmpty 00Y M.T n
W W
• Bit 5W – UDRIEn: W .100 USART O MData W .1Interrupt
C O Enable
WWbit to.1one .C TW WW Y. W
Writing this
W
00Yenables
O M.interrupt on the UDREn W .100Flag. AOData M.T Register Empty interrupt will
C WW .the Y. C
be generated WWonly.1if0the 0Y.UDRIEn W
M.Tbit is written to one, 100Global Interrupt Flag in SREG is written
W O W
to one and W the WUDREn bit.Cin UCSRnA
Y W is set. WW
W .100 O M.T
WW .100Y.C M.TW
W O
WW .100Y.C 168
W W
7799D–AVR–11/10 W
.C OM
00Y .TW
W W.1 Y.COM W
W 00 .T
• Bit 4 – RXENn: Receiver Enable W W.1n Y.COM W
W W 00 .T
Writing this bit OM to.T one enables the USART W.1 Receiver. C OM The Receiver will override normal port oper-
. C W 0Y . .TWReceiver will flush the receive buffer
ation.10for 0Ythe RxDn M .TW pin when W enabled. W . 10Disabling O M the
W .C O W Flags. Y.C
WW invalidating
1 00Y the FEn, M
W
.TDORn, andW UPEn . 100 M .TW
W . O W O
M • Bit 3 – TXENn: O Transmitter Enable Wn O
Y.C
O
0 0 .T 1
. bit to one M enables the USART O The Transmitter will override normal port
W.1 OM WritingWthis
.CO .TW WW The
WTransmitter. Y.C TW
WW .100Y.C M.TW WW .1for
operation 00Y the TxDn M pin when enabled. . 1 0 0disabling M .of the Transmitter (writing TXENn to
W O W O W W .C O
W Y.C W W
zero) Wwill not 0 Y .C
become T W
effective
. until Wongoing 0
and 0 Y pending .T W
transmissions are completed, i.e.,
W .1 00 M .T . 1 0 M W . 1 O M
WW .100Y.C M.TW when Wthe Transmit 0Y ShiftMRegister
.10disabled, .TW and Transmit W Buffer Register
.100
Wlonger
.T do not contain data to be trans-
OM the TxDn port.
W O mitted. W W
When .C O the Transmitter will W no Y .C
override W
WW .100Y.C M.TW W . 100
Y
M .TW W
W .100 O M.T
W O
W O
WW .100Y.C M.TW • Bit 2W– UCSZn2:
W Y.C .TW WW .100Y.C M.TW
. 100 Character M Size n
W O W Y.C
O
WW bit
W .CO .TW
0YUCSRnC
WW .100Y.C M.TW The UCSZn2 WW bits . 1 0 0
combined M .T
withW the UCSZn1:0 . 1 0 in M sets the number of data bits
W .C O WW in0a0Y .CO the.TReceiver W W WW 00Y.use. CO W
W W
. 1 00 Y
M .TW (Character W SiZe)
W . 1 frame
O M
and Transmitter
W .1 O M.T
W O WW .100Y. C
W
• Bit 1 – RXB8n: W Receive O
Data Bit 8 n W C O
W
WW .100Y.C M.TRXB8n
O
W W Y.C TW WW .100Y. TW
M.with
is the
Wninth
W . 100 bit of O
data the M .received character when
W O
operating
C serial frames with nine
W O WW .
WW .100Y.C M.data TW bits. Must WW be read . 1 0Y.C reading
0before M .TWthe low bits from . 1 00Y
UDRn. M .TW
W O W O
W
WW .100Y.C M.TW
O
W O
W O • Bit 0 – TXB8n: W
W Transmit
W .CO Bit .8TW
Data n WW .100Y.C M.TW
WW .100Y.C M.TW .1 00Y M W O
OTXB8n is the ninth W W bit inYthe Ocharacter to be transmitted .Coperating
W
WW .100Y.C with .T W W
data
0 0 .C M.TW WW .1when 00Y M.T
Wwith serial frames
M nine data bits. Must W .
be1 written Obefore writing the low W
bits to UDRn.C O
W
WW .100Y.C M.TW
O
W
W O W C O
W
WW .1–00USART
O
Y.C Control .TW and Status WW Register Y.C .TW WW .100Y. M.T
W
18.11.4 UCSRnC
M W .100 n C O M W C O
W O W 2 00Y. 1
WW .100Y.CBit M.TW 7 WW 6 .100Y.C5 M.TW 4 3 W
.1 M.T 0
W
W O W C O
W .CO .TWUMSELn1 WUMSELn0 W Y.C
UPMn1
.TW
UPMn0 USBSn WW UCSZn1 Y.
UCSZn0 UCPOLn W UCSRnC
WW .100YRead/Write M W .100 R/W OMR/W W .100 R/W OM.TR/W
W .CO .TW
R/W R/W
Y.C
R/W R/W
WW1 .100Y1 .C W
WW .100Y WW .100 0 OM0.T
W M.T
Initial Value
O M 0 0
W 0 W .C O 0
W
W
O – UMSELn[1:0] USART W O W .C O
W
WW .•10Bits 0Y.C7:6 M .TW WW .10Mode 0Y.C Select .TW WW .100Y M.T
W
O W O M W .C O
W These bits select the mode of W
WW .100Y.C M.TW W operation Yof.Cthe USARTn
.TW
as shown WWin Table.100
18-4.. .TW
Y
W . 100 O M W OM
W W Table
. 1 0 0 Y
18-4.
M
UMSELn
.T W Bits W
Settings
W . 1 0 0
O M .T
W . 10
O M.T
W O W Y.C WW .100Y .C W
WW .100UMSELn1 Y.C .TW WUMSELn0 .100 M .TW
Mode M.T
O M W O W .C O
W
WW .100Y.C0 M.TW WW 0 .100Y.C Asynchronous .TW WW
USART W.10
0Y M.T
W
W O W O M W .C O
WW .100Y0.C M.TW WW1 .100Y.C Synchronous M .TW USART
W .100
Y
M.T
W
W O W O W W .C O
WW .100Y .C W W0W .100Y.C (Reserved) M.T
W W .100
Y
M.T
W
W 1 O M.T W O W W .C O
Y
M.T
W
W O 1 W MasterO SPI (MSPIM) (1)
W W .C O
Y .TW
W O W C O W W .C OM
Note:WW 1. .See Y.C W Mode” onW W 176 0for0Yfull . description W
M.T of the MasterW
W SPI Mode Y
.100 (MSPIM) .TW
W 100 “USART O M
in.T SPI page
W .1
C O W .C OM
WW .100Y.C M.TW
operation WW .100Y. M.T
W W .100
Y .TW
W O W C O W W .C OM
W Y.C Parity W WW .100Y. M.T
W W .100
Y
• BitsW5:4 – UPMn1:0:
W .100 O M.T Mode W C O W W
These W bitsWenable00and Y.C set type W WW .10and 0Y. check. W W
M.TIf enabled, the Transmitter will
W .1 O M.T of parity generation W C O
automatically WW generate Y.Cand send Wthe parityWofWthe transmitted Y. dataW bits within each frame. The
W .100 O M.T W .100 O M.T
WW .100Y. C
WW .100Y.C M.TW
W O W
WW .100Y.C M.TW WW
W O
WW .100Y.C M.TW
W O
WW .100Y.C 169
W W
7799D–AVR–11/10 W
.C OM
00Y .TW
W W.1 Y.COM W
W 00 .T
Receiver will generate a parity value W W.1for the .C OM
incoming data and compare it to the UPMn setting.
If a mismatch is .T W
detected, the
WUPEn .
Flag1 0 Y
0in UCSRnA M . TWwill be set.
.C OM WW 00Y.CO .TW
00 Y W W
W.1 18-5.
Table M.T Bits Settings WW.1
OUPMn .CO .TW
M
W Y .C W W 0 Y
W 00
W.1 UPMn1 OM
.T .10 M
W Y .C W UPMn0W WW 00YParity .CO Mode .TW
.T W W . 1 00 M .T . 1 M
M W O W O
.CO .TW WW .1000Y.C M.TW 0 WW Y.C
Disabled .TW
.100Y M W . 100 O M
W O
W O
WW .100Y.C M.TW WW .1000Y.C M.TW 1 WW
. 0Y.C M.TW
10Reserved
W O W O
0 WW
W .CO .TParity
WW .100Y.C M.TW WW .1100Y.C M.TW . 00Y Even
Enabled,
1 M
W
W O W O
W O
WW 1 .100Y.C M.TW 1 WW Enabled, Y.C Odd Parity W
WW .100Y.C M.TW W .100 O M.T
W O
W
WW .100Y.C M.TW
O
W O W O
W
WW .100Y.C M.TW
O • Bit 3 –W
W
USBSn: Y
0 0 .C Bit .Select
Stop
T W WW .100Y.C M.TW
This bit selects 1
W. the number OMof stop bits to beW W
inserted by.C O Transmitter. The Receiver ignores
the
W O
WW .100Y.C M.TW this setting. WW .100Y.C M.TW W . 1 00Y M.T
W
W O W C O
W
WW .100Y.C M.TW
O
W
W O W C O
W
WW .100Y.C M.TW
O Table 18-6. WWUSBS Bit C
Y.Settings .TW WW .100Y. M.T
W
W . 100 O M W C O
W
WW .100Y.C M.TW
O
WWUSBSn Y.C .TW Stop Bit(s) WW .100Y. M.T
W
W . 100 O M W CO
W
WW .100Y.C M.TW
O
WW 0 .100Y.C M.TW1-bit WW .100Y. M.T
W
W O W C O
W
WW .100Y.C M.TW
O
WW1 .100Y.C M.TW 2-bit WW .100Y. M.T
W
W O W C O
W
WW .100Y.C M.TW
O
W
W O W C O
W
WW .100Y.C M.TW
O• Bit 2:1 – UCSZn1:0: Character Size
The UCSZn1:0 bits W
combined withO the UCSZn2 bit in W
UCSRnB sets
C O the number of data bits
W O
WW .100Y.C (Character .T W SiZe) inWaW 0
.C
0YReceiver .TandW WW .100Y. M .TW
frame . 1the M Transmitter use.
W O
W OM W O
WW .100Y.C M.TW
W O
W O 18-7. UCSZn Bits
Table W
WW Settings .CO .TW WW .100Y.C M.TW
WW .100Y.C M.TW . 1 00Y M
W O W O WWCharacter .CO .TW
WW .100Y.C UCSZn2 T W WW UCSZn1 0 0Y.C M.TWUCSZn0 W 1 00Y Size
OM 0
. .1
WW
. OM
W .C WW0 00Y.CO .TW 0 W 0 Y.C W
W W
. 1 00 Y
M .T W W
W .1 O M
5-bit
W .1 0
O M.T
W O 0 WW6-bit.100Y .C
WW .100Y.C M .TW WW 0 .100Y.C M.TW 1 M.T
W
O W O W .C O
W
WW .100Y.C 0M.TW WW1 .100Y.C M.TW0 WW 7-bit .100Y M.T
W
W O W O W W .C O
WW .100Y.C 0 M.TW WW Y.C .TW W8-bit .100
Y
M.T
W
1
W . 100 O M 1
W C O
W O W .
WW .100Y.C1 M.TW W0W .100Y.C M.T0W W
Reserved .100
Y
M.T
W
O W O W .C O
W
WW .100Y.C .TW
W Y.C W WW .100Y M.T
W
1 M
W0
W .100 O M 1.T Reserved W C O
W O W Y.C WW 0Y . W
WW .100Y1.C M.TW 1W . 100 M 0 .T
W
ReservedW.10 O M.T
W O W O W .C
WW .1001Y.C M.TW WW .100Y.C 1M.TW W .100
Y
M.T
W
W O 1 W O 9-bit
W W .C O
Y
M.T
W
W O W O W W .C O
W 0 – UCPOLn:
•WBit Y.C ClockW PolarityWW .100Y.C M.TW W .100
Y
M.T
W
WW
This bit is used C synchronous
.for .TW mode WW only. Write Y.Cthis bit .toW zero whenWasynchronous .100 mode
Y
M.Tis
W
W . 1 00Y
O M W .100 O MT W W .C O
used.W The UCPOLn Y.C bit sets the relationship WW between C
Y. data output W change W and data input Y sample,.TW
W .100
W
M.T (XCKn). W .100 O M.T W .100 OM
and the synchronous
W Oclock
WW .100Y. C W Y.C .TW
WW .100Y.C M.TW M .T W W
W . 1 0 0
OM
W O W C O W .C
TableW W
18-8. Y.C Bit .Settings
UCPOLn W WW .100Y. M.T
W W .100
Y
W .100 O MT W C O W W
WW .10Transmitted 0Y.C M.TData W Changed WW .100Y. Received W
M.T Data Sampled
W
W O W C O
UCPOLn
WW .100Y.C M.TW
(Output of TxDn Pin)
WW .100Y. (Input M.T
on WRxDn Pin)
W O W C O
0
WW .100Y.C M.TW
Rising XCKn Edge WW .100Y. Falling XCKn Edge
W O W
1
WW Falling 00Y
.C Edge
XCKn
.TW WW Rising XCKn Edge
W . 1 O M
WW .100Y.C M.TW
W O
WW .100Y.C 170
W W
7799D–AVR–11/10 W
.C OM
00Y .TW
W W.1 Y.COM W
W 00 .T
18.11.5 UCSRnD – USART Control and Status Register W Wn.1 D . C OM
.TW Y W
M
W
W . 100 4 OM.T3
Bit O 7 6 5 2 1 0
0 0 Y.C .T W WW - .100Y.-C M.T- W
W.1 Y.COR/W M- - - CTSEN RTSEN UCSRnD
W W W W W
0 Y .CO R/W .T W
W .100
Read/Write
O0M
.T R/W R/W
.10 R/W
OM0
R/W R/W R/W
WValue C W 0 W 0 Y.C
.T W W WInitial
1 00 Y .
M .T W 0
W . 1 0 0 M .TW 0 0 0
M . O W O
.CO .TW WW Y.C : USART .TW CTS Enable WW .100Y.C M.TW
.100Y M • Bits 1.1–00
W CTSEN M W O
W O
W O
WW .100Y.C M.TW WW
Set this bit to
0 0 Yone
.C by firmware .T W to enable WWthe transmission
. 1 0 0Y.C Mflow .TWcontrol (CTS). Transmission is
W . 1 O M W O
W
WW .100Y.C M.TW
O
WW if CTS
allowed 00Y =.C 0. .TW WW .100Y.C M.TW
. 1
W to zero O M W O
W
WW .100Y.C M.TW
O Set W thisWbit 0 0 Y.C by firmware . T W to disable WW the transmission
. 1 0 0Y.C M .TW
flow control (CTS). Transmission is
W . 1 O M W C O
W O always W
allowed. .C W Y . W
WW .100Y.C M.TW W . 100
Y
M .TW W
W .100 O M.T
W O
W O
WW .100Y.C M.TW • BitsW
W Y.C W WW .100Y.C M.TW
0 – RTSEN . 100 : USART M .TRTS Enable
W O W W .C O WW 00Y.CO .TW
WW .100Y.C M.TW Set this W bit to one 1 0 0
by Yfirmware
M .TtoWenable theWreceive .1flow control M(RTS).
W .C O WzeroW. Y .CO .to W WW flow 0 .CO (RTS).
Ycontrol W
W Y W Set this bit
W to by 0 firmware T disable the W receive .1 0 M.T
W . 1 00 M .T W . 10 O M W C O
W
WW .100Y.C M.TW
O
W
W O W C O
W
WW UBRRnL .CO .TW WW Baud Y.C .TW WW .100Y. M.T
W
18.11.6 . 1 00Y and M UBRRnH – USART W . 100 RateORegisters M W C O
W
WW .100Y.C M.TBitW
O
WW15 .100Y14.C M.13 TW WW .100Y. .TW
12 11 W 10 OM 9 8
W Y . W W 0 Y .T W W 0 0 .T
W .100 M.T .10 W.1 Y.COM W
– – – – UBRR[11:8] UBRRnH
W C O W W . C OM W
WW .100Y. M .TW W .1060
Y
M .TW UBRR[7:0] W
W .1002 O M.T
UBRRnL
W O C
W
WW .100Y.C Read/Write
O
.TW
7
W Y.C 5
TW R
4
WW .100Y.
3 1
M.T R/W
W 0
M
W R
W . 1R00 ORM. R/W W R/W
C O R/W
W O
WW R/W Y.C WW R/W Y. R/W .TWR/W
WW .100Y.C M.TW R/W
. 100 R/W M .TWR/W R/W .100 M
W .C O 0 WW 0
W Y .C0 O
W 0 WW
W
0 00Y.
CO0 W0
W M.T
Y Initial Value W 0 T 0
W 1 00 M .T .10 M . W .1 O
. W O C
W
WW .100Y.C M.TW
O 0
WW .100Y.C M.TW
0 0 0 0
WW .100Y. 0 0
M .TW
0
W O W O
W
WW .100Y CO
• . Bit 15:12 .T W– Reserved WW Bits 0 0Y.C M.TW WW .100Y.C M.TW
.1 W O
W OM WW O
Y.C For compatibility WWfuture 0Y.C M .TWbit must be
WW .100These Y.C bits.Tare W reservedWfor future
.1 0 0use. M . TW with . 1 0devices, these
M
O zero when UBRRH W O W .C O
W
WW .10written 0Y.C to M .TW WWis written. Y.C .TW WW .100Y M.T
W
W . 100 O M W C O
W O WW .100Y .
WW .•10Bit 0Y.C TW
.UBRR[11:0]: WW .100Y.C M.TW M.T
W
11:0 O M– USART W Baud Rate O Register W .C O
WW This
W .C W WWcontains Y.C .TWbaud rate. WW .100Y W
M.T the four
. 1 00Y is a 12-bit M .Tregister which W . 100 the USART O M TheW UBRRH C contains
O
W O W Y.C the eight WW .bits Y . W
WW most Y.C
00significant W and the W
bits,
.T UBRRL .contains100 M .TW least significant 100 of theOUSART M.T baud
. 1 O M W O W .C
W
WW rate..1Ongoing .C transmissions .TW byWthe W Transmitter Y.C and .Receiver TW will WbeW corrupted Y
.100 if theObaud
W
M.T rate is
00Y M W .100 O M W C
W
changed. O
Writing UBRRL will trigger Y.C update WWrate .prescaler. . W
WW .100Y.C M.TW WW an .immediate100 M .TW of the baud 100
Y
M.T
O W O W W .C O
WW 00Y.C .TW WW .100Y.C M.TW W .100
Y
M.T
W
18.12 Examples ofW Baud . 1
Rate SettingO M W O W W .C O
WW 00Y.C TWresonatorWfrequencies,
W Y.C W W Y
.100rates O .TW
WFor standard
W .1 crystal
O M.and W .100 theOmost M.T commonly used W Wbaud .C forMasyn-
WW .1operation .C W generated WW Y.C W W Y
.10to0 TableO18-12. M.T
W
chronous
W
00Y
O
can
M .Tbe by using
W .100the UBRR O M.Tsettings in TableW18-9 W .C
.C yield WW rate.1differing .C less.Tthan W 0.5% from Y .TW
WW values
UBRR
.100
Y
which
M.T
Wan actual baud
W
00Y
O M
W the target
W .100 baud OM rate,
W O Y. C W Y .C W
areW W in the
bold
00Y
.C Higher
table.
.TWerror ratings WWare .acceptable, 100
but W
M.T
the Receiver W will have .100 less noise M.T
resistance W . 1 O M
when the error ratings are high,W W C O W W .C O
WW .100Y.C M.TW W especially Y.for large.Tserial
.100 are calculated
W framesW(see “Asynchronous Y
.100equation: .TW
Operational W Range” C onOpage 163). The error W
values C O M using the W
following
W .C OM
WW .100Y. W WW .100Y. M.T
W W .100
Y
W O M.T W C O W W
W W
W O BaudRate W C O
WW .100Y.C Error[%] W =  -------------------------------------------------------
WWClosest Match Y.  .TW
.100 - – 1OM100%
W O M.T BaudRate W
W O W
WW .100Y.C M.TW WW
W O
WW .100Y.C M.TW
W O
WW .100Y.C 171
W W
7799D–AVR–11/10 W
.C OM
00Y .TW
W W.1 Y.COM W
W 00 .T
W W.1 Y.COM W
.TW W 00
W.1Oscillator OM
.T
Table 18-9. Examples of UBRRn Settings
.C OM for Commonly Used W Y .C Frequencies
W
fosc = 1.0000. 1 00Y
MHz M .TW W
f = W .
1.8432 100 MHz OM.T fosc = 2.0000 MHz
W O osc W .C
Baud WW .100Y.C M.TW W . 1 00Y M .TW
U2Xn = 0 W U2Xn = 1O U2Xn = 0 WW U2Xn .CO =1 U2Xn = 0 U2Xn = 1
Rate
.T W WW .100Y.C M.TW W . 1 00Y M .TW
(bps) OM UBRR Error W
UBRR Error O UBRR Error WW UBRR Y.CError O UBRR Error UBRR Error
0 0 Y.C .T W WW .100Y.C M.TW W . 1 00 M .TW
.1 M W O W O
W 2400 O 25 0.2% 51
WW .100Y.C M.TW
0.2% 47 0.0% W 95 Y.C0.0% .TW51 0.2% 103 0.2%
WW .100Y.C M.TW W
W . 100 O M
W 4800 O 12 25W O 0.0% WW 47 .C
WW .100Y.C M.TW
0.2% 0.2% 23 Y0.0% 25 0.2% 51 0.2%
WW .100Y.C M.TW . 100 M .TW
O W O
W9600 O6 -7.0%
W12 WW 0.2% Y.C 11 W 0.0% WW23 Y .C
0.0% 12W 0.2% 25 0.2%
WW .100Y.C M.TW . 100 M .T W .100 O M.T
O W O Y.C
W
WW .100Y.C M.TW
14.4k 3 8.5% 8W -3.5% Y.C 7 .TW 0.0% WW 15
.100
0.0%
M.T
8W -3.5% 16 2.1%
W
W . 100 O M W C O
W
19.2k 0Y.C2 O W .C 5 .TW0.0% W Y . W
WW 8.5%
W 6W -7.0%
.100
Y W11 00
0.0% 6.T -7.0% 12 0.2%
W .10 O M.T W .C O M W W.1 Y.COM W
W Y.1C W W 8.5%00Y 3 .TW W 00 3 .T
W28.8k .100 M.T
8.5% 3W
.1
0.0% 7 0.0%
W.1 Y.COM W
8.5% 8 -3.5%
W C O W W .C OM W
W
38.4k Y1. -18.6%W 2 W 8.5%100Y 2 W
.T0.0% 5W 00
0.0% 2 .T 8.5% 6 -7.0%
W
W .100 O M.T W .
.C OM W W.1 Y.COM W
C W TW
WW .1000Y.
57.6k 8.5%
M.T
W 1 W 8.5% .100Y 1 .0.0% 3W 00
W.1 Y.C1OM 8.5%
0.0% .T 3 8.5%
W C O W W .C OM W W
W Y. W W -18.6% .10 1 0 Y .T W W 0.0%.1 0 0 .T
W
76.8k 0–0 – .T 1 -25.0%
M 2 1 M -18.6% 2 8.5%
W
115.2k –00 – .T 0 W8.5% .1 0 0.0%
M 1 0.0% .1 0 M 8.5% 1 8.5%
W – 00 .T – W 0.0%W.1
230.4k
W.1 Y.COM W
– – .1 – M– 0 – OM – – –
W W WW 00Y.CO .TW W W 0 0 Y.C .T W
250k W – .100 – M.T – – .1– –M – – W.1 – .COM– 0 0.0%
W W Y .C O
1 00Y .TW
(1) W 00 .T . 1 M . M
Max. W.1 kbps OM 125 kbps
62.5 W115.2 kbpsO 230.4 kbps WW CO
125 .kbps 250 kbps
WW .100Y.C M.TW WW .100Y.C M.TW W . 100Y M .TW
W O W O
WW .100Y.C M.TW
1. UBRR = W 0, Error = 0.0%
O
W O W O
W
WW .100Y.C M.TW
O
W O W O
W
WW .100Y.C M.TW
O
W O W O
W
WW .100Y.C M.TW
O
W O W O
W
WW .100Y.C M.TW
O
W O W O
W
WW .100Y.C M.TW
O
W W .C O
Y W
W
.C W
WW .100Y M .TW W
W . 100 O M .T W
W .100 OM
.T
WW .100Y M .TW W
W .100 O M .T W .10 O M.T
W O WW .100Y .C
W
W O W O W W .C O
Y
M.T
W
W O W O W W .C O
Y
M.T
W
W O W O W W .C O
Y
M.T
W
W O W O W W .C O
Y .TW
W O W C O W W .C OM
W W .100
Y .TW
W O W C O W W .C OM
W W .100
Y .TW
W O W C O W W .C OM
W W .100
Y
W O W C O W W
W W
W O W C O
W
W O W C O
W O W
WW .100Y.C M.TW WW
W O
WW .100Y.C M.TW
W O
WW .100Y.C 172
W W
7799D–AVR–11/10 W
.C OM
00Y .TW
W W.1 Y.COM W
W 00 .T
W W.1 Y.COM W
.TW W 00
W.1Oscillator OM
.T
.C OM for Commonly Used W Y .C Frequencies (Continued)
W
0Y W W .100 M.T
fosc = 3.6864 MHz W.10 O M.T fosc = 4.0000 MHz W O fosc = 7.3728 MHz
Baud WW .100Y.C M.TW WW .100Y.C M.TW
U2Xn = 0 W =1 O
U2Xn U2Xn = 0 W U2Xn = 1 O U2Xn = 0 U2Xn = 1
Rate
.1
W 2400 O 95 M 0.0% W
191 0.0% O 103 0.2% W 207 Y.CW O
0.2% 191 0.0% 383 0.0%
WW .100Y.C M.TW WW .100Y.C M.TW W . 100 M .TW
W 4800 O 47 95W O W
0.2% WW 103 0Y0.2% .C O
WW .100Y.C M.TW
0.0% 0.0% 51 95 0.0% 191 0.0%
WW .100Y.C M.TW . 10 M .TW
O W O
W9600 O23 0.0%
W47 WW 0.0% Y.C 25 W 0.2% WW51 Y .C
0.2% 47W 0.0% 95 0.0%
WW .100Y.C M.TW . 100 M .T W .100 O M.T
O W O Y.C
W
WW .100Y.C M.TW
14.4k 15 0.0% 31W 0.0% Y.C 16 .TW 2.1% WW 34
.100
-0.8%
M.T
31W 0.0% 63 0.0%
W
W . 100 O M W C O
W
19.2k 0Y.C O W .C
Y 12 .TW0.2% W Y . W
WW 11 0.0%
W 23
W 0.0%
.100
W25 00
0.2% 23.T 0.0% 47 0.0%
W Y.7C W W 0.0%00Y 8 .TW W 00 15 .T
W28.8k .100 M.T
0.0% 15 W
.1
-3.5% 16 2.1%
W.1 Y.COM W
0.0% 31 0.0%
W C O W W .C OM W
W
38.4k Y5. 0.0%W 11 W 0.0%100Y 6 W
.T-7.0% 12W 00
0.2% 11 .T 0.0% 23 0.0%
W
W .100 O M.T W .
.C OM W W.1 Y.COM W
C W TW
WW .1003Y.
57.6k 0.0%
M.T
W 7 W 0.0% .100Y 3 .8.5% 8W 00
W.1 Y.C7OM 0.0%
-3.5% .T 15 0.0%
W C O W W .C OM W W
W Y. W W 0.0% .10 2 0 Y .T W W .1 0 0 .T
W
76.8k 020 0.0%.T 5 M8.5% 6 -7.0% 5 M 0.0% 11 0.0%
W
115.2k 100 0.0% .T 3 W0.0% .1 1 8.5%
M 3 8.5% .1 3 M 0.0% 7 0.0%
W 0 00 0.0% .T 1 W 8.5%W.1
230.4k
W.1 Y.COM W
0.0% W.1 0 M
8.5% 1 1 OM0.0% 3 0.0%
W W W 0 Y.CO .TW W W 0 0 Y.C .T W
250k W 0 .100 -7.8% M.T 1 -7.8% .100 0.0% M 1 0.0% W.1 1 .CO-7.8% M 3 -7.8%
W W Y. CO
1 0 0 Y .TW
W 00 .T . 1 M . M
0.5M – .1
WW 00Y.CO .TW
– M 0 -7.8% W– –O 0 0.0%WW 0 .CO -7.8% 1 -7.8%
W WW .100Y.C M.TW W . 1 00Y M .TW
1M – W.1 – OM – – W– –O – – WW – .CO– .TW 0 -7.8%
Max. (1)
230.4
Wkbps O 460.8 kbps W250 kbps O 0.5 Mbps
WW 460.8
W .CO .TW921.6 kbps
kbps
1. UBRR = W W = 0.0%
0, Error .C O
W 00 Y .T W .1 M .1 M
W 00 .T W .1 M .1 M
W 00 .T W .1 M .1 M
W 00 .T W .1 M . 1 M
W 00 .T W .1 M . 1 M
W 0 0 .T W .1 M . 1 M
W 0 .T W 1
W.1
0
OM W.1 OM W. OM
W O W O
W
WW .100Y.C M.TW
O
W O W O
W
WW .100Y.C M.TW
O
W O W O
W
WW .100Y.C M.TW
O
W O W O
W
WW .100Y.C M.TW
O
W O W O
W
WW .100Y.C M.TW
O
W O W O
W
WW .100Y.C M.TW
O
W O W O
W
WW .100Y.C M.TW
O
O W O W
W
W O W O
W O W O
W O W
WW .100Y.C M.TW WW
W O
WW .100Y.C M.TW
W O
WW .100Y.C 173
W W
7799D–AVR–11/10 W
.C OM
00Y .TW
W W.1 Y.COM W
W 00 .T
W W.1 Y.COM W
.TW W 00
W.1Oscillator OM
.T
W
fosc = 8.0000 . 1 00Y
MHz M .TW f
W
= .
11.0592
W 100 MHzOM.T fosc = 14.7456 MHz
W O osc W .C
Rate
.T W WW .100Y.C M.TW W . 1 00Y M .TW
.1
W 2400 O 207 M 0.2% W
416 -0.1% O 287 0.0% W 575 Y.C W O
0.0% 383 0.0% 767 0.0%
W 4800 O 103 207W O 0.0% WW 287 0Y0.0%W .C O
WW .100Y.C M.TW
0.2% 0.2% 143
WW .100Y.C M.TW . 10 M .T191
W 0.0% 383 0.0%
O W O
W9600 O51 0.2% 103WW 0.2% Y.C 71 W 0.0% WW 143 Y .C
0.0% 95W 0.0% 191 0.0%
WW .100Y.C M.TW W . 100 M .T W .100 O M.T
O W O Y.C
W
WW .100Y.C M.TW
14.4k 34 -0.8% 68W 0.6% Y.C 47 .TW 0.0% WW 95
.100
0.0%
M.T
63W 0.0% 127 0.0%
W
W . 100 O M W C O
W
19.2k 0Y.C O W .C
Y 35 .TW0.0% W Y . W
WW 25 0.2%
W 51W 0.2%
.100
W71 00
0.0% 47.T 0.0% 95 0.0%
W .C W W -0.8%00Y 23 .TW W 00 31 .T
W28.8k .100
Y16
M.T
2.1% 34 W
.1
0.0% 47 0.0%
W.1 Y.COM W
0.0% 63 0.0%
W C O W W .C OM W
W
38.4k Y.
12 0.2%W 25 W 0.2%100Y 17 W
.T0.0% 35W 00
0.0% 23 .T 0.0% 47 0.0%
W
W .100 O M.T W .
.C OM W W.1 Y.COM W
C W TW
WW .1008Y.
57.6k -3.5%
M.T
W 16 W 2.1% .100Y11 M.0.0% 23W 0.0% 00
W.1 Y.C15OM 0.0%
.T 31 0.0%
W C O W W .C O W W
W Y. W W 0.2% .10 8 0 Y .T W W 0.0%.1 0 0 .T
W
76.8k 060 -7.0% .T 12 M0.0% 17 11 M 0.0% 23 0.0%
W
115.2k 300 8.5% .T 8 W
-3.5% .1 5 0.0%
M 11 0.0% .1 7 M 0.0% 15 0.0%
W 1 00 8.5% .T 3 W 0.0%W.1
230.4k
W.1 Y.COM W
8.5% W.1 2 M
0.0% 5 3 OM0.0% 7 0.0%
250k W 1 .100 0.0% M.T 3 0.0% .120 -7.8%M 5 -7.8% W.1 3 .CO-7.8% M 6 5.3%
W W Y .C O
1 0 0 Y .TW
W 00 .T . 1 M . M
0.5M 0 .1 0.0% M 1
WW 00Y.CO .TW
0.0% W– –O 2 -7.8%WW 1 .CO -7.8% 3 -7.8%
W WW .100Y.C M.TW W . 1 00Y M .TW
1M – W.1 – OM 0 0.0% W– –O – – WW 0 O
.C-7.8% 1 -7.8%
Max. (1)
0.5W Mbps O 1 Mbps W kbps O
691.2 1.3824 Mbps
WW 921.6
W .CO .TW
kbps 1.8432 Mbps
W O W O
1. UBRR = W
W
W = 0.0%
0, Error
0 Y.C
O
0 O
W.1 OM W O W
WW .100Y.C M.TW
W O W O
W
WW .100Y.C M.TW
O
W O W O
W
WW .100Y.C M.TW
O
W W .C O
Y W
W
.C W
WW .100Y M .TW W
W . 100 O M .T W
W .100 OM
.T
W . C O W Y .C W W W 0 Y .C W
WW .100Y M .TW W
W .100 O M .T W .10 O M.T
W O WW .100Y .C
W
W O W O W W .C O
Y
M.T
W
W O W O W W .C O
Y
M.T
W
W O W O W W .C O
Y
M.T
W
W O W O W W .C O
Y .TW
W O W C O W W .C OM
W W .100
Y .TW
W O W C O W W .C OM
W W .100
Y .TW
W O W C O W W .C OM
W W .100
Y
W O W C O W W
W W
W O W C O
W
W O W C O
W O W
WW .100Y.C M.TW WW
W O
WW .100Y.C M.TW
W O
WW .100Y.C 174
W W
7799D–AVR–11/10 W
.C OM
00Y .TW
W W.1 Y.COM W
W 00 .T
W W.1 Y.COM W
.TW W 00
W.1Oscillator OM
.T
W
fosc = 16.0000. 1 0Y
0MHz M .TW f
W
= W . 100 MHz OM.T
18.4320 fosc = 20.0000 MHz
W O osc W .C
Rate
.T W WW .100Y.C M.TW W . 1 00Y M .TW
.1
W 2400 O 416 M -0.1% W
832 0.0% O 479 0.0% W 959 Y.C W O
0.0% 520 0.0% 1041 0.0%
W 4800 O 207 416W O 0.0% WW 479 0Y0.0% W .C O
WW .100Y.C M.TW
0.2% -0.1% 239
WW .100Y.C M.TW . 10 M .T259
W 0.2% 520 0.0%
O W O
W9600 O103 0.2% 207WW 0.2% Y.C 119 0.0% WW 239 Y .C
0.0% 129 W 0.2% 259 0.2%
O W O Y.C
W
WW .100Y.C M.TW
14.4k 68 0.6% WW -0.1%
138 Y.C 79 .TW 0.0% WW 159
.100
0.0%
M.T
86W -0.2% 173 -0.2%
W . 100 O M W C O
W
19.2k 0Y.C O W .C
Y 59 .TW0.0% W Y . W
WW 51 0.2%
W 103 W 0.2%
.100
W 119 00
0.0% 64.T 0.2% 129 0.2%
W .C W W 0.6%00Y 39 .TW W 00 42 .T
W28.8k .100
Y34
M.T
-0.8% 68 W
.1
0.0% 79 0.0%
W.1 Y.COM W
0.9% 86 -0.2%
W C O W W .C OM W
W
38.4k Y.
25 0.2%W 51 W 0.2%100Y 29 W
.T0.0% 59W 00
0.0% 32 .T -1.4% 64 0.2%
W
W .100 O M.T W .
.C OM W W.1 Y.COM W
C W TW
WW .1016
57.6k 0Y. 2.1%
M.T
W 34 W -0.8% .100Y19 M.0.0% 39W 00
W.1 Y.C21OM -1.4%
0.0% .T 42 0.9%
W C O W W .C O W W
W Y . W W 0.2% .10 14 0 Y .T W W 0.0%.1 0 0 .T
W
76.8k 00
12 0.2%.T 25 M0.0% 29 15 M 1.7% 32 -1.4%
W
115.2k 800 -3.5% .T 16 W2.1% .1 9 0.0%
M 19 0.0% .1 10 M-1.4% 21 -1.4%
W 3 00 8.5% .T 8 W 0.0%W.1
230.4k
W.1 Y.COM W
-3.5% W.1 4 M
0.0% 9 4 OM8.5% 10 -1.4%
250k W 3 .100 0.0% M.T 7 0.0% .140 -7.8% M 8 2.4% W.1 4 .CO0.0% M 9 0.0%
W W Y.C O
1 0 0 Y .TW
W 0 0 .T . 1 M . M
0.5M 1 .1 0.0% M 3
WW 00Y.CO .TW
0.0% W– –O 4 -7.8%WW – .CO – .TW 4 0.0%
W WW .100Y.C M.TW W . 1 00Y M
1M 0 W.1 0.0% OM 1 0.0% W– –O – – WW – .CO– .TW – –
Max. (1)
1 Mbps
W O 2 Mbps W Mbps O
1.152 2.304 Mbps
WW 1.25
W Mbps.CO .TW 2.5 Mbps
1. UBRR = W W = 0.0%
0, Error .C O
W 00 Y .T W .1 M .1 M
W 00 .T W .1 M .1 M
W 00 .T W .1 M .1 M
W 00 .T W .1 M . 1 M
W 00 .T W .1 M . 1 M
W 0 0 .T W .1 M . 1 M
W 0 .T W 1
W.1
0
OM W.1 OM W. OM
W O W O
W
WW .100Y.C M.TW
O
W O W O
W
WW .100Y.C M.TW
O
W O W O
W
WW .100Y.C M.TW
O
W O W O
W
WW .100Y.C M.TW
O
W O W O
W
WW .100Y.C M.TW
O
W O W O
W
WW .100Y.C M.TW
O
W O W O
W
WW .100Y.C M.TW
O
O W O W
W
W O W O
W O W O
W O W
WW .100Y.C M.TW WW
W O
WW .100Y.C M.TW
W O
WW .100Y.C 175
W W
7799D–AVR–11/10 W
.C OM
00Y .TW
W W.1 Y.COM W
W 00 .T
W W.1 Y.COM W
.TW W 00
W.1 Y.COM W
.T
.C OM W
19. USART in SPI Mode .100
Y
M.T
W W 00 .T
WW .100Y M.T
W W .100 .T
W C O W W .C OM
19.1 Features WW .100Y . .TW W 100
Y .TW
M .TW O M W . O M
.CO .TW WWDuplex,
• Full
00Y
.Three-wire
C
.TW
SynchronousWData Transfer
W 100
Y.C .TW
.100Y M
W
• Master . 1
Operation O M W . O M
W O WW 00Y.C WW (Mode Y.C .TW
WW .100Y.C M.TW •W Supports . 1 all four SPI M .TW of Operation
Modes W . 100 0, 1, 2, O M
and 3)
W C O W
WFirst O
.C First .Data W C
Y.Data W
W Y. W • W
LSB or0 0 Y
MSB T W Transfer W (Configurable 1 0 0 . T
Order)
W .1 00 M .T W . 1 O M W . O M
W O
WW Operation .C Buffered) WW Y.C W
WW .100Y.C M.TW
• Queued
. 1 00Y (Double M .TW W .100 O M.T
W O
W O
WW .100Y.C M.TW • High
• High Resolution
WW .100Y.C M.TW
Baud Rate Generator
WW .100Y.C M.TW
Speed W Operation O (fXCKmax = fCK/2) W O
W O
WW .100Y.C M.TW • Flexible WWInterrupt 0 0 Y .C .T W WW .100Y.C M.TW
W. 1 Generation
OM W O
W
WW .100Y.C M.TW
O
W O W O
W
WW Overview
19.2 0 Y.C
O
0 O
W.1 OM W O
Y.C and .Asynchronous WW Receiver 0Y.C and TW
WW .100Y.C M.TW The Universal WWSynchronous . 1 0 0 M T W Wserial . 1 0 M.Transmitter (USART) can be
W O W C O W W .C O
C set to a master W SPI compliant. mode .TW of operation. Setting Y
both UMSELn1:0W bits to one enables
WW .100Y. M .TW W . 100
Y
M
W
W .100 O M.T
O the USART in MSPIM W O
logic. In this mode of operation C
Y. master.Tcontrol
W
WW .100Y.C M.control TW over the WW .100Y.C M.TW WW the SPI
.100 theOtransmitter
M
W logic takes direct
O USART
W resources. O These resources Winclude .C and receiver shift
W
WW .100Y.C Mregister .TW and buffers, WW and Y.C
00the .TWgenerator. WW . 1 00Ygenerator M .TW
. 1 baud M rate The parity and checker, the data
W W .C O
W
W
Wlogic, Y .C O
W W WW 00Y.CO .TW
Y and clock recovery W 0
and the RX .Tand TX control logic is disabled. The USART RX and TX
W
W .100 O M.T W .10
.C OM W W.1 Y.COM W
C W TW transfer W
WW .100Y. control M.T
Wlogic is replaced W by0a0Y
.1
common .SPI control logic. .100 However, OM
.T the pin control logic
W C Oand interrupt generation W W logic is C OM in both modesW
identical
. of Woperation. Y .C W
WW .100Y. M .TW W . 100
Y
M .TW W
W .100 O M.T
W O C
W
WW .100Y.CThe M
O I/O register locations
.TW WW are .C in.T
theYsame W modes.W
both W
However, 0Y. of the
.10some
W
M.Tfunctionality of the
W .100 O M W CO
W
WW .100Y.C M.TW
O registers changes
control WW when Y.C MSPIM.
using
.TW WW .100Y. M.T
W
W . 100 O M W C O
WW
W .CO .TW WW .100Y.C M.TW WW .100Y. M.T
W
19.3 Clock . 1
Generation00Y M W O W .C O
W O WW .100Y
WW .100The Y.C W
.TGeneration WW .100Y.C M.TW W
M.TReceiver. For
Clock
O M logic generates
W the
O base clock for the W
Transmitter .C O and
W
WW .10USART 0Y.C MSPIM .TW mode ofW
W 0Y.Cinternal W
.Tclock WW (i.e. 0Y
.10master M.T
W
M operation W . 10only O M generation W
C O operation) is sup-
W W .C O W Y .C XCKn.Tpin W W W 0 Y . .T W
Y
ported. The Data W Direction W Register .10 0
for the (DDR_XCKn) must
10 therefore be set to one
W
W .100 O M.T W W .C OM W W. Y .C OM
W
WW .100Y (i.e. as .Coutput) for
W the USART W in MSPIM 00Y to operate .T Wcorrectly. W
Preferably 00
the DDR_XCKn .T should
W be set up O M.T the USART in W
before W.1 isYenabled
MSPIM .C OM (i.e. TXENn andWRXENn W.1 bit Y .CsetOM to one).W
.C W W 0
WW .100Y M .TW W
W . 100 O M .T W .10 O M.T
W O Y.Cmode is WUSART Y .C W
WW The.1internal00Y
.C clock.Tgeneration
W WW in MSPIM
used
.100 M
W
.Tidentical to Wthe
.100synchronous M.T mas-
O M
W mode. The baud rate or UBRRn W O W W .C O
ter
WW .100Y.C M.TW WW .setting Y.C can therefore.TW
be Wcalculated
.100
Yusing the.Tsame W
equations, see Table 19-1: W 100 O M W C O M
W O W .
Y
M.T
W
W O W O W W . C O
Y
M.T
W
W O W O W W .C O
Y
M.T
W
W O W O W W .C O
Y .TW
W O W C O W W .C OM
W W .100
Y .TW
W O W C O W W .C OM
W W .100
Y .TW
W O W C O W W .C OM
W W .100
Y
W O W C O W W
W W
W O W C O
W
W O W C O
W O W
WW .100Y.C M.TW WW
W O
WW .100Y.C M.TW
W O
WW .100Y.C 176
W W
7799D–AVR–11/10 W
.C OM
00Y .TW
W W.1 Y.COM W
W 00 .T
W W.1 Y.COM W
W W 00 .T
O M.T W W.1 Y.COM W
Table 19-1. Equations for Calculating Y .C Baud Rate Register
W W Setting 00 .T
W .100 O M.T W W.1 (1)Y.COM W
Operating Mode WW .100Equation Y .C forW CalculatingW Baud Rate 00 T
.Equation for Calculating UBRRn Value
W WW .100Y .C W W 00 .T
Y.C W WW .100Y .C W W 00 .T
W .100 O M.T W O M.T W W.1 Y.COM W
WW .100Y .C
WW .100Y.C M.TW M.T
W
f OSC
W 00
W.1 Y.COM W
.T f OSC
W O
Synchronous Master mode W .C O W
WW .100Y.C M.TW WW .100BAUD Y = .--------------------------------------
T
2 
W
UBRRn +
W-
1  . 1 00 M .TUBRRn = -------------------- – 1
2BAUD
W OM W O
W
WW .100Y.C M.TW
O
W O W O
W
WW .100Y.C M.TW
O
W O W O
W
WW .100Y.C M.TW
O
W O
W O 1. W
W .COis defined WW rate .Cper
0inYbit .TW (bps)
WW .100Y.C M.TW Note: W The baud
. 1 0 0 Y
rate
M .T Wto be the transfer
W . 1 0
O Msecond
W O W O
.C rate W bps)Y. C W
WW .100Y.C M.TW BAUD WW .100YBaud M .T(in W bits per W second,
.100 M.T
W O W C O
W O
fOSCWW Y.C W Y. W
WW .100Y.C M.TW . 100System M .TW
Oscillator clockW frequency
W .100 O M.T
W O W O W Y. C
WW .100Y.C M.TW UBRRn WW .10Contents 0Y.C M W
of.Tthe UBRRnH Wand UBRRnL.100 Registers,
W
M.T (0-4095)
W O W C O
W
WW .100Y.C M.TW
O
W
W O W C O
19.4 WSPIWW Data .CO .Tand WW .100Y.C M.TW WW .100Y. M.T
W
. 1 00YModes M
W Timing
W O W C O
W O
WW .100Yof.CXCKn
W polarity Y. W
WW .100Y.C There M .TWare four combinations M TW phaseW
.(SCK) and
W .100 with respect
O M.T to serial data, which
Oare determined by W W O .C
W
WW .100Y.C M.TW W control bits Y.C UCPHAnW and UCPOLn. WW The.1data 00Y transfer timing
W
M.T edges of the XCKn
diagrams are
shown in Figure 19-1. W .
Data 100bits are O M .T
shifted out and latched W in on C O
opposite
W
WW .100Y.C signal,
O
W WW time Y.C .TW to stabilize. WW .100Y. .TW
M .Tensuring sufficient W . 100 for data O M signals The
W UCPOLn C O M and UCPHAn function-
W W Y .C O
W W W 0 Y .C .T W W W 0 0 Y. .T W
W . 1 00 ality M T
is .summarized in Table.119-2.
W
0 NoteM
O that changing the setting W .1 of any OofM these bits will corrupt
W COongoing .C WW .100Y. C W
WW .100Y.all .TWcommunication WW for.1both 00Y the Receiver M .TW and Transmitter. M.T
M W O W C O
W
Table 19-2. W UCPOLn . 1 and UCPHAn
O M Functionality- W O W .C O
W
WW .10UCPHAn 0Y.C M.TW SPI Mode WW .100Y.C M.TW WW .100Y M.T
W
UCPOLn O W Leading O Edge W Trailing Edge
.C O
W
W
0 0 O 0 W Sample O
(Rising) W
Setup C
(Falling)
. O
W
W
O W O W . C O
0 W
WW .100Y.C M.TW
1 1
WW .100Y.C M.TW
Setup (Rising)
WW .100Y
Sample (Falling)
M.T
W
W 0 O W O W
W (Rising) .C O
WW .100Y.C M.TW
1 2 Sample (Falling) WSetup Y W
WW .100Y.C M.TW W .100 O M.T
W1 O W O W (Rising) .C
1
WW .100Y.C M.TW
3
WWSetup Y.C
(Falling)
.TW WSample
.100
Y
M.T
W
W .100 O M W C O
W O Y.C WW .100Y . W
WWFigure 0Y.C UCPHAn
019-1. .TW and UCPOLn WW data . 100transfer M .TW diagrams.
timing M.T
WW .100Y.C M.TWUCPOL=0W
W Y.C .TW W .100
Y
M.T
W
W . 100 O M UCPOL=1W C O
W O W .
Y
M.T
W
W O W O W W .C O
UCPHA=1
WW XCK Y.C W WW .100Y.CXCK M.TW W .100

Y
M.T
W
W .100 O M.T W C O W W .C O
WW Data.1setup .C
00Y(TXD) M.TW WW .100Y.Data M.T(TXD)
W W .100
Y .TW
W O W C O setup
W W .C OM
WWData sample Y.C W WW .100YData .
M.T(RXD)
W W .100
Y .TW
W .100 (RXD) O M.T W C
sample
O W W .C OM
W W .100
Y .TW
W O W C O W W .C OM
W W .100
Y
UCPHA=0
XCK W O W XCK C O W W
W W
W (TXD) CO W C O
WW .100Y.
Data setup Data setup (TXD)
WW .100Y. .TW W
W (RXD) .COM W O M.T
Data sample
WW .100Y.
Data sampleC (RXD)
WW .100Y M.T
W
W O W
WW .100Y.C M.TW WW
W O
WW .100Y.C M.TW
W O
WW .100Y.C 177
W W
7799D–AVR–11/10 W
.C OM
00Y .TW
W W.1 Y.COM W
W 00 .T
19.5 Frame Formats W W.1 Y.COM W
.TW W 00
W.1to beY.one OM
.T
A serial frame C OM for the MSPIM is defined W C character of 8 data bits. The USART in MSPIM
mode 1
.
0Y two valid
0has M .TW frame formats:
W . 100 M .TW
W . O W O
• 8-bit
W data with
O MSB first W O
OM • 8-bit
W data withOLSB first W O
0 dataO
W.1 OM A frame W startsYwith .CO the .least or most significant W
WW .100Y.C M.TW
bit. Then the next data bits, up to a total of
WW .100Y.C M.TW WW are.succeeding,
eight, 1 00 M T W
ending with the most or least significant bit accordingly. When a complete
W W .C O
W W W Y .CO W W WW 00Y.CO .TW
W 00 Y .T W
frame is transmitted, 0 0 aMnew T
. frame can directly .1follow it, orMthe communication line can be set to
W.1 Y.COM W W.1 state.
W(high) Y .CO .TW WW 00Y.CO .TW
W an idle
W 0 0 W .1
W 00 .T W
The UDORDn.1bit 0
0 in UCSRnC T
M. sets the frame format
.1 usedOby M the USART in MSPIM mode. The
W.1 Y.COM W ReceiverW W Y .CO use W W WW Note 0 Y .C changing W the setting of any of these
W W
. 1 00 M .T W and
W
Transmitter
. 10 0
O M .T the same setting.
W .1 0 that
O M.T
W O bits will W corrupt
W all0ongoing Y.C communication forWboth the .C
Receiver
Y and W Transmitter.
WW .100Y.C M.TW . 1 0 M .TW W
W .100 O M.T
O W O Y. C
W
WW .100Y.C M.TW16-bit data WW transfer0can Y.C .TW by writing WWtwo data .100 bytesOto .TW A UART transmit com-
W . 1 0 beOachieved M W C
MUDRn.
W O plete interrupt .C that WW has.1been . W
WW .100Y.C M.TW WWwill then . 100
Ysignal
M .TW
the 16-bit value 00Y shifted M.T
out.
W O W C O
W
WW USART .CO .TW WW .100Y.C M.TW WW .100Y. M.T
W
19.5.1 . 1 00Y MSPIM M Initialization W O W C O
W O W 0Y.C hasMto.Tbe
W Y. W
WW .100Y.C M.The TWUSART in WMSPIM . 10mode
WinitializedWbefore
W .100communication
any O M.T can take place. The
W C O W
W normally O
.Cconsists W Y.C W
W Y. W
initialization W
process 0 Y .T W
of setting W
the baud 0 0
rate, setting .T
master mode of operation
W
W .100 O M.T W .10
.C OM W W.1 Y.COM W
C (by setting DDR_XCKn W to one), setting.TW frame format and enabling the Transmitter and the
WW .100Y. M .TW W .100
Y
M
W
W .100 O M.T
OReceiver. Only the W W O .C
W
WW .100Y.C tion, .TtheW W
transmitter can operate
.C
00Y should .TW
independently.WW .For 00Y
interrupt
1interrupts M .driven
TW USART opera-
M Global Interrupt W . 1Flag O M be cleared (and thusW C O globally disabled) when
W
WW .100Y.C doing
O
.T W initialization. WW .100Y.C M.TW WW .100Y. M .TW
the W O
W OM W O
WW .100Y.C M.TW
WW .100Y.CNote:M.TTo W WW .100Y.C M.TW
W O ensure immediate
WW
initialization
.COof the XCKn output the W
Wbaud-rate .CO (UBRRn)
Yregister .TW
must be
WW .100Y.C M.zero TW at the time Wthe . 1 00Y is enabled.
transmitter M .TWContrary toWthe normal W . 1 00mode USART
O M operation the
W C O W W . C Odesired value after theWtransmitter Y . C W
WW .100Y. M
UBRRn
.TW
must then
W be written
. 0Yto
10Setting
the
M .TW W
W
is enabled,
.100the transmitter
O
but before
M.T is not neces-
the
W O first transmission is W
started. OUBRRn to zero before Wenabling .C
WW .100Y.C M .TW WW is done Y.C W a reset W Y
.100 is reset to.T
W
sary if the initialization
W .100immediately O M .Tafter since UBRRn
W C O M zero.
W O W .
0Y.C doing
WW .10Before .TaWre-initialization WW with . 0Y.C M
10changed .TWrate, dataW
baud mode,Wor 0Y format,
.10frame
W
M.T be sure that
M W O .C O
W
WW .there .CO ongoing WW .during Y.C period .TW the registers WW are.1changed. 00Y W
M.TTXCn Flag
1 00Y is noM .TW transmissions W 100 the O M W . C O
The
O
W can be used to check that theW Y.Chas completed WW .1and W
WW .100Y.C M.TW W Transmitter . 100 M .TW all transfers, 00Ythe RXCn M.T
Flag can
be used to
O check that there are W
no unread O
data in the receive buffer. W Note C
that
. O the TXCn Flag
W
WW must 0 Y.C .T W W W 0 0Y.C M.TW WW .100Y M .TW
1 0 be cleared before each transmission . 1 (before UDRn is written) if it
W is used for Othis purpose.
W. OM W O
WW .100Y.C M.TW
The
W following .COsimple USART initialization WW 0code Y .CO examples W show one W
W
W
assembly
0 .COone .C
Yand TWfunc-
WWtion that1 0 0 Y .T W W . 1 0 M .T . 1 0
O M
WW rate
. are
.
equal
CO
M in
W
functionality. The examples
WW 00Y.CO .TW
assume polling (no
W WW 00Y.C
interrupts enabled).
.T WThe
Wbaud 0 Y T W 1
.10 is given Mas . a function parameter. W.1 For the OMassembly code, the baud W. rate parameter OM is
WW 0to
assumed
W 0 Ybe.CO stored.TinWthe r17:r16 WW registers. 0 0 Y.C .T W WW .100Y.C M.TW
W.1 OM W.1 OM W O
W O W O
W
WW .100Y.C M.TW
O
W O W O
W
WW .100Y.C M.TW
O
W O W O
W
WW .100Y.C M.TW
O
W O W O
W
WW .100Y.C M.TW
O
O W O W
W
W O W O
W O W O
W O W
WW .100Y.C M.TW WW
W O
WW .100Y.C M.TW
W O
WW .100Y.C 178
W W
7799D–AVR–11/10 W
.C OM
00Y .TW
W W.1 Y.COM W
W 00 .T
(1) W W.1 Y.COM W
.C OM W W.1 Y.COM W
Y
USART_Init: W W 00 .T
WW .100Y clr .Cr18 W W 00 .T
W WW .100Y
out . C
UBRRnH,r18 W W 00 .T
O M.T W out O
UBRRnL,r18 M.T W W.1 Y.COM W
Y.C WW .100Y .C
W .TW W 0
.10output, .T
W .100 O M.T W ; Setting C O M
the XCKn port pin W W as .C OM enables master mode.
WW .100Y.C M.TW WW sbi 1 0Y .
0XCKn_DDR, M
W
.TXCKn W . 100
Y
M .TW
W . O W O
W
WW .100Y.C M.TW
O
WW ; Set Y.C mode
00MSPI .TW WW and.10SPI 0Y.CdataMmode .TW 0.
W . 1 O M of operation W O
W
WW .100Y.C M.TW
O
WWldi .r18, Y.C .TW WW .100Y.C M.TW
W 100 (1<<UMSELn1)|(1<<UMSELn0)|(0<<UCPHAn)|(0<<UCPOLn)
O M W O
W
WW .100Y.C M.TW
O W UCSRnC,r18
Wout 0 0 Y.C .T W WW .100Y.C M.TW
W. 1 OM and transmitter. W O
W
WW .100Y.C M.TW
O
W;W Enable
0 0 Y.C
receiver
.T W WW .100Y.C M.TW
W. 1 OM W O
W
WW .100Y.C M.TW
O ldi
0Y.C M.TW
WWr18,.10(1<<RXENn)|(1<<TXENn) WW .100Y.C M.TW
W O W O
W
WW .100Y.C M.TW
O out W
W
UCSRnB,r18
0 0 Y.C .T W WW .100Y.C M.TW
. 1 OM W O
W O ; Set baud
WW 0rate. Y.C WW .100Y.C M.TW
WW .100Y.C M.TW W
; IMPORTANT: . 1 0 The Baud M .T W
Rate must be set W after the O transmitter is enabled!
WW O
W
WW .100Y.C M.TW
O
out W UBRRnH,.10r17 0Y.C M.TW WW .100Y.C M.TW
W O
W O

34 Atmel ATMEGA8,16,32 PDF

Uploaded by

Document Information

Original Title

Copyright

Available Formats

Share this document

Share or Embed Document

Sharing Options

Did you find this document useful?

Is this content inappropriate?

Copyright:

Available Formats

34 Atmel ATMEGA8,16,32 PDF

Uploaded by

Copyright:

Available Formats

.

PC5 ( PCINT9/ OC.1B)

PC5 ( PCINT9/ OC.1B)

(PDI / MOSI / PCINT2) PB2

(SCLK / PCINT1) PB1

(PDI / MOSI / PCINT2) PB2

(SS / PCINT0) PB0

WW .100Y.C M.TW WW .100Y.C M.TW

W O WW 00Y.CO PLL.TW WW 00Y.CO .TW

WW SPI .100Y.C M.TW WW .100Y.C M.TW W . 1 0 0Y

O 0 0 W See BitO Description

WW .100Y.C M.TW Q CLR

0 0 Y.C .T W WW Clear . 1 0 0Control M .TW (Int.Req.)

0 Y.C .T W WW .100Y.C M.TW WW .100Y.C M.TW

W W WW 00Y.CO .TW Timer/Counter

W W.1 Y.COM W WW 00Y.CO .TW W WW 00Y.CO .TW(Int.Req.)

W W.1 Y.COM W WW 00Y.CO .TW

WW .100Y. Y .TW W CHECKER.100 .T

WW XCK Y.C W WW .100Y.CXCK M.TW W .100

You might also like