INTRODUCTION

.In this Lab, you will design and verify a Switch RTL core

SPECIFICATION

Switch specification

This is a simple switch. The switch drives the incoming packet which comes from
.the input port to output ports based on the address contained in the packet

The switch has one input port from which the packet enters. It has two output
.ports where the packet is driven out

Packet Format

.Packet contains 3 parts: Header, data and Parity Sequence

Packet width is 8 bits and the length of the packet can be between 4 bytes to 259
.bytes

Packet Header

.Packet header contains three fields DA, SA and length

.DA - Destination address of the packet. 8 bits length

The switch drives the packet to respective ports based on the destination address
of the packets. Each output port has 8-bit unique port address. If the destination
address of the packet matches the output port address, then the switch drives the
.packet to that output port. The output ports are numbered 0 and 1

SA - Source address of the packet from where it originates. 8 bits length. Will be a
 .constant – FFh

Length - Length of the data is of 8 bits and can be from 0 to 255. Length is
.measured in terms of bytes
If Length = 0, it means data length is 0 bytes
If Length = 1, it means data length is 1 bytes
If Length = 2, it means data length is 2 bytes
If Length = 255, it means data length is 255 bytes

.Data - Data should be in terms of bytes and can have any value

PS - Parity Sequence
Contains the Parity calculation of the packet. It is calculated over the header and
.the data

Configuration

.The Switch has two output ports numbered 0 and 1

The switch matches the DA field of the input packet with the number of the out
.port and sends the packet to the correct port

Interface Specification

The Switch has one input Interface, from where the packet enters and 2 output
.interfaces from where the packet comes out
.Switch also has a clock and asynchronous reset signal

Input Port

.Packets are sent into the switch using the input port
All the signals are active high and are synchronous to the positive edge of clock
.signal
 :input port has 2 input signals
;input [7:0] data
;input valid

,To send the packet in to switch

.Assert the valid signal .1

.Send the packet on the data signal byte by byte .2
.After sending all the data bytes, deassert the valid signal .3
.There should be at least 2 clock cycles difference between packets .4

Output Port

.The switch sends the packets out using the output ports
.There are 2 ports, each having data and ready signals
All the signals are active high and are synchronous to the positive edge of clock
.signal

Signal list is
;output [7:0] port0
;output [7:0] port1
;output ready_0
;output ready_1

When the data is ready to be sent out from the port, the switch asserts ready_*
.signal high indicating that data is ready to be sent
If the read_* signal is asserted, when ready_* is high, then the data comes out of
.the port_* signal after one clock cycle
 VERIFICATION PLAN
Features to Be Verified

.This section contains list of all the features to be verified

Packet DA - DA field of packet should be any of the port address. All the 2-port .1
.address should be used
Packet payload (data) - Length can be from 0 to 255. Send packets with all the .2
.lengths
Length - Length field contains length of the payload. Send Packet with correct .3
.length field and incorrect length fields

Stimulus Generation Plan

.Packet DA: Generate packet DA with all port address .1
.Payload length: generate payload length ranging 0 from to 255 .2
.Correct or Incorrect Length field .3

Coverage Plan

.Cover all the port address .1

.Cover all the packet lengths .2
.Cover all correct and incorrect length fields .3
.Cover all the above combinations .4
 VERIFICATION ENVIRONMENT

DESIGN & VERIFICATION RECOMMENDED STEPS

.Following are recommended steps to design & verify the Switch RTL core
Understand the specification .1
Develop Verification Plan .2
Develop coverage Plan .3

Step 1 – Write the code for the switch RTL

.Develop a Verification testbench in SystemVerilog .4

Step 2 – Write a testbench in System Verilog. Write top module with clock and
.reset generators

Develop a Verification environment in SystemVerilog (the Diagram is only a .5

.recommendation, you can change it)

.Step 2 - Develop the interfaces and integrate them with the DUT in top module
Add the clock generator. (Do not use clocking block, use modport only for
the DUT)
.Step 3 - Develop a packet class based on the stimulus plan
Step 4 - Develop a generator class and a driver class. Packets are generated using
.the generator and sent to the DUT using the driver

Step 5 - Develop the monitor class. Monitors collect the packets coming from the
output ports of the DUT (Actual Monitor) and also from the input port of the DUT
 (Expected Monitor)

Step 6 - Develop scoreboard (checker) class which does the comparison of the
.expected packet with the actual packet received from the monitors
.Step 7 – Develop the Environment class. Add reset method and reset the DUT
Add the mailboxes
.Step 8 - Develop coverage class based on the coverage plan

.Step 9 - Write testcases and analyze the coverage report