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  • Attendance Register: List of Students Registered

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    dvdiyen
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    This document is an attendance register for a module titled "Modelling and Simulation of Electronic Circuits" that was conducted from December 18, 2017 to December 30, 2017. It lists two students, Anush B N and Manjushree K, who were registered for the course, and shows that they each attended all 20 classes with 100% attendance, making them eligible to appear for the semester end examination. The document was signed by the subject leader, head of department, quality director and academic registrar to verify the number of classes conducted.

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    1_2017_EC_030_attendance.pdf

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    This document is an attendance register for a module titled "Modelling and Simulation of Electronic Circuits" that was conducted from December 18, 2017 to December 30, 2017. It lists two students, Anush B N and Manjushree K, who were registered for the course, and shows that they each attended all 20 classes with 100% attendance, making them eligible to appear for the semester end examination. The document was signed by the subject leader, head of department, quality director and academic registrar to verify the number of classes conducted.

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    © All Rights Reserved
    Download as PDF, TXT or read online from Scribd
    Flag for inappropriate content
    Download as pdf or txt
    32 views1 page

    Attendance Register: List of Students Registered

    Uploaded by

    dvdiyen
    This document is an attendance register for a module titled "Modelling and Simulation of Electronic Circuits" that was conducted from December 18, 2017 to December 30, 2017. It lists two students, Anush B N and Manjushree K, who were registered for the course, and shows that they each attended all 20 classes with 100% attendance, making them eligible to appear for the semester end examination. The document was signed by the subject leader, head of department, quality director and academic registrar to verify the number of classes conducted.

    Copyright:

    © All Rights Reserved
    Download as PDF, TXT or read online from Scribd
    Flag for inappropriate content
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    of 1

    Attendance Register

    Faculty : Faculty of Engineering and Technology (ET) Department : Electronics and Communication Engineering

    Programme : M.Tech. in Electronic Systems Design Engineering Batch : FT - 2017 Start Date : 18th December 2017

    Module Code : ECE503 Module Title : Modelling and Simulation of Electronic Circuits ModuleLeader(s) : D. Varun, Divya Kiran End Date : 30th December 2017

    List of Students Registered

    Session No. --> 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20

    18- 18- 19- 19- 20- 20- 21- 21- 22- 22- 26- 26- 27- 27- 28- 28- 29- 29- 30- 30- No. of No. of
    Sl. Condoned Attendance Eligibility
    Reg. No. Name 12- 12- 12- 12- 12- 12- 12- 12- 12- 12- 12- 12- 12- 12- 12- 12- 12- 12- 12- 12- Classes Classes Penalty
    No. Classes % for SEE
    17 17 17 17 17 17 17 17 17 17 17 17 17 17 17 17 17 17 17 17 Conducted Attended

    1 17ETEC030001 ANUSH B N 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 20 0 20 100 % E

    MANJUSHREE
    2 17ETEC030002 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 20 0 20 100 % E
    K

    Signature of Subject Leader Head Of Department


    Date Date

    Quality Director * Academic Registrar (Faculty) *


    Date Date

    * Verified and Confirmed that the specified number of Classes have been conducted.

    08 Jan 2018 Page 1 / 1

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