MGA-633P8 GaAs MMIC Low Noise Amplifier

Enables 450 MHz wireless communications bands

with Industry Best Noise Figure and Linearity

Application Note 5559

Introduction Device and package technologies

The Avago MGA-633P8, which is optimized for the 400 The MGA-633P8 is a microwave monolithic integrated
MHz to 1.5 GHz range, is part of a new active-bias LNA circuit (MMIC) built on a new process optimized for low
family that provides a common printed circuit board (PCB) noise. The Avago GaAs enhancement-mode pseudo-mor-
footprint for the 400 MHz to 4 GHz range. It is ideal for ap- phic high electron mobility transistors (ePHEMT) process
plications where premium noise figure is required. Typical has a 0.25 μm feature size.
applications include, the tower mounted LNA application,
The MGA-633P8 is a common-source amplifier with an ac-
other uses are found in base transceiver station (BTS) radio
tive bias regulator. Quiescent current (Ids) can be adjusted
cards, repeaters, remote radio heads, consumer premises
by varying either RBIAS, which connects the supply voltage
equipment (CPE) and access points (AP), Industrial Scien-
Vdd to the shunt regulator, or by the external VBIAS control
tific and Medical (ISM) and Military Radio applications. For
voltage. The regulator’s drive bias current is a low 1 mA
optimum performance at frequencies from 1.5 GHz to 2.2
maximum, which makes it compatible with most CMOS
GHz the MGA-634P8 and from 2.3 GHz to 4.0 GHz MGA-
control circuits. The adjustable bias enables better linear-
635P8 LNA’s is recommended.
ity but with higher power.
Design Goals Available in an 8-pin Quad Flat No-lead (QFN) package
The original design draft was a low noise amplifier with an measuring 2.0 x 2.0 x 0.75 mm, the MGA-633P8 is suitable
Output Third Order Intercept Point (OIP3) of 36dBm with for compact applications where space and volume are
a noise figure below to 0.6dB at from 400MHz to 500MHz limited.
and 20dB gain response. The use of RC-feedback was not
required for good input and output match, as the MGA-
633P8 is a large gate width device. This helps keep the Vb & Rbias vs. Id @ Vdd=5 V
noise performance as low as possible. The amplifier must mV Vbias Rbias kΩ
450 9.5
be able to run from a 5 volt supply and consume less than
440 9
60mA.
430 8.5
420 8
Vbias [1] Bias Cct [8] NU 410 7.5
400 7
RFin [2] [7] RFout 390 6.5
380 6
NU [3] [6] NU 370 5.5
360 5
NU [4] [5] NU 350 4.5
Centre: 50.00 mA Id Span: 50.00 mA
Figure 1. MMIC internal structures(top) and characteristic of the adjustable Figure 2. VBIAS, RBIAS vs. Idd with Vdd = 5V
internal bias regulator
Background Application Demonstration
The weakest signal that a wireless receiver can recover is To evaluate RF performance, a 450 MHz LNA for wire-
defined by its sensitivity and is calculated by Equation 1, less communications applications a circuit was designed
[1]: around the MGA-633P8. External components C1-L1 and
C2-L2 provide the matching and biasing functions. In ad-
Rx_sen (dBm) = -174 + 10log BW + SNR + F Eq. 1 dition to the DC blocking and RF choking functions, C1-
L1 also rolls-off undesirable gain below the operating fre-
BW is the bandwidth in Hz, SNR the required signal to
quency. Both L1 and L2 should be operated below their
noise ratio, and F the system noise figure.
self resonant frequency (SRF) for effective choking.
A low noise amplifier (LNA), as its name implies, improves
The insertion loss, A(f ), of a single transmission resonator
the receiver sensitivity by reducing the cascade noise
at an evaluated frequency (f ) is given by the Equation 3,
figure. The Friis formula, Equation 2, is used to calculate [3]:
the total noise figure of a cascade of stages, each with
its own noise factor and gain. As Equation 1 shows, the 
noise figure, F1, of the 1st amplifying stage in the receiver  
 2
− 0

 2Ql
 
chain—the LNA—dominates the noise performance, and  1 +
 0  
the noise factor of subsequent stages, F2, F3 and so on are A() = −10 log   Eq. 3
less important.    Ql
 2 
 1 − 
 
F2 − 1 F3 − 1    Qu
 
Ftotal = F1 + + +... Eq. 2 
G1 G1 G2
f0 is the resonant frequency; Ql is the loaded Q of the
Gn is the gain of the nth stage in the receive chain. matching network; and Qu is the components’ unloaded
Base transceiver stations (BTS) and microwave relays Q, usually the Qu of the inductor as it is lower than that of
have detached LNA stages located in the aerial tower to the capacitor. At the centre of the resonator’s pass-band,
decrease NF degradation from pre-LNA cable loss. In the f0 can be substituted for f, hence
typical BTS architecture, the LNA stage is preceded by a
Qu − Q1
Transmit-Receive (Tx-Rx) diplexer for duplexing a com- A = 20 log Eq. 3(a)
mon aerial and an interference filter for preventing out- Qu
of-band blocking or desensitization. However, both the
The loaded Ql of the matching network is determined by
duplexer and filter have losses that must be minimized as
the ratio of input and source impedances, RHI/RLO [4]:
they occur before amplification [2]. A LNA with extra noise
performance margin will relax the duplexer-filter’s loss re-
quirement and potentially lower overall system cost. RHI
QL = −1 Eq. 4
Other critical LNA performance parameters include high RLO
gain to overcome loss in the long cable connecting the
tower-mounted LNA and the ground-level radio shack Substituting for Ql gives:
and high linearity as the RF spectrum can be very crowd-
ed due to site sharing with other wireless transmitters. RHI
Qu − −1 Eq. 5
RLO
A = 20 log
Qu

When the RHI/RLO ratio approaches 1, insertion loss, A,

is approximately 0 dB. The lowest loss is achieved when
the source and input impedances are equal. So that the
RHI/RLO ratio is kept close to unity the Avago proprietary
ePHEMT process noise was optimized by scaling the tran-
sistor size and bias current for an input impedance of ap-
proximately 50 Ω

2
Capacitors C3-C5 decouple RF from the bias lines. By se- Vdd
lecting C4 so that its reactance is approximately 6 Ω at f0,
it also works with R1 to roll-off the gain below f0. Rbias
C5 C6
When it is required to switch the LNA via a logic-level con-
trol signal applied to pin 1 (Vbias), C3 should be reduced R1 R2
to the lowest capacitance value that will still provide a low C3 C4
reactance at f0 , for example 100 pF at 450 MHz. This low
C3 value will speed up the switching time that is limited L2
by the RBIAS x C3 time constant. Turn-on time is typically L1 P1 P8
R3
several microseconds for small C3 values in the pF range. P2 P7
Input Output
P3 P6
The printed circuit board (PCB), which measures 21.5 mm C1 C2
P4 P5
x 18 mm x 1.4 mm, is made from 10 mil Rogers RO4350 mi-
Centre tab
cro-strip with a co-planar ground and 1.2 mm FR4 mate-
rial glued to the bottom as stiffener. RF connections were MGA-633P8
made through edge-launch SMA-to-micro-strip transi- Figure 3. LNA Circuit Schematic
tions (Emerson Network Power/Johnson Component P/N
142-0701-856). The DC supply was connected via a 2-pin
straight PCB header.
The LNA demonstration board is powered from a single
5V power supply. At the nominal Idd of 55 mA, approxi-
mately 0.5V is dropped across R1, giving a Vds of approxi-
mately 4.75V.
The component values in Table 1 were used for the dem-
onstration board and circuit but may be slightly different
if either a different layout or PCB material is used.
Table 1. MGA-633P8 demonstration board part list
Position Value Description
C1 100 pF Murata GRM15
C2 18 pF Murata GRM15
L1 82 nH Toko LL1005
L2 68nH Toko LL1005
C3, C4 22 pF Murata GRM15
C5, C6 10 nF Murata GRM
R1 100 Ω
R2 4.7 Ω Figure 3b. Demoboard component placement diagram
R3 270 Ω
Rbias 6200 Ω
SMA Connectors 142-0701-856 Johnson
Note: All components are 0402 size unless otherwise noted

Figure 3c. Photograph of assembled demonstration board

3
The demonstration LNA was simulated in Agilent Tech-
nologies ADS2009U1 software in order to obtain the
matching network components initial values. The MGA-
633P8 was modelled using Touchstone formatted scatter-
ing (s-parameter) and noise parameter files supplied by
Avago Technologies. To reduce the circuit complexity and
simulation time, passive chip components SRLC and INDQ
were used. The inductor model used typical QUL values at
the nearest frequency (800 MHz) published by the vendor
[5]. Inductor parasitic capacitances were calculated from
their published typical SRF values but with an extra 0.1 pF
added to account for pad-to-pad capacitance. The parasit-
ic inductance and resistance, in the SRLC capacitor model
was also obtained from the vendor [6]. The 2-pin header
and its associated pads were excluded because they were
found to have little impact on the simulated results. The
ADS2009U1 optimization tool was used to help calculate
the values of the matching networks. The optimization
Tee7
Subst="MSub1"
W1 W mm
W1=W
W2=W mm
W3=W mm
tool lets the designer provided weighed values to which
parameters are most important to the end design. The
passive models were then replaced with components
from the Murata design kit. The design kit can be down-
loaded from the Murata web site. The design kit typically
contains measured s-parameters to 20GHz for the capaci-
tors and above 5GHz for the inductors. R1 was used for
low frequency termination. Typically 50 would suffice but
the optimization tool derived 100 ohm value to minimize
impact on noise figure. R3 was used for increased stability
margin. A lower value of R3 can be used if higher margin
is required. R3 had little impact on output linearity. R3 had
to be placed on the demo board at an angle since the ge-
neric board does not have a dedicated pad for a shunt re-
sistor next to L2. A 4.7uF capacitor was added to the eval-
uation board in order to adequately decouple the bench
power supplies used in testing.
TL24 TL25 Tee12
Subst="MSub1" Subst="MSub1" Subst="MSub1"
W=W mm W=W mm W1 W mm
W1=W
L=4.0 mm L=4.0 mm W2=W mm
W3=W mm

V1
SRLC5 R3
D=10.0 mil SRC1
R=0.1 Ohm R=6000 Ohm Tee9
H=10.0 mil TL22 Vdc=5.0 V
T=0.7 mil L=0.8 nH Subst="MSub1" Subst="MSub1"
Rho=1 0
Rho=1.0 C=10
C 10 nF W=W mm W1=W mm
W=20.0 mil L=1.0 mm {-t} V7 W2=W mm
SRLC13 W3=W mm
Var VAR1
D=10.0 mil Eqn

R=0.1 Ohm W=0.6

SRL1 H=10.0 mil
R=100 Ohm {o} T=0.7 mil L=0.8 nH SRL2
L=0.5 nH Rho=1.0 C=10 nF R=4.7 Ohm {o}
W=20.0 mil L=0.5 nH
MSub
TL13
Subst="MSub1" TL19 MSub1
SRLC10 SRLC12 Subst="MSub1"
W W mm
W=W H=10 mil
R=0.1 Ohm R=0.1 Ohm W=W mm
L=0.4 mm Er=3.48
L=0.46 nH L=0.46 nH Tee4
L=0.4 mm Mur=1
C=22 pF C=22 pF Subst="MSub1"
Tee6 W1=W mm Cond=4.10E+7
Subst="MSub1" W2=W mm Hu=3.9e+034 um
V2
W1=W mm D=10.0 mil W3=W mm T=17 um
TL26 W2=W mm H=10.0 mil TanD=0.001
V8
Subst="MSub1" W3=W mm T=0.7 mil TL18 Rough=0 um
D=10.0 mil
W=W mm Rho=1.0
Rho 1.0 Subst="MSub1"
H=10 0 mil
H=10.0
L=0.4 mm W=W mm
T=0.7 mil W=20.0 mil
L=0.4 mm
Rho=1.0
W=20.0 mil Taper1
C10 L8
TL15 C=0.1 pF L=82 nH {o} Subst="MSub1" C11 L9 SRL3
Subst="MSub1" SRLC9 W1=W mm C=0.1 pF L=68 nH {o} R=270 OhmTL23
Q=50.0 TL16
W=W mm R=0.1 Ohm W2=0.250 mm Q=50.0 L=0.5 nH Subst="MSub1"
F=800.0 MHz Subst="MSub1"
L=0.46 nH L=1 mm F=800.0 MHz W=W mm
L=4.437 mm Mode=proportional to freq W=W mm
Mode=proportional to freq L=0.5 mm
C=100 pF {o} Rdc=0.05 Ohm L=4.437 mm
Rdc=0
Rdc 0.05
05 Ohm
1 2

Ref

Tee3 Tee10 Tee11 SRLC11

TL14 Subst="MSub1" Subst="MSub1" Subst="MSub1" R=0.1 Ohm Term2
Term1 Subst="MSub1" W1=W mm W1=W mm W1=W mm L=0.46 nH
SNP1 Num=2
Num=1 W=W mm W2=W mm W2=W mm W2=W mm C=18 pF {o} Z=50 Ohm
File="MGA633P8 5V_55mA.s2p"
Z=50 Ohm L=0.4 mm W3=W mm W3=W mm W3=W mm

MGA-633P8 Board SPAR & NPAR simulation

Figure 4. Agilent Technologies ADS2006A simulation circuit of a MGA-633P8 based 900 MHz LNA

4
Results and discussion
The general measurement conditions were f0 = 450 MHz,
Vdd = 5V, and Idd = 55 mA. Key specifications for design
engineers are low noise in conjunction with good return
loss (RL). This is because diplexers and filters are detuned
by reflective terminations.
At 450 MHz the demonstration board LNA achieved a
noise figure, F, of 0.46 dB, a gain, G, of 22.45 dB and both
IRL and ORL better than –15 dB. The wide bandwidth of
the input and output match is favorable from the system
standpoint as it prevents detuning of the input/output fil-
ters out-of-band frequency response. For both the G and
RL parameters there is good agreement between simu-
lated and measured results.
25
22
Sim Gain
19 Meas Gain
Gain, dB
Although this LNA targets 400-500MHz Cellular applica-
tions, the good noise figure and return loss results from
UHF to S-band show that the MGA-633P8 will be useful
in wideband/multi-band applications such as Cable/Sat-
ellite TV distribution infrastructure, scanners, and military
and multi-service radios.
The measured Rollett stability factor, k, is greater than 1
when evaluated from HF to approximately 20 times the
operating frequency. The Geometrically derived stabil-
ity factor, Mu, for both source and load is greater than 1
also. This means the LNA will be unconditionally stable
with any termination having a positive real part. For ad-
ditional margin on the stability factors resistor R3 can be
decreased at the expense of lower IP3.
2.5
11.00
2 StabFact_K
Mu_load
9.00
Noise Figure, dB
Mu_source
1.5

Sim NF
Meas NF Stability 7.00
16 1
5.00
13 0.5
3.00
10 0
100 300 500 700 900
MHz 1.00
0 2000 4000 6000 8000 10000
Figure 5. Simulated and measured Gain and Noise Figure vs. frequency MHz
Figure 7. Wideband Rollett and Geometrically Derived source and load
The simulated noise figure is 0.1 dB higher than the mea- stability factors vs. frequency
sured result at f0. This small difference is not unusual and
has been ascribed to a system repeatability issues. An ATN
With a 55 mA quiescent bias, the gain dropped 1 dB from
source-pull system was used for device noise character-
nominal at an RF input drive of 3.0 dBm. This corresponds
ization whereas an Agilent 8970S noise figure meter was
to an output 1-dB compression point (P1dB) of 22.3 dBm.
used for the final measurement. There are also different
sample and day-to-day variations that contribute to re- 25 70
peatability [ 5]. 68
Output Power, dBm and Gain, dB

20
Fundamental 66
0 15 Gain 64
Sim IRL Id
Sim ORL 10 62
Id, mA

-5 Meas IRL 60
Meas ORL 5 58
Return Loss, dB

-10 56
0
54
-15 -5
52
-10 50
-20 -30 -25 -20 -15 -10 -5 0 5
Input Power, dBm

-25 Figure 8. Po, G and Idd vs. Pi

100 300 500 700 900
MHz
Figure 6. Simulated and measured noise figure vs. frequency

5
The point where the fundamental signal power (Pfund) Appendix 1 – Improved input matching version
and the third order intermodulation distortion theoreti-
cally intersect is called the third order intercept point, For an application that requires better input match than
OIP3, is a measure of amplifier linearity. Equation 6 shows -15 dB, the component values under the “improved IRL”
how OIP3 is calculated: column resulted in IRL = -22 dB (fig. 11). An additional
inductor L3 is required. The noise figure was slightly de-
ΔIM graded (0.62 dB) in this LNA version with a 3-element in-
OIP3 = Pfund + Eq. 6 put match.
2
ΔIM is difference between the fundamental and the inter- Table 3. MGA-633P8 demonstration board part list with im-
modulation product power in dB. Two input tones at 445 proved IRL
MHz and 455 MHz were used for this measurement; how- Position Value Description
ever, other frequency spacing is not expected to change C1 100 pF Murata GRM15
the results significantly. In the linear operating region (Pi <
C2, C3 22 pF Murata GRM15
-10 dBm), OIP3 is above 37 dBm at standard biasing.
L1, L2 68 nH Toko LL1005
40 39
L3 100nH Toko LL1005
20 37 C4 47 pF Murata GRM15
0 35 C5, C6 10 nF Murata GRM
R1 100 Ω
IP3, dBm
-20 33
dBm

R2 4.7 Ω
-40 31
Rbias 6200 Ω
-60 29 SMA Connectors 142-0701-851 Johnson
IMD
Pout Note: All components are 0402 size unless otherwise noted
-80 27
IP3
Vdd
-100 25
-30 -25 -20 -15 -10 -5
Input Power, dBm Rbias
Figure 9. Fundamental, 3rd order intermodulation product, and, OIP3 vs. Pi C5 C6

R1 R2
If either higher or lower linearity is required, the OIP3 can C4
C3
be varied as much as 10 dB by operating at different Idd
values in the 25 mA to 75 mA range. Gain and P1dB are L2
minimally affected (ΔG and ΔP1dB ≤ ~0.5 dB) when Idd is L1
P1 P8
varied. Using the same bias and matching networks the P2 P7
Input Output
Vdd was dropped to 3.3V. The Id decreased to 30mA. The P3 P6
IP3 decreased to 32dBm. Gain, noise figure and return loss L3 C1 C2
P4 P5
remained similar to results presented. Centre tab

MGA-633P8
Summary Figure 10. Improved input RL LNA circuit schematic
An MGA-633P8 LNA for 400-500MHz applications has
30.00 5.00
been designed and prototyped. Measured and simulated dB(S(1,1)) dB(S(1,2))
results show that the Avago MGA-633P8 has excellent NF, 20.00 dB(S(2,2)) dB(S(2,1))
Gain, Isolation, IPRL and OPRL, dB

StabFact1
G, and ORL performance with minimal external compo- 10.00 4.00
0.00
Stability Factor, K

nent count.
-10.00 3.00
Table 2. Typical Performance for MGA-633P8 application
-20.00
demoboard. (Results at 450 MHz)
-30.00 2.00
Parameter Typ. Unit -40.00
Gain 22.5 dB -50.00 1.00
OIP3 37.8 dBm -60.00

P1dB 22.3 dBm -70.00 0.00

0 2000 4000 6000 8000 10000
NF 0.46 dB Frequency, MHz
Figure 11. Improved input RL LNA circuit results
6
References and Resources
1. Agilent Technologies application note, “AN57-1 Fundamentals of RF and Microwave Noise Figure Measurements,”
[Online] Available: http://www.agilent.com
2. I. Hunter, R. Ranson, A. Guyette, and A. Abunjaileh, “Microwave Filter Design from a Systems Perspective,” IEEE
Microwave Magazine, pp. 71-77, Oct. 2007.
3. K. V. Puglia, “A General Design Procedure for Bandpass Filters Derived From Low Pass Prototype Elements: Part I”,
Microwave Journal, pp. 28, Dec. 2000.
4. C. Bovick, RF Circuit Design. Carmel, IN: Howard W. Sams, 1982, pp. 68.
5. C. A Morales-Silva, L. Dunleavy, and R. Connick, “Noise Parameter Measurement Verification by Means of Benchmark
Transistors”, High Frequency Electronics, Feb. 2009.
6. Avago Web: http://www.avagotechwireless.com/
7. Avago Flash Video: http://www.avagotech.com/pages/wimaxfrontend/
8. Avago Wireless Semiconductor Solutions for RF and Microwave Communications: http://avagotechwireless.com/
collateral/wireless_semi_Solns_SG.pdf
9. Avago Semiconductor Wireless Applications and Selection Guides: http://avagotechwireless.com/collateral/
Semi_wireless_apps_SG.pdf

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Data subject to change. Copyright © 2005-2012 Avago Technologies. All rights reserved.
AV02-3792EN - September 11, 2012