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UC3842A, UC3843A, UC2842A, UC2843A High Performance Current Mode Controllers
UC3842A, UC3843A, UC2842A, UC2843A High Performance Current Mode Controllers
UC2842A, UC2843A
High Performance
Current Mode Controllers
The UC3842A, UC3843A series of high performance fixed
frequency current mode controllers are specifically designed for http://onsemi.com
off−line and DC−to−DC converter applications offering the designer a
cost effective solution with minimal external components. These
integrated circuits feature a trimmed oscillator for precise duty cycle PDIP−8
control, a temperature compensated reference, high gain error N SUFFIX
amplifier, current sensing comparator, and a high current totem pole CASE 626
8
output ideally suited for driving a power MOSFET.
1
Also included are protective features consisting of input and
reference undervoltage lockouts each with hysteresis, cycle−by−cycle
current limiting, programmable output deadtime, and a latch for single SOIC−14
D SUFFIX
pulse metering. 14 CASE 751A
These devices are available in an 8−pin dual−in−line plastic package
1
as well as the 14−pin plastic surface mount (SOIC−14). The SOIC−14
package has separate power and ground pins for the totem pole output
stage.
8 SOIC−8
The UCX842A has UYLO thresholds of 16 V (on) and 10 V (off), D1 SUFFIX
ideally suited for off−line converters. The UCX843A is tailored for 1 CASE 751
lower voltage applications having UVLO thresholds of 8.5 V (on) and
7.6 V (off).
NC 6 9 GND
(Top View)
ORDERING INFORMATION
See detailed ordering and shipping information in the package
dimensions section on page 15 of this data sheet.
VCC 7(12)
Vref VCC
5.0V
Undervoltage
Reference
8(14) R Lockout
Vref VC
R Undervoltage
Lockout 7(11)
RTCT Output
Oscillator
4(7) Latching 6(10)
Voltage PWM Power
Feedback + Ground
Input − 5(8)
2(3) Error Current
Output Amplifier Sense
Compensation 3(5) Input
1(1)
GND 5(9)
Pin numbers in parenthesis are for the D suffix SOIC−14 package.
MAXIMUM RATINGS
Rating Symbol Value Unit
Bias and Driver Voltages (Zero Series Impedance, see also Total Device spec) VCC, VC 30 V
Total Power Supply and Zener Current (ICC + IZ) 30 mA
Output Current, Source or Sink (Note 1) IO 1.0 A
Output Energy (Capacitive Load per Cycle) W 5.0 J
Current Sense and Voltage Feedback Inputs Vin − 0.3 to + 5.5 V
Error Amp Output Sink Current IO 10 mA
Power Dissipation and Thermal Characteristics
D Suffix, Plastic Package
Maximum Power Dissipation @ TA = 25°C PD 862 mW
Thermal Resistance, Junction−to−Air RJA 145 °C/W
N Suffix, Plastic Package
Maximum Power Dissipation @ TA = 25°C PD 1.25 W
Thermal Resistance, Junction−to−Air RJA 100 °C/W
Operating Junction Temperature TJ + 150 °C
Operating Ambient Temperature TA °C
UC3842A, UC3843A 0 to + 70
UC2842A, UC2843A − 25 to + 85
Storage Temperature Range Tstg − 65 to + 150 °C
Maximum ratings are those values beyond which device damage can occur. Maximum ratings applied to the device are individual stress limit
values (not normal operating conditions) and are not valid simultaneously. If these limits are exceeded, device functional operation is not implied,
damage may occur and reliability may be affected.
1. Maximum Package power dissipation limits must be observed.
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UC3842A, UC3843A, UC2842A, UC2843A
ELECTRICAL CHARACTERISTICS (VCC = 15 V, [Note 2], RT = 10 k, CT = 3.3 nF, TA = Tlow to Thigh [Note 3],
unless otherwise noted.)
UC284XA UC384XA
Long Term Stability (TA = 125°C for 1000 Hours) S − 5.0 − − 5.0 − mV
Output Short Circuit Current ISC − 30 − 85 − 180 − 30 − 85 − 180 mA
OSCILLATOR SECTION
Frequency fosc kHz
TJ = 25°C 47 52 57 47 52 57
TA = Tlow to Thigh 46 − 60 46 − 60
Frequency Change with Voltage (VCC = 12 V to 25 V) fosc/V − 0.2 1.0 − 0.2 1.0 %
Frequency Change with Temperature fosc/T − 5.0 − − 5.0 − %
TA = Tlow to Thigh
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UC3842A, UC3843A, UC2842A, UC2843A
ELECTRICAL CHARACTERISTICS (VCC = 15 V, [Note 4], RT = 10 k, CT = 3.3 nF, TA = Tlow to Thigh [Note 5],
unless otherwise noted.)
UC284XA UC384XA
Characteristics Symbol Min Typ Max Min Typ Max Unit
CURRENT SENSE SECTION
Current Sense Input Voltage Gain (Notes 6 & 7) AV 2.85 3.0 3.15 2.85 3.0 3.15 V/V
Maximum Current Sense Input Threshold (Note 6) Vth 0.9 1.0 1.1 0.9 1.0 1.1 V
Power Supply Rejection Ratio PSRR dB
VCC = 12 to 25 V (Note 6) − 70 − − 70 −
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UC3842A, UC3843A, UC2842A, UC2843A
80 100
20
20
8.0 10
5.0
5.0
2.0 VCC = 15 V
TA = 25°C 2.0
0.8 1.0
10 k 20 k 50 k 100 k 200 k 500 k 1.0 M 10 k 20 k 50 k 100 k 200 k 500 k 1.0 M
fOSC, OSCILLATOR FREQUENCY (Hz) fOSC, OSCILLATOR FREQUENCY (Hz)
Figure 2. Timing Resistor versus Figure 3. Output Deadtime versus
Oscillator Frequency Oscillator Frequency
VCC = 15 V CT = 3.3 nF
VOSC = 2.0 V 90 TA = 25°C
8.5
80 Idischg = 7.2 mA
8.0 70
60
7.5
50 Idischg = 9.5 mA
7.0 40
−55 −25 0 25 50 75 100 125 800 1.0 k 2.0 k 3.0 k 4.0 k 6.0 k 8.0 k
TA, AMBIENT TEMPERATURE (°C) RT, TIMING RESISTOR ()
Figure 4. Oscillator Discharge Current Figure 5. Maximum Output Duty Cycle
versus Temperature versus Timing Resistor
VCC = 15 V VCC = 15 V
2.55 V AV = −1.0 3.0 V AV = −1.0
TA = 25°C TA = 25°C
20 mV/DIV
200 mV/DIV
2.5 V 2.5 V
2.45 V 2.0 V
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UC3842A, UC3843A, UC2842A, UC2843A
40 90 0.6
Phase TA = 125°C
20 120 0.4 TA = −55°C
0 150 0.2
−20 180 0
10 100 1.0 k 10 k 100 k 1.0 M 10 M 0 2.0 4.0 6.0 8.0
f, FREQUENCY (Hz) VO, ERROR AMP OUTPUT VOLTAGE (V)
Figure 8. Error Amp Open Loop Gain and Figure 9. Current Sense Input Threshold
Phase versus Frequency versus Error Amp Output Voltage
0 110
VCC = 15 V
VCC = 15 V
−4.0
RL ≤ 0.1
−8.0 90
−12
−16 TA = 125°C 70
TA = 55°C
−20 TA = 25°C
−24 50
0 20 40 60 80 100 120 −55 −25 0 25 50 75 100 125
Iref, REFERENCE SOURCE CURRENT (mA) TA, AMBIENT TEMPERATURE (°C)
Figure 10. Reference Voltage Change Figure 11. Reference Short Circuit Current
versus Source Current versus Temperature
, OUTPUT VOLTAGE CHANGE (2.0 mV/DIV)
, OUTPUT VOLTAGE CHANGE (2.0 mV/DIV)
VCC = 15 V
VCC = 12 V to 25 V
IO = 1.0 mA to 20 mA
TA = 25°C
TA = 25°C
O
O
ΔV
ΔV
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UC3842A, UC3843A, UC2842A, UC2843A
3.0
TA = −55°C
2.0 TA = 25°C
10%
1.0 Sink Saturation
(Load to VCC) GND
0
0 200 400 600 800 50 ns/DIV
IO, OUTPUT LOAD CURRENT (mA)
25
VCC = 30 V
CL = 15 pF
I CC , SUPPLY CURRENT (mA)
20 V/DIV
TA = 25°C 20
15
I CC , SUPPLY CURRENT
10 RT = 10 k
CT = 3.3 nF
100 mA/DIV
UCX843A
UCX842A
VFB = 0 V
5 ISense = 0 V
TA = 25°C
0
100 ns/DIV 0 10 20 30 40
VCC , SUPPLY VOLTAGE
Figure 16. Output Cross Conduction Figure 17. Supply Current versus
Supply Voltage
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UC3842A, UC3843A, UC2842A, UC2843A
VCC Vin
VCC 7(12)
Vref 36V
Reference +
8(14) Regulator −
VCC +
R Internal UVLO
2.5V Bias −
+ VC
RT R + − 7(11)
3.6V Vref
− UVLO
Output Q1
Oscillator
4(7) T Q 6(10)
CT +
1.0mA
S Power Ground
+ Q
− 5(8)
Voltage Feedback − 2R R PWM
+
Input 2(3) Latch
Error R 1.0V Current Sense Input
Output Amplifier
Compensation Current Sense 3(5)
1(1) Comparator RS
Capacitor CT
Latch
‘‘Set’’ Input
Output/
Compensation
Current Sense
Input
Latch
‘‘Reset’’ Input
Output
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UC3842A, UC3843A, UC2842A, UC2843A
OPERATING DESCRIPTION
The UC3842A, UC3843A series are high performance, is removed, or at the beginning of a soft−start interval
fixed frequency, current mode controllers. They are (Figures 24, 25). The Error Amp minimum feedback
specifically designed for Off−Line and DC−to−DC resistance is limited by the amplifier’s source current
converter applications offering the designer a cost effective (0.5 mA) and the required output voltage (VOH) to reach the
solution with minimal external components. A comparator’s 1.0 V clamp level:
representative block diagram is shown in Figure 18. 3.0 (1.0 V) + 1.4 V
Rf(min) ≈ = 8800
0.5 mA
Oscillator
The oscillator frequency is programmed by the values Current Sense Comparator and PWM Latch
selected for the timing components RT and CT. Capacitor CT The UC3842A, UC3843A operate as a current mode
is charged from the 5.0 V reference through resistor RT to controller, whereby output switch conduction is initiated by
approximately 2.8 V and discharged to 1.2 V by an internal the oscillator and terminated when the peak inductor current
current sink. During the discharge of CT, the oscillator reaches the threshold level established by the Error
generates and internal blanking pulse that holds the center Amplifier Output/Compensation (Pin 1). Thus the error
input of the NOR gate high. This causes the Output to be in signal controls the peak inductor current on a
a low state, thus producing a controlled amount of output cycle−by−cycle basis. The current Sense Comparator PWM
deadtime. Figure 2 shows RT versus Oscillator Frequency Latch configuration used ensures that only a single pulse
and Figure 3, Output Deadtime versus Frequency, both for appears at the Output during any given oscillator cycle. The
given values of CT. Note that many values of RT and CT will inductor current is converted to a voltage by inserting the
give the same oscillator frequency but only one combination ground referenced sense resistor RS in series with the source
will yield a specific output deadtime at a given frequency. of output switch Q1. This voltage is monitored by the
The oscillator thresholds are temperature compensated, and Current Sense Input (Pin 3) and compared a level derived
the discharge current is trimmed and guaranteed to within from the Error Amp Output. The peak inductor current under
±10% at TJ = 25°C. These internal circuit refinements normal operating conditions is controlled by the voltage at
minimize variations of oscillator frequency and maximum pin 1 where:
output duty cycle. The results are shown in Figures 4 and 5.
V(Pin 1) − 1.4 V
In many noise sensitive applications it may be desirable to Ipk =
3 RS
frequency−lock the converter to an external system clock.
This can be accomplished by applying a clock signal to the Abnormal operating conditions occur when the power
circuit shown in Figure 21. For reliable locking, the supply output is overloaded or if output voltage sensing is
free−running oscillator frequency should be set about 10% lost. Under these conditions, the Current Sense Comparator
less than the clock frequency. A method for multi unit threshold will be internally clamped to 1.0 V. Therefore the
synchronization is shown in Figure 22. By tailoring the maximum peak switch current is:
clock waveform, accurate Output duty cycle clamping can 1.0 V
Ipk(max) =
be achieved. RS
When designing a high power switching regulator it
Error Amplifier
becomes desirable to reduce the internal clamp voltage in
A fully compensated Error Amplifier with access to the
order to keep the power dissipation of RS to a reasonable
inverting input and output is provided. It features a typical
level. A simple method to adjust this voltage is shown in
dc voltage gain of 90 dB, and a unity gain bandwidth of
Figure 23. The two external diodes are used to compensate
1.0 MHz with 57 degrees of phase margin (Figure 8). The
the internal diodes yielding a constant clamp voltage over
noninverting input is internally biased at 2.5 V and is not
temperature. Erratic operation due to noise pickup can result
pinned out. The converter output voltage is typically divided
if there is an excessive reduction of the Ipk(max) clamp
down and monitored by the inverting input. The maximum
voltage.
input bias current is −2.0 A which can cause an output
A narrow spike on the leading edge of the current
voltage error that is equal to the product of the input bias
waveform can usually be observed and may cause the power
current and the equivalent input divider source resistance.
supply to exhibit an instability when the output is lightly
The Error Amp Output (Pin 1) is provide for external loop
loaded. This spike is due to the power transformer
compensation (Figure 31). The output voltage is offset by
interwinding capacitance and output rectifier recovery time.
two diode drops (≈ 1.4 V) and divided by three before it
The addition of an RC filter on the Current Sense Input with
connects to the inverting input of the Current Sense
a time constant that approximates the spike duration will
Comparator. This guarantees that no drive pulses appear at
usually eliminate the instability; refer to Figure 27.
the Output (Pin 6) when Pin 1 is at its lowest state (VOL).
This occurs when the power supply is operating and the load
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UC3842A, UC3843A, UC2842A, UC2843A
4 7 RT/CT The Oscillator frequency and maximum Output duty cycle are programmed by connecting
resistor RT to Vref and capacitor CT to ground. Operation to 500 kHz is possible.
5 − GND This pin is the combined control circuitry and power ground (8−pin package only).
6 10 Output This output directly drives the gate of a power MOSFET. Peak currents up to 1.0 A are
sourced and sunk by this pin.
− 8 Power Ground This pin is a separate power ground return (14−pin package only) that is connected back
to the power source. It is used to reduce the effects of switching transient noise on the control
circuitry.
− 11 VC The Output high state (VOH) is set by the voltage applied to this pin (14−pin package only).
With a separate power source connection, it can reduce the effects of switching transient
noise on the control circuitry.
− 9 GND This pin is the control circuitry ground return (14−pin package only) and is connected back to
the power source ground.
− 2,4,6,13 NC No connection (14−pin package only). These pins are not internally connected.
Undervoltage Lockout and has a typical rise and fall time of 50 ns with a 1.0 nF load.
Two undervoltage lockout comparators have been Additional internal circuitry has been added to keep the
incorporated to guarantee that the IC is fully functional Output in a sinking mode whenever an undervoltage lockout
before the output stage is enabled. The positive power is active. This characteristic eliminates the need for an
supply terminal (VCC) and the reference output (Vref) are external pull−down resistor.
each monitored by separate comparators. Each has built−in The SOIC−14 surface mount package provides separate
hysteresis to prevent erratic output behavior as their pins for VC (output supply) and Power Ground. Proper
respective thresholds are crossed. The VCC comparator implementation will significantly reduce the level of
upper and lower thresholds are 16 V/10 V for the UCX842A, switching transient noise imposed on the control circuitry.
and 8.4 V/7.6 V for the UCX843A. The Vref comparator This becomes particularly useful when reducing the Ipk(max)
upper and lower thresholds are 3.6V/3.4 V. The large clamp level. The separate VC supply input allows the
hysteresis and low startup current of the UCX842A makes designer added flexibility in tailoring the drive voltage
it ideally suited in off−line converter applications where independent of VCC. A zener clamp is typically connected
efficient bootstrap startup techniques are required to this input when driving power MOSFETs in systems
(Figure 34). The UCX843A is intended for lower voltage dc where VCC is greater than 20 V. Figure 26 shows proper
to dc converter applications. A 36 V zener is connected as power and control ground connections in a current sensing
a shunt regulator form VCC to ground. Its purpose is to power MOSFET application.
protect the IC from excessive voltage that can occur during
system startup. The minimum operating voltage for the Reference
UCX842A is 11 V and 8.2 V for the UCX843A. The 5.0 V bandgap reference is trimmed to ±1.0%
tolerance at TJ = 25°C on the UC284XA, and ± 2.0% on the
Output UC384XA. Its primary purpose is to supply charging current
These devices contain a single totem pole output stage that to the oscillator timing capacitor. The reference has short
was specifically designed for direct drive of power circuit protection and is capable of providing in excess of
MOSFETs. It is capable of up to ±1.0 A peak drive current 20 mA for powering additional control system circuitry.
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UC3842A, UC3843A, UC2842A, UC2843A
DESIGN CONSIDERATIONS
Do not attempt to construct the converter on (t3) decreases to (I + I m2/m1) (m2/m1). This perturbation
wire−wrap or plug−in prototype boards. High Frequency is multiplied by m2.m1 on each succeeding cycle, alternately
circuit layout techniques are imperative to prevent pulse increasing and decreasing the inductor current at switch
width jitter. This is usually caused by excessive noise turn−on. Several oscillator cycles may be required before
pick−up imposed on the Current Sense or Voltage Feedback the inductor current reaches zero causing the process to
inputs. Noise immunity can be improved by lowering circuit commence again. If m2/m1 is greater than 1, the converter
impedances at these points. The printed circuit layout should will be unstable. Figure 20B shows that by adding an
contain a ground plane with low−current signal and artificial ramp that is synchronized with the PWM clock to
high−current switch and output grounds returning on the control voltage, the I perturbation will decrease to zero
separate paths back to the input filter capacitor. Ceramic on succeeding cycles. This compensation ramp (m3) must
bypass capacitors (0.1 F) connected directly to VCC, VC, have a slope equal to or slightly greater than m2/2 for
and Vref may be required depending upon circuit layout. stability. With m2/2 slope compensation, the average
This provides a low impedance path for filtering the high inductor current follows the control voltage yielding true
frequency noise. All high current loops should be kept as current mode operation. The compensating ramp can be
short as possible using heavy copper runs to minimize derived from the oscillator and added to either the Voltage
radiated EMI. The Error Amp compensation circuitry and Feedback or Current Sense inputs (Figure 33).
the converter output voltage divider should be located close
to the IC and as far as possible from the power switch and I
(A)
other noise generating components. Control Voltage
Current mode converters can exhibit subharmonic m2
oscillations when operating at a duty cycle greater than 50% m1
Inductor I + I m2 m2 m2
with continuous inductor current. This instability is Current m1 I + I m m1
1
independent of the regulators closed−loop characteristics Oscillator Period
and is caused by the simultaneous operating conditions of t0 t1 t2 t3
fixed frequency and peak current detecting. Figure 20A
shows the phenomenon graphically. At t0, switch
(B)
conduction begins, causing the inductor current to rise at a Control Voltage m3
slope of m1. This slope is a function of the input voltage
divided by the inductance. At t1, the Current Sense Input I
reaches the threshold established by the control voltage. m1
m2 Inductor
This causes the switch to turn off and the current to decay at Current
a slope of m2 until the next oscillator cycle. The unstable Oscillator Period
condition can be shown if a perturbation is added to the
control voltage, resulting in a small I (dashed line). With t4 t5 t6
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UC3842A, UC3843A, UC2842A, UC2843A
Vref
8(14) R
Bias RA 8(14) R
RT R
8 4 Bias
R
RB
Osc 6 5.0k
External + + Osc
CT 4(7) − R
Sync 0.01 3 +
5.0k
5 Q 4(7)
Input +
− 2 + S
2R − 7 +
47 2(3) EA −
R 5.0k MC1455 EA 2R
C 2(3)
R
1(1) 1
1(1)
5(9)
To 5(9)
1.44 RB Additional
The diode clamp is required if the Sync amplitude is large enough to f= Dmax =
(RA + 2RB)C RA + 2RB UCX84XA’s
cause the bottom side of CT to go more than 300 mV below ground.
Figure 21. External Clock Synchronization Figure 22. External Duty Cycle Clamp and
Multi Unit Synchronization
VCC
Vin
7(12)
5.0Vref +
− +
8(14) R
Bias + −
R + −
7(11) 5.0Vref
− Q1 8(14) R
Osc Bias
+ 6(10) +
4(7) VClamp R −
+
1.0mA S
+ − Q −
R2 − + R 5(8)
EA 2R Osc
2(3) Comp/Latch
R 4(7) +
1.0V 3(5) 1.0mA S
1(1) RS + − Q
R1 − + R
EA 2R
5(9) 2(3)
1.0M R
1.0V
1.67 R1 R2 VClamp 1(1)
VClamp = + 0.33 x 10 − 3 Ipk(max) = C
R1 + R2 RS
R2 5(9)
+1 Where: 0 ≤ VClamp ≤ 1.0 V tSoft−Start 3600C in F
R1
Figure 23. Adjustable Reduction of Clamp Level Figure 24. Soft−Start Circuit
VCC
Vin RS Ipk rDS(on)
VCC VPin 5 =
Vin (12) rDM(on) + RS
7(12)
If: SENSEFET = MTP10N10M
+ RS = 200
+ 5.0Vref −
5.0Vref − +
+ Then: Vpin 5 = 0.075 Ipk
8(14) R −
− + D SENSEFET
Bias + −
R − +
+ (11)
7(11) S
−
− Q1
Osc (10) G K
4(7) + 6(10) M
VClamp S
1.0mA S − Q
+ − Q + R (8)
− + R 5(8) Power Ground
EA 2R Comp/Latch
2(3) Comp/Latch To Input Source
R
R2 (5) Return
1.0V 3(5) RS
1(1) RS 1/4 W
Control CIrcuitry
MPSA63 5(9) Ground:
C
R1 To Pin (9)
1.67
VClamp = Ipk(max) = VClamp Where: 0 ≤ VClamp ≤ 1.0 V
R2 RS
+1 Virtually lossless current sensing can be achieved with the implementation of a
R1 VC R1 R2
tSoftstart = − In 1− C SENSEFET power switch. For proper operation during over current conditions, a
3VClamp R1 + R2 reduction of the Ipk(max) clamp level must be implemented. Refer to Figures 23 and 25.
Figure 25. Adjustable Buffered Reduction of Figure 26. Current Sensing Power MOSFET
Clamp Level with Soft−Start
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UC3842A, UC3843A, UC2842A, UC2843A
VCC
VCC Vin
Vin 7(12)
7(12)
5.0Vref +
5.0Vref + −
− +
+
+ −
+ − −
− +
+ 7(11)
7(11) Rg
− Q1
− Q1
6(10)
6(10)
S
S − Q
− Q + R 5(8)
+ R 5(8)
R Comp/Latch
Comp/Latch
3(5)
3(5)
RS
C RS
Series gate resistor Rg will damp any high frequency parasitic oscillations
The addition of the RC filter will eliminate instability caused by the leading caused by the MOSFET input capacitance and any series wiring inductance
edge spike on the current waveform. in the gate−source circuit.
Figure 27. Current Waveform Spike Suppression Figure 28. MOSFET Parasitic Oscillations
IB
Vin
+ VCC Vin
7(12)
0
Base
Charge + Isolation
− Removal 5.0Vref −
C1 + Boundary
ÉÉ É
+ − VGS Waveforms
+ − Q1
É
É ÉÉ
Q1 7(11) +
+
6(1) − 0 0
− −
6(1) 50% DC 25% DC
5(8) S V(pin 1) − 1.4 NP
− Q Ipk =
+ R 5(8) NS
3 RS
Comp/Latch R
3(5)
RS 3(5) C
RS NS Np
The totem−pole output can furnish negative base current for enhanced
transistor turn−off, with the addition of capacitor C1.
Figure 29. Bipolar Transistor Drive Figure 30. Isolated MOSFET Drive
From VO
2.5V +
Ri 2(3) 1.0mA
+
8(14) R −
EA 2R
Bias Rd CI Rf R
R
1(1)
Osc 5(9)
4(7) +
1.0mA Error Amp compensation circuit for stabilizing any current−mode topology except
+
− for boost and flyback converters operating with continuous inductor current.
EA 2R
2(3)
R
From VO
1(1) 2.5V +
MCR 2N 5(9) Rp 2(3) 1.0mA
Ri +
101 3905 −
EA 2R
2N Rd CI Rf
3903 Cp R
1(1)
5(9)
The MCR101 SCR must be selected for a holding of less than 0.5 mA at TA(min).
The simple two transistor circuit can be used in place of the SCR as shown. All Error Amp compensation circuit for stabilizing current−mode boost and flyback
resistors are 10 k. topologies operating with continuous inductor current.
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UC3842A, UC3843A, UC2842A, UC2843A
VCC
Vin
7(12)
8(14) +
5.0Vref −
R +
RT Bias
+
−
MPS3904 −
R +
7(11)
4(7) −
RSlope
Osc
From VO CT 6(10)
+ −m
Ri 1.0mA S
2(3) + Q
− −
2R + R 5(8)
EA
Cf R 1.0V Comp/Latch
Rd Rf
m 3(5)
1(1) RS
−3.0 m
5(9)
The buffered oscillator ramp can be resistively summed with either the voltage feedback or current sense inputs to provide slope compensation.
L1
+ MBR1635
4.7 MDA 250 4.7k 3300pF 5.0V/4.0A
202 T1 + +
56k 2200 1000
115Va
c 5.0V RTN
MUR110
1N4935 1N4935 12V/0.3A
+ L2 +
1000 10
7(12) + +
68 47 ±12V RTN
100
8(14) 1000 10
+ + +
5.0Vref −12V/0.3A
− +
0.01 1N4937 MUR110
Bias 680pF L3
+
+ −
10k 7(11) 1N4937
2.7k
4(7) 22
Osc
4700pF + 6(10) MTP
18k 4N50 L1 − 15 H at 5.0 A, Coilcraft Z7156.
2(3) S L2, L3 − 25 H at 1.0 A, Coilcraft Z7157.
+ Q
−
− + R 5(8)
EA
150k
100pF
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UC3842A, UC3843A, UC2842A, UC2843A
ORDERING INFORMATION
Device Operating Temperature Range Package Shipping †
UC3842AN PDIP−8
UC3842ANG PDIP−8
(Pb−Free)
50 Units / Rail
UC3842AN2 PDIP−8
UC3842AN2G PDIP−8
(Pb−Free)
UC3843AN PDIP−8
UC3843ANG PDIP−8
(Pb−Free)
50 Units / Rail
UC3843AN2 PDIP−8
UC3843AN2G TA = 0° to +70°C PDIP−8
(Pb−Free)
UC3843AD1R2 SOIC−8
UC3843AD1R2G SOIC−8
(Pb−Free)
2500 / Tape & Reel
UC3843AD2R2 SOIC−14
UC3843AD2R2G SOIC−14
(Pb−Free)
†For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging
Specifications Brochure, BRD8011/D.
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15
UC3842A, UC3843A, UC2842A, UC2843A
ORDERING INFORMATION
Device Operating Temperature Range Package Shipping †
UC2842AN PDIP−8 50 Units / Rail
UC2842ANG PDIP−8 50 Units / Rail
(Pb−Free)
MARKING DIAGRAMS
x = 2 or 3
A = Assembly Location
WL, L = Wafer Lot
YY, Y = Year
WW, W = Work Week
G or G = Pb−Free Package
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16
UC3842A, UC3843A, UC2842A, UC2843A
PACKAGE DIMENSIONS
PDIP−8
N SUFFIX
CASE 626−05
ISSUE L
NOTES:
1. DIMENSION L TO CENTER OF LEAD WHEN
8 5 FORMED PARALLEL.
2. PACKAGE CONTOUR OPTIONAL (ROUND OR
SQUARE CORNERS).
−B− 3. DIMENSIONING AND TOLERANCING PER ANSI
Y14.5M, 1982.
1 4
MILLIMETERS INCHES
DIM MIN MAX MIN MAX
A 9.40 10.16 0.370 0.400
F B 6.10 6.60 0.240 0.260
C 3.94 4.45 0.155 0.175
NOTE 2 −A− D 0.38 0.51 0.015 0.020
L F 1.02 1.78 0.040 0.070
G 2.54 BSC 0.100 BSC
H 0.76 1.27 0.030 0.050
J 0.20 0.30 0.008 0.012
C K 2.92 3.43 0.115 0.135
L 7.62 BSC 0.300 BSC
M −−− 10 _ −−− 10_
−T− J N 0.76 1.01 0.030 0.040
SEATING N
PLANE
M
D K
H G
0.13 (0.005) M T A M B M
SOIC−14
D SUFFIX
CASE 751A−03
ISSUE G
NOTES:
−A− 1. DIMENSIONING AND TOLERANCING PER
14 8 ANSI Y14.5M, 1982.
2. CONTROLLING DIMENSION: MILLIMETER.
3. DIMENSIONS A AND B DO NOT INCLUDE
MOLD PROTRUSION.
4. MAXIMUM MOLD PROTRUSION 0.15 (0.006)
−B− P 7 PL PER SIDE.
5. DIMENSION D DOES NOT INCLUDE
0.25 (0.010) M B M
DAMBAR PROTRUSION. ALLOWABLE
DAMBAR PROTRUSION SHALL BE 0.127
1 7 (0.005) TOTAL IN EXCESS OF THE D
DIMENSION AT MAXIMUM MATERIAL
G R X 45 _ F CONDITION.
C
MILLIMETERS INCHES
DIM MIN MAX MIN MAX
A 8.55 8.75 0.337 0.344
−T− B 3.80 4.00 0.150 0.157
K M J C 1.35 1.75 0.054 0.068
SEATING D 14 PL D 0.35 0.49 0.014 0.019
PLANE
0.25 (0.010) M T B S A S F 0.40 1.25 0.016 0.049
G 1.27 BSC 0.050 BSC
J 0.19 0.25 0.008 0.009
K 0.10 0.25 0.004 0.009
M 0_ 7_ 0_ 7_
P 5.80 6.20 0.228 0.244
R 0.25 0.50 0.010 0.019
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17
UC3842A, UC3843A, UC2842A, UC2843A
PACKAGE DIMENSIONS
SOIC−8
D1 SUFFIX
CASE 751−07
ISSUE AG
−X− NOTES:
1. DIMENSIONING AND TOLERANCING PER
A ANSI Y14.5M, 1982.
2. CONTROLLING DIMENSION: MILLIMETER.
3. DIMENSION A AND B DO NOT INCLUDE
MOLD PROTRUSION.
8 5 4. MAXIMUM MOLD PROTRUSION 0.15 (0.006)
PER SIDE.
B S 0.25 (0.010) M Y M 5. DIMENSION D DOES NOT INCLUDE DAMBAR
PROTRUSION. ALLOWABLE DAMBAR
1 PROTRUSION SHALL BE 0.127 (0.005) TOTAL
4 IN EXCESS OF THE D DIMENSION AT
−Y− K MAXIMUM MATERIAL CONDITION.
6. 751−01 THRU 751−06 ARE OBSOLETE. NEW
STANDARD IS 751−07.
G
MILLIMETERS INCHES
C N X 45 _ DIM MIN MAX MIN MAX
A 4.80 5.00 0.189 0.197
SEATING
PLANE B 3.80 4.00 0.150 0.157
−Z− C 1.35 1.75 0.053 0.069
D 0.33 0.51 0.013 0.020
0.10 (0.004) G 1.27 BSC 0.050 BSC
H M J H 0.10 0.25 0.004 0.010
D J 0.19 0.25 0.007 0.010
K 0.40 1.27 0.016 0.050
M 0_ 8_ 0 _ 8 _
0.25 (0.010) M Z Y S X S
N 0.25 0.50 0.010 0.020
S 5.80 6.20 0.228 0.244
SOLDERING FOOTPRINT*
1.52
0.060
7.0 4.0
0.275 0.155
0.6 1.270
0.024 0.050
ON Semiconductor and are registered trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make changes without further notice
to any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does SCILLC assume any liability
arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages.
“Typical” parameters which may be provided in SCILLC data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All
operating parameters, including “Typicals” must be validated for each customer application by customer’s technical experts. SCILLC does not convey any license under its patent rights
nor the rights of others. SCILLC products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications
intended to support or sustain life, or for any other application in which the failure of the SCILLC product could create a situation where personal injury or death may occur. Should
Buyer purchase or use SCILLC products for any such unintended or unauthorized application, Buyer shall indemnify and hold SCILLC and its officers, employees, subsidiaries, affiliates,
and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death
associated with such unintended or unauthorized use, even if such claim alleges that SCILLC was negligent regarding the design or manufacture of the part. SCILLC is an Equal
Opportunity/Affirmative Action Employer. This literature is subject to all applicable copyright laws and is not for resale in any manner.
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18