Kingdom of Saudi Arabia

Ministry of Higher Education

Majmaah University
College of Engineering
EE & CEN

Logic Design (CE 207, CE 213)

Chapter No. 2 – Part No. 2
Problem 2.14: Implement the Boolean Function
F  xy  x' y ' y ' z
Part (a): with AND, OR and Inverter Gates
F  xy  x' y ' y ' z

Part (b): with OR and Inverter Gates

F  xy  x' y ' y ' z
 F  ( x' y ' )'( x  y )'( y  z ' )'

Part (c): with AND and Inverter Gates

F  xy  x' y ' y ' z
 F  [( xy)' ( x' y ' )' ( y ' z )' ]'

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 Part (d): with NAND and Inverter Gates
F  xy  x' y ' y ' z
 F  [( xy)' ( x' y ' )' ( y ' z )' ]'

Part (e): with NOR and Inverter Gates

F  xy  x' y ' y ' z
 F  ( x' y ' )'( x  y )'( y  z ' )'

Problem 2.17: Obtain the Truth Table of the following function and express each
function in sum-of-minterms and product-of-maxterms form:

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 Part (a): ( xy  z )( y  xz)
x y z xy (xy + z) xz (y + xz) (xy + z)(y + xz)
0 0 0 0 0 0 0 0
0 0 1 0 1 0 0 0
0 1 0 0 0 0 1 0
0 1 1 0 1 0 1 1
1 0 0 0 0 0 0 0
1 0 1 0 1 1 1 1
1 1 0 1 1 0 1 1
1 1 1 1 1 1 1 1

Sum of Minterms: F ( x, y, z )  (3,5,6,7)

Product of Maxterm: F ( x, y, z )  (0,1,2,4)

Part (b): ( x  y ' )( y ' z )

x y z y’ (x + y’) (y’ + z) (x + y’)(y’ + z)
0 0 0 1 1 1 1
0 0 1 1 1 1 1
0 1 0 0 0 0 0
0 1 1 0 0 1 0
1 0 0 1 1 1 1
1 0 1 1 1 1 1
1 1 0 0 1 0 0
1 1 1 0 1 1 1

Sum of Minterms: F ( x, y, z )  (0,1,4,5,7)

Product of Maxterms: F ( x, y, z )  (2,3,6)

Problem 2.18: For the Boolean function:

F  xy' z  x' y ' z  w' xy  wx' y  wxy

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Part (a): Obtain the Truth Table of F
w x y z w’ x’ y’ xy’z x’y’z w’xy wx’y Wxy F
0 0 0 0 1 1 1 0 0 0 0 0 0
0 0 0 1 1 1 1 0 1 0 0 0 1
0 0 1 0 1 1 0 0 0 0 0 0 0
0 0 1 1 1 1 0 0 0 0 0 0 0
0 1 0 0 1 0 1 0 0 0 0 0 0
0 1 0 1 1 0 1 1 0 0 0 0 1
0 1 1 0 1 0 0 0 0 1 0 0 1
0 1 1 1 1 0 0 0 0 1 0 0 1
1 0 0 0 0 1 1 0 0 0 0 0 0
1 0 0 1 0 1 1 0 1 0 0 0 1
1 0 1 0 0 1 0 0 0 0 1 0 1
1 0 1 1 0 1 0 0 0 0 1 0 1
1 1 0 0 0 0 1 0 0 0 0 0 0
1 1 0 1 0 0 1 1 0 0 0 0 1
1 1 1 0 0 0 0 0 0 0 0 1 1
1 1 1 1 0 0 0 0 0 0 0 1 1

Part (b): Draw the Logic Diagram, using the original Boolean Expression
F  xy' z  x' y ' z  w' xy  wx' y  wxy

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 Part (c): Use Boolean Algebra to simplify the function to a minimum number of
literals
F  xy' z  x' y ' z  w' xy  wx' y  wxy
 F  xy' z  x' y ' z  w' xy  wxy  wx' y
 F  y ' z ( x  x)  xy( w' w)  wx' y
 F  y ' z (1)  xy(1)  wx' y
 F  y ' z  xy  wx' y
 F  y ' z  y ( x  x' w)
 F  y ' z  y ( x  w)
 F  y ' z  xy  wy
 F  wy  xy  y ' z

Part (d): Obtain the Truth Table of the function from the simplified expression and show
that it is the same as the one in Part (a)
 F  wy  xy  y ' z
w x y z y’ wy xy y’z F
0 0 0 0 1 0 0 0 0
0 0 0 1 1 0 0 1 1
0 0 1 0 0 0 0 0 0
0 0 1 1 0 0 0 0 0
0 1 0 0 1 0 0 0 0
0 1 0 1 1 0 0 1 1
0 1 1 0 0 0 1 0 1
0 1 1 1 0 0 1 0 1
1 0 0 0 1 0 0 0 0
1 0 0 1 1 0 0 1 1
1 0 1 0 0 1 0 0 1
1 0 1 1 0 1 0 0 1
1 1 0 0 1 0 0 0 0
1 1 0 1 1 0 0 1 1
1 1 1 0 0 1 1 0 1
1 1 1 1 0 1 1 0 1

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 Part (e): Draw the Logic Diagram from the simplified expression and compare the
total number of gates with the diagram of Part (b)

Note: In Part (b), there are three (03) Inverter, five (05) 3-Inputs AND, one (01)
5-Inputs OR Gates, while in Part (e), there are one (01) Inverter, three (03)
3-inputs AND, one (01) 3-Inputs OR Gates.

Problem 2.20: Express the complement of the functions in sum of minterms form:
Part (a): F ( A, B, C , D)  (3,5,9,11,15)
F ' ( A, B, C , D)  (0,1,2,4,6,7,8,10,12,13,14)

Problem 2.22: Convert each of the following expression into sum of products and
product of sums:
Part (a): ( AB  C )( B  C ' D)
 ABB  BC  ABC ' D  CC' D
 AB  BC  ABC ' D  (0) D
 BC  AB  ABC ' D
 BC  AB(1  C ' D)
 BC  AB(1)
 BC  AB Sum of Products
 B (C  A) Product of Sums

Part (b): x' x( x  y ' )( y  z ' )

 x' x[( x  y ' )( y  z ' )]
 ( x' x)[ x'( x  y ' )( y  z ' )] DeMorgan Law

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  (1)[ x'( x  y ' )( y  z ' )]
 [ x'( x  y ' )( y  z ' )] Using DeMorgan Law, we get
 ( x' x  y ' )( x' y  z ' ) Product of Sums
 x' x' x' y  x' z ' xx' xy  xz' x' y ' yy' y ' z '
 x' x' y  x' z '0  xy  xz' x' y '0  y ' z '
 x' x' y  xy  x' z ' xz' x' y ' y ' z '
 x' y ( x' x)  z ' ( x' x)  x' y ' y ' z '
 x' y (1)  z ' (1)  x' y ' y ' z '
 x' y  z ' x' y ' y ' z '
 x' y  z ' y ' z ' x' y '
 x' y  z ' (1  y ' )  x' y '
 x' y  z ' (1)  x' y '
 x' x' y ' y  z '
 x' (1  y' )  y  z '
 x' (1)  y  z '
 x' y  z '

Problem 2.28: Write Boolean Expression and construct the Truth Table describing the
output of the circuit described by the following logic diagram

y  [(a (bcd )' e)' ]'

 y  a(bcd )' e
 y  a(b'c' d ' )e DeMorgan Law

 y  ab' e  ac' e  ad ' e

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a b c d e b’ c’ d’ ab’e ac’e ad’e y
0 0 0 0 0 1 1 1 0 0 0 0
0 0 0 0 1 1 1 1 0 0 0 0
0 0 0 1 0 1 1 0 0 0 0 0
0 0 0 1 1 1 1 0 0 0 0 0
0 0 1 0 0 1 0 1 0 0 0 0
0 0 1 0 1 1 0 1 0 0 0 0
0 0 1 1 0 1 0 0 0 0 0 0
0 0 1 1 1 1 0 0 0 0 0 0
0 1 0 0 0 0 1 1 0 0 0 0
0 1 0 0 1 0 1 1 0 0 0 0
0 1 0 1 0 0 1 0 0 0 0 0
0 1 0 1 1 0 1 0 0 0 0 0
0 1 1 0 0 0 0 1 0 0 0 0
0 1 1 0 1 0 0 1 0 0 0 0
0 1 1 1 0 0 0 0 0 0 0 0
0 1 1 1 1 0 0 0 0 0 0 0
1 0 0 0 0 1 1 1 0 0 0 0
1 0 0 0 1 1 1 1 1 1 1 1
1 0 0 1 0 1 1 0 0 0 0 0
1 0 0 1 1 1 1 0 1 1 0 1
1 0 1 0 0 1 0 1 0 0 0 0
1 0 1 0 1 1 0 1 1 0 1 1
1 0 1 1 0 1 0 0 0 0 0 0
1 0 1 1 1 1 0 0 1 0 0 1
1 1 0 0 0 0 1 1 0 0 0 0
1 1 0 0 1 0 1 1 0 1 1 1
1 1 0 1 0 0 1 0 0 0 0 0
1 1 0 1 1 0 1 0 0 1 0 1
1 1 1 0 0 0 0 1 0 0 0 0
1 1 1 0 1 0 0 1 0 0 1 1
1 1 1 1 0 0 0 0 0 0 0 0
1 1 1 1 1 0 0 0 0 0 0 0

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