2.

5 PARALLEL IN- SERIAL OUT (PISO) SHIFT REGISTER

In this type of shift register, data bits are entered simultaneously in all flip-flops and output is obtained
serially from last flip-flop after applying clock pulses. The logic diagram of parallel in-serial out shift
register is shown in Fig. 2.5. Parallel input data lines A,B,C, D are connected to inputs of all four flip-flops.
MSB bit A is fed to the input of FFA flip-flop, output of FFA is ORing with B and fed to input of FFB. The
output of FFB is ORing with C and fed to the input of FFC. The output of FFC is ORing with LSB bit D and
fed to the input of last flip-flop FFD. Final output is obtained from last FFD flip-flop in serial form.
4 bit Parallel Data Input

A B C D

D QA D QB D QC D QD Serial Data Output

C C C C
FFA FFB FFC FFD

CLK
CLR
Fig 2.5: 4 bit parallel in-serial out shift register
When apply one clock pulse then input data bits are shifted into the respective flip-flops. As an example
1101 data bits put on ABCD input data lines of each flip-flop, with LSB in FFD and MSB in FFA. Initially
all flip-flops are clear (QAQBQCQD=0000) by applying active low signal on CLR line.
1st CLK: Data 1101 at parallel input data line ABCD, apply first clock pulse, then MSB bit ‘1’ shifted into
FFA. next bit ‘1’ ORed with ‘0’ shifted into FFB, next bit ‘0’ ORed with ‘0’ shifted into FFC and LSB bit ‘1’
ORed with ‘0’ shifted into FFD. After 1st clock pulse, outputs are QAQBQCQD =1101.
2nd CLK: Data ABCD=0000, ‘0’ at input of FFA , ’1’ of QA ORed with ‘0’ at FFB, ’1’ of QB ORed with ‘0’
at FFC, ’0’ of QC ORed with ‘0’ at FFD. Then after 2nd clock pulse, ‘0’ shifted into FFA, ‘1’ shifted into FFB,
‘1’ shifted into FFC and ‘0’ shifted into FFD. After 2nd clock pulse, outputs are QAQBQCQD =0110.
3rd CLK: Again ABCD=0000, ‘0’ at input of FFA , ’0’ of QA ORed with ‘0’ at FFB, ’1’ of QB ORed with
‘0’ at FFC, ’1’ of QC ORed with ‘0’ at FFD. Then after 3rd clock pulse, ‘0’ shifted into FFA, ‘0’ shifted into
FFB, ‘1’ shifted into FFC and ‘1’ shifted into FFD. After 3rd clock pulse, outputs are QAQBQCQD =0011.
4th CLK: Data bits ABCD=0000, ‘0’ at input of FFA , ’0’ of QA ORed with ‘0’ at FFB, ’0’ of QB ORed with
‘0’ at FFC, ’1’ of QC ORed with ‘0’ at FFD. Then after 4th clock pulse, ‘0’ shifted into FFA, ‘0’ shifted into
FFB, ‘0’ shifted into FFC and ‘1’ shifted into FFD. After 4th clock pulse outputs are QAQBQCQD =0001.
After 5th clock pulse all 4 bit data serially shifted out from the last flip-flop-D and outputs are
QAQBQCQD =0000, shown in Table 2.4.
Table 2.4 : Truth table of Parallel in- Serial out shift register
Parallel Input Data Serial output data
Clock pulses A B C D QD
1 1 1 0 1 1
2 0 0 0 0 0
3 0 0 0 0 1
4 0 0 0 0 1
5 0 0 0 0 0