Lecturas

EE 240B – Spring 2018
Advanced Analog Integrated Circuits

Lecture 1: Introduction
Elad Alon
Dept. of EECS
Course Focus
• Focus is on analog design methodology
• Methodology = how to translate a set of

specs in to a circuit (topology + sizing)
• Note that also need to understand where the specs
came from
• Especially in analog, some things are

much “easier” to do than others
• Concrete methodology helps to make tradeoffs
more clear
• Sometimes (often) the right thing to do is change
the specs
EE 240B Lecture 1 2
Course Goal
• Learn how to create systematic
methodologies to analog design
• Based on fundamental principles
• For a wide variety of applications
• And that can be captured within an executable
program (generator – more later)
• Will develop increasingly more complete

design methodology examples
• And will introduce additional topologies/circuits as we
realize the need for them
EE 240B Lecture 1 3
Teaching Staff
• Elad’s office hours
• 519 Cory Hall
• Office hours TBA
• GSI: Eric Chang

• Office hours TBA
EE 240B Lecture 1 4
Administrative
• Course web page:
https://inst.eecs.berkeley.edu/~ee240b/sp18/
• Lecture videos
• Volunteers for recording?
• All announcements made through piazza

• In case you weren’t already enrolled:
http://www.piazza.com/berkeley/spring2018/ee240b
EE 240B Lecture 1 5
Lecture Notes
• Compilation from offerings by multiple
faculty/instructors:
• Prof. Bernhard Boser, Prof. Ali Niknejad, Dr. Simone
Gambini, Dr. Lingkai Kong, and myself
• Primary source of material for the class

• No required text – reference texts on next slide
• Notes posted on the web
EE 240B Lecture 1 6
Reference Texts
• Analysis and Design of Integrated Circuits,
Paul R. Gray, Paul J. Hurst, Stephen H. Lewis, Robert G. Meyer,
4th Ed., Wiley, 2001.
• Design of Analog CMOS Integrated Circuits,

Behzad Razavi, McGraw-Hill, 2000.
• The Design of CMOS Radio-Frequency Integrated Circuits,

Thomas H. Lee, 2nd Ed., Cambridge University Press, 2003.
• Analog Integrated Circuit Design,

D. Johns and K.Martin, Wiley, 1997.
• The Designers Guide to SPICE & SPECTRE,

K. S. Kundert, Kluwer Academic Press, 1995.
• Operation and Modeling of the MOS Transistor,
Y. Tsividis, McGraw-Hill, 2nd Edition, 1999.
EE 240B Lecture 1 7
Grading
• HW: 10%
• One HW roughly every two weeks
• You will be “graded” purely by on-time submission
• You should “self-grade and make sure you understand
the solutions – falling behind/not doing this will doom
you to failure everywhere else.
• Project: 30%
• Groups of 2 – find a partner ahead of time
• Midterm: 25%
• Final Exam: 35%
EE 240B Lecture 1 8
Homework
• Can discuss/work together
• But write-up must be individual
• Submission via gradescope

• Further details will be announced later
• Generally due 5pm on Thursdays
• No late submissions
• Start early!
EE 240B Lecture 1 9
Schedule Notes
• ISSCC Week: 2/12 - 2/15 (no lectures)
• Midterm: March 8 (tentative)
• Spring break: 3/26 – 3/30
• Project (tentative)
• Part 1 due Apr. 10
• Part 2 due Apr. 19
• Part 3 due May 3
• Final: Wed., May 10, 8am – 11am
EE 240B Lecture 1 10
Course Material Introduction
Analog and Mixed-Signal Circuits
EE 247A EE 240A EE 240B EE 241A/B
… EE 240B EE 240C EE 251A
EE 242A …
Signal
A/D
Physical World Conditioning
Transducers DSP
Signal
D/A
Conditioning
Why Analog Circuits?
• The “real” or “physical” world is analog
• Analog is required to interface to just about anything
• Digital signals have analog characteristics too…
• In many applications, design of analog

components is in the critical path
• More later
Example: RF Transceiver
http://www.ti.com/product/CC110L
Another Example
Image from http://ihsmarkit.com

From P. Upadhyaya, ISSCC 2015
• Power is once again the key motivating

factor
EE 240B Lecture 1 Initial eye 15
Not Just Communications
[Lemkin, JSSC 4/1999]

Some Important Context
Image from moorinsightsstrategy.com
Image from chiprebel.com
What You Will Therefore Be Doing
• You will be tasked with building many
different variants of the same function/block
• You will be tasked with building many

different blocks
• You will be tasked with putting many

different blocks together to realize a (sub-)
system
• How do you do this efficiently without

(re-)introducing any known errors?
Re-Use is the Key
• Today: Integrate pre-designed blocks (IP)
• But re-use is still limited – IP is blackbox, so if ever
need to extend/modify, usually end up building your
own
• Berkeley view: Capture designer’s

knowledge (methodology) as an executable
generator
• Good methodologies will be parameterized (i.e.,
support variants)
• New features supported by incrementally extending
the code
In Other Words…
• Your goal as an analog designer should not
be to deliver a specific instance.
• Instead, you should strive to realize the best

generator that you can
• So that the generator can be executed to realize any
instance you are tasked with building
• And so that you can actually effectively re-use your
colleagues work (and they can re-use yours)
Berkeley Analog Generator (BAG)
• Hierarchical, Python-based
framework allowing
executable specification
of design procedure
• I.e., BAG takes care of the BAG
“plumbing”
Specifications Python Verified
Generator Design
• Will not require Tech. File Instance
you to use BAG External Tools
in this class J. Crossley et al., ICCAD Nov. 2013
• But forcing yourself to codify your methodology is an
outstanding way to check and develop your
understanding
BAG Example
SOI
FinFET
Bulk
Course Outline (approx.)
• Module 1: Analog design core
• “Modeling” MOS transistors
• Electronic noise and noise analysis
• GBW- and noise-limited amplifier design
• Module 2: MOS amplifier implementation

• OTA topologies and design
• Time-domain behavior (settling)
• Interference mitigation
• Common-mode feedback
Course Outline (approx.)
• Module 3: AFE system (Photonic Link) design
• Link circuit components and analysis
• Comparators
• Layout and matching effects
• Offset cancellation
• Module 4: Wrap-up
• Discrete time analog circuits
• Sampling
• Biasing and references
• Design strategies/motifs

Lecture 2: MOS Transistor Models
Elad Alon
Dept. of EECS
Square Law Model?
1 W
= ⋅ µn ⋅ Cox ⋅ ⋅ (VGS − Vth )
2
I D , sat
2 L
• Assumptions made to come up with this model:

• Charge density determined only by vertical field
• Drift velocity set only by lateral field
• Neglects diffusion currents (“magic” Vth)
• Constant mobility
• And about 102 – 103 more parameters in a real SPICE
model…
EE 240B Lecture 2 2
Graphically
180nm NMOS
Square Law
BJT
[ B. Murmann ]
EE 240B Lecture 2 3
Better Hand Models?
• There are better (less inaccurate) “hand” models
out there
• Velocity saturation
• Alpha-power law
• EKV
• …
• But all of them either (1) neglect certain effects or

(2) are too unwieldy to be useful for hand
analysis
• This is particularly true if you want to say anything about ro
(which we do typically care about in analog)
EE 240B Lecture 2 4
Taking a Step Back
• Reminder: the model you use should be tailored
to the question you are trying to answer
• “Hand” models are good for building intuition,

and to a lesser extent, checking reasonableness
of simulation results
• Simulation models are the ones you will have to

use to “sign off” on your design
• So our design methodology should be using the results from
the full simulation models too
EE 240B Lecture 2 5
Basic Small Signal Transistor Model
(for Design)
EE 240B Lecture 2 6
Biasing…
• In quadratic model, Vod = (VGS – VTH) told us a lot
about important biasing tradeoffs:
• gm = 2*ID/Vod
• ro “large” for VDS > Vod
• “Boundary between saturation and triode”
• ωT = gm/Cgg ∝ Vod
• But real transistors clearly aren’t quadratic

• And even worse, there is no way to actually measure Vod
• Idea: work with a new (measurable) transistor

FoM inspired by Vod…
EE 240B Lecture 2 7
Transistor FoM #1: V* (gm/ID)
• Define:
2ID gm 2
V* = ⇔ =
gm ID V *
e.g. V* = 200mV  gm/ID = 10 V-1
• Inspired by the fact that V* = Vod for square law

• Devices definitely not square law, but can
measure V*
• It will (by definition) set current efficiency
• And (approximately) give you insight in to other parameters
(ro, ωT, etc.)
EE 240B Lecture 2 8
Simplest Possible Usage of V*
EE 240B Lecture 2 9
Simplest Possible Usage of V*
“Best” Possible V*?
Tradeoff for Low V*
Transistor FoM #2: ωT
• Reminder: ωT defined by ||ig(ωT)|| = ||id(ωT)||
• Measureable both in simulation and in hardware
• In our simplified small-signal model, ωT = gm/Cgg
• (Cdd usually some fixed multiple relative to Cgg, so ωT is a
good FoM to capture this too.)
• Lower V* results in better current efficiency, but

lower ωT
• Best balance depends on transistor characteristics,
desired gain-bandwidth
• More on that next lecture
What About L?
• How does transistor L affect V*?
• How does transistor L affect ωT?
Transistor FoM #3: av0
• Most of the time you don’t actually care about
value of ro itself
• Just care about how it impacts circuit-level
specifications
• Most commonly, gain (AV)
• So, often use intrinsic gain av0 = gm*ro instead

• Still measurable (from I-V curves) in both simulation
and hardware
Example Usage of av0
Intrinsic Gain vs. L
Intrinsic Gain vs. VDS
Loose End #1
• Talked about transistors so far as if they all have
the same FoMs for given W, L, VGS, VDS, …
• If you have 5 billion transistors on a single chip,

do you think all of those transistors behave
exactly the same?
• If you ship 100 million chips, do you think all of

those chips will have the same specifications?
Process Corners
Loose End #2
Carusone, Johns, Martin, Analog Integrated

Circuit Design, 2nd Edition, Wiley, 2011, p. 31.
Small Signal Capacitances
Subthreshold Triode Saturation
CGS Col CGC/2 + Col 2/3 CGC + Col
CGD Col CGC/2 + Col Col
CGB CGC || CCB 0 0
CSB CjSB CjsB + CCB/2 CjsB + 2/3 CCB
CDB CjDB CjDB + CCB/2 CjDB
CGC = CoxWL
ε Si
CCB = WL
xd
“Complete” Small Signal Model
[ B. Murmann ]
To Make Matters Worse…
Image from Intel/www.legitreviews.com
“More Complete” Small Signal
Model
So What Do We Do?
So What Do We Do?
Final Note on Simplified Small
Signal Model
Lecture 3: Gain-Bandwidth Limited Amplifier
Design Methodology
Elad Alon
Dept. of EECS
Preliminaries
• This will be the first in a series of design
methodologies we will develop
• To keep the discussion manageable, will generally assume
that only a couple of specifications are critical
• And that all other specs will “automatically” be met
• In practice, can inspect specs and technology capabilities to
figure out which constraints are really active, and utilize the
appropriate methodology
• Will largely ignore biasing details for now

• But will patch this later
EE 240B Lecture 3 2
1
CS Amplifier Design Methodology
• Input specifications:
• Minimum small signal gain Av
• Minimum 3dB bandwidth bw
• Fixed capacitive load CL
• Supply voltage Vdd
• Goal: minimize power
• What are our design

variables?
EE 240B Lecture 3 3
Small Signal Model and Analysis
EE 240B Lecture 3 4
2
Power and gm
EE 240B Lecture 3 5
First Pass Methodology
EE 240B Lecture 3 6
3
Side Discussion: Digital vs. Analog
Power
Pdigital  01CLVDD2 fclk Panalog  12 CLVDDV * Avbw
• What needs to be true for analog to be lower

power than digital?
EE 240B Lecture 3 7
gm vs. GBW revisited (1)
EE 240B Lecture 3 8
4
EE 240B Lecture 3 9
5
Direct Implication
1 AV bwV *CL  0.6

ID   
2  1  AV bw T   
C = 20fF
L
0.5
C = 40fF
L
0.4
C = 80fF
L
m
0.3
G
• For a given V*, there is 0.2
a maximum GBW you 0.1
can achieve 0
• No matter how much power you 0 0.2 0.4 0.6 0.8 1
spend, cannot exceed this limit GBW/( / )
T
(with this topology)
Methodology Take 2
6
Methodology Take 2`
What about ro?
7
Bias Point
Extension #1: Differential Amplifier
8
Extension #2: Multi-Stage Amplifier
Extension #3: “Inverter” Amplifier
9
Lecture 4: Electronic Noise
Elad Alon
Dept. of EECS
Electronic Noise
• Why is noise important?
• Sets minimum signals we can deal with
• Ensuring sufficiently low noise will be another
“active constraint” that we will develop a design
methodology around
• Most often care about “signal-to-noise ratio”

• How do you make the signal larger?
• Will see today and next time how to make noise
smaller, but can you guess what it takes?
EE 240B Lecture 4 2
1
Types of “Noise”
• Interference
• Not actually “noise” – deterministic
• Signal coupling
• Capacitive, inductive, substrate, etc.
• Supply variations
• Device noise
• Caused by discreteness of charge
• “Fundamental physics” related – thermal and shot
noise
• “Technology” related – flicker noise
EE 240B Lecture 4 3
Noise in Electrical Circuits
• Noise is random
• Has to be treated statistically – can’t predict actual
value
• Deal with mean (average), variance, spectrum
EE 240B Lecture 4 4
2
Origin and Properties of Thermal
Noise
• Origin: Brownian Motion
• Thermally agitated particles
• (Everything that can generate heat has
this type of noise)
• Independent of DC current flow
• Zero mean, Gaussian PDF, i.i.d.
• Available noise power: PN  k BT f

• Noise power in bandwidth Δf delivered to a matched load
• Power spectral density is “white” up to ~THz frequencies
• kbT = 4e-21 J (T = 290K)
J.B. Johnson, “Thermal Agitation of Electricity in conductors,” Phys. Rev., July 1928
EE 240B Lecture 4 5
Resistor Noise Model
vn2
PN  k BT f 
4R
Mean square noise voltage:
vn2  4k BTRf
EE 240B Lecture 4 6
3
Resistor Noise Model (current)
EE 240B Lecture 4 7
Thermal Noise in Capacitors?
EE 240B Lecture 4 8
4
Noise Power Spectral Density (PSD)
EE 240B Lecture 4 9
Noise Calculations
• Noise calculations
• Instantaneous voltages add
• Power spectral densities add
• RMS voltages do NOT add
• Example: R1+R2 in series
5
Calculating Noise in Passive Networks
• Capacitors and inductors only shape spectrum:
,T  f    H x ( s ) s  2jf v x  f 
2 2 2
von
x
Side Note on Shot Noise (Diodes)

• Shot noise
• Zero mean, Gaussian pdf, white
• Proportional to current
in2  2qI D f
• Independent of temperature
• Example:
ID = 1mA  17.9pA/rt-Hz
1MHz bandwidth  σ = 17.9nA
• Shot noise versus thermal noise

• gdiode = Id/(kbT/q)
• Thermal noise density: 4kbTgdiode = 4qId
• Shot noise half of this (current flow in 1 direction)
6
Simplified FET Noise Model
Simplified FET Noise Model
7
Word of Caution
Flicker Noise
8
1/f Noise Modeling
• Flicker noise
• Kf,NMOS = 6 x 10-29 A*F
Kf,PMOS = 3 x 10-29 A*F
• Strongly process dependent
• Example: ID = 10A, L = 1m,

• Cox = 15fF/m2, fhi = 1MHz
flo = 1Hz  σ = 0.74nA
flo = 1/year  σ = 1.11nA
Modified FET Noise PSD
9
1/f Noise Corner Frequency
• Definition (MOS)
K f I D f K f ID 1
 4k BTr  g m f f co 
L2Cox f co L2Cox 4k BTr  g m
Kf 1 1

4k BTr  Cox L2 gm I D
Kf V*

8k BTr  Cox L2
• Example:
• V* = 100mV,  = 1.16
NMOS PMOS
L = 100nm  2MHz 233kHz
L = 300nm  222kHz 25.9kHz
Noise PSD Calculation in an

Amplifier
10
Lecture 5: Noise and SNR Analysis
Elad Alon
Dept. of EECS
General Noise Analysis

• Method:
1) Create small-signal model
2) All inputs = 0 (linear superposition)
3) Pick output vo or io
4) For each noise source vx, ix
Calculate Hx(s) = vo(s) / vx(s) (… io, ix)
5) Total noise at output is:
,T  f    H x ( s) s2jf vx  f 
2 2 2
von
x

,T   von ,T  f df
2 2
von
0
• Tedious but simple …
EE 240B Lecture 5 2
1
Important Integrals
2

1 
0 1  s df  4o
o
2 2
s
 
1 o oQ
 s s 2
df  
s s 2
df 
4
0
1  0
1 
o Q o2 o Q o2
2
s
 1
z oQ  o 2 
 s s 2
df    1
4  z 2 
0
1  2
oQ o
EE 240B Lecture 5 3
Noise in a Real Circuit: RC
2
• Noise on the capacitor: 1
2
von  f   4kBTR
1  sRC
1 k T
 voT
2
 4k BTR  B
4 RC C
• Note that effective bandwidth is:

1 ω 
f   o  fo
4 RC 4 2
EE 240B Lecture 5 4
2
Noise PSD
EE 240B Lecture 5 5
Equipartition Theorem
EE 240B Lecture 5 6
3
CS Amplifier Noise
2
 1  RL
2
von  f   4 k BT    g m 
 L
R  1  sRL CL
2
 1   1
2
voT  4 k BT    g m  RL2  df
 L
R  0 1  sR LCL
 1  1
 4 k BT    g m  RL2
 L
R  4 R LCL
k BT
 1   g m RL 
CL

k BT
CL
1   Avo 
k BT
 nF
CL
EE 240B Lecture 5 7
Optional: Two-Stage Amplifier
EE 240B Lecture 5 8
4
Signal-To-Noise Ratio
• SNR: Psig
SNR 
Pnoise
• Signal Power (sinusoidal source):

Psig  12 Vzero
2
 peak
• Noise Power (assuming thermal noise dominates):

k BT
Pnoise  nf
C
• So:
1 2
CVzero SNR  6dB
2  peak
SNR 
n f k BT
C  4
EE 240B Lecture 5 9
SNR versus Bits

• Quantization “noise”
N dB
• Quantizer step size: 
8 50
2
• Box-car pdf variance: SQ  16 98
12
24 146
• SNR of N-Bit sinusoidal signal

2
11 
• Signal power Psig   2 Nbits  
22 
Psig
• SNR SNR   1.5  22 Nbits
SQ
• 6.02 dB per Bit  1.76  6.02 N bits  dB
5
SNR versus CL
• For a 1V sinusoidal signal at 100oC:
Bits SNR [dB] C

3.0 20 4.1 aF
6.3 40 412 aF
9.7 60 41 fF
13.0 80 4.1 pF
16.3 100 412 pF
19.6 120 41 nF
23.0 140 4.1 F
SNR versus Power

• 1 Bit  6dB  4x SNR
• 4x SNR  4x C
• Circuit bandwidth ~gm/C  4x gm
• Keeping V* constant  4x ID, 4x W
• Thermal noise limited circuit:

• Each bit QUADRUPLES power!
• Comparison vs. digital circuits…
6
Input and Output Referred Noise
Output Input
· , ·
,
, , ,
Noise Example
R2
vn
R1
Vi
inf Vo
• Ignoring noise from R1, R2:

R2  R  R R  R2
vo  vi  vn 1  2   vi 2  vn 1
R1
  R1  R
1
R1
 Av 0  Av 0
2 2 2
 R  R2 R1  2  R1  R2 
 1 
2
vieq  vn2  1   vn    vn 1 
2

 R1 R2   R2   Av 0 
• “Ideal” feedback, why is vi,eq2 > vn2?

7
Source Impedance
8
Lecture 6: Noise- and SNR-Limited Amplifier
Design Methodology
Elad Alon
Dept. of EECS
Noise Density Limited Amplifier

Design Methodology
RL • Minimum small signal gain Av
Vout • Fixed V*
Vin + • Maximum input-referred noise
- spectral density vi,n2/f
EE 240B Lecture 6 2
1
Small Signal Model and Noise
Analysis
RL
Vout
Vin +
-
EE 240B Lecture 6 3
Resulting Design
EE 240B Lecture 6 4
2
Discussion (1)
• Why did we not even specify the capacitive load?
EE 240B Lecture 6 5
Discussion (2)
• If you could exactly set av0, what value would you
pick?
EE 240B Lecture 6 6
3
Integrated Noise-Limited Amplifier
• Fixed V*
• Maximum noise variance vo,n2
EE 240B Lecture 6 7
Required CL, gm, and ID
EE 240B Lecture 6 8
4
Discussion (1)
• For both noise-density and integrated noise-
limited amplifiers, what V* should you pick?
EE 240B Lecture 6 9
Discussion (2)
• How would one know the vi,n2/f or vo,n2 spec?
5
Signal Swing Limitations
RL
Vout
Vin +
-
Why Linearity Matters

• Option 1: Retaining the original shape of the input
inherently matters
• E.g., oscilloscope, spectrum analyzer
• (Actually also often matters in communication systems)
• Option 2: Need to be able to discern a (small)
signal out of the combination of many others
• E.g., RF, neural front-ends
• “Other” signals could
• Precise linearity metric depends on usage
scenario
• More next time – will use simplified metric for now
6
Sources of Non-Linearity
• Output limited: • Input limited:
Non-linear Zout (ro) Non-linear gm
Input Non-Linearity with a Diff. Pair
Vi+ Vi-
7
Full Circle: SNR-Limited Design
(noise density)
RL • Minimum small signal gain Av
Vout • Input-referred maximum linear
amplitude Vi,max
Vin +
- • Signal shape (usually sinusoid)
and amplitude Vsig
• Externally determined
bandwidth fbw
• Minimum signal-to-noise ratio
SNRmin

Required vi,n/f
8
Required V*
SNR-Limited Design (total noise)

• Input-referred maximum linear
amplitude Vi,max
• Signal shape (usually sinusoid)
and amplitude Vsig
• Minimum signal-to-noise ratio
SNRmin
9
Discussion
10
Lecture 7: Operational Transconductance
Amplifiers (I)
Elad Alon
Dept. of EECS
OpAmps and OTAs

OpAmp OTA
+ +
- -
+ +
+ AVVi V
-Vi - - i GMVi
• High voltage gain, high • High “voltage” gain,

input impedance high input impedance
• Voltage source output • Current source output
(low impedance) (high impedance)
EE 240B Lecture 7 2
1
Opamp & OTA in CMOS
EE 240B Lecture 7 3
Opamp vs. OTA Noise

OpAmp OTA
4 k BT 1 k T Rn k BT
vo ,n 2   B vo ,n 2 
g m 4 Rs CL CL Rs CL
EE 240B Lecture 7 4
2
Simplest Single-Ended OTA
EE 240B Lecture 7 5
Differential Input?
Vout
Vin
• Why use a differential input?

• Diff. version has extra device(s) – more power, noise, etc.
• Real reason is systematic offset
• All voltages are relative
• If used a differential input, often might as well use
differential output too…
EE 240B Lecture 7 6
3
Simple Diff. Input OTA
Vbp
Vi+ Vi-
EE 240B Lecture 7 7
Simple Diff. Input OTA: Noise (1)
Vbp
Vi+ Vi-
EE 240B Lecture 7 8
4
Vbp
Vi+ Vi-
EE 240B Lecture 7 9
5
More Careful Look at Noise…
More Careful Look at Noise…
6
Real R vs. Current Source (1)
Real R vs. Current Source (2)
7
Limitations of Simple OTA
Vbp
Vi+ Vi-
Telescopic Cascoded OTA
Vbp1
Vbp2
Vo- Vo+
Vbn
Vi+ Vi-
8
Why Cascoding Helps
Cascode Sizing for ro
9
Cascode Noise?
Cascode Noise?
10
More Complete Analysis
More Complete Analysis
11
Cascode Sizing
12
Lecture 8: Operational Transconductance
Amplifiers (II)
Elad Alon
Dept. of EECS
Closer Look at Cascode Dynamics
EE 240B Lecture 8 2
1
Aside: Useful TF Properties
EE 240B Lecture 8 3
Cascode Zout vs. f
EE 240B Lecture 8 4
2
Pole-Zero Doublets
EE 240B Lecture 8 5
Discussion
• Doublet generally not important in “simple”
cascode since it shows up at high frequencies
• But, doublets can show up in similar circuits

• In particular, when you try and increase the gain
beyond what a simple cascode can support
EE 240B Lecture 8 6
3
Gain Boosting
• Use feedback to further
increase Rout
• No increase of Vmin
(unlike double cascode)
• References:
• B. J. Hosticka, “Improvement of
the gain of MOS amplifiers,”
JSSC, Dec. 1979 , pp. 1111-4.
• E. Sackinger and W.
Guggenbuhl, “A high-swing high-
impedance MOS cascode circuit”,
JSSC, Feb. 1990, pp. 289-298.
• K. Bult, G. Geelen, “A fast-settling
CMOS op-amp for SC circuits
with 90-dB DC gain,” JSSC, Dec.
1990 , pp. 1379-84.
EE 240B Lecture 8 7
Stability?
EE 240B Lecture 8 8
4
Gain-Boosted Zout
EE 240B Lecture 8 9
If it works, do it again!
• Since in advanced scaled CMOS gmro is small, we can use

nested gain boosting for higher output impedance.
• Watch out for pole-zero doublets!
5
Telescopic OTA: Common Mode vs.
Swing
Vbp
Vi+ Vi-
Folded-Cascode Schematic
Vbp1
Iss
Vbp2
Vi+ Vi-
Vbn2
Vbn1
6
Folded-Cascode Noise
M5
Vbp1
Iss
Vbp2
Vi+ M1 Vi-
Vbn2
Vbn1 M3
Low Frequency Gain: av and Av
7
Output Resistance
Beware of ro imbalance between NMOS and PMOS

current sources
Simulation Schematic
Many more transistors, but overall characteristics very similar to common-source stage.
8
Input Cascode
Iss Vbp1
Vbp2
Vi+ Vi-
Vbp3
Vbn2
Vbn1
Reminder: Cascode Zin
9
Biasing and Parasitic Feedback
Vbp1
Vbp2
Vi+ Vi- V
bn2
Vbn1
Many more transistors, but overall characteristics very similar to common-source stage.
10
Lecture 9: Feedback
Elad Alon
Dept. of EECS
Feedback
• Assume you are familiar with feedback
benefits, issues
• Review: G&M Ch. 8 & 9, Razavi Ch. 8
• Focus today on stability analysis and

simulation
EE 240B Lecture 9 2
1
Generic Feedback System
Vi + Verr Vo
+ av +
-
• Open-loop gain: av
• Feedback factor: f
• Loop gain: T = av f
• Closed-loop gain: A  Vo  av  1 1  1
Vi 1
1+ T f 1 T f
EE 240B Lecture 9 3
Feedback + Feedforward
Vi + Verr Vo
+ av +
-
EE 240B Lecture 9 4
2
Is This Circuit “Stable”?
Vbp
Vout
Vin
EE 240B Lecture 9 5
Stability
• Nearly all circuits are actually
non-linear and time-varying Vbp
• “Poles” only accurate for
given bias, temp., etc. Vout
Vin
• What we usually mean by stability:

• Circuit always converges to the “origin” for zero
input within finite time
• (Exponential stability)
• Another common definition: BIBO stability
EE 240B Lecture 9 6
3
Stability In Practice
Vbp
Vout
Vin
• Linearize the circuit and look at its poles
• Remember: this is only an approximation!

• Perform linear analysis over several corners, temps,
supplies, etc.
• Likely need to do a couple of transient sims too
EE 240B Lecture 9 7
Linear Stability: Phase Margin

• Approximate
method to
evaluate stability
• Works well for

most circuits of
interest
• Sometimes have
to use Nyquist
stability test
EE 240B Lecture 9 8
4
Simulating Stability (1)
Cf
Vout
Cs CL
Vin
• Stability set by T(s)
• T(s) is an open-loop parameter - need to break

the loop
• Easy to do in hand analysis: break at controlled
source
• Not as easy in simulation…
EE 240B Lecture 9 9
Simulating Stability (2)
Cf
Vout
Cs CL
Vin
5
Common Approach
General Setup
• Any single loop feedback circuit can be represented
as:
Z1Z 2
T (s)  g m 
Z1  Z 2
• Can‘t break the loop at the gm, but can break it

between Z1 and Z2
freq, Hertz
6
Middlebrook Method (1975)
vtest
vy Z2
Z1 vx (ac)
Z2 vy
 Tv  g m  Z 2  Solving
gm vx Z1
yields:
True Loop T  g m  Z1Z 2 TvTi  1
ix iy Z1  Z 2 T 
Gain: Tv  Ti  2
Z1 iy Z1
gm Z2  Ti  g m  Z1 
ix Z2
itest
(ac)
• Measure Tv and Ti, then calculate actual T

• Implemented in many simulators (e.g., stb)
freq, Hertz
Multi-Loop Feedback
7
Lecture 10: Settling-Limited Amplifier Design
Methodology
Elad Alon
Dept. of EECS
Why “Settling”?
• Really (time-domain) waveform fidelity that is
of interest
• Often important not just in oscilloscopes
• Step-response used as a means to

characterize this
• Sometimes actually dealing with “inputs” that
actually look like steps (e.g., switched-capacitor
circuits – more later)
1
Step Response: Error Breakdown
Simple Settling Limited Amplifier

Design Methodology
gm • Minimum small signal gain Av
CL • Maximum relative dynamic
settling error dyn
2
Dynamic Settling Error: Single Pole
System
Dynamic Settling Error

⁄
1% 4.6
0.1% 6.9
0.01% 9.2
10-6 13.8
3
Methodology Implication
Settling Limited Amplifier Design

Methodology (w/Feedback)
Vin +
gm • Known “feedback factor” F
‐ • Maximum relative static settling
CL
error stat
• Maximum relative dynamic
F settling error dyn
4
Step Response
Static Error
5
Side Note
Dynamic Error
6
Simple Settling Limited Amplifier
Design Methodology
gm • Minimum small signal gain Av
CL • Total settling error dyn + stat

• How to allocate between static and dynamic
errors?
Patching Some Things Up

• Basic methodology doesn’t really change
• Just that dynamic settling in particular will be
affected by things like zeros and additional poles in
the OTA
• Look at these effects next

• Good news: (linear) dynamic settling still basically
set by OTA gm – just get some extra scale factors
• (Slewing is a little different – will look at that too)
7
Feedforward Zero
Feedforward Example
8
Second-Order OTA (Cascode)
Vin + • Model with:

Gm(s) gm
‐ Gm  s  
CL 1  s  p2
 p 2  K u
F
u is unity gain bandwidth of T  s 
Step Response
9
Dynamic Error
Settling Time
 dyn  103
• Optimum at K=3.3
10
Optimal K
• Optimum K depends on required accuracy
• But always want to avoid K<~2

Side Note: Pole-Zero Doublets
11
Feedback and Slewing
• Use of feedback allows you to decouple V* from
overall “amplifier” linearity
• Often intentionally want low V* for the gm (for current
efficiency)
• When first apply an input step, actual input to OTA

may exceed V*
• This is the source of slewing
Slewing Model
12
Settling Time with Slewing
Putting It All Together
13
Methodology
14
Lecture 11: Multistage OTA Design
Elad Alon
Dept. of EECS
Single vs. Multi-Stage
1
Stability for Simple 2-Stage Amp
Vout
C1 C2
Vin M1 M2
p1 = p2 =
• Two (closely spaced) poles - is this circuit stable?
Compensation Techniques
• Many options – best one depends on
situation at hand
• Look at a few general categories:

• Narrowbanding
• Miller
• Advanced Miller
2
Narrowbanding
• Narrowbanding
• Lower one of the poles
• Or introduce a new one
• Stability OK, but (feedback)

GBW limited by second pole
Miller Compensation
Cc
Vout
C1 CL
Vin M1 M2
3
Pole Splitting
Miller Compensated Poles
4
Not Quite That Simple…
Cc
Vout
C1 CL
Vin M1 M2
Why Right-Half Plane Zero?
Cc
Vout
C1 CL
Vin M1 M2
5
Effect on Stability
Nulling Resistor
Rz Cc
Vout
C1 CL
Vin M1 M2
1 gm2 • Rz limits feedforward current

z at high frequency
1  g m 2 RZ  Cc • Pushes feedforward zero to
p1 , p2 : no change higher frequency
1 • Adds new pole p3
p3  
Rz C1
6
Choice of Rz
Cascode Compensation (Ahuja)
• No RHP zero
• But cost in power can be high
• (I2 needs to slew Cc)
7
Cascode Compensation (Ribner)
Noise Analysis
• Need a simplified model:
8
Noise Analysis cont’d
1 1  sC 
vo   in1  in 2 c 
2
Fg m1 s s  gm2 
1 
oQ o2
with
Fg m1 g m 2
o2 
Cc Cc  CL 
Fg m1
oQ 
Cc
Total Noise at Output
k BT  k BT
2
voT   
Cc F  Cc  CL 
k BT   FCc 
2
voT  1  
Cc F  Cc  CL 
• Noise from first stage dominates

• Noise capacitor: Cc (NOT CL!)
9
Design Methodology
• Integrated noise limited:
• gm2 = K*u*CL, K chosen by settling or stability
• Cc = ~kT/(F*vo2)
• gm1 = Cc*u/F
• GBW-limited:
• gm2 = K*u*CL, K chosen by settling or stability
• Make gm1 and Cc as small as possible (while making sure
Av2*Cc > C1)
Design Methodology
• “Noise density” limited:
• gm2 = K*u*CL, K chosen by stability
• Find gm1 based on noise density/SNR constraint
• Size Cc based on u
• (May need to iterate/upsize gm1 to include effect of gm2
noise at edge of band)
10
Lecture 12: Interference
Elad Alon
Dept. of EECS
Course Material Outline

• Except for a couple of items we’ll look at later,
now basically done with “core” amplifier
functionality
• In many cases though, amplifier design driven

not just by core functionality, but by robustness
to external interference
• Cover some of the sources of interference and how to
mitigate them today/next lecture
1
Interference
Typical Interferers
• Power supplies
• Clocks
• Digital signals
• Electrical interferers can couple in to your circuit:

• Directly by capacitive coupling (most common on IC)
• Directly by inductive coupling (more common on PCB)
• Indirectly due to finite supply impedance (common
everywhere)
2
Fully Differential Circuits
Vi+ ‐ + Vo+
Vi‐ + ‐ Vo‐
• Fully differential circuits:

• Vid = Vi+-Vi- Vic = (Vi++Vi-)/2
• Try to make all interfering signals affect only

common mode
• And “reject” common mode as much as possible
Example
Single Ended Differential
interference interference
signal+
signal
signal-
3
Fully Differential Amplifier Gains
vod
Adm  
Input Output vid
voc
Acm  0
Adm vic
Vid Vod vod
Adcm Acdm  0
vic
vod
Acdm AVDD  0
Vic Voc vDD
Acm vod
AVSS  0
vSS
CMRR, PSRR, …
Adm Adm
CMRRdirect   PSRRVDD  
Acm AVDD
Adm Adm
CMRRcross   PSRRVSS  
Acdm AVSS
4
PSRR Example
Differential Input Stage Options
5
Differential Input Stage Options
Vi+ Vi-
Side Note
Vi+ Vi- Vi+ Vi-
6
Design Methodology Implications
• Can “add” a CMRRdirect spec to any of our
methodologies
• Since Iss is fixed by gm, only degrees of freedom are
Vtail* and Ltail
• How would you pick Vtail* and Ltail?
Design Methodology Implications

• In practice, need to specify CMRRdirect(f)
requirement
• Could be pairs of f and CMRR, worst-case across
range of f, etc.
• High-f CMRR may limit allowable Vtail* and Ltail

• Sometimes cascode tail for this reason, although can
still be hard to maintain high-f CMRR
• Is there anything else we can do?
7
Lecture 13: Common-Mode Feedback
Elad Alon
Dept. of EECS
Review: CMRR Limit
IL IL
Vi+ Vi-
Itail
1
A Related Problem
• What if IL < Itail/2?

• Does (typical) feedback IL IL
solve this?
Vi+ Vi-
Itail
Solution: Common-Mode Feedback
IL IL
Vi+ Vi-
Itail
2
Adjusting Common-Mode
• Really only two knobs:
• Knob A: adjust load

current
• Knob B: adjust tail current
Knob A vs. Knob B
3
Common-Mode Sensing
• Simplest CM sensor: pair

of resistors IL VCM IL
• How to pick value of R? R R

Vi+ Vi-
Itail
Isolated Sensing
IL IL
Vi+ Vi- Vsense
Itail
• Works well as long as stay in the linear range

of the “diff. pair”
• Otherwise Vsense tracks just one side
4
Capacitive Sensing
IL VCM IL
C C
Vi+ Vi-
Itail
• Avoids DC loading
• But can’t fix DC (biasing) concerns
• And does add extra capacitive loading
Common Implementation
5
Methodology Implications
(Noise-Limited)
Methodology Implications
(GBW-Limited)
6
GBW-Limited CMFB
7
Lecture 14: Photonic Link Overview
Elad Alon
Dept. of EECS
Why Photonic Links?
Basic Link Issues
• Signaling: getting bits from the TX to the RX
Decision
Channel
DTX Ser. E to O O to E Deser. DRX
(Fiber)
• Timing: determining which bit is which
TX: E to O (1)
TX: E to O (2)
RX: O to E
RX: O to E Model
Photonic RX: Attempt #1
Photonic RX: Attempt #2
Noise à BER
clk
• RX circuits always have noise

• If noise is ever larger than the input signal (at
sampling point), RX will decode the bit incorrectly
• BER = Bit Error Rate
• I.e., average # of incorrectly received bits / total
transmitted bits
Min. Signal Amplitude
clk
• Min. signal set by noise σ and residual offset:

æ Vin,ampl - Voff ö
BER = erfc ç
1
÷÷
2 ç 2s noise
è ø
• BER = 10-12: (Vin,ampl – Voff) = 7σn
• BER = 10-20: (Vin,ampl – Voff) = 9.25σn
So What?
• Why not just hit the RX with a larger signal?
• (Not a stupid question – this is often what people do)
• Simple (hand wavy) answers:

• Generating optical power can be (very) expensive
• Wall-plug efficiency usually ~1-10%
• Larger swing doesn’t help with ISI…
Intersymbol Interference (ISI)
ISI continued
Receiver Design Revisited
TIA-Based Front-End
TIA-Based Receiver
Front-end Bandwidth
Performance Limits
Overcoming PD Bandwidth Limit:
Multi-Level Signaling
2PAM: 4PAM:
00
0 0
01
11
1 1
10
1bit/symbol 2 bits/symbol
4PAM RX
Lecture 15: Transimpedance Amplifier Design
Elad Alon
Dept. of EECS
Review: Resistor “TIA”
1
Opamp-Based TIA
Common-Gate TIA
2
Common-Gate TIA Noise (1)
Common-Gate TIA Noise (2)
3
Common-Gate TIA SNR
Limitations of Common-Gate TIA

• Input capacitance of the CG device limits
achievable bandwidth:
• Achievable RL (TIA “gain”) limited by voltage

headroom and av0
• Increasing L often unattractive because of above
consideration
4
Regulated Cascode (RGC) TIA
RGC Phase Margin
5
RGC Limitations
• Make sure the entire “stack” can fit in the
supply
• Gain boost stage usually the hardest to fit in
• Watch out for linearity of CG device

• Intentionally amplifying its VGS
Opamp TIA Revisited
6
OTA TIA Design (1)
OTA TIA Design (2)
7
OTA TIA Noise (1)
OTA TIA Noise (2)
8
OTA TIA Noise (3)
OTA TIA SNR
9
Inverter-Based TIA
10
Lecture 16: Comparators I
Elad Alon
Dept. of EECS
Comparator
• Specs and issues:
• Clock rate fs • Power dissipation

• Offset • CM rejection
• Resolution • Kickback noise
• Hysteresis • …
• Input cap
1
Comparator Gain-Bandwidth
Example:
• 10Gb/s link
• Minimum ΔV: 1mV
• Vdd = 1V
 Av > 1V / 1mV = 1000 in < 100ps!
Operational Amplifier?
fu 2 1
f 3dB  
Avo 3 Tbit
2 Avo
fu 
3Tbit
2 1000
  6.67THz
3 100ps
2
Open-Loop Amplifier Cascade
Cascaded Amplifier
• Simplified bandwidth analysis:
• Open-circuit time constants
• (Not most accurate, but leads to nearly the right
answer for design optimization)
3
Bandwidth/Gain Optimization
Bandwidth/Gain Optimization
4
Power Consumption
Regenerative Latch
5
CML Comparator (Latch)
CML Comparator Analysis (1)
6
CML Comparator Analysis (2)
CML Comparator Design
7
Lecture 17: Comparators II
Elad Alon
Dept. of EECS
CML Comparator Power Revisited

• Gain spec driven by smallest signal you need to
resolve
• But real inputs will often be larger than this
• For larger inputs, diff. output will clip at +/- Ibias*RL

• I.e., dissipating Ibias just to produce a constant voltage
• Can we modify the comparator to spend power only when
it is actually providing (regenerative) gain?
1
CMOS Comparator
StrongArm Comparator (Latch)
2
StrongArm Analysis (1)
3
Hysteresis
4
Kickback
Kickback cont’d
5
Kickback cont’d
Overdrive Recovery
6
Lecture 18: Matching I
Elad Alon
Dept. of EECS
Offset
Vi+ Vi-
• To achieve zero offset, comparator devices

must be perfectly matched to each other
• How well-matched can the devices be made?

• Not arbitrary – direct function of design choices
1
Device Mismatch Categories
• Die-to-die
• All devices on same chip (or wafer) have same
characteristics
• Within die (long-range)

• All devices within certain region have same
characteristics
• Local (short-range)
• Every device different, random
• Usually most important source of mismatch
Sources of Local Variation

• Deterministic sources:
• Local poly density, stress, litho interactions, …
• Random sources:
• Dopant fluctuations
• Line-edge roughness
• Oxide traps
• Focus our modeling on random variations

• Deterministic handled with good layout practices
2
Local Mismatch Statistics
• Total mismatch set by composite of many single,
independent events
• Correlation distance << device dimensions
• E.g., number of dopant atoms implanted into the channel
• Individual effects are small: linear superposition

holds
•  Mismatch is zero mean, Gaussian distribution
Mismatch Basics
Ref: M. Pelgrom, “Matching Properties of MOS Transistors,” JSCC, Oct. 1989

3
Parameter Mismatch Model
AP2
 2  P    S P2 Dx2
AD
 2  P  : variance of P
AD : active device area
Dx : distance between device centers
AP : measured area proportionality constant
SP : measured distance proportionality constant,
:  0 for "good" layout
Example Parameters (180nm)
Parameter Value
AVt (MOS) 5 mV-m
A (MOS) 1 %-m
AC/C (MIM capacitor) 1 %-m
AR/R (Poly resistor) 3 %-m
4
AVt Data for 180nm
Ref: M. Pelgrom et al, “A designer’s view on

mismatch,” Chapter 13 in Nyquist A/D
Converters, Sensors, and Robustness,
Springer 2012, pp. 245-67.
• Good match between model and data, except:

• Minimum channel length (actual L smaller than drawn)
• Very narrow device
Edge Roughness
5
Edge Roughness Model
Example: Mismatch
 2    2 W   2 L   2 Cox   2 n 
   
2 W2 L2 Cox2 n2
For:  2 W   1 L and  2 L   1W
Simplifies to:
 2    AL2 AW2 AC2 A2

   
ox
2 WL2 W 2 L WL WL
6
Process Dependence
• AVt drops by
~1mV*m for every
1nm drop in gate
insulator thickness
(“tox”)
• Watch out for edge
effects in small
devices
Ref: M. Pelgrom et al, “A designer’s view on
mismatch,” Chapter 13 in Nyquist A/D • Fully-depleted
Converters, Sensors, and Robustness,
Springer 2012, pp. 245-67. channels (FinFET,
FDSOI) get 1.5-2X
benefit over bulk
Avoiding Systematic Issues:

Orientation Effects
• Si and transistors are not

(perfectly) isotropic
•  keep direction of
current flow same!
7
“Golden Rule” of Layout for Matching
• Everything you can think of might matter
• Even whether or not there is metal above the
devices
• How to avoid systematic errors?
Ref: A. Hastings, “The art of analog layout,” Prentice Hall, 2001
Common Centroid Layout

• Cancels linear gradients
• Required for “large” structures (arrays)
8
Lecture 19: Matching II
Elad Alon
Dept. of EECS
Computing Mismatch Variance

• Same basic approach as noise computations
• Assume each mismatch source is “small” and adds to
the others linearly
• So can use superposition to find effect of each source
and then add them all up
1
Current Matching
Voltage Matching
2
Yield
• Just like noise, can only put a statistical bound on
mismatch
• So define “yield” as fraction of parts with target
parameter being less than some specification
Interval Yield Fraction Bad
2 95.4% 1/22
3 99.7% 1/370
4 99.99% 1/16,000
5 99.999% 1/1,700,000
6 99.999 999 8% 1/507,000,000
• Given target parameter and yield:

• N,yieldP = Ptarg
Note About Yield
3
Mismatch-Limited Design
Methodology
RL RL • Minimum 3dB bandwidth bw
• Fixed capacitive load CL
Vi+ Vi-
• Maximum input-referred offset
Voff at required yield level cyield
Methodology
4
Methodology
Important Things To Note
5
How to Simulate Mismatch
• Brute force: Monte Carlo
• HSPICE “throws the dice”…
How I Handle Mismatch
6
Note About Extracting Mismatch
Parameters from Simulation
7
Lecture 20: Passive Devices and Layout
Elad Alon
Dept. of EECS
Passives: Resistors
1
Resistors
• Resistance is bad for digital circuits
• But, often want large-valued, well-controlled R for
analog
• E.g., a 1kOhm resistor made out of copper
interconnect (~200m/ would require 5000 ’s
• Fortunately, most processes include explicit

provisions for large resistors
• Up to ~20nm, typically unsilicided poly or n-well
• Typically get ~1k/
• Even with explicit resistors, still need to watch out
for a few things however
Resistor Variations
• Almost always temperature dependent:
• Also often voltage dependent:
2
Systematic Variations from Layout
• Example:
2R?
• Use unit element instead:

2R
R
Better Unit Element
3
Resistor Layout (cont.)
Serpentine layout for large values:
Better layout (mitigates offset due to thermoelectric effects):
See Hastings, “The art of analog layout,” Prentice Hall, 2001.
Electromigration and Parasitics

• Electromigration rules limit maximum
current density
• Same value resistance must be physically larger
to carry more current
• Hence, more current  larger capacitive parasitcs
4
Passives: Capacitors
Capacitors
• Simplest capacitor:
substrate
• What’s the problem with this?
5
Capacitors
• “Improved” capacitor:
substrate
• Is this only 1 capacitor?
Capacitor Options
Type C [aF/m2] VC [ppm/V] TC
[ppm/oC]
Gate 10,000 Huge Big
Poly-poly 1000 10 25
(option)
Metal-metal 50 20 30
Metal-substrate 30
Metal-poly 50
Poly-substrate 120
Junction caps ~ 1000 Big Big

6
MOS Capacitor
• High non-linearity,
temperature coefficient
• But, still useful in many

applications, e.g.:
• (Miller) compensation
capacitor
• Bypass capacitor
(supply, bias)
“MOM” Capacitors
• Metal-Oxide-Metal capacitor. Free and most

common in modern CMOS.
• Use lateral flux (~Lmin) and multiple metal layers
to realize high capacitance values
7
MOM Capacitor Cross Section
• Use a wall of metal and

vias to realize high
density
• More layers – higher

density
• May want to chop off lower
layers to reduce Cbot
• Reasonably good
matching and accuracy
Another MOM Option
8
Capacitor Parasitics
Passives: Inductors
9
What About Inductors?
• Mostly not used in analog/mixed-signal design

• Usually too big
• More of a pain to model than R’s and C’s
• But they do occasionally get used
• Example inductor app.: shunt peaking
• Can boost bandwidth by up to 85%!
• Q not that important (L in series with R)
• But frequency response may not be flat
Spiral Inductors
• Used widely in RF circuits for small L (~1-10nH).

• Use top metal for Q and high self resonance
frequencies.
• Very good matching and accuracy – if you model them
right
10
Lecture 21: Offset Cancellation
Elad Alon
Dept. of EECS
Offset Cancellation Overview

• Two main ideas/approaches
• Modulate and/or filter offset so that it is outside

of signal band
• Correlated Double Sampling (auto-zero)
• Chopping (synch. detection, DEM)
• Inject a “DC” signal that opposes the offset

• AC-coupling or Feedback-based
• Trimming - often digitally controlled (especially for
comparators)
1
Filtering/Modulating Offset
• General idea:
• Put elements around the amplifier that treat offset
differently than signal
• CDS:
• Configure amplifier so that offset is (approx.) differentiated
• We’ll talk more about this one after we introduce discrete
time circuits
• Chopping:
• Modulate offset to frequencies beyond signal band, then
filter it out
Chopping (1)
2
Chopping (2)
Nested Chopper Amplifier
• Inner chopper at high freq. to remove 1/f noise

• Outer chopper at low frequency to minimize
“spiking” and remove residual offset from inner
chopper.
3
AC Coupling for Offset Cancellation
AC Coupled Sizing Methodology
4
Auxiliary Amplifier Offset Cancellation
Aux. Amplifier Implementation
5
Offset Trimming
Digital Trimming
6
Comparator Trimming
Trim Implementation Issues

• Infinite number of ways to introduce digitally
controlled offset
• People have tried just about all of them
• Key issues:
• Power overhead
• Circuit Imbalance
• Effective resolution
• Area overhead
7
Comparator Trim Schemes
Pre-Amp Trim
8
Pre-Amp Trim
AC-Coupled Again
9
Lecture 22: Biasing and References
Elad Alon
Dept. of EECS
Biasing: Current Mirror
1
Biasing: Cascode
Reference Circuits
• Where did those constant currents come from?
• May need to generate those internally – usually known as
a “reference”
• Tons of “constant X” reference circuits in the

literature
• Important considerations include power, accuracy, PSRR,
output impedance, etc.
• Most important question: what do you really

want to be constant?
2
Constant Current Bias?
Constant Gain Example
3
Supply “Independent” Biasing
Improved VGS Reference
4
PTAT Reference
CMOS PTAT Reference
Vertical PNP
p- substrate p+ diffusion
n- well n+ diffusion
C E B
5
Startup Circuit
Conceptual Band-Gap
• VBE has a tempco of roughly -2 mV/°C

• Add VBE to PTAT voltage (with right M)  Vbg
independent of T
• Reference derived from band-gap of Si (1.205V)
6
Constant gm Reference
7
Lecture 22: Discrete Time Circuits
Elad Alon
Dept. of EECS
Discrete Time Systems

• Focused on everything in continuous time so far
• But most communication systems (like our link) are of
course discrete time
• And even sensor systems usually end up going through
some sampling process at the end (usually for data-
conversion)
• Can we make use of the fact that signals are

discrete-time to improve our circuits?
• Or at least get around some of the issues we’ve
encountered before?
1
Ex 1: Offset Cancellation
• Don’t want to store offset on capacitors for
extended time periods
• But if refresh the capacitor value every sample, may not be
so bad…
• General category of these techniques known as
“correlated double sampling”
CDS #1: Output Offset Cancellation
• Relatively insensitive
to switch errors
• Storing amplified
offset
Phase 1 : • But, what happens if

VC   AVos gain is large?
Phase 2 :
Vout  AVin  Vos   VC
 AVin
2
CDS #2: Input Offset Cancellation
Multistage Cancellation
• Open switches left to right

• Errors from S1 … SN-1 cancelled by final stage
• Application: continuous time comparators
3
CDS and Flicker Noise
V1/f
S2 V1 V2 S2
Vi A . S/H  Vo
S1
S1
S2
V1
V2
time
[kT]
T = 1/fs
Flicker Noise Analysis

 
  T  
Vo kT   AVi kT   V1 / f kT   V1 / f  kT   
   2 
 signal 
 input referred error Vnieq 
Laplace Transform
Delay by t d  e  std
 s 
T
Vnieq s   V1 / f s 1  e 2 
 
H n s 
4
Ex 2: Large Resistors
• Saw that we wanted large resistors in e.g.
common-mode extractor or feedback network (to
minimize OTA DC gain reduction)
• Not uncommon to want resistors in the Mto G range…
• These kinds of resistors usually take a lot of area, hence
have high parasitic capacitance…
Switched Cap. Resistor
5
Aside: Switched Cap Low-Pass Filter
Switched-Cap. R Feedback?
6
Switched-Capacitor Gain Stage
• Many possible topologies – one example shown

here
• Clocks generally non-overlapping
SC Gain Stage Phases
• Phase 1: Cf
Cs
Vi -
Vo
+
• Phase 2: Cf
Vo/Vi =
Cs
-
Vo
+
7
SC Gain Stage Noise
SC Gain Design Methodology
8
Ex 3: Lowering Power
Alternative Waveform
9
Typical Implementation
Current Integration Design

Methodology (GBW)
10
Methodology (Noise)

Methodology (Noise)
11
Lecture 24: Sampling in CMOS
Elad Alon
Dept. of EECS
Sampling
• Even in a communication system where signal
was originally discrete time
• Any non-idealities in the communication channel or
circuits will result in continuous time variations
• So, often want or need to sample the signal so that

it actually becomes constant over some period
• Most often achieved with a switch
clk
Vin ADC Dout
1
MOS Track & Hold
Ideal Sampling Practical Sampling
1 1
vIN vOUT vIN vOUT

S1 M1
C C
• kT/C noise
• Grab exact value
• Limited bandwidth
of Vin when switch
• Rsw = f(Vin)  distortion
turns off
• Switch charge injection
• Clock jitter, leakage, …
Switch Resistance
2
Acquisition Bandwidth
• Finite switch R  finite bandwidth
1
• Assuming constant Vin
and C starts at 0V: vIN vOUT
R S1
C
vout (t )  vin 1  e  t / 
• Leads to min. switch size for given bandwidth,

resolution
• Linear settling calc. – remember may only get T/2
• (Will C always start at 0V?)

Switch Ron Non-Linearity
3
Constant VGS Sampling
• Switch overdrive voltage is independent of signal

• Error from finite RON is linear (to first order)
Constant VGS Sampling Circuit
Ref: A. Abo et al, “A 1.5-V, 10-bit, 14.3-MS/s CMOS Pipeline Analog-

to-Digital Converter,” JSSC May 1999, pp. 599.
4
Charge Injection
• “Extra” charge dumped onto holding capacitor

• Channel charge has to go somewhere
• (Also get charge from parasitic gate capacitance)
• Problems:
• Offset
• Distortion (error charge is function of VIN)
Charge Injection Analysis
Ref: Wegmann, “Charge Injection in Analog MOS Switches,” JSSC, Dec. 1987.
5
Dummy Switch
• Dummy switch is
half width
• Depends on
equal charge
split between
source and drain
Ref: Bienstman et al,

JSSC 12/1980, pp. 1051.
Eichenberger et al,
JSSC 8/1989, pp. 1143.
Rejecting Injection Error
6
Bottom-Plate Sampling
1b
• Turn off 1a first
C2
Vin V2
• Injected charge is
constant
1a • Removed in differential
output
1a
on
off • Switch 1b opens later

time • C2 disconnected
1b  “zero” charge injected
on
off
time • Is this useful?
• V2 = 0V…
Using Bottom-Plate Sampling
7
Flip-Around Track and Hold
Ref: W. Yang, D. Kelly, I. Mehr, M. T. Sayuk, and L. Singer, "A 3-V 340mW
14-b 75-Msample/s CMOS ADC with 85-dB SFDR at Nyquist input,"
IEEE Journal of Solid-State Circuits, vol. 36, pp. 1931 - 1936,
December 2001.

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EE 240B – Spring 2018

Advanced Analog Integrated Circuits

• Methodology = how to translate a set of

• Especially in analog, some things are

• Will develop increasingly more complete

• GSI: Eric Chang

• All announcements made through piazza

• Primary source of material for the class

• Notes posted on the web

• Design of Analog CMOS Integrated Circuits,

• The Design of CMOS Radio-Frequency Integrated Circuits,

• Analog Integrated Circuit Design,

• The Designers Guide to SPICE & SPECTRE,

• Submission via gradescope

• Generally due 5pm on Thursdays

• In many applications, design of analog

Image from http://ihsmarkit.com

• Power is once again the key motivating

[Lemkin, JSSC 4/1999]

Image from moorinsightsstrategy.com

Image from chiprebel.com

• You will be tasked with building many

• You will be tasked with putting many

• How do you do this efficiently without

• Berkeley view: Capture designer’s

• Instead, you should strive to realize the best

• Module 2: MOS amplifier implementation

Advanced Analog Integrated Circuits

• Assumptions made to come up with this model:

• But all of them either (1) neglect certain effects or

• “Hand” models are good for building intuition,

• Simulation models are the ones you will have to

• But real transistors clearly aren’t quadratic

• Idea: work with a new (measurable) transistor

e.g. V* = 200mV  gm/ID = 10 V-1

• Inspired by the fact that V* = Vod for square law

• Lower V* results in better current efficiency, but

• How does transistor L affect ωT?

• So, often use intrinsic gain av0 = gm*ro instead

• If you have 5 billion transistors on a single chip,

• If you ship 100 million chips, do you think all of

Carusone, Johns, Martin, Analog Integrated

CGS Col CGC/2 + Col 2/3 CGC + Col

CGD Col CGC/2 + Col Col

CGB CGC || CCB 0 0

CSB CjSB CjsB + CCB/2 CjsB + 2/3 CCB

CDB CjDB CjDB + CCB/2 CjDB

Image from Intel/www.legitreviews.com

• Will largely ignore biasing details for now

• Goal: minimize power

• What are our design

Small Signal Model and Analysis

First Pass Methodology

• What needs to be true for analog to be lower

gm vs. GBW revisited (1)

gm vs. GBW revisited (3)

1 AV bwV *CL  0.6

What about ro?