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HKT400ARL
HKT400ARL
AGP SLOT 16
IDE CONNECTORS 21
1 1
VCORE
L2 1.5uH
4 4
+12V
+5V
R78
D
10K CB47 Q5
1 2 PWMBOOT1 CB46 .1u .1u FDD6690A
3 4 CPU VCORE PWM PWMUGATE1 R120 2.7 G
5 6
7 8 +5V6301 +5V R104 10K
U15 PWMPHASE1
DS
RN10 L4 0.7uH
10K CB31 R82 1 8
.1u 10 UGATE PHASE Q13 R130 C35
U13 2 7
BOOT PVCC FDB7045L 2.2 10u/10V C36
3 PWM_VID4 1 VID4 VCC 20 3 PWM VCC 6
2 19 4 5 PWMLGATE1 G 10u/10V
3 PWM_VID3 VID3 PGOOD PWRGD_PWM 3,5 GND LGATE
3 PWM_VID2 3 VID2 PWM4 18
4 17 HIP6601 CB44
3 PWM_VID1 VID1 ISEN4 ISEN1
S
5 16 R108 2.7K .01u
3 PWM_VID0 PWMCOMP VID0 ISEN1 PWMDRV1
6 COMP PWM1 15
PWMFB 7 14 PWMDRV2
PWMFS FB PWM2 ISEN2 R95 1.8K CE14 CE13 C55
8 FS/DIS ISEN2 13
9 12 ISEN3 R102 2.7K +12V 1500u/6.3V 820u/4V 10u/10V
PWMVSEN GND ISEN3 PWMDRV3 C22 CM17
10 VSEN PWM3 11
GDNPWM
D
CB40 HIP6301V ISEN: CB53 10u/16V 1u/25V
.1u Current seneing input with nominal full PWMBOOT2 CB52 .1u .1u Q9
load 50uA and overcurrent condition as
R85 82.5uA input. PWMUGATE2 R127 2.7 G
3 4.7K <Application> FDD6690A 3
R103 Risen = I* Rds / 50uA R107 10K
U17 PWMPHASE2
DS
CB35 200K 1. Rds = 4.5mOhm for FDB7045L L3 0.7uH
CB36 120p 2. Full load current set at 20A/Phase in our 1 8
R113 UGATE PHASE Q15 R137
application. 2 BOOT PVCC 7
2K 3300p => Risen := 1.8K Ohm with 33A as 3 6 FDB7045L 2.2 C33 C34
PWM VCC PWMLGATE2 10u/10V 10u/10V
over-current detection trip point. 4 GND LGATE 5 G
Output Ripple Current per Phase, FB: Vcore Droop Selection HIP6601 CB49
S
The avarage current through the 3 Risen .01u
R105 R91
Ipk-pk:
will go out from the FB and through Rin
47K 47K(OPT) Ipk-pk = dI = (Vi-Vo) * Ton / L then into VCORE plane. The more load
= Vo / L * Toff CE18 CE31 C38
current, the higher Vdroop.
where Ton is the time of high-side +12V 1500u/6.3V 1500u/6.3V(OPT)
+5V MOSFEST on, Toff is off. <Application> C21 CM16 10u/10V
In our application, Ipk-pk = 7.25A/phase The full loading Vdroop can be set as
D
LIGHT LOADING VCORE followed, CB51 10u/16V 1u/25V
OFFSET SETTING In multi-phase application, current ripple Vdroop := Rin / 50uA PWMBOOT3 CB50 .1u .1u Q8
can be reduced by each other. So, In our application, Vdroop(Max) =
Inductor must be placed close together 100mV(AMD spec). PWMUGATE3 R126 2.7 G
=> Rin := 2K Ohm R106 10K FDD6690A
and also place Low ERS capacitors
close to them. U16 PWMPHASE3
DS
FS : Channel Frequency Select L1 0.7uH
In our application, Rfs = 100K Ohm. Thus 1 8
R114 0 UGATE PHASE Q14 R109
COREFB+ 6 set the switching frequency of each 2 BOOT PVCC 7
phase to be about 250KHz. 3 6 FDB7045L 2.2 C27 C28
R115 0 PWM VCC PWMLGATE3 10u/10V 10u/10V
COREFB- 6 4 GND LGATE 5 G
2
HIP6601 CB38 2
S
R116 R112 .01u
0 1k(OPT)
R111
BULK CAPACITOR SELECTION : <NOTE>
5.1K(OPT) 1. Because each capacitor's ESR is not the same, the total
<ASSUMPTION>
1.VOLATGE TOLERANCE : +/- 100mV capacitance is derived acording to the ESR. Simplely Adding
2. MAXIMUM TRANSIENT CURRENT : 30A up all capacitance on the board is incorrect.
3. PWM RESPONSE TIME : 3uS
2. ESR caculation is determined by Max. transient
<EQUCATION> current and allowable volt drop. And with one distinct
ATX POWER CONNECTOR C = ( I * dT) / (dV - ESR * I), dV > ESR * I
C : TOTAL CAPACITANCE VALUE
ESR value, the total capacitance value is acording
-12V +5V +3.3V +5V +5VSUS +12V I : TRANSIENT CURRENT to the PWM response time.
dT : PWM RESPONSE TIME 3. The PWM voltage droop function can help to reduce the
dV : ALLOWABLE VOLATGE DROP ESR and capacitance required.
ESR : THE ESR IN TOTAL
+5VSUS C30 C37 C24 C20 4. Because trancient current will act as current ripple, and
<SOLUTION> the lower the ESR, the higher the ripple current flow through.
4.7u/16V 10u/10V 10u/10V 4.7u/16V ESR(max) = 7mOhm So, one should take good care of the lowest ESR catacitor
CN2 => SET ESR = 5mOhm
in case its current ripple over spec.
R122 11 1 C = 1,800 uF
4.7K 3V3 3V3 5. High side current ripple is significant and constant, so Vin
12 -12V 3V3 2
13 GND GND 3 capacitor should be able to endure large ripple current.
R134 1K(OPT) 14 4
25 -CPU_PT PS-ON 5V
15 GND GND 5
1 1
16 6
C
GND 5V
17 GND GND 7
R118 10K B Q11 18 8
3,13 -SUSB -5V PW-OK PWRGD_ATX 5
MMBT3904 19 9
5V 5VSB
20 5V 12V 10 TOPSTAR TECHNOLOGIES, INC.
E
ATX-NOPOST_CNTR_2X10 CE12
1000u/16V Title
VCORE
Size Document Number Rev
C HKT400ARL 0.1
D
8
+3.3V Q19 1u
+2.5VDIMM. Thus, we don't need anyextra schottky 1D5VREF 3 + FDD6690A
+12V CM27 barrier for power sequence issue. 1 CE20
1u 2 - G 1000u/6.3V
4
CB157 R412 CB144 CB145 R377 4
D
.1u 820 U32B Q21 .1u 1000p 1.5K 1% LM358M
S
FDD6690A
4
2D5VREF 5
+
7 G +2.5V
R411 6 - R294 CB115 C65 CE22
2.7K CB156 0 .1u 10u/10V 1000u/6.3V
S
.01u LM358M
4
CB132 C76 C75 CE27 CE23
.1u
10u/10V 10u/10V 1000u/6.3V 1000u/6.3V
ADD
+2.5VDIMM Design Notice :
+3.3V& +2.5V SUSTAIN POWER +2.5VDIMM FOR STR POWER 1.North Bridge's VCCM is an isolated power plane for Memory I/F. So, +2.5VDIMM can
V_DRAM share with VCCM for better power plane cutting.
+12V 2. North Bridge core power shouldn't arrive before Memory I/F power, ortiwill damage
+5VSUS +3.3VSUS the memory controler.
R479 CM31
10K 1u
U37 Q32 +2.5VDIMM
AMS1117-3V3 1 8
C
+5V S D
I V_IN V_OUT O 2 S D 7
B Q31 3 6
3
4 5
GND
E
R502 MMBT3904 FDS6680A
4.7K +3.3VSUS
Suspend Power for LAN PHY
G
U43
1 5 +5VSUS Q2 +3.3VSUSLAN
2,5 PWRGD_PWM AME8800AEFT-3V3
2,13 -SUSB 2
+5VSUS +2.5VSUS 3 4 R472 10K I V_IN V_OUT O
U44 NC7SZ00 CB212
GND
AMS1117-2V5 .1u(opt) CB167 CB166 CB28 CB30
I O +2.5VSUS 1u .1u .1u .1u
V_IN V_OUT +3.3VSUS
G
C92 CB213 U39 Q29
GND
10u/10V .1u 1 5 1 6
D S
13 -SUSC 2 2 D D 5
3 4 3 G S 4
G
NC7SZ00 NDC632P
VID Codes
+5VSUS +2.5VSUS_SB +5VSUS +3.3V
VID[4:0] VCC_CORE VID[4:0] VCC_CORE
U33 CE29
AME8805DEET-2V5 CB226
2
4
6
8
I 1000u/6.3V 1u 00000 1.850 10000 1.450
V_IN V_OUT O RN91
D
2
C81 CB162 Q37 00001 1.825 10001 1.425 2
GND
SC431CSK
1 CE37
V_DRAM 00100 1.750 10100 1.350
S
1000u/6.3V
3 OVERRIDE WP 18
VID0 4 17 VID0 R307 0 (OPT) PWM_VID0
6,8 VID[4:0] VID1 I0 NMO
5 16 R299 0
VID2 I1 MUX_SEL PWM_VID0 GPIOC 13 PWM_VID1
6 15 VID1 8 7
VID3 I2 Y0 PWM_VID1 PWM_VID[4:0] 2 PWM_VID2
VID2
VID4
7
8
I3 Y1 14
13 PWM_VID2 VID3
6
4
5
3 PWM_VID3 TOPSTAR TECHNOLOGIES, INC.
R318 0 I4 Y2 PWM_VID3 VID4 PWM_VID4
From Processor 9 LEVEL Y3 12 2 1
10 11 PWM_VID4 Title
GND Y4 RN17 0 8P4R(OPT)
CM22
MISCELLANEOUS DC-DC CONVERTERS
FM3570MT20/TSSOP Size Document Number Rev
1u (OPT) LAYOUT: Place The C 0.1
TO PWM REGULATOR HKT400ARL
Resistors Under U71
BANKS A B C D
Date: Monday, September 15, 2003 Sheet
E
3 of 27
A B C D E
ON ON ON ON ON 156 78 39
4 U18 ON ON ON ON OFF 154 77 38.5 4
R140 68 CLK14 46
6 APICCLKCPU REF2 OFF OFF ON ON OFF 120 60 30
+3.3VCLK 31
SDATA SMBDT 3,13,15,16,25 OFF OFF ON OFF ON 110 66.6 33.3
FOR CPU INPUT TOLERANCE 45 30
X1
X2
REF_STP SCLK SMBCK 3,13,15,16,25 OFF OFF ON OFF OFF 66.6 66.6 33.3
R139
(+2.5V LEVEL) 287 W312/ICS94228/C9854
OFF OFF OFF ON ON 200 66.6 33.3
4
X3 OFF OFF OFF ON OFF 166.6 66.6 33.3
1 2 OFF OFF OFF OFF ON 100 66.6 33.3
OFF OFF OFF OFF OFF 133.3 66.6 33.3
+3.3V VCC25_CLK CB43 14.318MHz CB42 OPTIONAL CAPACITORS
U14 FOR AGP CLOCK SKEW CONTROL
I O 10p 10p (TEST ONLY)
V_IN V_OUT +3.3V
C26 AGPCLK0 CB66 22p(OPT) Frequency table for ICS94228
GND
OFF ON ON ON 140 70 35
2
+2.5VDIMM +2.5VBFR OFF ON ON OFF 120 60 30 2
2
4
6
8
9 GND 3 4 DCLK6+ 16
14 21 DDRCLK6+ 1 2 RN11 R150
GND DDR5T/SDRAM8 DCLK6- 16
18 22 DDRCLK6- 1K 8P4R 1K
GND DDR5C/SDRAM9 RN89 10 8P4R JFSB1 JFSB2
26 GND DDRCLK2+
1
3
5
7
31 GND DDR6T 28 7 8 DCLK2- 15 13 FS0_SDA0
35 27 DDRCLK2- 5 6
GND DDR6C DCLK2+ 15
FS0 R123 10K
2
1
2
1
40 GND 3 4 DCLK5- 15
46 30 DDRCLK5+ 1 2 FS1 R131 10K
GND DDR7T DCLK5+ 15
29 DDRCLK5-
SMBDT DDR7C 13 FS1_SDA2
24 FS2 R117 10K S2 KNOT-OPEN
SMBCK SDATA DDRCLK8+ R494 0 FS3 R133 10K S1 KNOT-OPEN
25 SCLK DDR8T 34 DCLK8+ 16
33 DDRCLK8- R488 0 FS4 R157 10K S3 KNOT-OPEN
DDR8C DCLK8- 16
1 1
R511 22 DCLKFB 1
DDR10C 42
TOPSTAR TECHNOLOGIES, INC.
9 DCLKI FBOUT
DDR11T 45
44 Title
DDR11C
CLOCK SYNTHESIZER
W255/B9847/ICS93718
Size Document Number Rev
C 0.1
HKT400ARL
BANKS A B C D
Date: Monday, September 15, 2003 Sheet
E
4 of 27
A B C D E
+5V +5V
14
14
PW-LED +5V +5V
1 2 3 4 R514 22
-IDERST 21,23
+3.3VSUS
R486 R477 +3.3VSUS F04 F04
330 1K HD-LED +5V +5V
J4 R503 U45
PW_LED 4.7K U46C U46D
14
14
1 2 12 -PCIRST 1 5
3 4 -HD_LED 2
PW_BN R496 -HD_LED 23 2 PWRGD_ATX
5 6 68 3 4 5 6 9 8 R493 22
-PWRBTN 13 -RESET_NB 10
7 8
9 10 PW-BN CB218 R524 0(OPT) NC7SZ08 F04 F04
4
11 12 .1u +5V +5V 4
13 -EXTSMI
HEADER_2X6 R526 U46E U46F
14
14
EXTSMI 0(OPT)
11 10 13 12 R515 22
-PCIRSTX 13,17,18,19,20,22,27
R523 0
RESET F04 F04
C
-CPURST 6
R509 R508 1K B Q38 C99
22 .01u
E
+5VSUS MMBT2222A
R499
10K
4 PWRGD
RST_SW POWER GOOG LOGIC
D
+5V CB223 CT15
-PWGD G Q35
.1u 10u/10V NDS7002A
+5VSUS VCORE
TO DDR DIMMs
S
14
3 1 5 3
D
R489 7
0.01u G Q17 .1u
0 VCORE NDS7002A
S
R196 10K 1% B Q16
2,3 PWRGD_PWM +3.3VSUS
CE39
47u/10V(OPT)
+5VSUS TO SOUTH C39 MMBT2222A
E
R201
U38B R475 BRIDGE 27K 1% 470n
14
4.7K
PWROK circuit for
3 4 PWRGD_SB 13 Socket-462 CPU
DM7407M +2.5VPLLCPU
C
7
E
R214
462 39p 10K 1% 470n
2 2
+3.3V +3.3VSUS
330 1K(opt)
+3.3VSUS LED_D50-P25_2
1
13 -RSMRST R519 1
CM30 G Q39
13 GPO0
1u
0 NDS7002A
S
R279 10K
CPU1A CB91
COREFB- R276 10K .01u R236 R247
-SDATA0 AA35 AE1 60.4 1% 60.4 1%
8 -SDATA[63:0] -SDATA1 SDATA0 A20M -A20M 14
W37 AG1 FERR
-SDATA2 SDATA1 FERR R239
W35 SDATA2 INIT AJ3 -INIT 14
-SDATA3 Y35 AL1 Near socket-A
-SDATA4 SDATA3 INTR INTR 14
U35 SDATA4 IGNNE AJ1 -IGNNE 14
-SDATA5 U33 AN3 NMI VCORE +3.3V 301 1%(OPT)
4 -SDATA6 SDATA5 NMI 4
S37 SDATA6 RESET AG3 -CPURST 5
-SDATA7 S33 AN5 CPUCK+ CB89 .1u
-SDATA8 SDATA7 SMI -SMI 14,22 CPUCLK+ 4
AA33 AC1 R286 R283
-SDATA9 SDATA8 STPCLK -STPCLK 14 CPUCK-
AE37 680 1K CB96 .1u
-SDATA10 SDATA9 CPUCLK- 4
AC33 SDATA10 PWROK AE3 POWER_OK 5
-SDATA11 AC37 -FERR
-SDATA12 SDATA11 -FERR 14
Y37
C
-SDATA13 SDATA12
AA37 SDATA13 PICCLK N1 APICCLKCPU 4
-SDATA14 AC35 N3 FERR B
-SDATA15 SDATA14 PICD0/BYPASSCLK APICD0 14
S35 SDATA15 PICD1/BYPASSCLK N5 APICD1 14
-SDATA16 Q37 Q20 VREF_SYS is set at 50%
-SDATA17 SDATA16
E
Q35 AG13 MMBT2222A VCORE
-SDATA18 N37
SDATA17 COREFB-
AG11
COREFB- 2 of VCC_CORE to CPU
-SDATA19 SDATA18 COREFB+ COREFB+ 2
J33 SDATA19
-SDATA20 G33 AN17 CPUCK+ R257
-SDATA21 SDATA20 CLKIN CPUCK- 100 1%
G37 SDATA21 CLKIN AL17
-SDATA22 E37 VREF_SYS
-SDATA23 SDATA22
G35 SDATA23 RSTCLK AN19
-SDATA24 Q33 AL19 CB102 R255
-SDATA25 SDATA24 RSTCLK CB111 100 1%
N33 SDATA25
-SDATA26 L33 AL21 CLKOUT+ .1u .01u
-SDATA27 SDATA26 K7CLKOUT CLKOUT-
N35 SDATA27 K7CLKOUT AN21
-SDATA28 L37
-SDATA29 SDATA28
J37 SDATA29
-SDATA30 A37 AJ13
-SDATA31 SDATA30 ANALOG
E35 SDATA31
-SDATA32 E31 AA5 VREFMODE
-SDATA33 SDATA32 SYSVREFMODE VREF_SYS VCORE
E29 SDATA33 VREF_SYS W5
-SDATA34 A27 +2.5VCPU
3
-SDATA35 SDATA34 ZN
3
BANKS A B C
R520 0
D
Date: Monday, September 15, 2003 Sheet
E
6 of 27
1
2
3
4
BANKS
Q7
G7
G9
G23
G15
G17
G25
F8
AG9
AG7
Y7
K8
N7
H8
H6
AJ7
F30
AJ9
AG27
AG17
AG29
AG15
AL7
K30
AL9
H32
H30
H28
H10
AF8
AF6
AA7
AK8
AH6
AN7
AH8
AD8
AF32
AF30
AF28
AF10
AM8
AH30
AD30
H14 VSS1 H12
VCC_CORE1
H18 H16
KEY
KEY
KEY
KEY
KEY
KEY
KEY
KEY
AMD
VSS2 VCC_CORE2
KEY8
KEY6
KEY4
H20
KEY18
KEY16
KEY14
KEY12
KEY10
H22 VSS3
VCC_CORE3
H26 H24
VSS4 VCC_CORE4
M30 M8
VSS5 VCC_CORE5
VCC_SRAM9
VCC_SRAM8
VCC_SRAM7
VCC_SRAM6
VCC_SRAM5
VCC_SRAM4
VCC_SRAM3
VCC_SRAM2
VCC_SRAM1
P8 P30
VCC_SRAM31
VCC_SRAM30
VCC_SRAM29
VCC_SRAM28
VCC_SRAM27
VCC_SRAM26
VCC_SRAM25
VCC_SRAM24
VCC_SRAM23
VCC_SRAM22
VCC_SRAM21
VCC_SRAM20
VCC_SRAM19
VCC_SRAM17
VCC_SRAM16
VCC_SRAM14
VCC_SRAM13
VCC_SRAM11
VSS6 VCC_CORE6
R30 R8
VSS7 VCC_CORE7
T8 VSS8 T30
VCC_CORE8
V30 V8
+3.3V
A
A
VSS9 VCC_CORE9
1u
X8 X30
VSS10 VCC_CORE10
Z30 Z8
CM20
VSS11 VCC_CORE11
AB8 AB30
VSS12 VCC_CORE12
AF12 AF14
VSS13 VCC_CORE13
AF16 AF18
VSS14 VCC_CORE14
AF20 AF22
I
VSS15 VCC_CORE15
AF24 AF26
VSS16 VCC_CORE16
AM36 AM34
VSS17 VCC_CORE17
AK32 AK36
V_IN
VSS18 VCC_CORE18
U19
AK28 AK34
VSS19 VCC_CORE19
G AK24 AK30
GND VSS20 VCC_CORE20
AK20 AK26
VSS21 VCC_CORE21
AMD K7 CPU 2 OF 2
AK16 AK22
VSS22 VCC_CORE22
AK12 AK18
VSS23 VCC_CORE23
AK4 AK14
VSS25 VCC_CORE24
AK2 AK10
AME8805DEET-2V5
V_OUT O
VSS26 VCC_CORE25
AH36 AL5
VSS27 VCC_CORE26
AM32 AH26
VSS28 VCC_CORE27
AH34 AM30
VSS29 VCC_CORE28
AH32 AH22
VSS30 VCC_CORE29
AH28 AH18
VSS31 VCC_CORE30
AH24 AH14
VSS32 VCC_CORE31
AH20 AH10
VSS33 VCC_CORE32
AH16 AH4
VSS34 VCC_CORE33
C46
AH12 AH2
+2.5VCPU
VSS35 VCC_CORE34
AF4 AF36
VSS37 VCC_CORE35
4.7u/16V
AF2 AF34
VSS38 VCC_CORE36
AD36 AD6
VSS39 VCC_CORE37
AD34 AM26
.1u
VSS40 VCC_CORE38
AD32 AD4
CB68
VSS41 VCC_CORE39
B
B
AB6 AD2
VSS42 VCC_CORE40
AB4 AB36
FB20
VSS43 VCC_CORE41
AB2 AB34
VSS44 VCC_CORE42
C47
V36 X32
VSS52 VCC_CORE50
VCORE
V34 V6
VSS53 VCC_CORE51
4.7u/16V
V32 V4
VSS54 VCC_CORE52
SBK201209T-600Y-S
T6 V2
VSS55 VCC_CORE53
.1u
VSS56 VCC_CORE54
T2 T34
CB69
VSS57 VCC_CORE55
R36 T32
VSS58 VCC_CORE56
CB70
1000p
VSS62 VCC_CORE60
+2.5VPLLCPU
P4 P36
VSS63 VCC_CORE61
P2 P34
VSS64 VCC_CORE62
M36 P32
VSS65 VCC_CORE63
M34 M4
VSS66 VCC_CORE64
M32 M6
VSS67 VCC_CORE65
K6 M2
VSS68 VCC_CORE66
K4 K36
VSS69 VCC_CORE67
K2 K34
VSS70 VCC_CORE68
AM20 K32
VSS71 VCC_CORE69
H36 H4
C
C
VSS72 VCC_CORE70
H34 H2
VSS73 VCC_CORE71
F26 AM14
VSS74 VCC_CORE72
F22 F36
VSS75 VCC_CORE73
F18 F34
VSS76 VCC_CORE74
F14 F32
VSS77 VCC_CORE75
F10 F28
VSS78 VCC_CORE76
F6 F24
VSS79 VCC_CORE77
F4 F20
VSS80 VCC_CORE78
F2 F16
VSS81 VCC_CORE79
AM16 F12
VSS82 VCC_CORE80
D36 D32
VSS83 VCC_CORE81
D34 D28
VSS84 VCC_CORE82
D30 AM10
3
1
VSS85 VCC_CORE83
D26 D24
VSS86 VCC_CORE84
D22 D20
VSS87 VCC_CORE85
D18 D16
FAN2
VSS88 VCC_CORE86
CPU FAN
D14 D12
2
VSS89 VCC_CORE87
D10 D8
VSS90 VCC_CORE88
D6 D4
VSS91 VCC_CORE89
FAN_CNTR_1X3
+12V B34 D2
VSS92 VCC_CORE90
CONNECTOR
AM12 B36
VSS93 VCC_CORE91
B30 B32
VSS94 VCC_CORE92
B26 AM2
VSS95 VCC_CORE93
B22 B28
VSS96 VCC_CORE94
B18 B24
VSS97 VCC_CORE95
B14 B20
VSS98 VCC_CORE96
B10 B16
VSS99 VCC_CORE97
B6 B12
VSS100 VCC_CORE98
B2 B8
VSS101 VCC_CORE99
AM4 B4
VSS102 VCC_CORE100
D
D
AK6 AJ5
VSS103 VCC_CORE101
AM6
VSS104
AC7
VCC_Z
AE7
VSS_Z
AJ23
NC9
NC8
NC7
NC6
NC3
NC2
NC1
NC45
NC44
NC43
NC42
NC37
NC36
NC35
NC34
NC33
NC32
NC31
NC30
NC29
NC28
NC27
NC25
NC24
NC23
NC22
NC21
NC20
NC19
NC18
NC17
NC16
NC15
NC13
NC12
NC11
NC10
BP3_CUT
BP2_CUT
BP1_CUT
BP0_CUT
VCC_A
J5
Y5
S7
U7
W7
J31
L31
Y31
S31
U31
N31
G19
G21
Q31
G31
G29
G27
G13
G11
AN9
AG5
W31
AJ27
AJ19
AJ17
AJ15
AJ11
AL25
AL27
AL11
AE31
AA31
+2.5VPLLCPU
AN25
AN27
AN11
AC31
AG21
AG19
AG31
AG25
AG23
CPU1B
Title
Size
Date:
PPGA_462
Custom
CPU_D-
CPU_D+
OC_FID3
OC_FID2
OC_FID1
OC_FID0
Document Number
27
27
27
27
22,25
22,25
VCORE
CB104
CB105
CB106
CB107
CB108
CB109
CB101
CB244
CB247
CB251
CB252
CB257
.22u
.22u
.22u
.22u
.22u
.22u
.22u
.22u
.22u
.22u
.22u
.22u
.22u
.22u
.22u
.22u
.22u
.22u
.22u
.22u
.22u
.22u
.22u
.22u
.22u
.22u
.22u
E
E
HKT400ARL
Sheet
.22u(BOT)
.22u(BOT)
.22u(BOT)
.22u(BOT)
.22u(BOT)
7
Changed on 1999/12/14
VCORE
0.22uF(0603) X 22 [X7R]
0.22uF(0603) X 32 [X7R]
C54
C52
C53
C51
of
CB92
CB82
CB75
CB100
capacitors
27
TOPSTAR TECHNOLOGIES, INC.
.01u
.01u
.01u
.01u
Located at Socket-A Cavity
10uF(1206) X 4
10u/10V
10u/10V
10u/10V
10u/10V
Rev
Spare decoupling
0.01uF(0603) X 4
0.1
1
2
3
4
A B C D E
VCORE
CB255 .1u(BOT)
CB253 .1u(BOT)
AD29
AD30
AD31
AD32
AD33
AD34
AE29
AE30
AE31
AE32
AE33
AE34
W23
W24
M18
M20
M21
M22
M23
M24
M19
G29
C20
C21
D20
D21
N23
N24
R23
R24
U23
U24
H30
A33
A34
B33
B34
A20
A21
B20
B21
E20
E21
P23
P24
V23
V24
K30
F20
F21
T23
T24
L18
L20
L21
L22
L23
L19
U20A
AVDD1
VTS2K
VDS2K
VTT
VTT
VTT
VTT
VTT
VTT
VTT
VTT
VTT
VTT
VTT
VTT
VTT
VTT
VTT
VTT
VTT
VTT
VTT
VTT
VTT
VTT
VTT
VTT
VTT
VTT
VTT
VTT
VTT
VTT
VTT
VTT
VTT
VTT
VTT
VTT
VTT
VTT
VTT
VTT
VTT
VTT
VTT
VTT
VTT
VTT
VTT
VTT
VTT
VTT
VTT
VTT
VTT
VTT
VTT
-AIN2 E26 A27 -SDATA0
6 -AIN[14:2] AIN2 D0 -SDATA[63:0] 6
-AIN3 A25 E29 -SDATA1
-AIN4 AIN3 D1 -SDATA2
E24 AIN4 D2 A29
-AIN5 A26 B29 -SDATA3
-AIN6 AIN5 D3 -SDATA4
C25 AIN6 D4 A30
-AIN7 D25 C29 -SDATA5
-AIN8 AIN7 D5 -SDATA6
C24 AIN8 D6 C30
-AIN9 C23 A31 -SDATA7
-AIN10 AIN9 D7 -SDATA8
D23 AIN10 D8 C27
-AIN11 D26 E27 -SDATA9
-AIN12 AIN11 D9 -SDATA10
E23 AIN12 D10 C26
-AIN13 A24 E28 -SDATA11
-AIN14 AIN13 D11 -SDATA12
B23 AIN14 D12 A28
D28 -SDATA13
-AINCLK D13 -SDATA14
6 -AINCLK B25 AINCLK D14 B26
D29 -SDATA15 S2K_VREF is set at 50%
-AOUT2 D15 -SDATA16 VCORE
6 -AOUT[14:2] W34 D32
-AOUT3 W33
AOUT2 D16
D34 -SDATA17 of VCC_CORE to NB
-AOUT4 AOUT3 D17 -SDATA18
Y32 AOUT4 D18 E30
-AOUT5 AA32 H32 -SDATA19 R273
3
D63
AC34
AC33
AC32
AC31
AC30
AC29
W30
M30
C31
C33
C34
D24
D27
D30
D31
H33
H31
H29
N30
R30
R29
U33
U31
D22
A32
B24
B27
B30
B31
B32
E33
E31
P33
P31
P30
P29
B22
Y33
Y31
Y30
F27
F26
T30
T29
F30
L33
L31
J29
VT8377
AGND1
-DICLK0 L5 L6 -DICLK_0
6 -DICLK[0:3] LCN0603T-10NJ-S LCN0603T-10NJ-S
-DICLK1 L7 L8 -DICLK_1 2
1
LCN0603T-10NJ-S LCN0603T-10NJ-S 1
+2.5V AVDD_MEM
+2.5VDIMM
+2.5VDIMM +2.5V AVDD_MEM FB25
SBK201209T-600Y-S
R295 C95 CB118 CB117
4.7K
-QDRRD 1u .1u .1u MD_34 R341 22 MD34
MD[63:0] 15,16
AG29
AG30
AG31
AG32
AG33
AG34
AH29
AH30
AH31
AH32
AH33
AH34
MD_0
AF29
AF30
AF31
AF32
AF33
AF34
FB26 MD0
AJ10
AJ11
AJ13
AJ14
AJ21
AJ22
AJ24
AJ25
AJ34
AJ17
1 2
AG1
AG2
AG3
AG4
AG5
AG6
AH1
AH2
AH3
AH4
AH5
AH6
AJ1
AJ2
AJ3
AJ4
AJ5
AJ6
MD_4 3 4 RN27 MD4
U20B SBK201209T-600Y-S AGND2 bottom layer MD_5 5 6 22 8P4R MD5
MD_1 7 8 MD1
VCC3
VCC3
VCC3
VCC3
VCC3
VCC3
VCC3
VCC3
VCC3
VCC3
VCC3
VCC3
VCC3
VCC3
VCC3
VCC3
VCC3
VCC3
VCC3
VCC3
VCC3
VCC3
VCC3
VCC3
VCC3
VCC3
VCC3
VCC3
VCC3
VCC3
VCC3
VCC3
VCC3
VCC3
VCC3
VCC3
AVDD2
AVDD3
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
MD_2 1 2 MD2
4 MD_6 3 4 RN28 MD6 4
SWEB -SWEB 16
AK18VSS
VSS
VSS
VSS
VSS
VSS
AJ23 VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
AN11
AN14
AN17
AN18
AN21
AN24
AN27
AN30
AN33
AK16
AK19
AL11
AL14
AL16
AL17
AL18
AL19
AL21
AL24
AL27
AL30
AL33
AJ15
AJ16
AJ20
AJ26
AJ27
AJ29
AJ30
AJ31
AJ32
AJ33
AJ18
1 1
AN2
AN5
AN8
AL2
AL5
AL8
AJ8
AJ9
+2.5VDIMM
VCCQ
C68 R314
.1u 0
C2
C3
C4
D4
D5
N1
N2
N3
N4
N5
N6
R1
R2
R3
R4
R5
R6
A1
A2
B2
B3
E5
E6
P1
P2
P3
P4
P5
P6
Y4
+2.5V
F5
F6
F7
F8
J6
U20C
VCC1
VCC1
VCC1
VCC1
VCC1
VCC1
VCC1
VCC1
VCC1
VCC1
VCC1
VCC1
VCC1
VCC1
VCC1
VCC1
VCC1
VCC1
VCC1
VCC1
VCC1
VCC1
VCC1
VCC1
VCC1
VCC1
VCC1
VCC1
VCC1
VCC1
VCC1
VCC1
VCC1
VSUS25
VCCQQ
R251 C59
4 Kt400 4/1 3K 1% .1u 4
GD28 A9 +2.5V
GD28
GD29 C9 GD29
GD30 B9 +2.5V -TESTIN R280 4.7K
GD30
GD31 A10 GD31 VCC2 AC1
VCC2 AC2
-SBA0 B14 AC3
17 -SBA[7:0] -SBA1 SBA0 VCC2
A14 AC4 +2.5V
-SBA2 SBA1 VCC2
A13 SBA2 VCC2 AC5
-SBA3 C14 AC6 LPAR R249 8.2K
-SBA4 SBA3 VCC2
A11 SBA4 VCC2 AD1
-SBA5 C11 AD2
-SBA6 SBA5 VCC2 VCCQ
C10 SBA6 VCC2 AD3
-SBA7 B11 AD4
SBA7 VCC2 AGPCOMP R227 60 1%
VCC2 AD5
17 -C/BE0 H1 C/BE0 VCC2 AD6
17 -C/BE1 B1 C/BE1
17 -C/BE2 A3 C/BE2
17 -C/BE3 A7 C/BE3 Kt400 4/1
AD_STBF0 G2 LCOMPP R250 300 1%
17 AD_STBF0 AD_STBF0
17 AD_STBS0 AD_STBS0 G1 AD_STBS0 VD0 V3 VLAD0 14
17 AD_STBF1 AD_STBF1 C6 AD_STBF1 VD1 V1 VLAD1 14
17 AD_STBS1 AD_STBS1 C7 AD_STBS1 VD2 AA3 VLAD2 14
VD3 AA1 VLAD3 14
17 SB_STBF SB_STBF B12 SB_STBF VD4 U1 VLAD4 14
17 SB_STBS SB_STBD A12 SB_STBS VD5 U3 VLAD5 14
VD6 AB2 VLAD6 14 Decoupling capacitors under NB
DBIH_PIPE E8 AB1 VCCQ
17 DBIH_PIPE DBIH VD7 VLAD7 14
2
DBIL E9 2
4 GCLK_NB M2 GCLK
AGPCOMP K5 AGPCOMP
AGPVREFGC F10
17 AGPVREFGC AGPVREF0
J5 AGPVREF1
VSSQQ
1 1
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
AA2
AA4
AB6
AE1
AE2
AE3
AE4
AE5
AE6
AF1
AF2
AF3
AF4
AF5
AF6
D10
D13
B10
B13
E13
W5
M3
M4
M5
G5
C1
D7
H2
H4
H5
U4
U5
U6
K6
B4
B7
E2
E4
K4
V2
V4
V5
T1
F9
T2
T3
T4
T5
T6
L2
L4
L5
VT8377
TOPSTAR TECHNOLOGIES, INC.
Title
NORTH BRIDGE VT8377 (AGP & VLINK)
Size Document Number Rev
Custom 0.1
HKT400ARL
Date: Monday, September 15, 2003 Sheet 10 of 27
A B C D E
A B C D E
U20D
+2.5V +2.5V
Y29 VDD
W29 VDD VCC2 U11
V29 VDD VCC2 U12
U29 VDD VCC2 V11
N29 VDD VCC2 V12
M29 VDD VCC2 W11
F29 VDD VCC2 W12
4 F28 4
VDD
F25 VDD
F24 VDD
F23 VDD
F22 VDD VSS B19
F16 VDD VSS B18
F15 VDD VSS L17
E16 VDD VSS M17
E15 VDD VSS AA21
D16 VDD VSS AA20
D15 VDD VSS AA19
C16 VDD VSS AA18
C15 VDD VSS AA17
B16 VDD VSS AA16
B15 VDD VSS AA15
A16 VDD VSS AA14
A15 VDD VSS Y21
A17 VDD VSS Y20
B17 VDD VSS Y19
C17 VDD VSS Y18
D17 VDD VSS Y17
E17 VDD VSS Y16
F17 VDD VSS Y15
VCCQ Y14
VSS
VSS W21
Decoupling capacitors L13 VCC1 VSS W20
L14 W19
under NB M13
VCC1 VSS
W18
+2.5V VCC1 VSS
3 M14 VCC1 VSS W17 3
L16 VCC1 VSS W16
L15 VCC1 VSS W15
CB254 .01u(BOT) M16 W14
VCC1 VSS
M15 VCC1 VSS V21
CB250 .01u(BOT) T12 V20
VCC1 VSS
T11 VCC1 VSS V19
CB246 .1u(BOT) R12 V18
VCC1 VSS
R11 VCC1 VSS V17
CB233 .1u(BOT) P12 V16
VCC1 VSS
P11 VCC1 VSS V15
CB242 .1u(BOT) N12 V14
VCC1 VSS
N11 VCC1 VSS U21
CB245 1u(BOT) M12 U20
VCC1 VSS
M11 VCC1 VSS U19
CB243 1u(BOT) L12 U18
+2.5VDIMM VCC1 VSS
VSS U17
CB232 1u(BOT) Y23 U16
VCC3 VSS
Y24 VCC3 VSS U15
AD23 VCC3 VSS U14
AD22 VCC3 VSS T21
AD21 VCC3 VSS T20
AD20 VCC3 VSS T19
AD19 VCC3 VSS T18
AD18 VCC3 VSS T17
AD17 VCC3 VSS T16
AD16 VCC3 VSS T15
Decoupling capacitors AD15 VCC3 VSS T14
AD14 R21
2 under NB AD13
VCC3 VSS
R20
2
VCC3 VSS
AD12 VCC3 VSS R19
+2.5VDIMM AC24 R18
VCC3 VSS
AC23 VCC3 VSS R17
CB227 .01u(BOT) AC22 R16
VCC3 VSS
AC21 VCC3 VSS R15
CB228 .01u(BOT) AC20 R14
VCC3 VSS
AC19 VCC3 VSS P21
CB229 .1u(BOT) AC18 P20
VCC3 VSS
AC17 VCC3 VSS P19
CB230 .01u(BOT) AC16 P18
VCC3 VSS
AC15 VCC3 VSS P17
CB231 .1u(BOT) AC14 P16
VCC3 VSS
AC13 VCC3 VSS P15
CB234 .01u(BOT) AC12 P14
VCC3 VSS
AC11 VCC3 VSS F19
CB235 .1u(BOT) AB24 F18
VCC3 VSS
AB23 VCC3 VSS E19
CB236 .01u(BOT) AB12 E18
VCC3 VSS
AB11 VCC3 VSS D19
CB237 .1u(BOT) AA24 D18
VCC3 VSS
AA23 VCC3 VSS C19
CB238 .01u(BOT) AA12 C18
VCC3 VSS
AA11 VCC3 VSS A19
CB239 .1u(BOT) Y12 A18
VCC3 VSS
Y11 VCC3
CB240 .1u(BOT)
1 1
VT8377
USBDT2+ 24
USBP2- USBDT2- R261 15K
USBDT2- 24
USBP3+ USBDT3+R284 15K
USBDT3+ 24
AC18
AC19
AA21
AB10
AB11
AB14
AB15
AB20
AB21
USBP3- USBDT3- R285 15K
AB6
AB7
R21
D24
C24
C25
C26
USBDT3- 24
P21
Y21
A24
A25
A26
B24
B25
B26
F12
F13
F16
F17
W5
M5
R5
E5
P5
Y5
F5
F7
F8
L5
U26A USBP4+ USBDT4+R264 15K
USBDT4+ 24
H3
VCC33
VCC33
VCC33
VCC33
VCC33
VCC33
VCC33
VCC33
VCC33
VCC33
VCC33
VCC33
VCC33
VCC33
VCC33
VCC33
VCC33
VCC33
VCC33
VCC33
VCC33
VCC33
VCC33
VCC33
VCC33
VCC33
VCC33
VCC33
USBVDD
USBVDD
USBVDD
USBVDD
USBVDD
USBVDD
USBVDD
USBVDD
USBVDD
USBVDD
18,19,20,21 A_D0 AD0
J2 +2.5VSUS_SB USBP4- USBDT4- R265 15K
18,19,20,21 A_D1 AD1 USBDT4- 24
18,19,20,21 A_D2 H2 AD2
J1 USBP5+ USBDT5+R281 15K
18,19,20,21 A_D3 AD3 USBDT5+ 24
18,19,20,21 A_D4 G3 AD4
H1 T4 USBP5- USBDT5- R282 15K
18,19,20,21 A_D5 AD5 VSUS25 USBDT5- 24
18,19,20,21 A_D6 G2 AD6 VSUS25 U4
18,19,20,21 A_D7 G1 AD7
G4 D15 Kt400 4/1
18,19,20,21 A_D8 AD8 USBSUS25
18,19,20,21 A_D9 F2 AD9
F1 VDDUSB +2.5V
18,19,20,21 A_D10 AD10
18,19,20,21 A_D11 E1 AD11
F3 D22 FB34
18,19,20,21 A_D12 AD12 PLLVDDA
E2 A23 SBK201209T-600Y-S
18,19,20,21 A_D13 AD13 PLLVDDA
E3 CB129 CT13 CB128
18,19,20,21 A_D14 AD14
D2 .1u .1u
18,19,20,21 A_D15 AD15
B5 B23 10u/10V
18,19,20,21 A_D16 AD16 PLLGNDA
A5 E22 FB32
18,19,20,21 A_D17 AD17 PLLGNDA
C6 SBK201209T-600Y-S
18,19,20,21 A_D18 AD18
B6 GNDUSB
3
18,19,20,21 A_D19 AD19 3
C16
C17
C18
C19
C20
C21
C22
D16
D18
D20
E16
E23
E25
A16
A18
A20
A22
B16
B18
B20
B22
E18
E20
VT8235
F18
F19
F21
F20
L11
G5
A1
A2
B1
B2
E9
K4
CE25 1000u/6.3V
1 1
GNDUSB
+3.3VSUS +2.5V
Power Up Strappings :
SA[19:16] => CPU Clock Divider
AB16
AB17
0000 11 1000 7
AC4
AC5
AA4
AB4
AB8
AB9
U21
U22
K21
F14
F10
F15
T21
J21
H5
U5
K5
V5
F9
T5
0001 11.5 1001 7.5
J5
U26B 0010 12 1010 8
PDD0 AA24 T3 0011 12.5 1011 8.5
VSUS33
VSUS33
VSUS33
VSUS33
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
23 PDD[0:15] PDD0 ACBITCLK BIT_CLK 26,27
4
PDD1 AA25 T2 0100 5 1100 9 4
C
SDD15 SA14/SDD14 IOR Q33 MMBT3904 +3.3VSUS
AE21 SA15/SDD15 IOW AD9 -IOW 2
AF9 TEST SDA2 4 3 B
TEST FS1_SDA2 4
AE15 AD10 -IORDY R492 -PWROK_NB R395 10K
23 SDDREQ SDDRQ IORDY/GPI19
AD22 1K
23 -SDDACK SDDACK SA16 +3.3V
E
AF22 AF11 NC7SZ125 -SUSA R375 10K
23 -SDIOR SDIOR/SHDMARDY/SHSTROBE SA16/GPO16 SA17
23 -SDIOW AC21 SDIOW/SSTOP SA17/GPO17 AE11
AD15 AD11 SA18 SDA1 R458 2.7K R464 1K -SUSST R373 10K
23 SIORDY SDRDY/SDDMARDY/SDSTROBE SA18/GPO18
-SDCS1 AC23 AC11 SA19 -SOE R398 1.2K
23 -SDCS1 SDCS1 SA19/GPO19 +3.3V
-SDCS3 AD23 RN99 4.7K 8P4R -ROMCS R404 4.7K SUS_CLK R379 10K
23 -SDCS3 SDCS3
2
SDA0 AE23 AC14 1 2 -SDCS1 R429 10K 2
N11
N12
N13
N16
P11
N5
1 1
U29
+3.3VSUS NC7SZ66
5 1 SMBCK
4
2
3
SMBCK2 14 TOPSTAR TECHNOLOGIES, INC.
5 PWRGD_SB
U31 Title
NC7SZ66 SOUTH BRIDGE VT8235 (PM, HW, ISA)
5 1 SMBDT
2 Size Document Number Rev
SMBDT2 14
C 0.1
4 3 HKT400ARL
Date: Monday, September 15, 2003 Sheet 13 of 27
A B C D E
A B C D E
+3.3V
4 4
M21
M22
M23
M24
M25
M26
G21
H21
N21
N22
N23
N24
N25
N26
D13
D11
D12
E13
E11
E12
F22
L21
L22
U26C
EEPROM DPSLP R356 4.7K
F25 R24 GHI U23 GHI R358 4.7K
MIISUS25
MIISUS25
VCCVK
VCCVK
VCCVK
VCCVK
VCCVK
VCCVK
VCCVK
VCCVK
VCCVK
VCCVK
VCCVK
VCCVK
VCCVK
VCCVK
VCCVK
VCCVK
VCCVK
MIIVCC
MIIVCC
MIIVCC
MIIVCC
10 VLAD0 VD0 GHI/GPI22/GPO22
F26 P25 VIDSEL SEECS 1 8 AGPBZ R304 4.7K
10 VLAD1 VD1 VIDSEL/GPI28/GPO28 CS VCC +3.3V
J26 P24 VRDSLP CB116
10 VLAD2 VD2 VRDSLP/GPI29/GPO29
J25 A8 AGPBZ VIDSEL R355 4.7K
10 VLAD3 VD3 AGPBZ/GPI6 SEEDO
E26 P26 DPSLP 4 5 .1u VRDSLP R354 4.7K
10 VLAD4 VD4 DPSLP/GPI23/GPO23 SEEDI DO GND
10 VLAD5 E24 VD5 3 DI NC 6
K24 T25 SEECLK 2 7
10 VLAD6 VD6 A20M -A20M 6 SK NC
10 VLAD7 K26 VD7 FERR U26 -FERR 6
D25 T26 -IGNNE 6 93C46-3GR
VD8 IGNNE
F23 VD9 INIT R25 -INIT 6
G23 T23 +3.3V
VD10 INTR INTR 6
G22 VD11 NMI R23 NMI_SB 6
H22 U25 -SLP SPEAK R416 4.7K
VD12 SLP
G24 VD13 SMI T24 -SMI 6,22
J22 R26 SERIRQ R415 4.7K
VD14 STPCLK -STPCLK 6
K22 VD15
B13 -SLP R364 4.7K
MCRS CRS 20
LAD0 AF8 C13
22,27 LAD0 LAD0 MCOL COL 20 APICCLK_SB R359
LAD1 AE8 4.7K(opt)
22,27 LAD1 LAD1 TXEN
LAD2 AD8 B12 R302 33
22,27 LAD2 LAD2 MTXENA TXEN 20
LAD3 AF7 C12 R287 33
22,27 LAD3 LAD3 MTXD0 TXD0 20
A11 R303 33 +3.3VSUS
MTXD1 TXD1 20
AD7 B11 R297 33
22 -LDRQ LREQ MTXD2 TXD2 20
C11 R288 33 CPUMISS R369 4.7K
MTXD3 TXD3 20
22,27 -LFRAME AE7 LFRM MTXCLK A12 TXCLK 20
3 3
AB12
AB13
AB18
AB19
AE25
AE22
AE19
AE16
W21
W25
S4
AA5
AB5
R14
R15
R13
R11
R12
V21
V22
P13
P14
P15
P16
VT8235 KNOT-OPEN
T11
T12
T13
T14
T15
T16
AOLGPI
R4
V4
X1
X2
INTRUDER
S5 KNOT-OPEN
X5
2 1
C79 4 3 C78
+3.3VSUS
10p 10p
D5 32.768KHz
+2.5V
2
BAT54C
3
R334 C69
1
JBAT1 VBAT Kt400 4/1 3K 1% .1u 1
1
1
2 LVREF_SB
R473 3 CB169
1K Kt400 4/1 R329 C70
R454 .1u 1K 1% .1u
1K
CE38
TOPSTAR TECHNOLOGIES, INC.
47u/10V
BAT1 Title
B-CR2032-C SOUTH BRIDGE VT8235(LPC, LAN, VLINK)
The voltage level of
Size Document Number Rev
LVREF_SB is 0.9V C 0.1
HKT400ARL
Date: Monday, September 15, 2003 Sheet 14 of 27
A B C D E
A B C D E
+2.5VDIMM
+2.5VDIMM
DIMM1
104
112
128
136
143
156
164
172
180
108
120
148
168
15
22
30
54
62
77
96
38
46
70
85
DIMM2
104
112
128
136
143
156
164
172
180
108
120
148
168
15
22
30
54
62
77
96
38
46
70
85
7
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
MAA0 48 2 MD0
9,16 MAA[15:0] A0 D0 MD[63:0] 9,16
MAA1 43 4 MD1 MAA0 48 2 MD0
4
MAA2 A1 D1 MAA1 43 A0 D0 4
41 A2 D2 6 MD2
A1 D1 4 MD1
MAA3 130 8 MD3 MAA2 41 6 MD2
MAA4 A3 D3 MAA3 130 A2 D2
37 A4 D4 94 MD4
A3 D3 8 MD3
MAA5 32 95 MD5 MAA4 37 94 MD4
MAA6 A5 D5 MAA5 32 A4 D4
125 A6 D6 98 MD6
A5 D5 95 MD5
MAA7 29 99 MD7 MAA6 125 98 MD6
MAA8 A7 D7 MAA7 29 A6 D6
122 A8 D8 12 MD8
A7 D7 99 MD7
MAA9 27 13 MD9 MAA8 122 12 MD8
MAA10 A9 D9 MAA9 27 A8 D8
141 A10 D10 19 MD10
A9 D9 13 MD9
MAA13 118 20 MD11 MAA10141 19 MD10
MAA14 A11 D11 MAA13118 A10 D10
115 A12 D12 105 MD12
A11 D11 20 MD11
MAA15 167 106 MD13 MAA14115 105 MD12
A13 D13 MAA15167 A12 D12
D14 109 MD14
A13 D13 106 MD13
MAA11 59 110 MD15 109 MD14
MAA12 BA0 D15 MAA11 59 D14
52 BA1 D16 23 MD16
BA0 D15 110 MD15
113 24 MD17 MAA12 52 23 MD16
BA2 D17 BA1 D16
D18 28 MD18 113 BA2 D17 24 MD17
9,16 -CS0 157 CS0 D19 31 MD19
D18 28 MD18
9,16 -CS1 158 CS1 D20 114 MD20 9,16 -CS2 157 CS0 D19 31 MD19
71 NC/CS2 D21 117 MD21 9,16 -CS3 158 CS1 D20 114 MD20
163 NC/CS3 D22 121 MD22 71 NC/CS2 D21 117 MD21
D23 123 MD23 163 NC/CS3 D22 121 MD22
9,16 DQM[7:0] DQM0 97 DQM0 D24 33 MD24
D23 123 MD23
DQM1 107 35 MD25 DQM0 97 33 MD24
DQM2 DQM1 D25 DQM1 DQM0 D24
119 DQM2 D26 39 MD26 107 DQM1 D25 35 MD25
DQM3 129 40 MD27 DQM2 119 39 MD26
DQM3 D27 DQM3 DQM2 D26
DQM4 149 DQM4 D28 126 MD28 129 DQM3 D27 40 MD27
DQM5 159 127 MD29 DQM4 149 126 MD28
DQM5 D29 DQM5 DQM4 D28
3 DQM6 169 DQM6 D30 131 MD30 159 DQM5 D29 127 MD29 3
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
NC/FETEN WP +2.5VDIMM
R393
10K(OPT)
100
116
124
132
139
145
152
160
176
11
18
26
34
42
50
58
66
74
81
89
93
DDRAM-DIMM_SOCKET_184P
3
100
116
124
132
139
145
152
160
176
11
18
26
34
42
50
58
66
74
81
89
93
R371 DDRAM-DIMM_SOCKET_184P
3
10K(OPT)
+2.5VDIMM
1000u/6.3V(OPT)
CE33 CE28 CE26 C83 C71 C72 C84
1000u/6.3V 1000u/6.3V
10u/10V 10u/10V 10u/10V 10u/10V
1 1
+2.5VDIMM
CB138 CB140 CB139 CB141 CB142 CB148 CB149 CB150 CB151 CB152 CB159 CB161 CB143 CB155 CB160 CB153 CB154
.1u .1u .1u .1u .1u .1u .1u .1u .1u .1u .1u .1u .1u .1u .1u .01u .01u TOPSTAR TECHNOLOGIES, INC.
Title
DIMM1 & DIMM2 (184 PIN DDR)
Size Document Number Rev
C 0.1
HKT400ARL
Date: Monday, September 15, 2003 Sheet 15 of 27
A B C D E
A B C D E
104
112
128
136
143
156
164
172
180
108
120
148
168
RN62
15
22
30
54
62
77
96
38
46
70
85
MD10 1 2 MAB10 3 4
7
MD11 3 4 RN59 MAA12 5 6
4
MD20 5 6 MAB12 7 8 33 4
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
MD16 7 8 33 MD13 1 2
MAB0 48 2 MD0 MD17 1 2 DQS1 3 4 RN58
9 MAB[15:0] A0 D0 MD[63:0] 9,15
MAB1 43 4 MD1 MAA14 3 4 RN60 MD14 5 6
MAB2 A1 D1 33
41 A2 D2 6 MD2 MD21 5 6 MD15 7 8
MAB3 130 8 MD3 DQS2 7 8 33 MD3 1 2
MAB4 A3 D3 VTT_MEM VTT_MEM RN57
37 A4 D4 94 MD4 MAB9 1 2 MD8 3 4
MAB5 32 95 MD5 MD18 3 4 RN76 MD9 5 6
MAB6 A5 D5 CB207 .1u CB208 .1u 33
125 A6 D6 98 MD6 MD22 5 6 MD12 7 8
MAB7 29 99 MD7 MAA7 7 8 33 MAA3 1 2
MAB8 A7 D7 CB209 .1u CB204 .1u RN81
122 A8 D8 12 MD8 MAB6 1 2 MAB3 3 4
MAB9 27 13 MD9 MD24 3 4 RN79 MAA2 5 6
MAB10 A9 D9 CB205 .1u CB170 .1u 33
141 A10 D10 19 MD10 MD28 5 6 MD26 7 8
MAB13 118 20 MD11 MD25 7 8 33 MD23 1 2
MAB14 A11 D11 CB172 .1u CB173 .1u RN78
115 A12 D12 105 MD12 MD30 1 2 MAA5 3 4
MAB15 167 106 MD13 MD27 3 4 RN82 MAB5 5 6
A13 D13 CB174 .1u CB176 .1u 33
D14 109 MD14 MAB2 5 6 MAA6 7 8
MAB11 59 110 MD15 MAB1 7 8 33 MAA8 1 2
MAB12 BA0 D15 CB177 .1u CB178 .1u DQS4 RN77
52 BA1 D16 23 MD16 1 2 MAB7 3 4
113 24 MD17 MD34 3 4 RN69 MAB8 5 6
BA2 D17 CB180 .1u CB181 .1u 33
D18 28 MD18 MD38 5 6 MD19 7 8
157 31 MD19 MAA11 7 8 33 MAB11 1 2
9 -CS4 CS0 D19
158 114 MD20 CB182 .1u CB184 .1u MD44 1 2 MD39 3 4 RN64
9 -CS5 CS1 D20
71 117 MD21 -SRASB 3 4 RN65 MD35 5 6
NC/CS2 D21 33
163 NC/CS3 D22 121 MD22 9,15 -SRASA 5 6 MD40 7 8
123 MD23 MD45 7 8 33 MD31 1 2
DQM0 D23 RN83
9,15 DQM[7:0] 97 DQM0 D24 33 MD24 9,15 -SWEA 1 2 MAA1 3 4
DQM1 107 35 MD25 -SWEB 3 4 RN66 MAA0 5 6
DQM2 DQM1 D25 33
3 119 DQM2 D26 39 MD26 MD41 5 6 MAA10 7 8 3
NC/FETEN WP +2.5VDIMM
10K(OPT) CB187 1u
CB191 1u
100
116
124
132
139
145
152
160
176
11
18
26
34
42
50
58
66
74
81
89
93
DDRAM-DIMM_SOCKET_184P
3
MVREF_DIM CB194 1u
15 MVREF_DIM
CB198 1u
CB146 CB147 +2.5VDIMM+3.3V
1
.1u 1000p U34 CB202 1u 1
+3.3V
+5V
VCCQ +5V +12V VCCQ
4 GCLK_SLOT GREQ
B7 CLK AGP V3.0 RST A7
GGNT -PCIRSTX 5,13,18,19,20,22,27 AD_STBF0 R235 8.2K(OPT)
4
D
AGPVREFCG AGPVREFGC AGPVREFGC 10
C63 AGP8X-1.5V_SLOT 4X : 0.75V 4.7K G Q12
.1u NDS7002A
C
8X : 0.35V
S
-AGP8XDET_GC R110 10K B Q6
10 GD[31:0]
MMBT3904 R129
E
200
R121
10K
R135
D
1K Q7
To AGP Slot R248 G -AGP8XDET_GC G NDS7002A To North Bridge
1
3.32K 1% 1
Q10 1 : 4X -AGP8XDET 10
S
NDS7002A 0 : 8X
VREF_CG R254 1.47K R99 1 : 4X
4X : 0.75V 2.2K 0 : 8X
8X : 0.35V
TOPSTAR TECHNOLOGIES, INC.
R271
C64 1.02K 1% Title
.01u
AGP SLOT
Size Document Number Rev
C 0.1
HKT400ARL
Date: Monday, September 15, 2003 Sheet 17 of 27
A B C D E
A B C D E
4 12,19,20,21 A_D[31:0] 4
+3.3V
+5V
-12V
PCI1 +12V
+5V
+3.3V +3.3V
+5V
-12V
PCI2 +12V
+5V
+3.3V
PCI-5V_SLOT_120P PCI-5V_SLOT_120P
+5V
+5V +5V
-REQ0 R143 2.2K
CE11
1000u/6.3V CB114 CB113 CB110 CB130 CB131 CB127 CB39 CB57 CB63 CB103 CB58 CB64
.1u .1u .1u .1u .1u .1u .1u .1u .1u .1u .1u .1u +5V
2,18,20,21 A_D[31:0]
PCI-5V_SLOT_120P PCI-5V_SLOT_120P
-IRDY R191 2.2K -INTR_A R96 4.7K -P3REQ64 R241 2.2K -REQ2 R152 2.2K
-TRDY R192 2.2K -INTR_B R89 4.7K -P3ACK64 R242 2.2K -REQ3 R148 2.2K
CN1B
USB/RJ45/LED_PORT_8/8/4
L1 TD+
L2 TD-
L3 RX+
L4 +3.3VSUSLAN
L5 R68 R69
L6 RX- FB7
L7
L8 49.9 1% 49.9 1% SBK201209T-600Y-S
4 4
G5 CB24
G6 .1u
RD1
RD2
LD1
LD2
G7
G8
+3.3VSUSLAN
12,18,19,21 A_D[0:31]
RD+
+3.3V -12V +12V +3.3V RD-
+5V +5V
PCI5 R57 R41
B1 A1 330
-12V TRST 330
B2 TCK +12V A2 -ACT
B3
B4
GND TMS A3
A4
-SP100
Chassis GND
TDO TDI
B5 +5V +5V A5
B6 A6 -INTR_A
+5V INTA -INTR_A 12,17,18,19
-INTR_B B7 A7 -INTR_C -INTR_C 12,18,19
12,17,18,19,21 -INTR_B INTB INTC
-INTR_D B8 A8 49.9 1%
12,18,19 -INTR_D INTD +5V
B9 A9 RX- R66
PRSNT1 RESERVED RX+ R67
B10 RESERVED +5V A10
B11 PRSNT2 RESERVED A11
B12 A12 +3.3VSUS 49.9 1% CB26
GND GND .01u
B13 GND GND A13
3 B14 RESERVED 3.3V_AUX A14 3
1000p +3.3V
117
108
116
U24
10
30
43
68
92
-DRVSRST R350 33 -RAIDRST2 -R_PHIORDY R460 4.7K
49 60 RPDD0 C73 -R_SHIORDY R461 4.7K
AVCC
VCC
VCC
VCC
VCC
VCC
VCC
VCCIK
12,18,19,20 A_D0 BAD0 PBDSD0 RPDD1
12,18,19,20 A_D1 48 BAD1 PBDSD1 62
46 65 RPDD2 1000p
12,18,19,20 A_D2 BAD2 PBDSD2 RPDD3
4 45 70 4
12,18,19,20 A_D3 BAD3 PBDSD3 RPDD4
12,18,19,20 A_D4 44 BAD4 PBDSD4 72
42 74 RPDD5 -RPHIOW 1 2 -R_PHIOW -RSHIOW 1 2 -R_SHIOW
12,18,19,20 A_D5 BAD5 PBDSD5 RPDD6 -RPHIOR -R_PHIOR -RSHIOR -R_SHIOR
12,18,19,20 A_D6 41 BAD6 PBDSD6 78 3 4 RN87 3 4 RN88
39 80 RPDD7 RPDA2 5 6 33 8P4R R_PDA2 -RSHIORDY 5 6 33 8P4R -R_SHIORDY
12,18,19,20 A_D7 BAD7 PBDSD7 RPDD8 -RPHIORDY -R_PHIORDY RSDA1 R_SDA1
12,18,19,20 A_D8 37 BAD8 PBDSD8 79 7 8 7 8
36 75 RPDD9
12,18,19,20 A_D9 BAD9 PBDSD9 RPDD10
12,18,19,20 A_D10 35 BAD10 PBDSD10 73
33 71 RPDD11
12,18,19,20 A_D11 BAD11 PBDSD11 RPDD12
12,18,19,20 A_D12 32 BAD12 PBDSD12 66
31 63 RPDD13 RPDA1 1 2 R_PDA1 RSDA0 1 2 R_SDA0
12,18,19,20 A_D13 BAD13 PBDSD13 RPDD14 RPDA0 R_PDA0 -RSHCS0
12,18,19,20 A_D14 29 BAD14 PBDSD14 61 3 4 RN94 3 4 RN95 -R_SHCS0
28 59 RPDD15 -RPHCS1 5 6 33 8P4R -R_PHCS1 RSDA2 5 6 33 8P4R R_SDA2
12,18,19,20 A_D15 BAD15 PBDSD15 -RPHCS0 -R_PHCS0 -RSHCS1
18 7 8 7 8 -R_SHCS1
12,18,19,20 A_D16 BAD16
12,18,19,20 A_D17 17 BAD17
16 54 RPDA0 -RPDMACK R463 33 -R_PDMACK -RSDMACK R470 22 -R_SDMACK
12,18,19,20 A_D18 BAD18 PBDSA0 RPDA1
12,18,19,20 A_D19 14 BAD19 PBDSA1 55
13 52 RPDA2
12,18,19,20 A_D20 BAD20 PBDSA2
12,18,19,20 A_D21 12 BAD21
11 50 -DRVPRST
12,18,19,20 A_D22 BAD22 DRVPRST# -RPINTR
12,18,19,20 A_D23 9 BAD23 DINT0 56
5 58 RPDMARQ RPDD7 1 2 R_PDD7 RSDD10 1 2 R_SDD10
12,18,19,20 A_D24 BAD24 DMARQ0 -RPDMACK RPDD8 RSDD5 R_SDD5
4 57 3 4 RN19 R_PDD8 3 4 RN21
12,18,19,20 A_D25 BAD25 DMACK0# -RPHIORDY RPDD6 RSDD11 R_SDD11
3 69 5 6 33 8P4R R_PDD6 5 6 33 8P4R
12,18,19,20 A_D26 BAD26 PCHRDY# -RPHIOR RPDD9 RSDD4 R_SDD4
2 76 7 8 R_PDD9 7 8
12,18,19,20 A_D27 BAD27 PIORD# -RPHIOW RPDD3 RSDD12 R_SDD12
128 67 1 2 R_PDD3 1 2
12,18,19,20 A_D28 BAD28 PIOWR# -RPHCS0 RPDD12 RSDD3 R_SDD3
127 53 3 4 RN43 R_PDD12 3 4 RN22
12,18,19,20 A_D29 BAD29 PBCS0# -RPHCS1 RPDD2 RSDD13 R_SDD13
126 51 5 6 33 8P4R R_PDD2 5 6 33 8P4R
12,18,19,20 A_D30 BAD30 PBCS1# RPDD13 RSDD2 R_SDD2
3 125 7 8 R_PDD13 7 8 3
12,18,19,20 A_D31 BAD31 RPDD1 RSDD14 R_SDD14
1 2 R_PDD1 1 2
89 RSDD0 RPDD14 3 4 RN44 R_PDD14 RSDD1 3 4 RN24 R_SDD1
SBDSD0 RSDD1 RPDD0 33 8P4R R_PDD0 RSDD15 33 8P4R R_SDD15
12,18,19,20 C_-BE0 38 BCBE0# SBDSD1 94 5 6 5 6
26 96 RSDD2 RPDD15 7 8 R_PDD15 RSDD0 7 8 R_SDD0
12,18,19,20 C_-BE1 BCBE1# SBDSD2 RSDD3 RPDD5 RSDD8 R_SDD8
19 100 1 2 R_PDD5 1 2
12,18,19,20 C_-BE2 BCBE2# SBDSD3 RSDD4 RPDD10 RSDD7 R_SDD7
6 102 3 4 RN23 R_PDD10 3 4 RN20
12,18,19,20 C_-BE3 BCBE3# SBDSD4 RSDD5 RPDD4 RSDD9 R_SDD9
104 5 6 33 8P4R R_PDD4 5 6 33 8P4R
SBDSD5 RSDD6 RPDD11 R_PDD11 RSDD6 R_SDD6
SBDSD6 106 7 8 7 8
A_D24 7 111 RSDD7
IDSEL SBDSD7 RSDD8
12,18,19,20 -FRAME 20 BFRAME# SBDSD8 112
21 107 RSDD9
12,18,19,20 -IRDY BIRDY# SBDSD9 RSDD10
12,18,19,20 -TRDY 22 BTRDY# SBDSD10 105
23 103 RSDD11
12,18,19,20 -DEVSEL BDEVSEL# SBDSD11 RSDD12 RPDMARQ R_PDMARQ -RPINTR -R_PINTR
24 101 R422 22 R474 82
12,18,19,20 -STOP BSTOP# SBDSD12 RSDD13
12,18,19,20 PAR 25 PAR SBDSD13 97
95 RSDD14
SBDSD14 RSDD15 C82 R448 C90 R482
SBDSD15 90
120 5.6K 10K
4 PCICLK_RAID -IDERST CLK
122 20p 20p
5,23 -IDERST RESET# RSDA0
12,17,18,19,20 -INTR_B 121 INTA# SBDSA0 84
-RAIDGNT 123 85 RSDA1
12 -GNT5 -RAIDREQ PCIGNT# SBDSA1 RSDA2 RSDMARQ R_SDMARQ -RSINTR -R_SINTR
124 82 R421 22 R478 82
12 -REQ5 PCIREQ# SBDSA2
R311 1K 109
+3.3V ECLK66 -DRVSRST
DRVSRST# 115
86 -RSINTR C80 R447 C91 R487
PPDIAGN DINT1 RSDMARQ 5.6K 10K
113 PCBLID DMARQ1 88
SPDIAGN 114 87 -RSDMACK 20p 20p
SCBLID DMACK1# -RSHIORDY
2 SCHRDY 91 2
93 -RSHIOR
SIORD# -RSHIOW
98
GNDIK
SIOWR#
AGND
+5V 83 -RSHCS0
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
110
119
3 4 3 4
15
27
34
40
47
64
77
99
5 6 5 6
R_PDD5 7 8 R_PDD10 R_SDD5 7 8 R_SDD10
R_PDD4 9 10 R_PDD11 R_SDD4 9 10 R_SDD11
PDC20276 R_PDD3 11 12 R_PDD12 R_SDD3 11 12 R_SDD12
RAIDGNDPLL R_PDD2 13 14 R_PDD13 R_SDD2 13 14 R_SDD13
R_PDD1 15 16 R_PDD14 R_SDD1 15 16 R_SDD14
R_PDD0 17 18 R_PDD15 R_SDD0 17 18 R_SDD15
19 20 19 20
R_PDMARQ 21 22 R_SDMARQ 21 22
-R_PHIOW 23 24 -R_SHIOW 23 24
-R_PHIOR 25 26 -R_SHIOR 25 26
-R_PHIORDY 27 28 -R_SHIORDY 27 28
-R_PDMACK 29 30 -R_SDMACK 29 30
-R_PINTR 31 32 -R_SINTR 31 32
R_PDA1 33 34 PPDIAGN R_SDA1 33 34 SPDIAGN
+3.3V +3.3VRAID +3.3V +3.3VRAIDPLL R_PDA0 35 36 R_PDA2 R_SDA0 35 36 R_SDA2
-R_PHCS0 37 38 -R_PHCS1 -R_SHCS0 37 38 -R_SHCS1
FB33 FB29 39 40 39 40
SBK201209T-600Y-S SBK201209T-600Y-S
CT14 CM26 CB122 CB126 CT12 CM25 CB120 CB121 IDE_CNTR_2X20 IDE_CNTR_2X20
FANCTL2
FANCTL3
FAN2
FAN3 +3.3V
VIA HWMGND +12V
-SMI R37 0(opt) S7 R29 6.8K 1%
CPU_D+ 7,25
S8 R27 47K 1% R26 HWMGND
24 IO_BEEP CPU_D- 7,25
+12VIN V 10K 1%
26 MSI
R28 10K HWMGND +12VIN
26 MSO
26 JAB2 R30 10K
VCORE
26 JBB2 VREF
HWMVCC SIO_VCC
26 JACY
VTIN1 HWMVCC FB3
26 JBCY SBK201209T-600Y-S
26 JBCX VTIN2
4
26 JACX CT5 C4 4
.1u
26 JBB1 10u/10V HWMGND FB4
26 JAB1 SBK201209T-600Y-S
VIA For VFIR function
128
127
126
125
124
123
122
121
120
119
118
117
116
115
114
113
112
111
110
109
108
107
106
105
104
103
R9 0(opt) ITMON_OFF
+3.3V U4
R61 4.7K VREF
JAB1/P12/GP10
JBB1/P13/GP11
JACX/P14/GP12
JBCX/P15/GP13
JBCY/P16/GP14
JACY/GP15
JBB2/GP16
JAB2/GP17
FANOUT1/GP20
FANOUT2/GP21
FANIO2
UIC5
UIC4
UIC3
UIC2
UIC1
MSI/OVFAN#(GP51)/WDTO
OVTEMP#/SMI#(W)
MSO/OVOLT#(PLED)/DSEL1(GP50)
BEEP
GNDA
DTDN
DTDP
VCCA
FANIO1/DTEST
VREF
RT2
t
DRVDEN0 1 102 R12 10K 1% HWMGND
-INDEX DSEL0# PLED/ITMOFF/GP22//VBAT
2 INDEX# COPEN#GP23/ATEST 101
SIO_VCC -MOA 3 100 IRRX1 VTIN1
-DSB MTRA# IRRX1/GP24//CIRRX RT_103JT-025
4 DRVB# GNDD//VSB 99
5 98 VIA
-DSA VCC SMI#//PME# R3 RT1
6 DRVA# MEMW#/GP25 97 -SIO_MEMW
t
-MOB 7 96 -SIO_MEMR R13 30K
-DIR MTRB# MEMR#/GP26 0(opt)
8 DIR# ROMCS#/GP27 95 -SIO_ROMCS
-STEP 9 94 IOXD0 VTIN2
-WDATA STEP# XD0/GP30 RT_103JT-025
10 WDATA# XD1/GP31 93 IOXD1
-PWE 11 92 IOXD2
-TRK0 WGATE# XD2/GP32 IOXD3 R2 0(opt)
12 TRCAK0# XD3/GP33 91 V -SMI 6,14
-WPT 13 90
-RDATA WPT# GNDD IOXD4
14 RDATA# XD4/GP34 89
-HDSEL 15 88 IOXD5 +12V
-DSKCHG HEAD# XD5/GP35 IOXD6
16 DSKCHG# XD6/GP36 87
17 86 IOXD7 U5 R94 4.7K
4,27 SIOCLK48 CLKIN XD7/GP37
18 85 12 13 IOXD0
E
GND VT1211 XA0/GP40 A0 D0 IOXD1 +3.3V
3
4 PCICLKSIO PCICLKSIO 19 PCICLK XA1/GP41 84 11 A1 D1 14 3
C
LAD3 23 80 7 19 IOXD5 R100
14,27 LAD3 LAD3 XA5/GP45 A5 D5
LAD2 24 79 6 20 IOXD6 +5V 10K
D
14,27 LAD2 LAD2 XA6/GP46 A6 D6
LAD1 25 78 5 21 IOXD7 CE6
14,27 LAD1 LAD1 XA7/GP47 A7 D7
LAD0 26 77 27 FANCTL2 R93 1K G Q3
14,27 LAD0 LAD0 XA8/GP50 A8 33u/10V
-LFRAME 27 76 26 24 -SIO_MEMR NDS7002A
14,27 -LFRAME LFRAME# XA9/GP51 A9 OE
5,13,17,18,19,20,27 -PCIRSTX -PCIRSTX 28 75 23 31 -SIO_MEMW R15 4.7K
LRESET# VCC A10 WE
S
25 P_SLCT 29 74 25 22 -SIO_ROMCSR16 4.7K
SLCT XA10/GP52 A11 CE R14 4.7K
25 P_PE 30 PE XA11/GP53 73 4 A12
25 P_BUSY 31 BUSY XA12/GP54 72 28 A13
32 71 29 +5V +5V FAN1
25 P_-ACK ACK# XA13/GP55 A14
25 P_-ERR 33 ERR# XA14/GP56 70 3 A15 VCC 32 1
25 P_-SLIN 1 2 34 SLIN# XA15/GP57 69 2 A16 2
3 4 RN3 35 68 30 R81 1K 3
25 P_PRD7 33 8P4R 36 PD7 XA16/GP60 A17
5 6 67 1 16
GP72/SMBCK/SOUT2
GP71/SMBDT/DCD2#
GP75/VID2/RTS2#
38 65 IRTX SST39SF020-90-4C-PH
GP73/VID0/SIN2
+12V
SOUT1
DCD1#
DSR1#
DTR1#
CTS1#
RTS1#
GNDD
AFD#
STB#
INIT#
IRRX
RL1#
SIN1
VCC
PD3
PD2
PD1
PD0
E
+3.3V
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
R491 1K B Q34
2
MMBT3906 2
25 P_PRD4 1 2 IRRX
C
3 4 RN2 R512
25 P_PRD3 33 8P4R 10K
5 6
D
25 P_PRD2 -RI2 25
7 8 +5V
25 P_PRD1 -DCD2 25
1 2 SOUT2 SOUT2 R19 4.7K(opt) FANCTL3 R501 1K G Q36 CE36
25 P_PRD0 TD2 25
3 4 RN1 NDS7002A
25 P_-INIT 33 8P4R 33u/10V
25 P_-AFD
5 6 RD2 25 For Winbond 48M strapping
S
25 P_-STB 7 8 -DTR2 25
25 -CTS1 -RTS2 25
25 -DSR1 -DSR2 25
+5V FAN3
25 -RTS1 -CTS2 25
+5V 1
25 -DTR1
25 RD1 2
R72 1K R485 1K 3
25 TD1 R199 1K
25 -DCD1 FAN3 D8 FDLL4148
SIO_VCC
1 2
RN12
SYS FAN
25 -RI1 3 4
5 6 1K 8P4R FAN_CNTR_1X3
FDD1 7 8
+3.3V V SIO_VCC For CIR
R58 0 1 2 DRVDEN0 +5V JIR1 fuction.
+5V Base address 3 4 1 2
R53 0(OPT) 0:4Eh/4Fh Base address 5 6 IRRX1 3 4
W 1:2Eh/2Fh +3.3V 7 8 -INDEX IRRX 5 6
R33 10K(OPT)-RTS1 R32 10K 9 10 -MOA 7 8
11 12 -DSB IRTX 9 10 ITMON_OFF
0:Normal Opreation 1:Test Mode 13 14 -DSA V
1
R25 2.2K -DTR1 R24 10K(OPT) 15 16 -MOB HEADER_2X5 1
PRIMARY
4 4
IDE3
-IDERST1 1 2
PDD_7 3 4 PDD_8
1 2 PDD_10 1 2 PDD_REQ PDD_6 5 6 PDD_9
13 PDD10 PDD_5 13 PDDREQ PDD_5 PDD_10
3 4 RN50 3 4 RN47 P_IORDY 7 8
13 PDD5 PDD_9 13 PIORDY PDD_15 PDD_4 PDD_11
5 6 22 8P4R 5 6 22 8P4R 9 10
13 PDD9 PDD_6 13 PDD15 PDD_0 PDD_3 PDD_12
13 PDD6 7 8 13 PDD0 7 8 11 12
1 2 PDD_8 PDD_2 13 14 PDD_13
13 PDD8 PDD_7 PDD_1 PDD_14
3 4 RN75 15 16
13 PDD7 IRQ_14 PD_A1 PDD_0 PDD_15
5 6 22 8P4R 1 2 17 18
13 IRQ14 IRQ_15 13 PDA1 -PDD_ACK
7 8 3 4 RN46 19 20
13 IRQ15 PDD_12 13 -PDDACK -PD_IOR PDD_REQ
1 2 5 6 22 8P4R 21 22
13 PDD12 PDD_3 13 -PDIOR -PD_IOW -PD_IOW
3 4 RN49 7 8 23 24
13 PDD3 PDD_11 13 -PDIOW -PD_IOR
5 6 22 8P4R 25 26
13 PDD11 PDD_4 P_IORDY CSEL_1
7 8 27 28 R498 470
13 PDD4 PDD_14 -PD_CS1 -PDD_ACK
13 PDD14 1 2 13 -PDCS1 1 2 29 30
3 4 RN48 PDD_1 3 4 RN45 -PD_CS3 IRQ_14 31 32
13 PDD1 PDD_13 13 -PDCS3 PD_A0 PD_A1
5 6 22 8P4R 5 6 22 8P4R 33 34
13 PDD13 PDD_2 13 PDA0 PD_A2 PD_A0 PD_A2 PIDE33/-66 13
13 PDD2 7 8 13 PDA2 7 8 35 36
-PD_CS1 37 38 -PD_CS3
-HD_LED1 39 40 R497
15K
These resistor should placed near South Bridge IDE_CNTR_2X20
3 3
SECONDARY
-IDERST
R481
R518
22
22
-IDERST1
-IDERST2
IDE4
5,21 -IDERST -IDERST2 1 2
SDD_7 3 4 SDD_8
1 2 SDD_7 SDA1 1 2 SD_A1 SDD_6 5 6 SDD_9
13 SDD7 SDD_6 13 SDA1 -SDD_ACK SDD_10
3 4 RN86 -SDDACK 3 4 RN84 SDD_5 7 8
13 SDD6 13 -SDDACK -SDIOR -SD_IOR SDD_11
5 6 22 8P4R SDD_5 5 6 22 8P4R SDD_4 9 10
13 SDD5 13 -SDIOR -SDIOW -SD_IOW SDD_12
7 8 SDD_4 7 8 SDD_3 11 12
13 SDD4 SDD_3 13 -SDIOW SDD_13
1 2 SDD_2 13 14
13 SDD3 SDD_2 SDD_14
3 4 RN54 SDD_1 15 16
13 SDD2 SDD_1 SDD_15
5 6 22 8P4R 1 2 SDD_0 17 18
13 SDD1 SDD_0
7 8 3 4 RN52 19 20
13 SDD0 SDD_15 S_IORDY SDD_REQ
1 2 5 6 22 8P4R 21 22
13 SDD15 SDD_14 13 SIORDY SDDREQ SDD_REQ -SD_IOW
3 4 RN85 7 8 23 24
13 SDD14 SDD_13 13 SDDREQ -SD_IOR
5 6 22 8P4R 25 26
13 SDD13 SDD_12 S_IORDY CSEL_2
7 8 27 28 R506 470
13 SDD12 -SDCS1 -SD_CS1 -SDD_ACK
1 2 SDD_11 1 2 29 30
13 SDD11 13 -SDCS1 -SD_CS3 IRQ_15
3 4 RN53 SDD_10 -SDCS3 3 4 RN51 31 32
13 SDD10 SDD_9 13 -SDCS3 SDA2 SD_A2 SD_A1
2
5 6 22 8P4R 5 6 22 8P4R 33 34 2
IDE_CNTR_2X20
These resistor should placed near South Bridge
+5V +5V
R507 R484
4.7K 4.7K +3.3V
-HD_LED1 D7 FDLL4148 P_IORDY R389 4.7K PDDREQ R384 5.6K PDD_7 R455 10K
-HD_LED 5
-HD_LED2 D9 FDLL4148
S_IORDY R425 4.7K SDDREQ R403 5.6K SDD_7 R457 10K
1 1
PS2 USB
+5V
PS2
+5V MINI-SMDC110
R71 470K
12 -OC0
4
PS1 R70 FB14 4
2
4
6
8
MINI-SMDC110 560K
RN101 PS2-KBMS1A SBK201209T-600Y-S
4.7K 8P4R G1
4 6 CN1A
1
3
5
7
2 G1 G3
G2 1 5
R528 22KB_DT 1 2 6
12 KB_DATA 12 USBDT0- USBDT1- 12,27
3 5 KB_CK 12 USBDT0+ 3 7 USBDT1+ 12,27
G3 4 8
G2 G4
R527 22 PS2_PORT_6X2 C14 CB20 CB23
12 KB_CLK
USB/RJ45/LED_PORT_8/8/4
10u/10V .1u .1u
CP42
CP44
180p(OPT) CB17
180p(OPT) PS2-KBMS1B
.1u G4
10 12 +5V +5V
8
560K 560K
FB24 FB23
CP43 CP45
SBK201209T-600Y-S SBK201209T-600Y-S
180p(OPT) 180p(OPT)
JUSB2 JUSB1
1 2 1 2
12 USBDT2- 3 4 USBDT3- 12 12 USBDT4- 3 4 USBDT5- 12
12 USBDT2+ 5 6 USBDT3+ 12 12 USBDT4+ 5 6 USBDT5+ 12
7 8 7 8
9 10 9 10
CB94 C57 CB93 C56
HEADER_2X5 HEADER_2X5
.1u 10u/10V .1u 10u/10V
+5V
C
BUZZ1
1 B R399 1K R387 10K D3 FDLL4148
-XRI2 25
2
2 R34 68 2
Q25 D4 C77
C
E
BUZZER_12PD05 CM10 MMBT3904 R388
B R20 2.2K 2K FDLL4148 4.7u/16V
1u
SPEAK 14,26,27 RING IN
Q1
E
MMBT3904
R18 0 (OPT) +5VSUS
IO_BEEP 22
WOL1
1
C
2
B R413 10K 3 WAKE ON LAN
Q27 WAFER_CNTR_1X3
ATX MAINBOARD DRILLS
E
MMBT3904
2 7 MMBT3904 100K 2
3
4
6
5
3
4
6
5
3 6 3
4
6
5
3 WAKE ON MODEM
4 5
CB165 WAFER_CNTR_1X3
1 1
9
1000p
9
C HKT400ARL 0.1
20 VCC V+ 1
19 2 RIN11 26 G1 1 2
22 -DCD1 ROUT1 RIN1 RIN21 22 P_PRD3
18 3 31 3 4 RN6
22 -DSR1 ROUT2 RIN2 RIN31 P_SLCT 22 P_-INIT
17 4 27 13 CP17 180p 5 6 4.7K 8P4R
22 RD1 ROUT3 RIN3 DOUT11 22 P_PRD2
22 -RTS1 16 DIN1 DOUT1 5 32 25 22 P_PRD1 7 8
15 6 DOUT21 28 12 P_PE CP18 180p
22 TD1 DIN2 DOUT2 RIN41
22 -CTS1 14 ROUT4 RIN4 7 33 24 22 P_-ERR 1 2
13 8 DOUT31 29 11 P_BUSY CP19 180p 3 4 RN7
22 -DTR1 DIN3 DOUT3 -XRI1 22 P_PRD0
12 9 34 23 5 6 4.7K 8P4R
22 -RI1 ROUT5 RIN5 P_-ACK 22 P_-AFD
11 10 30 10 CP20 180p 7 8
GND V- -XRI1 24 22 P_-STB
22
GD75232 CP5 100p 9 P_PRD7 CP21 180p
CP13 100p 21 +5V
-12V CP6 100p G4 8 P_PRD6 CP22 180p
CP14 100p 20 R42 4.7K
P_PRD5 22 P_SLCT
CP7 100p G5 7 CP23 180p
CP15 100p 19 1 2
P_PRD4 22 P_PE
CP8 100p G6 6 CP24 180p 3 4 RN4
COM2 +5V +12V CP16 100p 18
22
22
P_BUSY
P_-ACK 5 6 4.7K 8P4R
5 P_PRD3 CP26 180p 7 8
P_-SLIN 22 P_PRD7
U8 17 CP25 180p
20 1 4 P_PRD2 CP28 180p 1 2
VCC V+ RIN12 P_-INIT 22 P_PRD6
19 2 35 16 CP27 180p 3 4 RN5
22 -DCD2 ROUT1 RIN1 RIN22 P_PRD1 22 P_PRD5
18 3 40 3 CP29 180p 5 6 4.7K 8P4R
22 -DSR2 ROUT2 RIN2 RIN32 P_-ERR 22 P_PRD4
17 4 36 15 CP30 180p 7 8
22 RD2 ROUT3 RIN3 DOUT12 P_PRD0 22 P_-SLIN
16 5 41 2 CP31 180p
22 -RTS2 DIN1 DOUT1 DOUT22 P_-AFD
15 6 37 14 CP32 180p
22 TD2 DIN2 DOUT2 RIN42 P_-STB
14 7 42 1 CP33 180p
3
22 -CTS2 ROUT4 RIN4 DOUT32
3
2 2
+3.3V
+3.3V
C60
1 1
JCDIN1
1 R43 1K CD_L
2
3
4 R35 1K CD_R
+3.3V AVDD5 VDD5
HEADER_1X4 U3
R40 R39 FB5 1 25 FB2
47K 47K TB321611U520 DVDD1 AVDD1 TB321611U520
9 DVDD2 AVDD2 38
CT8 CB13 CT9 CB14 CB16 CB11 CB4 CT7
CD_IN CD_GND
4
10u/10V .1u 10u/10V .1u .1u 4 26 .1u .1u 10u/10V 4
22 JACX
R50 2K 11
22 JBCX
4 R79 10K
22 MSO 12
5 -PRI_DN
-PRI_DN 27
R47 2K 13 J1
22 JBCY
R46 2K 6 +5V 1
22 JACY
14 U11 2
22 JBB2
22 JAB2 7 5 1
22 MSI 15 2 BITCLK
8 R83 33 4 3
13,27 BIT_CLK
CP34 100p CP36 .01u
CP35 100p CP37 .01u G1 NC7SZ125 ON : On-board Codec is used
CP41 100p CP39 .01u CB18 OFF : ACR Slot is used
CP40 100p CP38 .01u .1u AUDIO/GAME_PORT_15/15
GND
4.7u/16V .1u 4.7u/16V .1u
AMS1117-5V
G
1 1
LINEOUTR CE4 220u/10V FB10 16 AUDIO_GAME1B
TB321611U520 17
19
LINEOUTL CE3 220u/10V FB9 20
TB321611U520
C9 C8
18
AUDIO/GAME_PORT_15/15 TOPSTAR TECHNOLOGIES, INC.
470p 470p Title
FB12 AC'97 CODEC & AUDIO/GAME PORT
TB321611U520
Size Document Number Rev
GND_LOUT C HKT400ARL 0.1
R88
AMR1 4.7K
B1 A1 R74 0
AUDIO_MUTE AUDIO_PWRDN
B2 GND MONO_PHONE A2 PHONE 26
14,24,26 SPEAK B3 MONO_OUT/PC_BEEP RESERVED A3
4 B4 A4 VCC 4
RESERVED RESERVED
B5 RESERVED RESERVED A5
26 -PRI_DN B6 PRIMARY_DN GND A6
B7 -12V +5VDUAL/+5VSB A7
B8 A8 R84 0(OPT) PR20 1
GND USB_OC -OC1 12,24
B9 +12V GND A9
B10 A10 R92 0(OPT)
GND USB+ USBDT1+ 12,24
B11 A11 R98 0(OPT)
+5VD USB- USBDT1- 12,24
PD1
1
AGND_AMR B12 A12 AGND_AMR 1N4148
+3.3V GND GND R119 0
B13 RESERVED S/P-DIF_IN A13
B14 RESERVED GND A14
B15 +3.3VD +3.3VDUAL/+3.3VSB A15
B16 A16 +5V VCC
GND GND VRM25
13,26 SDOUT B17 AC97_SDATA_OUT AC97_SYNC A17 SYNC 13,26
13,26 -ACRST B18 AC97_RESET GND A18
R147 22 B19 A19 R151 22
13 SDIN3 AC97_SDATA_IN3 AC97_SDATA_IN1 SDIN1 13
B20 A20 PR3 30K + EC1
R160 22 GND GND R159 22 1500UF
13 SDIN2 B21 AC97_SDATA_IN2 AC97_SDATA_IN0 A21 SDIN0 13,26
B22 A22 BOOT25
GND GND R165 22
B23 AC97_MSTRCLK AC97_BITCLK A23 BIT_CLK 13,26
3
PQ2
AMR_SLOT_46P PU1 AP60L02H 0.1UF +3.3_SEC
5
PC3
7 1 1
VCC
COMP BOOT HG25 PR4 2.2
UGATE 2
8 PL1
PR1 82K PHASE PHASE25 3.3U
2
3 3
PC6 12PF
GND
+5VSUSAMR +5VSUS 6 4 LG25 R224
FB LGATE
3
PQ1 PR2 4.7 PC1 0.1UF PC2
FB16 ISL6520 AP60L02H NC 3.32K 0.1UF
SBK201209T-600Y-S
3
RFB25
SDIN1 R142 4.7K 1
PC5
SDIN2 R169 4.7K +3.3VSUSAMR +3.3VSUS 470PF R225
2
SDIN3 R128 4.7K FB17 1K
SBK201209T-600Y-S PC4 4700PF FB25
FB15
SBK201209T-600Y-S
AGND_AMR
V_DRAM
13 NB_FID3
1
2
R392
13 NB_FID2
+3.3V
13 NB_FID1 PJ2
2
10K HEADER_1X2 2
NS
13 NB_FID0
U30A
14
G
74HC125
S D 2 3 +3.3_SEC PD21 +3.3V
6 FID0 OC_FID0 7
Q23
NDS7002A 3
1
+3.3V 2
U30B
14
G
74HC125
S D 5 6 TO263 DIOD
6 FID1 OC_FID1 7
Q24
1
2
NDS7002A
4
+3.3V
PJ1
U30C
14
G
74HC125
HEADER_1X2
6 FID2 S D 12 11 OC_FID2 7 NS
Q26
NDS7002A
13
+3.3V
U30D
14
G
74HC125
6 FID3 S D 9 8 OC_FID3 7
Q28
NDS7002A
10
8
7
6
5
1 SW2 DIP-SW_ESD104E(OPT) 1
ON
1
J2 2 Title
TV ENCODER
Size Document Number Rev
C 0.1
HKT400ARL
Date: Monday, September 15, 2003 Sheet 27 of 27
A B C D E