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MultiPlexer:
library IEEE;
use IEEE.std_logic_1164.all;
entity mux8bit is
port(A,B : in std_logic_vector(7 downto 0);
C : std_logic;
O: out std_logic_vector(7 downto 0));
End mux8bit;
Architecture MyMux of mux8bit is
Begin
With C select
O <= A when ‘0’,
B when ‘1’,
“xxxxxxxx” others;
End mymux
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Sommatore:
Library IEEE;
use IEEE.std_logic_1164.all;
entity rca is
port( D, E : in std_logic_vector(7 downto 0);
O : out std_logic_vector(8 downto 0));
End rca;
Architecture myrca of rca is
signal g,p : std_logic_vector(8 downto 0);
signal c : std_logic_vector(9 downto 0);
Begin
G(7 downto 0)<= d and e;
P(7 downto 0) <= d xor e;
g(8)<=g(7);
p(8)<=p(7);
c(0)<=’0’;
C(8 downto 1) <= g or p and c(8 downto 0);
O <= p xor c(8 downto 0);
End myrca;
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Main

library IEEE;
use IEEE.std_logic_1164.all;
entity main is
port(A, B : in std_logic_vector(7 downto 0);
C : in std_logic_vector(1 downto 0);
O : out std_logic_vector(8 downto0));
End main
Architecture MyMain o main
Signal d, notd, x, y : std_logic_vector(7 downto 0);
component rca is
port( D, E : in std_logic_vector(7 downto 0);
O : out std_logic_vector(8 downto 0));
End component
Component mymux8bit is
port(A,B : in std_logic_vector(7 downto 0);
C : std_logic;
O: out std_logic_vector(7 downto 0));
End component
Begin
Mux1: mux8bit port map(A,B,C(0),D);
notd<=not d;
mux2: mux8bit port map(d,notd,c(1),x);
mux3: mux8bit port map(“00000001”, “00000100”,c(1), y);
sum: rca port map(x,y,o);
End mymain
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