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Pic18F8722 Family Data Sheet: 64/80-Pin, 1-Mbit, Enhanced Flash Microcontrollers With 10-Bit A/D and Nanowatt Technology
Pic18F8722 Family Data Sheet: 64/80-Pin, 1-Mbit, Enhanced Flash Microcontrollers With 10-Bit A/D and Nanowatt Technology
Data Sheet
64/80-Pin, 1-Mbit,
Enhanced Flash Microcontrollers
with 10-Bit A/D and nanoWatt Technology
• Microchip believes that its family of products is one of the most secure families of its kind on the market today, when used in the
intended manner and under normal conditions.
• There are dishonest and possibly illegal methods used to breach the code protection feature. All of these methods, to our
knowledge, require using the Microchip products in a manner outside the operating specifications contained in Microchip’s Data
Sheets. Most likely, the person doing so is engaged in theft of intellectual property.
• Microchip is willing to work with the customer who is concerned about the integrity of their code.
• Neither Microchip nor any other semiconductor manufacturer can guarantee the security of their code. Code protection does not
mean that we are guaranteeing the product as “unbreakable.”
Code protection is constantly evolving. We at Microchip are committed to continuously improving the code protection features of our
products. Attempts to break Microchip’s code protection feature may be a violation of the Digital Millennium Copyright Act. If such acts
allow unauthorized access to your software or other copyrighted work, you may have a right to sue for relief under that Act.
External Bus
8/16-Bit
Timers
10-Bit CCP/
Device Flash # Single-Word SRAM EEPROM I/O A/D ECCP Master
(ch) (PWM) SPI
(bytes) Instructions (bytes) (bytes) I2C™
64-Pin TQFP
RD6/PSP6/SCK2/SCL2
RD5/PSP5/SDI2/SDA2
RE7/ECCP2(1)/P2A(1)
RD4/PSP4/SDO2
RD7/PSP7/SS2
RE2/CS/P2B
RD0/PSP0
RD1/PSP1
RD2/PSP2
RD3/PSP3
RE3/P3C
RE5/P1C
RE4/P3B
RE6/P1B
VDD
VSS
64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49
RE1/WR/P2C 1 48 RB0/INT0
RE0/RD/P2D 2 47 RB1/INT1
RG0/ECCP3/P3A 3 46 RB2/INT2
RG1/TX2/CK2 4 45 RB3/INT3
RG2/RX2/DT2 5 44 RB4/KBI0
RG3/CCP4/P3D 6 43 RB5/KBI1/PGM
RG5/MCLR/VPP 7 RB6/KBI2/PGC
PIC18F6527 42
RG4/CCP5/P1D 8 PIC18F6622 41 VSS
VSS 9 PIC18F6627 40 OSC2/CLKO/RA6
VDD 10 PIC18F6722 39 OSC1/CLKI/RA7
RF7/SS1 11 38 VDD
RF6/AN11 12 37 RB7/KBI3/PGD
RF5/AN10/CVREF 13 36 RC5/SDO1
RF4/AN9 14 35 RC4/SDI1/SDA1
RF3/AN8 15 34 RC3/SCK1/SCL1
RF2/AN7/C1OUT 16 33 RC2/ECCP1/P1A
17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32
RF0/AN5
RA2/AN2/VREF-
RA1/AN1
RA0/AN0
RC6/TX1/CK1
RA4/T0CKI
RC7/RX1/DT1
RA3/AN3/VREF+
RC0/T1OSO/T13CKI
AVSS
VSS
RA5/AN4/HLVDIN
RF1/AN6/C2OUT
RC1/T1OSI/ECCP2(1)/P2A(1)
AVDD
VDD
Note 1: The ECCP2/P2A pin placement is determined by the CCP2MX Configuration bit.
80-Pin TQFP
RD6/AD6/PSP6/SCK2/SCL2
RE7/AD15/ECCP2(1)/P2A(1)
RD5/AD5/PSP5/SDI2/SDA2
RD4/AD4/PSP4/SDO2
RD7/AD7/PSP7/SS2
RE2/AD10/CS/P2B
RE5/AD13/P1C(2)
RE4/AD12/P3B(2)
RE6/AD14/P1B(2)
RE3/AD11/P3C(2)
RD0/AD0/PSP0
RD1/AD1/PSP1
RD2/AD2/PSP2
RD3/AD3/PSP3
RH0/A16
RH1/A17
RJ0/ALE
RJ1/OE
VDD
VSS
80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61
RH2/A18 1 60 RJ2/WRL
RH3/A19 2 59 RJ3/WRH
RE1/AD9/WR/P2C 3 58 RB0/INT0
RE0/AD8/RD/P2D 4 57 RB1/INT1
RG0/ECCP3/P3A 5 56 RB2/INT2
RG1/TX2/CK2 6 55 RB3/INT3/ECCP2(1)/P2A(1)
RG2/RX2/DT2 7 54 RB4/KBI0
RG3/CCP4/P3D 8 53 RB5/KBI1/PGM
RG5/MCLR/VPP 9 PIC18F8527 52 RB6/KBI2/PGC
RG4/CCP5/P1D VSS
10 PIC18F8622 51
VSS 50 OSC2/CLKO/RA6
11 PIC18F8627
VDD 12 49 OSC1/CLKI/RA7
PIC18F8722
RF7/SS1 13 48 VDD
RF6/AN11 14 47 RB7/KBI3/PGD
RF5/AN10/CVREF 15 46 RC5/SDO1
RF4/AN9 16 45 RC4/SDI1/SDA1
RF3/AN8 17 44 RC3/SCK1/SCL1
RF2/AN7/C1OUT 18 43 RC2/ECCP1/P1A
RH7/AN15/P1B(2) 19 42 RJ7/UB
RH6/AN14/P1C(2) 20 41 RJ6/LB
21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40
RF1/AN6/C2OUT
RF0/AN5
RJ4/BA0
RJ5/CE
RA2/AN2/VREF-
RC1/T1OSI/ECCP2(1)/P2A(1)
RC7/RX1/DT1
RC6/TX1/CK1
RC0/T1OSO/T13CKI
RA3/AN3/VREF+
RA5/AN4/HLVDIN
RH5/AN13/P3B(2)
RH4/AN12/P3C(2)
AVDD
RA1/AN1
RA0/AN0
VDD
RA4/T0CKI
AVSS
VSS
Note 1: The ECCP2/P2A pin placement is determined by the CCP2MX Configuration bit and Processor mode settings.
2: P1B, P1C, P3B and P3C pin placement is determined by the ECCPMX Configuration bit.
Errata
An errata sheet, describing minor operational differences from the data sheet and recommended workarounds, may exist for current
devices. As device/documentation issues become known to us, we will publish an errata sheet. The errata will specify the revision
of silicon and revision of document to which it applies.
To determine if an errata sheet exists for a particular device, please check with one of the following:
• Microchip’s Worldwide Web site; http://www.microchip.com
• Your local Microchip sales office (see last page)
When contacting a sales office, please specify which device, revision of silicon and data sheet (include literature number) you are
using.
Data Bus<8>
Table Pointer<21>
PORTA
Data Latch
inc/dec logic 8 8 RA0:RA7(1)
Data Memory
PCLATU PCLATH (3.9 Kbytes)
21
20 Address Latch
PCU PCH PCL
Program Counter 12 PORTB
Data Address<12>
RB0:RB7(1)
31-Level Stack
Address Latch 4 12 4
Program Memory BSR FSR0 Access
STKPTR Bank
(48/64/96/128 FSR1
Kbytes) FSR2 12
PORTC
Data Latch
inc/dec RC0:RC7(1)
8 logic
Table Latch
8
Instruction State Machine
Decode and Control Signals
Control
PRODH PRODL PORTE
RE0:RE7(1)
8 x 8 Multiply
3
8
OSC1(3) Internal Power-up BITOP W
Oscillator Timer 8
Block 8 8
(3) Oscillator
OSC2
INTRC Start-up Timer PORTF
8 8
T1OSI Oscillator Power-on
Reset RF0:RF7(1)
8 MHz ALU<8>
T1OSO Oscillator Watchdog
Timer 8
Precision
Single-Supply Brown-out Band Gap
MCLR(2) Reset
Programming Reference
In-Circuit Fail-Safe PORTG
VDD, VSS Debugger Clock Monitor
RG0:RG5(1)
BOR ADC
10-bit Timer0 Timer1 Timer2 Timer3 Timer4 Comparators
HLVD
PORTA
Table Pointer<21> Data Latch
8 8 RA0:RA7(1)
Data Memory
inc/dec logic PCLATU PCLATH (3.9 Kbytes)
21 20 Address Latch
PCU PCH PCL PORTB
Program Counter 12 RB0:RB7(1)
Data Address<12>
31-Level Stack
Address Latch 4 12 4
System Bus Interface
8 inc/dec
logic PORTD
Table Latch
RD0:RD7(1)
ROM Latch
Address
Decode
Instruction Bus <16>
PORTE
IR
RE0:RE7(1)
AD15:AD0, A19:A16
(Multiplexed with PORTD, 8
PORTE and PORTH)
BITOP W
8 8 PORTG
8
RG0:RG5(1)
OSC1(3) Internal Power-up
Oscillator 8 8
Timer
Block
OSC2(3) Oscillator ALU<8>
INTRC Start-up Timer PORTH
T1OSI Oscillator Power-on 8
Reset RH0:RH7(1)
8 MHz
T1OSO Oscillator Watchdog
Timer
Precision
Single-Supply Brown-out Band Gap
MCLR(2) Reset PORTJ
Programming Reference
In-Circuit Fail-Safe RJ0:RJ7(1)
VDD, VSS Clock Monitor
Debugger
BOR ADC
10-bit Timer0 Timer1 Timer2 Timer3 Timer4 Comparators
HLVD
CEXT Loop
PIC18FXXXX Filter
VSS
OSC2/CLKO
FOSC/4
MUX
20 pF ≤ CEXT ≤ 300 pF
CEXT
PIC18FXXXX
VSS
RA6 I/O (OSC2)
÷4 VCO
CLKO SYSCLK
MUX
The PLL is available when the device is configured to Tuning the INTOSC source requires knowing when to
use the internal oscillator block as its primary clock make the adjustment, in which direction it should be
source (FOSC<3:0> = 1001 or 1000). Additionally, the made and in some cases, how large a change is
PLL will only function when the selected output fre- needed. Three compensation techniques are discussed
quency is either 4 MHz or 8 MHz (OSCCON<6:4> = 111 in Section 2.6.5.1 “Compensating with the
or 110). If both of these conditions are not met, the PLL EUSART”, Section 2.6.5.2 “Compensating with the
is disabled and the PLLEN bit remains clear (writes are Timers” and Section 2.6.5.3 “Compensating with the
ignored). CCP Module in Capture Mode” but other techniques
may be used.
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
Note 1: Available only in certain oscillator configurations; otherwise, this bit is unavailable and reads as ‘0’. See
Section 2.6.4 “PLL in INTOSC Modes” for details.
PIC18F6527/6622/6627/6722/8527/8622/8627/8722
Primary Oscillator LP, XT, HS, RC, EC
OSC2
1 MHz Clock
Control
MUX
8 MHz 100
Source 500 kHz
8 MHz 011
(INTOSC) 250 kHz
INTRC 010 FOSC<3:0> OSCCON<1:0>
Source 125 kHz
001
1 31 kHz Clock Source Option
31 kHz (INTRC) 000 for other Modules
0
OSCTUNE<7>
WDT, PWRT, FSCM
and Two-Speed Start-up
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
T1OSI 1 2 3 n-1 n
CPU
Clock
Peripheral
Clock
Program
Counter PC PC + 2 PC + 4
FIGURE 3-2: TRANSITION TIMING FROM SEC_RUN MODE TO PRI_RUN MODE (HSPLL)
Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3
T1OSI
OSC1
TOST(1) TPLL(1)
1 2 n-1 n
PLL Clock
Output
Clock
Transition(2)
CPU Clock
Peripheral
Clock
Program PC PC + 2 PC + 4
Counter
Note1:TOST = 1024 TOSC; TPLL = 2 ms (approx). These intervals are not shown to scale.
2: Clock transition typically occurs within 2-4 TOSC.
3.2.3 RC_RUN MODE This mode is entered by setting the SCS1 bit to ‘1’.
Although it is ignored, it is recommended that the SCS0
In RC_RUN mode, the CPU and peripherals are
bit also be cleared; this is to maintain software compat-
clocked from the internal oscillator block using the
ibility with future devices. When the clock source is
INTOSC multiplexer. In this mode, the primary clock is
switched to the INTOSC multiplexer (see Figure 3-3),
shut down. When using the INTRC source, this mode
the primary oscillator is shut down and the OSTS bit is
provides the best power conservation of all the Run
cleared. The IRCF bits may be modified at any time to
modes, while still executing code. It works well for user
immediately change the clock speed.
applications which are not highly timing-sensitive or do
not require high-speed clocks at all times. Note: Caution should be used when modifying a
If the primary clock source is the internal oscillator single IRCF bit. If VDD is less than 3V, it is
block (either INTRC or INTOSC), there are no distin- possible to select a higher clock speed
guishable differences between PRI_RUN and than is supported by the low VDD.
RC_RUN modes during execution. However, a clock Improper device operation may result if
switch delay will occur during entry to and exit from the VDD/FOSC specifications are violated.
RC_RUN mode. Therefore, if the primary clock source
is the internal oscillator block, the use of RC_RUN
mode is not recommended.
INTRC 1 2 3 n-1 n
CPU
Clock
Peripheral
Clock
Program
Counter PC PC + 2 PC + 4
Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3
INTOSC
Multiplexer
OSC1
TOST(1) TPLL(1)
1 2 n-1 n
PLL Clock
Output
Clock
Transition(2)
CPU Clock
Peripheral
Clock
Program PC PC + 2 PC + 4
Counter
Note1: TOST = 1024 TOSC; TPLL = 2 ms (approx). These intervals are not shown to scale.
2: Clock transition typically occurs within 2-4 TOSC.
OSC1
CPU
Clock
Peripheral
Clock
Sleep
Program
Counter PC PC + 2
OSC1
TOST(1) TPLL(1)
PLL Clock
Output
CPU Clock
Peripheral
Clock
Program PC PC + 2 PC + 4 PC + 6
Counter
Wake Event OSTS bit Set
Note1:TOST = 1024 TOSC; TPLL = 2 ms (approx). These intervals are not shown to scale.
Q1 Q2 Q3 Q4 Q1
OSC1
CPU Clock
Peripheral
Clock
Program PC PC + 2
Counter
FIGURE 3-8: TRANSITION TIMING FOR WAKE FROM IDLE TO RUN MODE
Q1 Q2 Q3 Q4
OSC1
TCSD
CPU Clock
Peripheral
Clock
Program PC
Counter
Wake Event
TABLE 3-2: EXIT DELAY ON WAKE-UP BY RESET FROM SLEEP MODE OR ANY IDLE MODE
(BY CLOCK SOURCES)
Clock Source Clock Source Clock Ready Status
Exit Delay
before Wake-up after Wake-up Bit (OSCCON)
LP, XT, HS
Primary Device Clock HSPLL OSTS
TCSD(1)
(PRI_IDLE mode) EC, RC
INTOSC(2) IOFS
LP, XT, HS TOST(3)
HSPLL TOST + trc(3) OSTS
T1OSC or INTRC
EC, RC TCSD(1)
INTOSC(2) TIOBST(4) IOFS
LP, XT, HS TOST(4)
HSPLL TOST + trc(3) OSTS
INTOSC(2)
EC, RC TCSD(1)
INTOSC(2) None IOFS
LP, XT, HS TOST(3)
None HSPLL TOST + trc(3) OSTS
(Sleep mode) EC, RC TCSD(1)
INTOSC(2) TIOBST(4) IOFS
Note 1: TCSD (parameter 38, Table 28-12) is a required delay when waking from Sleep and all Idle modes and runs
concurrently with any other required delays (see Section 3.4 “Idle Modes”).
2: Includes both the INTOSC 8 MHz source and postscaler derived frequencies. On Reset, INTOSC defaults
to 1 MHz.
3: TOST is the Oscillator Start-up Timer (parameter 32, Table 28-12). trc is the PLL Lock-out Timer
(parameter F12, Table 28-7); it is also designated as TPLL.
4: Execution continues during TIOBST (parameter 39, Table 28-12), the INTOSC stabilization period.
External Reset
MCLRE
MCLR
( )_IDLE
Sleep
WDT
Time-out
OST/PWRT
OST 1024 Cycles
Chip_Reset
10-bit Ripple Counter R Q
OSC1
31 μs 64 ms
PWRT
INTRC(1) 11-Bit Ripple Counter
Enable PWRT
Enable OST(2)
Note 1: This is the INTRC source from the internal oscillator block and is separate from the RC oscillator of the CLKI pin.
2: See Table 4-2 for time-out situations.
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
Note 1: It is recommended that the POR bit be set after a Power-on Reset has been detected so that subsequent
Power-on Resets may be detected.
2: Brown-out Reset is said to have occurred when BOR is ‘0’ and POR is ‘1’ (assuming that POR was set to
‘1’ by software immediately after POR).
HSPLL TPWRT(1) + 1024 TOSC + TPLL(2) 1024 TOSC + TPLL(2) 1024 TOSC + TPLL(2)
HS, XT, LP TPWRT(1) + 1024 TOSC 1024 TOSC 1024 TOSC
EC, ECIO TPWRT(1) — —
RC, RCIO TPWRT(1) — —
INTIO1, INTIO2 TPWRT(1) — —
Note 1: See parameter 33, Table 28-12.
2: 2 ms is the nominal time required for the PLL to lock.
VDD
MCLR
INTERNAL POR
TPWRT
OST TIME-OUT
INTERNAL RESET
FIGURE 4-4: TIME-OUT SEQUENCE ON POWER-UP (MCLR NOT TIED TO VDD): CASE 1
VDD
MCLR
INTERNAL POR
TPWRT
OST TIME-OUT
INTERNAL RESET
FIGURE 4-5: TIME-OUT SEQUENCE ON POWER-UP (MCLR NOT TIED TO VDD): CASE 2
VDD
MCLR
INTERNAL POR
TPWRT
OST TIME-OUT
INTERNAL RESET
VDD
MCLR
INTERNAL POR
TPWRT
PWRT TIME-OUT
TOST
OST TIME-OUT
INTERNAL RESET
FIGURE 4-7: TIME-OUT SEQUENCE ON POR w/PLL ENABLED (MCLR TIED TO VDD)
VDD
MCLR
INTERNAL POR
TPWRT
PLL TIME-OUT
INTERNAL RESET
TABLE 4-3: STATUS BITS, THEIR SIGNIFICANCE AND THE INITIALIZATION CONDITION
FOR RCON REGISTER
Program RCON Register STKPTR Register
Condition
Counter SBOREN RI TO PD POR BOR STKFUL STKUNF
Power-on Reset 0000h 1 1 1 1 0 0 0 0
RESET Instruction 0000h u(2) 0 u u u u u u
Brown-out Reset 0000h u(2) 1 1 1 u 0 u u
MCLR during Power-Managed 0000h u(2) u 1 u u u u u
Run Modes
MCLR during Power-Managed 0000h u(2) u 1 0 u u u u
Idle Modes and Sleep Mode
WDT Time-out during Full Power 0000h u(2) u 0 u u u u u
or Power-Managed Run Mode
MCLR during Full Power 0000h u(2) u u u u u u u
Execution
Stack Full Reset (STVREN = 1) 0000h u(2) u u u u u 1 u
(2)
Stack Underflow Reset 0000h u u u u u u u 1
(STVREN = 1)
Stack Underflow Error (not an 0000h u(2) u u u u u u 1
actual Reset, STVREN = 0)
WDT Time-out during PC + 2 u(2) u 0 0 u u u u
Power-Managed Idle or
Sleep Modes
Interrupt Exit from PC + 2(1) u(2) u u 0 u u u u
Power-Managed Modes
Legend: u = unchanged
Note 1: When the wake-up is due to an interrupt and the GIEH or GIEL bits are set, the PC is loaded with the
interrupt vector (008h or 0018h).
2: Reset state is ‘1’ for POR and unchanged for all other Resets when software BOR is enabled
(BOREN<1:0> Configuration bits = 01 and SBOREN = 1). Otherwise, the Reset state is ‘0’.
TOSU 6X27 6X22 8X27 8X22 ---0 0000 ---0 0000 ---0 uuuu(3)
TOSH 6X27 6X22 8X27 8X22 0000 0000 0000 0000 uuuu uuuu(3)
TOSL 6X27 6X22 8X27 8X22 0000 0000 0000 0000 uuuu uuuu(3)
STKPTR 6X27 6X22 8X27 8X22 00-0 0000 uu-u uuuu uu-u uuuu(3)
PCLATU 6X27 6X22 8X27 8X22 ---0 0000 ---0 0000 ---u uuuu
PCLATH 6X27 6X22 8X27 8X22 0000 0000 0000 0000 uuuu uuuu
PCL 6X27 6X22 8X27 8X22 0000 0000 0000 0000 PC + 2(2)
TBLPTRU 6X27 6X22 8X27 8X22 --00 0000 --00 0000 --uu uuuu
TBLPTRH 6X27 6X22 8X27 8X22 0000 0000 0000 0000 uuuu uuuu
TBLPTRL 6X27 6X22 8X27 8X22 0000 0000 0000 0000 uuuu uuuu
TABLAT 6X27 6X22 8X27 8X22 0000 0000 0000 0000 uuuu uuuu
PRODH 6X27 6X22 8X27 8X22 xxxx xxxx uuuu uuuu uuuu uuuu
PRODL 6X27 6X22 8X27 8X22 xxxx xxxx uuuu uuuu uuuu uuuu
INTCON 6X27 6X22 8X27 8X22 0000 000x 0000 000u uuuu uuuu(1)
INTCON2 6X27 6X22 8X27 8X22 1111 1111 1111 1111 uuuu uuuu(1)
INTCON3 6X27 6X22 8X27 8X22 1100 0000 1100 0000 uuuu uuuu(1)
INDF0 6X27 6X22 8X27 8X22 N/A N/A N/A
POSTINC0 6X27 6X22 8X27 8X22 N/A N/A N/A
POSTDEC0 6X27 6X22 8X27 8X22 N/A N/A N/A
PREINC0 6X27 6X22 8X27 8X22 N/A N/A N/A
PLUSW0 6X27 6X22 8X27 8X22 N/A N/A N/A
FSR0H 6X27 6X22 8X27 8X22 ---- 0000 ---- 0000 ---- uuuu
FSR0L 6X27 6X22 8X27 8X22 xxxx xxxx uuuu uuuu uuuu uuuu
WREG 6X27 6X22 8X27 8X22 xxxx xxxx uuuu uuuu uuuu uuuu
INDF1 6X27 6X22 8X27 8X22 N/A N/A N/A
POSTINC1 6X27 6X22 8X27 8X22 N/A N/A N/A
POSTDEC1 6X27 6X22 8X27 8X22 N/A N/A N/A
PREINC1 6X27 6X22 8X27 8X22 N/A N/A N/A
PLUSW1 6X27 6X22 8X27 8X22 N/A N/A N/A
Legend: u = unchanged, x = unknown, - = unimplemented bit, read as ‘0’, q = value depends on condition.
Shaded cells indicate conditions do not apply for the designated device.
Note 1: One or more bits in the INTCONx or PIRx registers will be affected (to cause wake-up).
2: When the wake-up is due to an interrupt and the GIEL or GIEH bit is set, the PC is loaded with the interrupt vector
(0008h or 0018h).
3: When the wake-up is due to an interrupt and the GIEL or GIEH bit is set, the TOSU, TOSH and TOSL are updated with
the current value of the PC. The STKPTR is modified to point to the next location in the hardware stack.
4: See Table 4-3 for Reset value for specific condition.
5: Bits 6 and 7 of PORTA, LATA and TRISA are enabled, depending on the oscillator mode selected. When not enabled
as PORTA pins, they are disabled and read ‘0’.
FSR1H 6X27 6X22 8X27 8X22 ---- 0000 ---- 0000 ---- uuuu
FSR1L 6X27 6X22 8X27 8X22 xxxx xxxx uuuu uuuu uuuu uuuu
BSR 6X27 6X22 8X27 8X22 ---- 0000 ---- 0000 ---- uuuu
INDF2 6X27 6X22 8X27 8X22 N/A N/A N/A
POSTINC2 6X27 6X22 8X27 8X22 N/A N/A N/A
POSTDEC2 6X27 6X22 8X27 8X22 N/A N/A N/A
PREINC2 6X27 6X22 8X27 8X22 N/A N/A N/A
PLUSW2 6X27 6X22 8X27 8X22 N/A N/A N/A
FSR2H 6X27 6X22 8X27 8X22 ---- 0000 ---- 0000 ---- uuuu
FSR2L 6X27 6X22 8X27 8X22 xxxx xxxx uuuu uuuu uuuu uuuu
STATUS 6X27 6X22 8X27 8X22 ---x xxxx ---u uuuu ---u uuuu
TMR0H 6X27 6X22 8X27 8X22 0000 0000 0000 0000 uuuu uuuu
TMR0L 6X27 6X22 8X27 8X22 xxxx xxxx uuuu uuuu uuuu uuuu
T0CON 6X27 6X22 8X27 8X22 1111 1111 1111 1111 uuuu uuuu
OSCCON 6X27 6X22 8X27 8X22 0100 q000 0100 q000 uuuu uuqu
HLVDCON 6X27 6X22 8X27 8X22 0-00 0101 0-00 0101 u-uu uuuu
WDTCON 6X27 6X22 8X27 8X22 ---- ---0 ---- ---0 ---- ---u
RCON(4) 6X27 6X22 8X27 8X22 0q-1 11q0 0q-q qquu uq-u qquu
TMR1H 6X27 6X22 8X27 8X22 xxxx xxxx uuuu uuuu uuuu uuuu
TMR1L 6X27 6X22 8X27 8X22 xxxx xxxx uuuu uuuu uuuu uuuu
T1CON 6X27 6X22 8X27 8X22 0000 0000 u0uu uuuu uuuu uuuu
TMR2 6X27 6X22 8X27 8X22 0000 0000 0000 0000 uuuu uuuu
PR2 6X27 6X22 8X27 8X22 1111 1111 uuuu uuuu uuuu uuuu
T2CON 6X27 6X22 8X27 8X22 -000 0000 -000 0000 -uuu uuuu
SSP1BUF 6X27 6X22 8X27 8X22 xxxx xxxx uuuu uuuu uuuu uuuu
SSP1ADD 6X27 6X22 8X27 8X22 0000 0000 0000 0000 uuuu uuuu
SSP1STAT 6X27 6X22 8X27 8X22 0000 0000 0000 0000 uuuu uuuu
SSP1CON1 6X27 6X22 8X27 8X22 0000 0000 0000 0000 uuuu uuuu
SSP1CON2 6X27 6X22 8X27 8X22 0000 0000 0000 0000 uuuu uuuu
Legend: u = unchanged, x = unknown, - = unimplemented bit, read as ‘0’, q = value depends on condition.
Shaded cells indicate conditions do not apply for the designated device.
Note 1: One or more bits in the INTCONx or PIRx registers will be affected (to cause wake-up).
2: When the wake-up is due to an interrupt and the GIEL or GIEH bit is set, the PC is loaded with the interrupt vector
(0008h or 0018h).
3: When the wake-up is due to an interrupt and the GIEL or GIEH bit is set, the TOSU, TOSH and TOSL are updated with
the current value of the PC. The STKPTR is modified to point to the next location in the hardware stack.
4: See Table 4-3 for Reset value for specific condition.
5: Bits 6 and 7 of PORTA, LATA and TRISA are enabled, depending on the oscillator mode selected. When not enabled
as PORTA pins, they are disabled and read ‘0’.
ADRESH 6X27 6X22 8X27 8X22 xxxx xxxx uuuu uuuu uuuu uuuu
ADRESL 6X27 6X22 8X27 8X22 xxxx xxxx uuuu uuuu uuuu uuuu
ADCON0 6X27 6X22 8X27 8X22 --00 0000 --00 0000 --uu uuuu
ADCON1 6X27 6X22 8X27 8X22 --00 0000 --00 0000 --uu uuuu
ADCON2 6X27 6X22 8X27 8X22 0-00 0000 0-00 0000 u-uu uuuu
CCPR1H 6X27 6X22 8X27 8X22 xxxx xxxx uuuu uuuu uuuu uuuu
CCPR1L 6X27 6X22 8X27 8X22 xxxx xxxx uuuu uuuu uuuu uuuu
CCP1CON 6X27 6X22 8X27 8X22 0000 0000 0000 0000 uuuu uuuu
CCPR2H 6X27 6X22 8X27 8X22 xxxx xxxx uuuu uuuu uuuu uuuu
CCPR2L 6X27 6X22 8X27 8X22 xxxx xxxx uuuu uuuu uuuu uuuu
CCP2CON 6X27 6X22 8X27 8X22 0000 0000 0000 0000 uuuu uuuu
CCPR3H 6X27 6X22 8X27 8X22 xxxx xxxx uuuu uuuu uuuu uuuu
CCPR3L 6X27 6X22 8X27 8X22 xxxx xxxx uuuu uuuu uuuu uuuu
CCP3CON 6X27 6X22 8X27 8X22 0000 0000 0000 0000 uuuu uuuu
ECCP1AS 6X27 6X22 8X27 8X22 0000 0000 0000 0000 uuuu uuuu
CVRCON 6X27 6X22 8X27 8X22 0000 0000 0000 0000 uuuu uuuu
CMCON 6X27 6X22 8X27 8X22 0000 0111 0000 0111 uuuu uuuu
TMR3H 6X27 6X22 8X27 8X22 xxxx xxxx uuuu uuuu uuuu uuuu
TMR3L 6X27 6X22 8X27 8X22 xxxx xxxx uuuu uuuu uuuu uuuu
T3CON 6X27 6X22 8X27 8X22 0000 0000 uuuu uuuu uuuu uuuu
PSPCON 6X27 6X22 8X27 8X22 0000 ---- 0000 ---- uuuu ----
SPBRG1 6X27 6X22 8X27 8X22 0000 0000 0000 0000 uuuu uuuu
RCREG1 6X27 6X22 8X27 8X22 0000 0000 0000 0000 uuuu uuuu
TXREG1 6X27 6X22 8X27 8X22 0000 0000 0000 0000 uuuu uuuu
TXSTA1 6X27 6X22 8X27 8X22 0000 0010 0000 0010 uuuu uuuu
RCSTA1 6X27 6X22 8X27 8X22 0000 000x 0000 000x uuuu uuuu
EEADRH 6X27 6X22 8X27 8X22 ---- --00 ---- --00 ---- --uu
EEADR 6X27 6X22 8X27 8X22 0000 0000 0000 0000 uuuu uuuu
EEDATA 6X27 6X22 8X27 8X22 0000 0000 0000 0000 uuuu uuuu
EECON2 6X27 6X22 8X27 8X22 0000 0000 0000 0000 0000 0000
EECON1 6X27 6X22 8X27 8X22 xx-0 x000 uu-0 u000 uu-u uuuu
Legend: u = unchanged, x = unknown, - = unimplemented bit, read as ‘0’, q = value depends on condition.
Shaded cells indicate conditions do not apply for the designated device.
Note 1: One or more bits in the INTCONx or PIRx registers will be affected (to cause wake-up).
2: When the wake-up is due to an interrupt and the GIEL or GIEH bit is set, the PC is loaded with the interrupt vector
(0008h or 0018h).
3: When the wake-up is due to an interrupt and the GIEL or GIEH bit is set, the TOSU, TOSH and TOSL are updated with
the current value of the PC. The STKPTR is modified to point to the next location in the hardware stack.
4: See Table 4-3 for Reset value for specific condition.
5: Bits 6 and 7 of PORTA, LATA and TRISA are enabled, depending on the oscillator mode selected. When not enabled
as PORTA pins, they are disabled and read ‘0’.
IPR3 6X27 6X22 8X27 8X22 1111 1111 1111 1111 uuuu uuuu
PIR3 6X27 6X22 8X27 8X22 0000 0000 0000 0000 uuuu uuuu(1)
PIE3 6X27 6X22 8X27 8X22 0000 0000 0000 0000 uuuu uuuu
IPR2 6X27 6X22 8X27 8X22 11-1 1111 11-1 1111 uu-u uuuu
PIR2 6X27 6X22 8X27 8X22 00-0 0000 00-0 0000 uu-u uuuu(1)
PIE2 6X27 6X22 8X27 8X22 00-0 0000 00-0 0000 uu-u uuuu
IPR1 6X27 6X22 8X27 8X22 1111 1111 1111 1111 uuuu uuuu
PIR1 6X27 6X22 8X27 8X22 0000 0000 0000 0000 uuuu uuuu(1)
PIE1 6X27 6X22 8X27 8X22 0000 0000 0000 0000 uuuu uuuu
MEMCON 6X27 6X22 8X27 8X22 0-00 --00 0-00 --00 u-uu --uu
OSCTUNE 6X27 6X22 8X27 8X22 00-0 0000 00-0 0000 uu-u uuuu
TRISJ 6X27 6X22 8X27 8X22 1111 1111 1111 1111 uuuu uuuu
TRISH 6X27 6X22 8X27 8X22 1111 1111 1111 1111 uuuu uuuu
TRISG 6X27 6X22 8X27 8X22 ---1 1111 ---1 1111 ---u uuuu
TRISF 6X27 6X22 8X27 8X22 1111 1111 1111 1111 uuuu uuuu
TRISE 6X27 6X22 8X27 8X22 1111 1111 1111 1111 uuuu uuuu
TRISD 6X27 6X22 8X27 8X22 1111 1111 1111 1111 uuuu uuuu
TRISC 6X27 6X22 8X27 8X22 1111 1111 1111 1111 uuuu uuuu
TRISB 6X27 6X22 8X27 8X22 1111 1111 1111 1111 uuuu uuuu
TRISA(5) 6X27 6X22 8X27 8X22 1111 1111(5) 1111 1111(5) uuuu uuuu(5)
LATJ 6X27 6X22 8X27 8X22 xxxx xxxx uuuu uuuu uuuu uuuu
LATH 6X27 6X22 8X27 8X22 xxxx xxxx uuuu uuuu uuuu uuuu
LATG 6X27 6X22 8X27 8X22 --xx xxxx --uu uuuu --uu uuuu
LATF 6X27 6X22 8X27 8X22 xxxx xxxx uuuu uuuu uuuu uuuu
LATE 6X27 6X22 8X27 8X22 xxxx xxxx uuuu uuuu uuuu uuuu
LATD 6X27 6X22 8X27 8X22 xxxx xxxx uuuu uuuu uuuu uuuu
LATC 6X27 6X22 8X27 8X22 xxxx xxxx uuuu uuuu uuuu uuuu
LATB 6X27 6X22 8X27 8X22 xxxx xxxx uuuu uuuu uuuu uuuu
LATA(5) 6X27 6X22 8X27 8X22 xxxx xxxx(5) uuuu uuuu(5) uuuu uuuu(5)
PORTJ 6X27 6X22 8X27 8X22 xxxx xxxx uuuu uuuu uuuu uuuu
PORTH 6X27 6X22 8X27 8X22 0000 xxxx uuuu uuuu uuuu uuuu
PORTG 6X27 6X22 8X27 8X22 --xx xxxx --uu uuuu --uu uuuu
PORTF 6X27 6X22 8X27 8X22 x000 0000 u000 0000 uuuu uuuu
PORTE 6X27 6X22 8X27 8X22 xxxx xxxx uuuu uuuu uuuu uuuu
PORTD 6X27 6X22 8X27 8X22 xxxx xxxx uuuu uuuu uuuu uuuu
PORTC 6X27 6X22 8X27 8X22 xxxx xxxx uuuu uuuu uuuu uuuu
PORTB 6X27 6X22 8X27 8X22 xxxx xxxx uuuu uuuu uuuu uuuu
Legend: u = unchanged, x = unknown, - = unimplemented bit, read as ‘0’, q = value depends on condition.
Shaded cells indicate conditions do not apply for the designated device.
Note 1: One or more bits in the INTCONx or PIRx registers will be affected (to cause wake-up).
2: When the wake-up is due to an interrupt and the GIEL or GIEH bit is set, the PC is loaded with the interrupt vector
(0008h or 0018h).
3: When the wake-up is due to an interrupt and the GIEL or GIEH bit is set, the TOSU, TOSH and TOSL are updated with
the current value of the PC. The STKPTR is modified to point to the next location in the hardware stack.
4: See Table 4-3 for Reset value for specific condition.
5: Bits 6 and 7 of PORTA, LATA and TRISA are enabled, depending on the oscillator mode selected. When not enabled
as PORTA pins, they are disabled and read ‘0’.
PORTA(5) 6X27 6X22 8X27 8X22 xx0x 0000(5) uu0u 0000(5) uuuu uuuu(5)
SPBRGH1 6X27 6X22 8X27 8X22 0000 0000 0000 0000 uuuu uuuu
BAUDCON1 6X27 6X22 8X27 8X22 01-0 0-00 01-0 0-00 uu-u u-uu
SPBRGH2 6X27 6X22 8X27 8X22 0000 0000 0000 0000 uuuu uuuu
BAUDCON2 6X27 6X22 8X27 8X22 01-0 0-00 01-0 0-00 uu-u u-uu
ECCP1DEL 6X27 6X22 8X27 8X22 0000 0000 0000 0000 uuuu uuuu
TMR4 6X27 6X22 8X27 8X22 0000 0000 0000 0000 uuuu uuuu
PR4 6X27 6X22 8X27 8X22 1111 1111 uuuu uuuu uuuu uuuu
T4CON 6X27 6X22 8X27 8X22 -000 0000 -000 0000 -uuu uuuu
CCPR4H 6X27 6X22 8X27 8X22 xxxx xxxx uuuu uuuu uuuu uuuu
CCPR4L 6X27 6X22 8X27 8X22 xxxx xxxx uuuu uuuu uuuu uuuu
CCP4CON 6X27 6X22 8X27 8X22 --00 0000 --00 0000 --uu uuuu
CCPR5H 6X27 6X22 8X27 8X22 xxxx xxxx uuuu uuuu uuuu uuuu
CCPR5L 6X27 6X22 8X27 8X22 xxxx xxxx uuuu uuuu uuuu uuuu
CCP5CON 6X27 6X22 8X27 8X22 --00 0000 --00 0000 --uu uuuu
SPBRG2 6X27 6X22 8X27 8X22 0000 0000 0000 0000 uuuu uuuu
RCREG2 6X27 6X22 8X27 8X22 0000 0000 0000 0000 uuuu uuuu
TXREG2 6X27 6X22 8X27 8X22 0000 0000 0000 0000 uuuu uuuu
TXSTA2 6X27 6X22 8X27 8X22 0000 0010 0000 0010 uuuu uuuu
RCSTA2 6X27 6X22 8X27 8X22 0000 000x 0000 000x uuuu uuuu
ECCP3AS 6X27 6X22 8X27 8X22 0000 0000 0000 0000 uuuu uuuu
ECCP3DEL 6X27 6X22 8X27 8X22 0000 0000 0000 0000 uuuu uuuu
ECCP2AS 6X27 6X22 8X27 8X22 0000 0000 0000 0000 uuuu uuuu
ECCP2DEL 6X27 6X22 8X27 8X22 0000 0000 0000 0000 uuuu uuuu
SSP2BUF 6X27 6X22 8X27 8X22 xxxx xxxx uuuu uuuu uuuu uuuu
SSP2ADD 6X27 6X22 8X27 8X22 0000 0000 0000 0000 uuuu uuuu
SSP2STAT 6X27 6X22 8X27 8X22 0000 0000 0000 0000 uuuu uuuu
SSP2CON1 6X27 6X22 8X27 8X22 0000 0000 0000 0000 uuuu uuuu
SSP2CON2 6X27 6X22 8X27 8X22 0000 0000 0000 0000 uuuu uuuu
Legend: u = unchanged, x = unknown, - = unimplemented bit, read as ‘0’, q = value depends on condition.
Shaded cells indicate conditions do not apply for the designated device.
Note 1: One or more bits in the INTCONx or PIRx registers will be affected (to cause wake-up).
2: When the wake-up is due to an interrupt and the GIEL or GIEH bit is set, the PC is loaded with the interrupt vector
(0008h or 0018h).
3: When the wake-up is due to an interrupt and the GIEL or GIEH bit is set, the TOSU, TOSH and TOSL are updated with
the current value of the PC. The STKPTR is modified to point to the next location in the hardware stack.
4: See Table 4-3 for Reset value for specific condition.
5: Bits 6 and 7 of PORTA, LATA and TRISA are enabled, depending on the oscillator mode selected. When not enabled
as PORTA pins, they are disabled and read ‘0’.
5.1 Program Memory Organization The program memory modes operate as follows:
• The Microprocessor Mode permits access only
PIC18 microcontrollers implement a 21-bit program to external program memory; the contents of the
counter, which is capable of addressing a 2-Mbyte on-chip Flash memory are ignored. The 21-bit
program memory space. Accessing a location between program counter permits access to a 2-Mbyte
the upper boundary of the physically implemented linear program memory space.
memory and the 2-Mbyte address will return all ‘0’s (a
• The Microprocessor with Boot Block Mode
NOP instruction).
accesses on-chip Flash memory from the boot
The PIC18F6527 and PIC18F8527 each have 48 Kbytes block. Above this, external program memory is
of Flash memory and can store up to 24,576 single-word accessed all the way up to the 2-Mbyte limit.
instructions. Program execution automatically switches
The PIC18F6622 and PIC18F8622 each have 64 Kbytes between the two memories as required. The boot
of Flash memory and can store up to 32,768 single-word block is configurable to 1, 2 or 4 Kbytes.
instructions. • The Microcontroller Mode accesses only
on-chip Flash memory. Attempts to read above the
The PIC18F6627 and PIC18F8627 each have 96 Kbytes
physical limit of the on-chip Flash (0BFFFh for the
of Flash memory and can store up to 49,152 single-word
PIC18F8527, 0FFFFh for the PIC18F8622,
instructions.
17FFFh for the PIC18F8627, 1FFFFh for the
The PIC18F6722 and PIC18F8722 each have PIC18F8722) causes a read of all ‘0’s (a NOP
128 Kbytes of Flash memory and can store up to instruction).
65,536 single-word instructions. The Microcontroller mode is also the only operating
PIC18 devices have two interrupt vectors. The Reset mode available to PIC18F6527/6622/6627/6722
vector address is at 0000h and the interrupt vector devices.
addresses are at 0008h and 0018h. • The Extended Microcontroller Mode allows
The program memory map for the PIC18F8722 family access to both internal and external program
of devices is shown in Figure 5-1. memories as a single block. The device can
access its entire on-chip Flash memory; above
this, the device accesses external program
memory up to the 2-Mbyte program space limit.
As with Boot Block mode, execution automatically
switches between the two memories as required.
In all modes, the microcontroller has complete access
to data RAM and EEPROM.
Figure 5-2 compares the memory maps of the different
program memory modes. The differences between
on-chip and external memory access limitations are
more fully explained in Table 5-1.
PC<20:0>
CALL,RCALL,RETURN 21
RETFIE,RETLW
Stack Level 1
•
•
•
Stack Level 31
017FFFh
018000h
01FFFFh
1FFFFFh
11111
11110
Top-of-Stack Registers 11101 Stack Pointer
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4
OSC1
Q1
Q2 Internal
Q3 Phase
Clock
Q4
PC PC PC + 2 PC + 4
OSC2/CLKO
(RC mode)
Execute INST (PC – 2)
Fetch INST (PC) Execute INST (PC)
Fetch INST (PC + 2) Execute INST (PC + 2)
Fetch INST (PC + 4)
All instructions are single cycle, except for any program branches. These take two cycles since the fetch instruction
is “flushed” from the pipeline while the new instruction is being fetched and then executed.
When ‘a’ = 0:
BSR<3:0> Data Memory Map
The BSR is ignored and the
00h 000h Access Bank is used.
= 0000 Access RAM 05Fh
Bank 0 The first 96 bytes are
GPR 060h
FFh 0FFh general purpose RAM
00h 100h (from Bank 0).
= 0001
Bank 1 GPR The second 160 bytes are
FFh 1FFh Special Function Registers
= 0010 00h 200h (from Bank 15).
Bank 2 GPR
FFh 2FFh When ‘a’ = 1:
= 0011 00h 300h
Bank 3 The BSR specifies the Bank
GPR
used by the instruction.
FFh 3FFh
00h 400h
= 0100 Bank 4
GPR
FFh 4FFh
= 0101 00h 500h
Bank 5
GPR
FFh 5FFh
= 0110 00h 600h
Bank 6 GPR
Access Bank
FFh 6FFh
= 0111 00h 700h 00h
Bank 7 Access RAM Low
GPR 5Fh
FFh 7FFh Access RAM High 60h
= 1000 00h 800h (SFRs)
Bank 8 FFh
GPR
FFh 8FFh
= 1001 00h 900h
Bank 9
GPR
FFh 9FFh
00h A00h
= 1010
Bank 10 GPR
FFh AFFh
= 1011 00h B00h
Bank 11
GPR
FFh BFFh
= 1100 00h C00h
Bank 12 GPR
FFh CFFh
= 1101 D00h
Bank 13 00h
GPR
FFh DFFh
00h E00h
= 1110
Bank 14 GPR
FFh EFFh
00h F00h
= 1111 GPR
Bank 15 F5Fh
SFR F60h
FFh FFFh
BSR(1)
Data Memory From Opcode(2)
7 0 000h 00h 7 0
0 0 0 0 0 0 1 1 Bank 0 1 1 1 1 1 1 1 1
FFh
100h 00h
Bank 1
Bank Select(2) 200h FFh
00h
Bank 2
300h FFh
00h
Bank 3
through
Bank 13
FFh
E00h
00h
Bank 14
F00h FFh
00h
Bank 15
FFFh FFh
Note 1: The Access RAM bit of the instruction can be used to force an override of the selected bank (BSR<3:0>) to
the registers of the Access Bank.
2: The MOVFF instruction embeds the entire 12-bit address in the instruction.
5.3.2 ACCESS BANK however, the instruction is forced to use the Access
Bank address map; the current value of the BSR is
While the use of the BSR with an embedded 8-bit
ignored entirely.
address allows users to address the entire range of
data memory, it also means that the user must always Using this “forced” addressing allows the instruction to
ensure that the correct bank is selected. Otherwise, operate on a data address in a single cycle, without
data may be read from or written to the wrong location. updating the BSR first. For 8-bit addresses of 60h and
This can be disastrous if a GPR is the intended target above, this means that users can evaluate and operate
of an operation, but an SFR is written to instead. on SFRs more efficiently. The Access RAM below 60h
Verifying and/or changing the BSR for each read or is a good place for data values that the user might need
write to data memory can become very inefficient. to access rapidly, such as immediate computational
results or common program variables. Access RAM
To streamline access for the most commonly used data
also allows for faster and more code efficient context
memory locations, the data memory is configured with
saving and switching of variables.
an Access Bank, which allows users to access a
mapped block of memory without specifying a BSR. The mapping of the Access Bank is slightly different
The Access Bank consists of the first 96 bytes of when the extended instruction set is enabled (XINST
memory (00h-5Fh) in Bank 0 and the last 160 bytes of Configuration bit = 1). This is discussed in more detail
memory (60h-FFh) in Block 15. The lower half is known in Section 5.5.3 “Mapping the Access Bank in
as the “Access RAM” and is composed of GPRs. This Indexed Literal Offset Mode”.
upper half is also where the device’s SFRs are
mapped. These two areas are mapped contiguously in 5.3.3 GENERAL PURPOSE REGISTER
the Access Bank and can be addressed in a linear FILE
fashion by an 8-bit address (Figure 5-6). PIC18 devices may have banked memory in the GPR
The Access Bank is used by core PIC18 instructions area. This is data RAM, which is available for use by all
that include the Access RAM bit (the ‘a’ parameter in instructions. GPRs start at the bottom of Bank 0
the instruction). When ‘a’ is equal to ‘1’, the instruction (address 000h) and grow upwards towards the bottom of
uses the BSR and the 8-bit address included in the the SFR area. GPRs are not initialized by a Power-on
opcode for the data memory address. When ‘a’ is ‘0’, Reset and are unchanged on all other Resets.
TABLE 5-2: SPECIAL FUNCTION REGISTER MAP FOR THE PIC18F8722 FAMILY OF DEVICES
Address Name Address Name Address Name Address Name Address Name
FFFh TOSU FDFh INDF2(1) FBFh CCPR1H F9Fh IPR1 F7Fh SPBRGH1
FFEh TOSH FDEh POSTINC2(1) FBEh CCPR1L F9Eh PIR1 F7Eh BAUDCON1
FFDh TOSL FDDh POSTDEC2(1) FBDh CCP1CON F9Dh PIE1 F7Dh SPBRGH2
FFCh STKPTR FDCh PREINC2(1) FBCh CCPR2H F9Ch MEMCON F7Ch BAUDCON2
FFBh PCLATU FDBh PLUSW2(1) FBBh CCPR2L F9Bh OSCTUNE F7Bh —(2)
FFAh PCLATH FDAh FSR2H FBAh CCP2CON F9Ah TRISJ(3) F7Ah —(2)
(3)
FF9h PCL FD9h FSR2L FB9h CCPR3H F99h TRISH F79h ECCP1DEL
FF8h TBLPTRU FD8h STATUS FB8h CCPR3L F98h TRISG F78h TMR4
FF7h TBLPTRH FD7h TMR0H FB7h CCP3CON F97h TRISF F77h PR4
FF6h TBLPTRL FD6h TMR0L FB6h ECCP1AS F96h TRISE F76h T4CON
FF5h TABLAT FD5h T0CON FB5h CVRCON F95h TRISD F75h CCPR4H
FF4h PRODH FD4h —(2) FB4h CMCON F94h TRISC F74h CCPR4L
FF3h PRODL FD3h OSCCON FB3h TMR3H F93h TRISB F73h CCP4CON
FF2h INTCON FD2h HLVDCON FB2h TMR3L F92h TRISA F72h CCPR5H
FF1h INTCON2 FD1h WDTCON FB1h T3CON F91h LATJ(3) F71h CCPR5L
FF0h INTCON3 FD0h RCON FB0h PSPCON F90h LATH(3) F70h CCP5CON
FEFh INDF0(1) FCFh TMR1H FAFh SPBRG1 F8Fh LATG F6Fh SPBRG2
FEEh POSTINC0(1) FCEh TMR1L FAEh RCREG1 F8Eh LATF F6Eh RCREG2
FEDh POSTDEC0(1) FCDh T1CON FADh TXREG1 F8Dh LATE F6Dh TXREG2
FECh PREINC0(1) FCCh TMR2 FACh TXSTA1 F8Ch LATD F6Ch TXSTA2
FEBh PLUSW0(1) FCBh PR2 FABh RCSTA1 F8Bh LATC F6Bh RCSTA2
FEAh FSR0H FCAh T2CON FAAh EEADRH F8Ah LATB F6Ah ECCP3AS
FE9h FSR0L FC9h SSP1BUF FA9h EEADR F89h LATA F69h ECCP3DEL
FE8h WREG FC8h SSP1ADD FA8h EEDATA F88h PORTJ(3) F68h ECCP2AS
FE7h INDF1(1) FC7h SSP1STAT FA7h EECON2(1) F87h PORTH(3) F67h ECCP2DEL
FE6h POSTINC1(1) FC6h SSP1CON1 FA6h EECON1 F86h PORTG F66h SSP2BUF
FE5h POSTDEC1(1) FC5h SSP1CON2 FA5h IPR3 F85h PORTF F65h SSP2ADD
FE4h PREINC1(1) FC4h ADRESH FA4h PIR3 F84h PORTE F64h SSP2STAT
FE3h PLUSW1(1) FC3h ADRESL FA3h PIE3 F83h PORTD F63h SSP2CON1
FE2h FSR1H FC2h ADCON0 FA2h IPR2 F82h PORTC F62h SSP2CON2
FE1h FSR1L FC1h ADCON1 FA1h PIR2 F81h PORTB F61h —(2)
FE0h BSR FC0h ADCON2 FA0h PIE2 F80h PORTA F60h —(2)
PORTJ(2) RJ7 RJ6 RJ5 RJ4 RJ3 RJ2 RJ1 RJ0 xxxx xxxx 60, 156
PORTH(2) RH7 RH6 RH5 RH4 RH3 RH2 RH1 RH0 0000 xxxx 60, 154
PORTG — — RG5(5) RG4 RG3 RG2 RG1 RG0 --xx xxxx 60, 151
PORTF RF7 RF6 RF5 RF4 RF3 RF2 RF1 RF0 x000 0000 60, 149
PORTE RE7 RE6 RE5 RE4 RE3 RE2 RE1 RE0 xxxx xxxx 60, 146
PORTD RD7 RD6 RD5 RD4 RD3 RD2 RD1 RD0 xxxx xxxx 60, 143
PORTC RC7 RC6 RC5 RC4 RC3 RC2 RC1 RC0 xxxx xxxx 60, 140
PORTB RB7 RB6 RB5 RB4 RB3 RB2 RB1 RB0 xxxx xxxx 60, 137
PORTA RA7(4) RA6(4) RA5 RA4 RA3 RA2 RA1 RA0 xx0x 0000 61, 135
SPBRGH1 EUSART1 Baud Rate Generator Register High Byte 0000 0000 61, 252
BAUDCON1 ABDOVF RCIDL — SCKP BRG16 — WUE ABDEN 01-0 0-00 61, 250
SPBRGH2 EUSART2 Baud Rate Generator Register High Byte 0000 0000 61, 252
BAUDCON2 ABDOVF RCIDL — SCKP BRG16 — WUE ABDEN 01-0 0-00 61, 250
ECCP1DEL P1RSEN P1DC6 P1DC5 P1DC4 P1DC3 P1DC2 P1DC1 P1DC0 0000 0000 61, 200
TMR4 Timer4 Register 0000 0000 61, 178
PR4 Timer4 Period Register 1111 1111 61, 178
T4CON — T4OUTPS3 T4OUTPS2 T4OUTPS1 T4OUTPS0 TMR4ON T4CKPS1 T4CKPS0 -000 0000 61, 178
CCPR4H Capture/Compare/PWM Register 4 High Byte xxxx xxxx 61, 180
CCPR4L Capture/Compare/PWM Register 4 Low Byte xxxx xxxx 61, 180
CCP4CON — — DC4B1 DC4B0 CCP4M3 CCP4M2 CCP4M1 CCP4M0 --00 0000 61, 179
CCPR5H Capture/Compare/PWM Register 5 High Byte xxxx xxxx 61, 180
CCPR5L Capture/Compare/PWM Register 5 Low Byte xxxx xxxx 61, 180
CCP5CON — — DC5B1 DC5B0 CCP5M3 CCP5M2 CCP5M1 CCP5M0 --00 0000 61, 179
SPBRG2 EUSART2 Baud Rate Generator Register Low Byte 0000 0000 61, 252
RCREG2 EUSART2 Receive Register 0000 0000 61, 260
TXREG2 EUSART2 Transmit Register 0000 0000 61, 257
TXSTA2 CSRC TX9 TXEN SYNC SENDB BRGH TRMT TX9D 0000 0010 61, 248
RCSTA2 SPEN RX9 SREN CREN ADDEN FERR OERR RX9D 0000 000x 61, 249
ECCP3AS ECCP3ASE ECCP3AS2 ECCP3AS1 ECCP3AS0 PSS3AC1 PSS3AC0 PSS3BD1 PSS3BD0 0000 0000 61, 201
ECCP3DEL P3RSEN P3DC6 P3DC5 P3DC4 P3DC3 P3DC2 P3DC1 P3DC0 0000 0000 61, 200
ECCP2AS ECCP2ASE ECCP2AS2 ECCP2AS1 ECCP2AS0 PSS2AC1 PSS2AC0 PSS2BD1 PSS2BD0 0000 0000 61, 201
ECCP2DEL P2RSEN P2DC6 P2DC5 P2DC4 P2DC3 P2DC2 P2DC1 P2DC0 0000 0000 61, 200
SSP2BUF MSSP2 Receive Buffer/Transmit Register xxxx xxxx 61, 170
SSP2ADD MSSP2 Address Register in I2C™ Slave mode. MSSP2 Baud Rate Reload Register in I2C Master mode. 0000 0000 61, 170
SSP2STAT SMP CKE D/A P S R/W UA BF 0000 0000 61, 216
SSP2CON1 WCOL SSPOV SSPEN CKP SSPM3 SSPM2 SSPM1 SSPM0 0000 0000 61, 217
SSP2CON2 GCEN ACKSTAT ACKDT ACKEN RCEN PEN RSEN SEN 0000 0000 61, 218
Legend: x = unknown, u = unchanged, - = unimplemented, q = value depends on condition
Note 1: The SBOREN bit is only available when the BOREN<1:0> Configuration bits = 01; otherwise, this bit reads as ‘0’.
2: These registers and/or bits are not implemented on 64-pin devices and are read as ‘0’. Reset values are shown for 80-pin devices;
individual unimplemented bits should be interpreted as ‘-’.
3: The PLLEN bit is only available in specific oscillator configuration; otherwise, it is disabled and reads as ‘0’. See Section 2.6.4 “PLL in
INTOSC Modes”.
4: RA6/RA7 and their associated latch and direction bits are individually configured as port pins based on various primary oscillator modes.
When disabled, these bits read as ‘0’.
5: RG5 and LATG5 are only available when Master Clear is disabled (MCLRE Configuration bit = 0); otherwise, RG5 and LATG5 read as ‘0’.
6: Bit 7 and Bit 6 are cleared by user software or by a POR.
7: Bit 21 of TBLPTRU allows access to the device Configuration bits.
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
Note 1: For borrow, the polarity is reversed. A subtraction is executed by adding the 2’s complement of the second
operand. For rotate (RRF, RLF) instructions, this bit is loaded with either bit 4 or bit 3 of the source register.
2: For borrow, the polarity is reversed. A subtraction is executed by adding the 2’s complement of the second
operand. For rotate (RRF, RLF) instructions, this bit is loaded with either the high or low-order bit of the
source register.
000h
When ‘a’ = 0 and f ≥ 60h:
060h
The instruction executes in
080h Bank 0
Direct Forced mode. ‘f’ is inter-
preted as a location in the 100h
Access RAM between 060h 00h
Bank 1
and 0FFh. This is the same as through 60h
locations 060h to 07Fh Bank 14 80h
Valid range
(Bank 0) and F80h to FFFh for ‘f’
(Bank 15) of data memory.
FFh
F00h Access RAM
Locations below 60h are not
Bank 15
available in this addressing
F80h
mode. SFRs
FFFh
Data Memory
BSR
When ‘a’ = 1 (all values of f): 000h 00000000
Bank 0
The instruction executes in
080h
Direct mode (also known as
Direct Long mode). ‘f’ is inter- 100h
preted as a location in one of
the 16 banks of the data Bank 1 001001da ffffffff
memory space. The bank is through
Bank 14
designated by the Bank Select
Register (BSR). The address
can be in any implemented F00h
bank in the data memory Bank 15
space. F80h
SFRs
FFFh
Data Memory
Instruction: TBLRD*
Program Memory
Table Pointer(1)
Table Latch (8-bit)
TBLPTRU TBLPTRH TBLPTRL
TABLAT
Program Memory
(TBLPTR)
Instruction: TBLWT*
Program Memory
Holding Registers
Table Pointer(1) Table Latch (8-bit)
TBLPTRU TBLPTRH TBLPTRL TABLAT
Program Memory
(TBLPTR)
Note1: Table Pointer actually points to one of 64 holding registers, the address of which is determined by
TBLPTRL<5:0>. The process for physically writing data to the program memory array is discussed in
Section 6.5 “Writing to Flash Program Memory”.
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
Note 1: When a WRERR occurs, the EEPGD and CFGS bits are not cleared.
This allows tracing of the error condition.
TABLE 6-1: TABLE POINTER OPERATIONS WITH TBLRD AND TBLWT INSTRUCTIONS
Example Operation on Table Pointer
TBLRD*
TBLPTR is not modified
TBLWT*
TBLRD*+
TBLPTR is incremented after the read/write
TBLWT*+
TBLRD*-
TBLPTR is decremented after the read/write
TBLWT*-
TBLRD+*
TBLPTR is incremented before the read/write
TBLWT+*
Program Memory
TABLAT
Write Register
8 8 8 8
Program Memory
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
The BW bit selects an 8-bit or 16-bit data bus width. This addressing mode is available in both 8-bit and
Setting this bit (default) selects a data width of 16 bits. certain 16-bit Data Width modes. Additional details are
provided in Section 7.5.3 “16-bit Byte Select Mode”
The ADW<1:0> bits determine the address bus width. and Section 7.6 “8-Bit Data Width Modes”.
The available options are 20-bit (default), 16-bit, 12-bit
and 8-bit. Selecting any of the options other than 20-bit
width makes a corresponding number of high-order
7.3 Wait States
lines available for I/O functions; these pins are no While it may be assumed that external memory devices
longer affected by the setting of the EBDIS bit. For will operate at the microcontroller clock rate, this is
example, selecting a 16-bit Address mode often not the case. In fact, many devices require longer
(ADW<1:0> = 10) disables A<19:16> and allows times to write or retrieve data than the time allowed by
PORTH<3:0> to function without interruptions from the the execution of table read or table write operations.
bus. Using smaller address widths allows users to tailor
To compensate for this, the External Memory Bus can
the memory bus to the size of the external memory
be configured to add a fixed delay to each table opera-
space for a particular design while freeing up pins for
tion using the bus. Wait states are enabled by setting
dedicated I/O operation.
the WAITx bit. When enabled, the amount of delay is
Because the ADW bits have the effect of disabling pins set by the WAIT<1:0> bits (MEMCON<5:4>). The delay
for memory bus operations, it is important to always is based on multiples of microcontroller instruction
select an address width at least equal to the data width. cycle time and are added following the instruction cycle
If 8-bit or 12-bit address widths are used with a 16-bit when the table operation is executed. The range is
data width, the upper bits of data will not be available from no delay to 3 TCY (default value).
on the bus.
All combinations of address and data widths require
multiplexing of address and data information on the
same lines. The address and data multiplexing, as well
as I/O ports made available by the use of smaller
address widths, are summarized in Table 7-2.
TABLE 7-2: ADDRESS AND DATA LINES FOR DIFFERENT ADDRESS AND DATA WIDTHS
Multiplexed Data and Address-Only
Ports Available
Data Width Address Width Address Lines (and Lines (and
for I/O
Corresponding Ports) Corresponding Ports)
All of PORTE and
8-bit —
PORTH
AD<11:8> PORTE<7:4>,
12-bit
(PORTE<3:0>) All of PORTH
AD<7:0>
8-bit AD<15:8>
16-bit (PORTD<7:0>) All of PORTH
(PORTE<7:0>)
A<19:16>, AD<15:8>
20-bit (PORTH<3:0>, —
PORTE<7:0>)
16-bit AD<15:0> — All of PORTH
16-bit (PORTD<7:0>, A<19:16>
20-bit PORTE<7:0>) —
(PORTH<3:0>)
A<19:16>(1)
CE
OE
WRH
WRL
Address Bus
Data Bus
Control Lines
Note 1: Upper-order address lines are used only for 20-bit address widths.
2: This signal only applies to table writes. See Section 6.1 “Table Reads and Table Writes”.
PIC18F8X27/8X22
AD<7:0> 373 A<20:1> JEDEC Word
A<x:0>
EPROM Memory
D<15:0>
D<15:0>
CE OE WR(2)
AD<15:8>
373
ALE
A<19:16>(1)
CE
OE
WRH
Address Bus
Data Bus
Control Lines
Note 1: Upper-order address lines are used only for 20-bit address widths.
2: This signal only applies to table writes. See Section 6.1 “Table Reads and Table Writes”.
PIC18F8X27/8X22
A<20:1>
AD<7:0> 373 A<x:1> JEDEC Word
Flash Memory
D<15:0>
D<15:0>
AD<15:8> 138(3) CE
373 A0
ALE BYTE/WORD OE WR(1)
(2)
A<19:16>
OE
WRH
WRL A<20:1>
A<x:1> JEDEC Word
BA0 SRAM Memory
I/O
D<15:0>
CE D<15:0>
LB LB
UB UB OE WR(1)
Address Bus
Data Bus
Control Lines
Note 1: This signal only applies to table writes. See Section 6.1 “Table Reads and Table Writes”.
2: Upper-order address lines are used only for 20-bit address width.
3: Demultiplexing is only required when multiple memory devices are accessed.
FIGURE 7-4: EXTERNAL MEMORY BUS TIMING FOR TBLRD WITH A 1 TCY WAIT STATE
(MICROPROCESSOR MODE)
Apparent Q Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q4 Q4 Q4 Q4
Actual Q Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4
BA0
ALE
OE
CE ‘0’ ‘0’
1 TCY Wait
Memory Opcode Fetch Table Read
Cycle MOVLW 55h of 92h
from 007556h from 199E67h
Instruction TBLRD Cycle 1 TBLRD Cycle 2
Execution
Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4
A<19:16> 0Ch
CE
ALE
OE
Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1
CE
ALE
OE
Note 1: Bus becomes inactive regardless of power-managed mode entered when SLEEP is executed.
PIC18F8X27/8X22
AD<7:0> A<19:0>
373 A<x:1>
ALE D<15:8> A0
D<7:0>
AD<15:8>(1)
CE
A<19:16>(1) OE WR(2)
BA0
CE
OE
WRL
Address Bus
Data Bus
Control Lines
Note 1: Upper-order address bits are used only for 20-bit address width. The upper AD byte is used
for all address widths except 8-bit.
2: This signal only applies to table writes. See Section 6.1 “Table Reads and Table Writes”.
Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4
AD<15:8>,
03Ah 03Ah CCFh 03Ah
A<19:16>(1)
AD<7:0> AAh 08h 00h ABh 55h 0Eh 33h 92h ACh 55h 0Fh
BA0
ALE
OE
Memory Opcode Fetch Opcode Fetch Table Read 92h Opcode Fetch
Cycle TBLRD * MOVLW 55h from 199E67h ADDLW 55h
from 007554h from 007556h from 007558h
Instruction
Execution INST(PC – 2) TBLRD Cycle 1 TBLRD Cycle 2 MOVLW
Note 1: The address lines actually used depends on the address width selected. This example assumes 20-bit addressing.
FIGURE 7-9: EXTERNAL BUS TIMING FOR TBLRD (EXTENDED MICROCONTROLLER MODE)
Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4
A<19:16>(1) 0Ch
AD<15:8>(1) CFh
CE
ALE
OE
Note 1: The address lines actually used depends on the address width selected. This example assumes 20-bit addressing.
Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1
BA0
CE
ALE
OE
Note 1: The address lines actually used depends on the address width selected. This example assumes 20-bit addressing.
2: Bus becomes inactive regardless of power-managed mode entered when SLEEP is executed.
Q1 Q2 Q3 Q4
AD<15:8>(1) 03Ah
BA0
ALE
OE
‘1’ ‘1’
WRL
Note 1: The address lines actually used depends on the address width selected. This example assumes 16-bit addressing.
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
Note 1: When a WRERR occurs, the EEPGD and CFGS bits are not cleared. This allows tracing of the error
condition.
TMR0IF Wake-up if in
TMR0IE Idle or Sleep modes
TMR0IP
RBIF
RBIE
RBIP
INT0IF
INT0IE
INT1IF
INT1IE Interrupt to CPU
INT1IP Vector to Location
INT2IF
INT2IE 0008h
PIR1<7:0>
PIE1<7:0> INT2IP
IPR1<7:0> INT3IF
INT3IE
INT3IP
GIEH/GIE
PIR2<7:6, 4:0>
PIE2<7:6, 4:0>
IPR2<7:6, 4:0> IPEN
PIR3<7:0> IPEN
PIE3<7:0>
IPR3<7:0> GIEL/PEIE
IPEN
PIR1<7:0>
PIE1<7:0>
IPR1<7:0>
PIR2<7:6, 4:0>
PIE2<7:6, 4:0>
IPR2<7:6, 4:0> Interrupt to CPU
TMR0IF Vector to Location
TMR0IE IPEN
PIR3<7:0> 0018h
PIE3<7:0> TMR0IP
IPR3<7:0>
RBIF
RBIE
RBIP GIEH/GIE
GIEL/PEIE
INT1IF
INT1IE
INT1IP
INT2IF
INT2IE
INT2IP
INT3IF
INT3IE
INT3IP
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
Note 1: A mismatch condition will continue to set this bit. Reading PORTB will end the mismatch condition and
allow the bit to be cleared.
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
Note: Interrupt flag bits are set when an interrupt condition occurs, regardless of the state of its corresponding
enable bit or the global interrupt enable bit. User software should ensure the appropriate interrupt flag bits
are clear prior to enabling an interrupt. This feature allows for software polling.
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
Note: Interrupt flag bits are set when an interrupt condition occurs, regardless of the state of its corresponding
enable bit or the global interrupt enable bit. User software should ensure the appropriate interrupt flag bits
are clear prior to enabling an interrupt. This feature allows for software polling.
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
• TRIS register (Data Direction register) Reading the PORTA register reads the status of the
• Port register (reads the levels on the pins of the pins, whereas writing to it, will write to the port latch.
device) The Data Latch register (LATA) is also memory
• LAT register (output latch) mapped. Read-modify-write operations on the LATA
register read and write the latched output value for
The Data Latch (LAT register) is useful for
PORTA.
read-modify-write operations on the value that the I/O
pins are driving. The RA4 pin is multiplexed with the Timer0 module
clock input to become the RA4/T0CKI pin. Pins RA6
A simplified model of a generic I/O port, without the
and RA7 are multiplexed with the main oscillator pins;
interfaces to other peripherals, is shown in Figure 11-1.
they are enabled as oscillator or I/O pins by the selec-
tion of the main oscillator in the Configuration register
FIGURE 11-1: GENERIC I/O PORT (see Section 25.1 “Configuration Bits” for details).
OPERATION When they are not used as port pins, RA6 and RA7 and
their associated TRIS and LAT bits are read as ‘0’.
RD LAT The other PORTA pins are multiplexed with the analog
VREF+ and VREF- inputs. The operation of pins
Data
Bus D Q
RA5:RA0 as A/D converter inputs is selected by
clearing or setting the PCFG<3:0> control bits in the
WR LAT I/O pin(1)
or Port ADCON1 register.
CKx
Data Latch Note: On a Power-on Reset, RA5 and RA<3:0>
are configured as analog inputs and read
D Q as ‘0’. RA4 is configured as a digital input.
WR TRIS
CKx
The RA4/T0CKI pin is a Schmitt Trigger input and an
TRIS Latch
open-drain output. All other PORTA pins have TTL
Input
Buffer input levels and full CMOS output drivers.
RD TRIS
The TRISA register controls the direction of the PORTA
pins, even when they are being used as analog inputs.
The user must ensure the bits in the TRISA register are
Q D maintained set when using them as analog inputs.
RA0/AN0 RA0 0 O DIG LATA<0> data output; not affected by analog input.
1 I TTL PORTA<0> data input; disabled when analog input enabled.
AN0 1 I ANA A/D input channel 0. Default input configuration on POR; does not affect
digital output.
RA1/AN1 RA1 0 O DIG LATA<1> data output; not affected by analog input.
1 I TTL PORTA<1> data input; disabled when analog input enabled.
AN1 1 I ANA A/D input channel 1. Default input configuration on POR; does not affect
digital output.
RA2/AN2/VREF- RA2 0 O DIG LATA<2> data output; not affected by analog input.
1 I TTL PORTA<2> data input. Disabled when analog functions enabled.
AN2 1 I ANA A/D input channel 2. Default input configuration on POR.
VREF- 1 I ANA Comparator voltage reference low input and A/D voltage reference low input.
RA3/AN3/VREF+ RA3 0 O DIG LATA<3> data output; not affected by analog input.
1 I TTL PORTA<3> data input; disabled when analog input enabled.
AN3 1 I ANA A/D input channel 3. Default input configuration on POR.
VREF+ 1 I ANA Comparator voltage reference high input and A/D voltage reference
high input.
RA4/T0CKI RA4 0 O DIG LATA<4> data output.
1 I ST PORTA<4> data input; default configuration on POR.
T0CKI x I ST Timer0 clock input.
RA5/AN4/HLVDIN RA5 0 O DIG LATA<5> data output; not affected by analog input.
1 I TTL PORTA<5> data input; disabled when analog input enabled.
AN4 1 I ANA A/D input channel 4. Default configuration on POR.
HLVDIN 1 I ANA High/Low-Voltage Detect external trip point input.
OSC2/CLKO/RA6 OSC2 x O ANA Main oscillator feedback output connection (XT, HS, HSPLL and LP modes).
CLKO x O DIG System cycle clock output (FOSC/4) in all oscillator modes except RC,
INTIO7 and EC.
RA6 0 O DIG LATA<6> data output. Enabled in RCIO, INTIO2 and ECIO modes only.
1 I TTL PORTA<6> data input. Enabled in RCIO, INTIO2 and ECIO modes only.
OSC1/CLKI/RA7 OSC1 x I ANA Main oscillator input connection.
CLKI x I ANA Main clock input connection.
RA7 0 O DIG LATA<7> data output. Disabled in external oscillator modes.
1 I TTL PORTA<7> data input. Disabled in external oscillator modes.
Legend: PWR = Power Supply, O = Output, I = Input, ANA = Analog Signal, DIG = Digital Output, ST= Schmitt Buffer Input,
TTL = TTL Buffer Input, x = Don’t care (TRIS bit does not affect port direction or is overridden for this option).
RF0/AN5 RF0 0 O DIG LATF<0> data output; not affected by analog input.
1 I ST PORTF<0> data input; disabled when analog input enabled.
AN5 1 I ANA A/D input channel 5. Default configuration on POR.
RF1/AN6/C2OUT RF1 0 O DIG LATF<1> data output; not affected by analog input.
1 I ST PORTF<1> data input; disabled when analog input enabled.
AN6 1 I ANA A/D input channel 6. Default configuration on POR.
C2OUT 0 O DIG Comparator 2 output; takes priority over port data.
RF2/AN7/C1OUT RF2 0 O DIG LATF<2> data output; not affected by analog input.
1 I ST PORTF<2> data input; disabled when analog input enabled.
AN7 1 I ANA A/D input channel 7. Default configuration on POR.
C1OUT 0 O TTL Comparator 1 output; takes priority over port data.
RF3/AN8 RF3 0 O DIG LATF<3> data output; not affected by analog input.
1 I ST PORTF<3> data input; disabled when analog input enabled.
AN8 1 I ANA A/D input channel 8 and Comparator C2+ input. Default input
configuration on POR; not affected by analog output.
RF4/AN9 RF4 0 O DIG LATF<4> data output; not affected by analog input.
1 I ST PORTF<4> data input; disabled when analog input enabled.
AN9 1 I ANA A/D input channel 9 and Comparator C2- input. Default input
configuration on POR; does not affect digital output.
RF5/AN10/CVREF RF5 0 O DIG LATF<5> data output; not affected by analog input. Disabled when
CVREF output enabled.
1 I ST PORTF<5> data input; disabled when analog input enabled. Disabled
when CVREF output enabled.
AN10 1 I ANA A/D input channel 10 and Comparator C1+ input. Default input
configuration on POR; not affected by analog output.
CVREF x O ANA Comparator voltage reference output. Enabling this feature disables
digital I/O.
RF6/AN11 RF6 0 O DIG LATF<6> data output; not affected by analog input.
1 I ST PORTF<6> data input; disabled when analog input enabled.
AN11 1 I ANA A/D input channel 11 and Comparator C1- input. Default input
configuration on POR; does not affect digital output.
RF7/SS1 RF7 0 O DIG LATF<7> data output.
1 I ST PORTF<7> data input.
SS1 1 I TTL Slave select input for SSP (MSSP1 module).
Legend: PWR = Power Supply, O = Output, I = Input, ANA = Analog Signal, DIG = Digital Output, ST = Schmitt Buffer Input,
TTL = TTL Buffer Input, x = Don’t care (TRIS bit does not affect port direction or is overridden for this option).
The timing for the control signals in Write and Read Note: I/O pin has protection diodes to VDD and VSS.
modes is shown in Figure 11-3 and Figure 11-4,
respectively.
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
CS
WR
RD
PORTD<7:0>
IBF
OBF
PSPIF
CS
WR
RD
PORTD<7:0>
IBF
OBF
PSPIF
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
FOSC/4 0
1
Sync with Set
1 Internal TMR0L TMR0IF
T0CKI pin Programmable 0 Clocks on Overflow
Prescaler
T0SE (2 TCY Delay)
T0CS 8
3
T0PS<2:0>
8
PSA Internal Data Bus
Note: Upon Reset, Timer0 is enabled in 8-bit mode with clock input from T0CKI max. prescale.
FOSC/4 0
1
Sync with Set
1 Internal TMR0L TMR0
High Byte TMR0IF
T0CKI pin Programmable 0 Clocks on Overflow
Prescaler 8
T0SE (2 TCY Delay)
T0CS 3 Read TMR0L
T0PS<2:0>
Write TMR0L
PSA
8
8
TMR0H
8
8
Internal Data Bus
Note: Upon Reset, Timer0 is enabled in 8-bit mode with clock input from T0CKI max. prescale.
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
T1OSO/T13CKI 1
Prescaler Synchronize
FOSC/4 0
1, 2, 4, 8 Detect
Internal
Clock 0
T1OSI 2
Sleep Input
T1OSCEN (1) TMR1CS Timer1
On/Off
T1CKPS<1:0>
T1SYNC
TMR1ON
TMR1 Set
Clear TMR1 TMR1L TMR1IF
High Byte
(CCP Special Event Trigger) on Overflow
Note 1: When enable bit, T1OSCEN, is cleared, the inverter and feedback resistor are turned off to eliminate power drain.
TMR1 Set
Clear TMR1 TMR1L TMR1IF
High Byte
(CCP Special Event Trigger) on Overflow
8
Read TMR1L
Write TMR1L
8
8
TMR1H
8
8
Internal Data Bus
Note 1: When enable bit, T1OSCEN, is cleared, the inverter and feedback resistor are turned off to eliminate power drain.
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
4 1:1 to 1:16
T2OUTPS<3:0> Set TMR2IF
Postscaler
2
T2CKPS<1:0> TMR2 Output
(to PWM or MSSP)
TMR2/PR2
Reset Match
1:1, 1:4, 1:16
FOSC/4 TMR2 Comparator PR2
Prescaler
8 8
8
Internal Data Bus
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
Note 1: When enable bit, T1OSCEN, is cleared, the inverter and feedback resistor are turned off to eliminate power drain.
Read TMR1L
Write TMR1L
8
8
TMR3H
8
8
Internal Data Bus
Note 1: When enable bit, T1OSCEN, is cleared, the inverter and feedback resistor are turned off to eliminate power drain.
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
Sets Flag
TMR4
Output(1) bit TMR4IF
Prescaler Reset
FOSC/4 TMR4
1:1, 1:4, 1:16
2 Postscaler
Comparator
EQ 1:1 to 1:16
T4CKPS<1:0>
PR4 4
T4OUTPS<3:0>
REGISTER 17-1: CCPxCON: CCPx CONTROL REGISTER (CCP4 AND CCP5 MODULES)
U-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0
— — DCxB1 DCxB0 CCPxM3 CCPxM2 CCPxM1 CCPxM0
bit 7 bit 0
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
Timer1 is used for all Capture Timer1 and Timer2 are used Timer1 and Timer2 are used Timer3 is used for all Capture
and Compare operations for for Capture and Compare or for Capture and Compare or and Compare operations for
all CCP modules. Timer2 is PWM operations for ECCP1 PWM operations for ECCP1 all CCP modules. Timer4 is
used for PWM operations for only (depending on selected and ECCP2 only (depending used for PWM operations for
all CCP modules. Modules mode). on the mode selected for each all CCP modules. Modules
may share either timer All other modules use either module). Both modules may may share either timer
resource as a common time Timer3 or Timer4. Modules use a timer as a common time resource as a common time
base. may share either timer base if they are both in base.
Timer3 and Timer4 are not resource as a common time Capture/Compare or PWM Timer1 and Timer2 are not
available. base if they are in Capture/ modes. available.
Compare or PWM modes. The other modules use either
Timer3 or Timer4. Modules
may share either timer
resource as a common time
base if they are in Capture/
Compare or PWM modes.
TMR3H TMR3L
Set Flag bit CCP4IF
T3CCP2 TMR3
Prescaler
Enable
÷ 1, 4, 16
RG3/CCP4 pin CCPR4H CCPR4L
TMR1
and
T3CCP2 Enable
Edge Detect
TMR1H TMR1L
CCP1CON<3:0>
Q’s
Q S Output
Logic Comparator
RG3/CCP4 pin R Match
TRISG<3>
Output Enable CCP4CON<3:0> T3CCP2 0 1
Mode Select
Note 1: The 8-bit TMR2 or TMR4 value is concatenated with the EQUATION 17-2:
2-bit internal Q clock, or 2 bits of the prescaler, to cre-
ate the 10-bit time base. PWM Duty Cycle = (CCPRxL:CCPxCON<5:4>) •
TOSC • (TMR2 Prescale Value)
A PWM output (Figure 17-5) has a time base (period)
and a time that the output stays high (duty cycle). CCPRxL and CCPxCON<5:4> can be written to at any
The frequency of the PWM is the inverse of the time, but the duty cycle value is not latched into
period (1/period). CCPRxH until after a match between PR2 (PR4) and
TMR2 (TMR4) occurs (i.e., the period is complete). In
FIGURE 17-5: PWM OUTPUT PWM mode, CCPRxH is a read-only register.
Period
Duty Cycle
REGISTER 18-1: CCPxCON: ENHANCED CCPx CONTROL REGISTER (ECCP1, ECCP2, ECCP3)
R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0
PxM1 PxM0 DCxB1 DCxB0 CCPxM3 CCPxM2 CCPxM1 CCPxM0
bit 7 bit 0
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
TRISx<x>
CCPR1H (Slave)
P1B P1B
Output TRISx<x>
Comparator R Q
Controller
P1C
P1C
TMR2 (Note 1)
S TRISx<x>
P1D P1D
Comparator
Clear Timer, TRISx<x>
set ECCP1 pin and
latch D.C.
PR2 ECCP1DEL
Note: The 8-bit TMR2 register is concatenated with the 2-bit internal Q clock, or 2 bits of the prescaler, to create the 10-bit time base.
18.4.2 PWM DUTY CYCLE The CCPR1H register and a 2-bit internal latch are
used to double-buffer the PWM duty cycle. This
The PWM duty cycle is specified by writing to the
double-buffering is essential for glitchless PWM opera-
CCPR1L register and to the CCP1CON<5:4> bits. Up
tion. When the CCPR1H and 2-bit latch match TMR2,
to 10-bit resolution is available. The CCPR1L contains
concatenated with an internal 2-bit Q clock or two bits
the eight MSbs and the CCP1CON<5:4> contains the
of the TMR2 prescaler, the ECCP1 pin is cleared. The
two LSbs. This 10-bit value is represented by
maximum PWM resolution (bits) for a given PWM
CCPR1L:CCP1CON<5:4>. The PWM duty cycle is
frequency is given by the equation:
calculated by the equation:
EQUATION 18-3:
EQUATION 18-2:
PWM Duty Cycle = (CCPR1L:CCP1CON<5:4>) • log FOSC ( ) bits
TOSC • (TMR2 Prescale Value) FPWM
PWM Resolution (max) =
log(2)
CCPR1L and CCP1CON<5:4> can be written to at any
time but the duty cycle value is not copied into
CCPR1H until a match between PR2 and TMR2 occurs Note: If the PWM duty cycle value is longer than
(i.e., the period is complete). In PWM mode, CCPR1H the PWM period, the ECCP1 pin will not
is a read-only register. be cleared.
P1A Active
P1D Modulated
P1A Inactive
P1D Inactive
Relationships:
• Period = 4 * TOSC * (PR2 + 1) * (TMR2 Prescale Value)
• Duty Cycle = TOSC * (CCPR1L<7:0>:CCP1CON<5:4>) * (TMR2 Prescale Value)
• Delay = 4 * TOSC * (ECCP1DEL<6:0>)
Note 1: Dead-band delay is programmed using the ECCP1DEL register (Section 18.4.6 “Programmable
Dead-Band Delay”).
P1A Modulated
Delay(1) Delay(1)
10 (Half-Bridge) P1B Modulated
P1A Active
P1D Modulated
P1A Inactive
P1D Inactive
Relationships:
• Period = 4 * TOSC * (PR2 + 1) * (TMR2 Prescale Value)
• Duty Cycle = TOSC * (CCPR1L<7:0>:CCP1CON<5:4>) * (TMR2 Prescale Value)
• Delay = 4 * TOSC * (ECCP1DEL<6:0>)
Note 1: Dead-band delay is programmed using the ECCP1DEL register (Section 18.4.6 “Programmable
Dead-Band Delay”).
PIC18F6X27/6X22/8X27/8X22 FET
Driver +
P1A V
-
Load
FET
Driver
+
P1B V
-
V-
Half-Bridge Output Driving a Full-Bridge Circuit
V+
PIC18F6X27/6X22/8X27/8X22
FET FET
Driver Driver
P1A
Load
FET FET
Driver Driver
P1B
V-
Forward Mode
Period
P1A(2)
Duty Cycle
P1B(2)
P1C(2)
P1D(2)
(1) (1)
Reverse Mode
Period
Duty Cycle
P1A(2)
P1B(2)
P1C(2)
P1D(2)
(1) (1)
Note 1: At this time, the TMR2 register is equal to the PR2 register.
Note 2: Output signal is shown as active-high.
Load
P1B
FET FET
Driver Driver
P1C
QB QD
V-
P1D
18.4.5.1 Direction Change in Full-Bridge Mode Figure 18-9 shows an example where the PWM direc-
tion changes from forward to reverse at a near 100%
In the Full-Bridge Output mode, the P1M1 bit in the
duty cycle. At time, t1, the outputs P1A and P1D
CCP1CON register allows users to control the forward/
become inactive, while output P1C becomes active. In
reverse direction. When the application firmware
this example, since the turn-off time of the power
changes this direction control bit, the module will
devices is longer than the turn-on time, a shoot-through
assume the new direction on the next PWM cycle.
current may flow through power devices QC and QD
Just before the end of the current PWM period, the (see Figure 18-7) for the duration of ‘t’. The same
modulated outputs (P1B and P1D) are placed in their phenomenon will occur to power devices QA and QB
inactive state, while the unmodulated outputs (P1A and for PWM direction change from reverse to forward.
P1C) are switched to drive in the opposite direction.
If changing PWM direction at high duty cycle is required
This occurs in a time interval of (4 TOSC * (Timer2
for an application, one of the following requirements
Prescale Value)) before the next PWM period begins.
must be met:
The Timer2 prescaler will be either 1, 4 or 16, depend-
ing on the value of the T2CKPSx bit (T2CON<1:0>). 1. Reduce PWM for a PWM period before
During the interval from the switch of the unmodulated changing directions.
outputs to the beginning of the next period, the 2. Use switch drivers that can drive the switches off
modulated outputs (P1B and P1D) remain inactive. faster than they can drive them on.
This relationship is shown in Figure 18-8.
Other options to prevent shoot-through current may
Note that in the Full-Bridge Output mode, the ECCP1 exist.
module does not provide any dead-band delay. In gen-
eral, since only one output is modulated at all times,
dead-band delay is not required. However, there is a
situation where a dead-band delay might be required.
This situation occurs when both of the following
conditions are true:
1. The direction of the PWM output changes when
the duty cycle of the output is at or near 100%.
2. The turn-off time of the power switch, including
the power device and driver circuit, is greater
than the turn-on time.
P1A (Active-High)
P1B (Active-High)
DC
P1C (Active-High)
(Note 2)
P1D (Active-High)
DC
Note 1: The direction bit in the ECCP1 Control register (CCP1CON<7>) is written any time during the PWM cycle.
2: When changing directions, the P1A and P1C signals switch before the end of the current PWM cycle at intervals
of 4 TOSC, 16 TOSC or 64 TOSC, depending on the Timer2 prescaler value. The modulated P1B and P1D signals
are inactive at this time.
P1A
P1B DC
P1C
P1D DC
tON(2)
External Switch C
tOFF(3)
External Switch D
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
Shutdown Event
ECCP1ASE bit
PWM Activity
Normal PWM
ECCP1ASE bit
PWM Activity
Normal PWM
ECCP1ASE
Cleared by
Start of Shutdown Shutdown Firmware PWM
PWM Period Event Occurs Event Clears Resumes
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
Note 1: In Master mode, the overflow bit is not set since each new reception (and transmission) is initiated by
writing to the SSPxBUF register.
2: When enabled, these pins must be properly configured as input or output.
3: Bit combinations not specifically listed here are either reserved or implemented in I2C™ mode only.
SDOx SDIx
Write to
SSPxBUF
SCKx
(CKP = 0
CKE = 0)
SCKx
(CKP = 1
CKE = 0)
4 Clock
SCKx Modes
(CKP = 0
CKE = 1)
SCKx
(CKP = 1
CKE = 1)
Input
Sample
(SMP = 1)
SSPxIF
Next Q4 Cycle
SSPxSR to after Q2↓
SSPxBUF
SSx
SCKx
(CKP = 0
CKE = 0)
SCKx
(CKP = 1
CKE = 0)
Write to
SSPxBUF
SDIx bit 0
(SMP = 0) bit 7 bit 7
Input
Sample
(SMP = 0)
SSPxIF
Interrupt
Flag
Next Q4 Cycle
SSPxSR to after Q2↓
SSPxBUF
SSx
Optional
SCKx
(CKP = 0
CKE = 0)
SCKx
(CKP = 1
CKE = 0)
Write to
SSPxBUF
SDIx
(SMP = 0) bit 7 bit 0
Input
Sample
(SMP = 0)
SSPxIF
Interrupt
Flag
Next Q4 Cycle
SSPxSR to after Q2↓
SSPxBUF
SSx
Not Optional
SCKx
(CKP = 0
CKE = 1)
SCKx
(CKP = 1
CKE = 1)
Write to
SSPxBUF
SDIx
(SMP = 0) bit 0
bit 7
Input
Sample
(SMP = 0)
SSPxIF
Interrupt
Flag
Next Q4 Cycle
after Q2↓
SSPxSR to
SSPxBUF
SSPxADD reg
Note: Only port I/O names are used in this diagram for
the sake of brevity. Refer to the text for a full list of
multiplexed functions.
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
Note 1: When enabled, the SDAx and SCLx pins must be configured as input.
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
Note 1: Value that will be transmitted when the user initiates an Acknowledge sequence at the end of a receive.
2: For bits ACKEN, RCEN, PEN, RSEN, SEN: If the I2C™ module is active, these bits may not be set (no
spooling) and the SSPxBUF may not be written (or writes to the SSPxBUF are disabled).
SDAx A7 A6 A5 A4 A3 A2 A1 ACK D7 D6 D5 D4 D3 D2 D1 D0 D7 D6 D5 D4 D3 D2 D1 D0
SCLx 1 2 3 4 5 6 7 8 9 1 2 3 4 5 6 7 8 9 1 2 3 4 5 6 7 8 9
S P
BF (SSPxSTAT<0>)
Cleared in software
SSPxBUF is read
SSPOV (SSPxCON1<6>)
SSPOV is set
because SSPxBUF is
still full. ACK is not sent.
CKP
(CKP does not reset to ‘0’ when SEN = 0)
I2C™ SLAVE MODE TIMING WITH SEN = 0 (RECEPTION, 7-BIT ADDRESS)
PIC18F8722 FAMILY
DS39646C-page 221
FIGURE 19-9:
DS39646C-page 222
Receiving Address R/W = 0 Transmitting Data Transmitting Data
ACK ACK
SDAx A7 A6 A5 A4 A3 A2 A1 ACK D7 D6 D5 D4 D3 D2 D1 D0 D7 D6 D5 D4 D3 D2 D1 D0
SCLx
1 2 3 4 5 6 7 8 9 1 2 3 4 5 6 7 8 9 1 2 3 4 5 6 7 8 9
S
Data in SCLx held low P
sampled while CPU
responds to SSPxIF
BF (SSPxSTAT<0>)
Cleared in software Cleared in software
From SSPxIF ISR From SSPxIF ISR
SSPxBUF is written in software SSPxBUF is written in software
CKP
Receive First Byte of Address Receive Second Byte of Address Receive Data Byte Receive Data Byte
R/W = 0 ACK
Bus master
terminates
SSPxIF (PIR1<3> or PIR3<7>) transfer
BF (SSPxSTAT<0>)
SSPOV is set
because SSPxBUF is
still full. ACK is not sent.
UA (SSPxSTAT<1>)
CKP
(CKP does not reset to ‘0’ when SEN = 0)
I2C™ SLAVE MODE TIMING WITH SEN = 0 (RECEPTION, 10-BIT ADDRESS)
PIC18F8722 FAMILY
DS39646C-page 223
FIGURE 19-11:
DS39646C-page 224
Bus master
terminates
Clock is held low until Clock is held low until transfer
update of SSPxADD has update of SSPxADD has Clock is held low until
taken place taken place CKP is set to ‘1’
R/W = 0
Receive First Byte of Address Receive Second Byte of Address Receive First Byte of Address R/W = 1 Transmitting Data Byte ACK
SDAx 1 1 1 1 0 A9 A8 ACK A7 A6 A5 A4 A3 A2 A1 A0 ACK 1 1 1 1 0 A9 A8 ACK D7 D6 D5 D4 D3 D2 D1 D0
SCLx 1 2 3 4 5 6 7 8 9 1 2 3 4 5 6 7 8 9 1 2 3 4 5 6 7 8 9 1 2 3 4 5 6 7 8 9
S Sr P
PIC18F8722 FAMILY
BF (SSPxSTAT<0>)
Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4
SDAx DX DX – 1
SCLx
Master device
CKP asserts clock
Master device
deasserts clock
WR
SSPxCON1
SDAx A7 A6 A5 A4 A3 A2 A1 ACK D7 D6 D5 D4 D3 D2 D1 D0 D7 D6 D5 D4 D3 D2 D1 D0
SCLx 1 2 3 4 5 6 7 8 9 1 2 3 4 5 6 7 8 9 1 2 3 4 5 6 7 8 9
S P
BF (SSPxSTAT<0>)
Cleared in software
SSPxBUF is read
SSPOV (SSPxCON1<6>)
SSPOV is set
because SSPxBUF is
still full. ACK is not sent.
CKP
CKP
If BF is cleared written
prior to the falling to ‘1’ in
edge of the 9th clock, software
CKP will not be reset BF is set after falling
to ‘0’ and no clock edge of the 9th clock,
stretching will occur CKP is reset to ‘0’ and
clock stretching occurs
I2C™ SLAVE MODE TIMING WITH SEN = 1 (RECEPTION, 7-BIT ADDRESS)
PIC18F8722 FAMILY
DS39646C-page 227
FIGURE 19-14:
DS39646C-page 228
Clock is held low until
update of SSPxADD has update of SSPxADD has Clock is not held low
Clock is held low until
taken place taken place because ACK = 1
CKP is set to ‘1’
Receive First Byte of Address Receive Second Byte of Address Receive Data Byte Receive Data Byte
R/W = 0 ACK
ACK ACK
SDAx 1 1 1 1 0 A9 A8 ACK A7 A6 A5 A4 A3 A2 A1 A0 D7 D6 D5 D4 D3 D2 D1 D0 D7 D6 D5 D4 D3 D2 D1 D0
SCLx 1 2 3 4 5 6 7 8 9 1 2 3 4 5 6 7 8 9 1 2 3 4 5 6 7 8 9 1 2 3 4 5 6 7 8 9
S P
BF (SSPxSTAT<0>)
SSPOV is set
because SSPxBUF is
still full. ACK is not sent.
UA (SSPxSTAT<1>)
SCLx
1 2 3 4 5 6 7 8 9 1 2 3 4 5 6 7 8 9
S
SSPxIF
BF (SSPxSTAT<0>)
Cleared in software
SSPxBUF is read
SSPOV (SSPxCON1<6>) ‘0 ’
GCEN (SSPxCON2<7>)
‘1 ’
Internal SSPM<3:0>
Data Bus SSPxADD<6:0>
Read Write
SSPxBUF Baud
Rate
Generator
SDAx Shift
Clock Arbitrate/WCOL Detect
SDAx In Clock
SSPxSR
(hold off clock source)
MSb LSb
Receive Enable
Acknowledge
Generate
SCLx
SSPM<3:0> SSPxADD<6:0>
SDAx DX DX – 1
BRG decrements on
Q2 and Q4 cycles
BRG
03h 02h 01h 00h (hold off) 03h 02h
Value
SCLx
TBRG
S
Sr = Repeated Start
BF (SSPxSTAT<0>)
PEN
R/W
I 2C™ MASTER MODE WAVEFORM (TRANSMISSION, 7 OR 10-BIT ADDRESS)
PIC18F8722 FAMILY
DS39646C-page 237
FIGURE 19-22:
DS39646C-page 238
Write to SSPxCON2<4>
to start Acknowledge sequence,
SDAx = ACKDT (SSPxCON2<5>) = 0
Write to SSPxCON2<0> (SEN = 1),
begin Start condition ACK from master, Set ACKEN, start Acknowledge sequence,
Master configured as a receiver SDAx = ACKDT = 0 SDAx = ACKDT = 1
SEN = 0 by programming SSPxCON2<3> (RCEN = 1)
PEN bit = 1
Write to SSPxBUF occurs here, RCEN cleared RCEN = 1, start RCEN cleared
ACK from Slave next receive automatically written here
start XMIT automatically
Transmit Address to Slave R/W = 0 Receiving Data from Slave Receiving Data from Slave
SDAx A7 A6 A5 A4 A3 A2 A1 ACK D7 D6 D5 D4 D3 D2 D1 D0 ACK D7 D6 D5 D4 D3 D2 D1 D0 ACK
Bus master
ACK is not sent terminates
transfer
1 2 3 4 5 6 7 8 9 1 2 3 4 5 6 7 8 9 1 2 3 4 5 6 7 8 9
SCLx S P
PIC18F8722 FAMILY
Set P bit
Cleared in software Cleared in software Cleared in software Cleared in software (SSPxSTAT<4>)
Cleared in
SDAx = 0, SCLx = 1, software and SSPxIF
while CPU
responds to SSPxIF
BF
(SSPxSTAT<0>) Last bit is shifted into SSPxSR and
contents are unloaded into SSPxBUF
SSPOV
ACKEN
I 2C™ MASTER MODE WAVEFORM (RECEPTION, 7-BIT ADDRESS)
SCLx 8 9
SSPxIF
Cleared in
SSPxIF set at software
the end of receive Cleared in
software SSPxIF set at the end
of Acknowledge sequence
Note: TBRG = one Baud Rate Generator period.
TBRG
SCLx
SDAx ACK
P
TBRG TBRG TBRG
SCLx brought high after TBRG
SDAx asserted low before rising edge of clock
to setup Stop condition
SDAx
BCLxIF
SDAx
SCLx
Set SEN, enable Start SEN cleared automatically because of bus collision.
condition if SDAx = 1, SCLx = 1 MSSP module reset into Idle state.
SEN
SDAx sampled low before
Start condition. Set BCLxIF.
S bit and SSPxIF set because
BCLxIF SDAx = 0, SCLx = 1.
SSPxIF and BCLxIF are
cleared in software
SSPxIF
TBRG TBRG
SDAx
FIGURE 19-28: BRG RESET DUE TO SDAx ARBITRATION DURING START CONDITION
SDAx = 0, SCLx = 1
Set S Set SSPxIF
Less than TBRG
TBRG
SCLx S
SCLx pulled low after BRG
time-out
SEN
Set SEN, enable START
sequence if SDAx = 1, SCLx = 1
BCLxIF ‘0’
SSPxIF
SDAx = 0, SCLx = 1, Interrupts cleared
set SSPxIF in software
SDAx
SCLx
RSEN
BCLxIF
Cleared in software
S ‘0’
SSPxIF ‘0’
TBRG TBRG
SDAx
SCLx
S ‘0’
SSPxIF
PEN
BCLxIF
P ‘0’
SSPxIF ‘0’
SDAx
SCLx goes low before SDAx goes high,
Assert SDAx
set BCLxIF
SCLx
PEN
BCLxIF
P ‘0’
SSPxIF ‘0’
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
0.3 — — — — — — — — — — — —
1.2 — — — 1.221 1.73 255 1.202 0.16 129 1.201 -0.16 103
2.4 2.441 1.73 255 2.404 0.16 129 2.404 0.16 64 2.403 -0.16 51
9.6 9.615 0.16 64 9.766 1.73 31 9.766 1.73 15 9.615 -0.16 12
19.2 19.531 1.73 31 19.531 1.73 15 19.531 1.73 7 — — —
57.6 56.818 -1.36 10 62.500 8.51 4 52.083 -9.58 2 — — —
115.2 125.000 8.51 4 104.167 -9.58 2 78.125 -32.18 1 — — —
0.3 — — — — — — — — — — — —
1.2 — — — — — — — — — — — —
2.4 — — — — — — 2.441 1.73 255 2.403 -0.16 207
9.6 9.766 1.73 255 9.615 0.16 129 9.615 0.16 64 9.615 -0.16 51
19.2 19.231 0.16 129 19.231 0.16 64 19.531 1.73 31 19.230 -0.16 25
57.6 58.140 0.94 42 56.818 -1.36 21 56.818 -1.36 10 55.555 3.55 8
115.2 113.636 -1.36 21 113.636 -1.36 10 125.000 8.51 4 — — —
0.3 0.300 0.00 8332 0.300 0.02 4165 0.300 0.02 2082 0.300 -0.04 1665
1.2 1.200 0.02 2082 1.200 -0.03 1041 1.200 -0.03 520 1.201 -0.16 415
2.4 2.402 0.06 1040 2.399 -0.03 520 2.404 0.16 259 2.403 -0.16 207
9.6 9.615 0.16 259 9.615 0.16 129 9.615 0.16 64 9.615 -0.16 51
19.2 19.231 0.16 129 19.231 0.16 64 19.531 1.73 31 19.230 -0.16 25
57.6 58.140 0.94 42 56.818 -1.36 21 56.818 -1.36 10 55.555 3.55 8
115.2 113.636 -1.36 21 113.636 -1.36 10 125.000 8.51 4 — — —
0.3 0.300 0.04 832 0.300 -0.16 415 0.300 -0.16 207
1.2 1.202 0.16 207 1.201 -0.16 103 1.201 -0.16 51
2.4 2.404 0.16 103 2.403 -0.16 51 2.403 -0.16 25
9.6 9.615 0.16 25 9.615 -0.16 12 — — —
19.2 19.231 0.16 12 — — — — — —
57.6 62.500 8.51 3 — — — — — —
115.2 125.000 8.51 1 — — — — — —
0.3 0.300 0.00 33332 0.300 0.00 16665 0.300 0.00 8332 0.300 -0.01 6665
1.2 1.200 0.00 8332 1.200 0.02 4165 1.200 0.02 2082 1.200 -0.04 1665
2.4 2.400 0.02 4165 2.400 0.02 2082 2.402 0.06 1040 2.400 -0.04 832
9.6 9.606 0.06 1040 9.596 -0.03 520 9.615 0.16 259 9.615 -0.16 207
19.2 19.193 -0.03 520 19.231 0.16 259 19.231 0.16 129 19.230 -0.16 103
57.6 57.803 0.35 172 57.471 -0.22 86 58.140 0.94 42 57.142 0.79 34
115.2 114.943 -0.22 86 116.279 0.94 42 113.636 -1.36 21 11.7647 -2.12 16
0.3 0.300 0.01 3332 0.300 -0.04 1665 0.300 -0.04 832
1.2 1.200 0.04 832 1.201 -0.16 415 1.201 -0.16 207
2.4 2.404 0.16 415 2.403 -0.16 207 2.403 -0.16 103
9.6 9.615 0.16 103 9.615 -0.16 51 9.615 -0.16 25
19.2 19.231 0.16 51 19.230 -0.16 25 19.230 -0.16 12
57.6 58.824 2.12 16 55.555 3.55 8 — — —
115.2 111.111 -3.55 8 — — — — — —
BRG Clock
RCxIF bit
(Interrupt)
Read
RCREGx
Note: The ABD sequence requires the EUSART module to be configured in Asynchronous mode and WUE = 0.
BRG Clock
ABDEN bit
ABDOVF bit
FFFFh
BRG Value XXXXh 0000h 0000h
TRMT SPEN
BRG16 SPBRGHx SPBRGx
TX9
Baud Rate Generator TX9D
Write to TXREGx
Word 1
BRG Output
(Shift Clock)
TXx (pin)
Start bit bit 0 bit 1 bit 7/8 Stop bit
Word 1
TXxIF bit
(Transmit Buffer 1 TCY
Reg. Empty Flag)
Write to TXREGx
Word 1 Word 2
BRG Output
(Shift Clock)
TXx (pin)
Start bit bit 0 bit 1 bit 7/8 Stop bit Start bit bit 0
RX9
SPEN
8
RCxIF
(Interrupt Flag)
OERR bit
CREN
Note: This timing diagram shows three words appearing on the RXx input. The RCREGx (receive buffer) is read after the third word
causing the OERR (Overrun) bit to be set.
RXx/DTx Line
RCxIF
Cleared due to user read of RCREGx
Note 1: The EUSART remains inactive while the WUE bit is set.
RXx/DTx Line
Note 1
RCxIF
Cleared due to user read of RCREGx
Sleep Command Executed Sleep Ends
Note 1: If the wake-up event requires long oscillator warm-up time, the auto-clear of the WUE bit can occur before the oscillator is ready. This
sequence should not depend on the presence of Q clocks.
2: The EUSART remains inactive while the WUE bit is set.
20.2.5.1 Break and Sync Transmit Sequence The second method uses the auto-wake-up feature
described in Section 20.2.4 “Auto-Wake-up on Sync
The following sequence will send a message frame Break Character”. By enabling this feature, the
header made up of a Break, followed by an Auto-Baud EUSART will sample the next two transitions on RXx/
Sync byte. This sequence is typical of a LIN bus DTx, cause an RCxIF interrupt and receive the next
master. data byte followed by another interrupt.
Note that following a Break character, the user will
typically want to enable the Auto-Baud Rate Detect
feature. For both methods, the user can set the ABD bit
once the TXxIF interrupt is observed.
Write to TXREGx
Dummy Write
BRG Output
(Shift Clock)
Break
TXxIF bit
(Transmit Buffer
Reg. Empty Flag)
TRMT bit
(Transmit Shift
Reg. Empty Flag)
SENDB sampled here Auto-Cleared
SENDB
(Transmit Shift
Reg. Empty Flag)
DTx
bit 0 bit 1 bit 2 bit 7 bit 0 bit 1 bit 7
Word 1 Word 2
CKx pin
(SCKP = 0)
CKx pin
(SCKP = 1)
Write to
TXREGx Reg Write Word 1 Write Word 2
TXxIF bit
(Interrupt Flag)
TRMT bit
Note: Sync Master mode, SPBRGx = 0, continuous transmission of two 8-bit words.
CKx pin
Write to
TXREGx reg
TXxIF bit
TRMT bit
TXEN bit
DTx pin
bit 0 bit 1 bit 2 bit 3 bit 4 bit 5 bit 6 bit 7
CKx pin
(SCKP = 0)
CKx pin
(SCKP = 1)
Write to
bit SREN
SREN bit
CREN bit ‘0’ ‘0’
RCxIF bit
(Interrupt)
Read
RCREGx
Note: Timing diagram demonstrates Sync Master mode with bit SREN = 1 and bit BRGH = 0.
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
AN14(1)
AN13(1)
AN12(1)
AN10
AN11
AN9
AN8
AN7
AN6
AN5
AN4
AN3
AN2
AN1
AN0
PCFG<3:0>
0000 A A A A A A A A A A A A A A A A
0001 D D A A A A A A A A A A A A A A
0010 D D D A A A A A A A A A A A A A
0011 D D D D A A A A A A A A A A A A
0100 D D D D D A A A A A A A A A A A
0101 D D D D D D A A A A A A A A A A
0110 D D D D D D D A A A A A A A A A
0111 D D D D D D D D A A A A A A A A
1000 D D D D D D D D D A A A A A A A
1001 D D D D D D D D D D A A A A A A
1010 D D D D D D D D D D D A A A A A
1011 D D D D D D D D D D D D A A A A
1100 D D D D D D D D D D D D D A A A
1101 D D D D D D D D D D D D D D A A
1110 D D D D D D D D D D D D D D D A
1111 D D D D D D D D D D D D D D D D
A = Analog input D = Digital I/O
Note 1: AN15 through AN12 are available only on 80-pin devices.
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
Note 1: If the A/D FRC clock source is selected, a delay of one TCY (instruction cycle) is added before the A/D
clock starts. This allows the SLEEP instruction to be executed before starting a conversion.
1111
AN15(1)
1110
AN14(1)
1101
AN13(1)
1100
AN12(1)
1011
AN11
1010
AN10
1001
AN9
1000
AN8
0111
AN7
0110
AN6
0101
AN5
0100
AN4
VAIN
(Input Voltage) 0011
10-Bit AN3
A/D
Converter 0010
AN2
0001
VCFG<1:0> AN1
AVDD 0000
AN0
X0
VREF+ X1
Reference 1X
Voltage VREF- 0X
AVSS
Note 1: Channels AN12 through AN15 are not available on 64-pin devices.
2: I/O pins have diode protection to VDD and VSS.
1022 LSB
1022.5 LSB
1023 LSB
1023.5 LSB
• Set GIE bit
3. Wait the required acquisition time (if required).
4. Start conversion:
Analog Input Voltage
• Set GO/DONE bit (ADCON0 register)
VSS
FIGURE 21-5: A/D CONVERSION TAD CYCLES (ACQT<2:0> = 010, TACQ = 4 TAD)
1 2 3 4 1 2 3 4 5 6 7 8 9 10 11 TAD1
b9 b8 b7 b6 b5 b4 b3 b2 b1 b0
Automatic
Acquisition Conversion starts Discharge
Time (Holding capacitor is disconnected)
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
RF1/AN6/C2OUT*
Two Common Reference Comparators Two Common Reference Comparators with Outputs
CM<2:0> = 100 CM<2:0> = 101
RF6/AN11 A VIN- RF6/AN11 A VIN-
RF1/AN6/C2OUT*
One Independent Comparator with Output Four Inputs Multiplexed to Two Comparators
CM<2:0> = 001 CM<2:0> = 110
RF6/AN11 A VIN-
RF6/AN11 A
CIS = 0 VIN-
VIN+ C1 C1OUT RF5/AN10/ A CIS = 1
RF5/AN10/ A VIN+ C1 C1OUT
CVREF CVREF
RF2/AN7/ RF4/AN9 A
C1OUT* CIS = 0 VIN-
RF3/AN8 A CIS = 1
D VIN- VIN+ C2 C2OUT
RF4/AN9
D VIN+ C2 Off (Read as ‘0’)
RF3/AN8 CVREF
From VREF Module
A = Analog Input, port reads zeros always D = Digital Input CIS (CMCON<3>) is the Comparator Input Switch
* Setting the TRISF<2:1> bits will disable the comparator outputs by configuring the pins as inputs.
MULTIPLEX
+
Port pins
CxOUT
-
D Q Bus
CxINV Data
Read CMCON EN
D Q Set
CMIF
bit
EN CL
From
Other
Reset Comparator
VDD
VT = 0.6V RIC
RS < 10k
Comparator
AIN Input
CPIN ILEAKAGE
VA VT = 0.6V ±500 nA
5 pF
VSS
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
CVRSS = 1
VREF+
AVDD
CVRSS = 0 8R
CVR<3:0>
CVREN R
16-to-1 MUX
R
16 Steps
CVREF
R
R
R
CVRR 8R
CVRSS = 1
VREF-
CVRSS = 0
AVSS
PIC18FXXXX
CVREF
R(1)
Module
+
Voltage RF5 CVREF Output
–
Reference
Output
Impedance
Note 1: R is dependent upon the voltage reference Configuration bits, CVRCON<3:0> and CVRCON<5>.
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
HLVDEN VDIRMAG
HLVDIN
16-to-1 MUX
Set
HLVDIF
HLVDEN
Internal Voltage
BOREN Reference
1.2V Typical
VDD
VHLVD
HLVDIF
Enable HLVD
TIRVST
IRVST
HLVDIF cleared in software
Internal Reference is stable
CASE 2:
VDD
VHLVD
HLVDIF
Enable HLVD
TIRVST
IRVST
Internal Reference is stable
HLVDIF cleared in software
VHLVD
VDD
HLVDIF
Enable HLVD
IRVST TIRVST
CASE 2:
VHLVD
VDD
HLVDIF
Enable HLVD
IRVST TIRVST
• Oscillator Selection The user will note that address 300000h is beyond the
user program memory space. In fact, it belongs to the
• Resets:
configuration memory space (300000h-3FFFFFh),
- Power-on Reset (POR)
which can only be accessed using table reads and
- Power-up Timer (PWRT)
table writes.
- Oscillator Start-up Timer (OST)
- Brown-out Reset (BOR) Programming the Configuration registers is done in a
• Interrupts manner similar to programming the Flash memory. The
• Watchdog Timer (WDT) WR bit in the EECON1 register starts a self-timed write
to the Configuration register. In normal operation mode,
• Fail-Safe Clock Monitor
a TBLWT instruction with the TBLPTR pointing to the
• Two-Speed Start-up
Configuration register sets up the address and the data
• Code Protection
for the Configuration register write. Setting the WR bit
• ID Locations starts a long write to the Configuration register. The
• In-Circuit Serial Programming Configuration registers are written a byte at a time. To
The oscillator can be configured for the application write or erase a configuration cell, a TBLWT instruction
depending on frequency, power, accuracy and cost. All can write a ‘1’ or a ‘0’ into the cell. For additional details
of the options are discussed in detail in Section 2.0 on Flash programming, refer to Section 6.5 “Writing
“Oscillator Configurations”. to Flash Program Memory”.
A complete discussion of device Resets and interrupts
is available in previous sections of this data sheet.
In addition to their Power-up and Oscillator Start-up
Timers provided for Resets, the PIC18F8722 family of
devices has a Watchdog Timer, which is either perma-
nently enabled via the Configuration bits or software
controlled (if configured as disabled).
The inclusion of an internal RC oscillator also provides
the additional benefits of a Fail-Safe Clock Monitor
(FSCM) and Two-Speed Start-up. FSCM provides for
background monitoring of the peripheral clock and
automatic switchover in the event of its failure. Two-
Speed Start-up enables code to be executed almost
immediately on start-up, while the primary clock source
completes its start-up delays.
All of these features are enabled and configured by
setting the appropriate Configuration register bits.
300001h CONFIG1H IESO FCMEN — — FOSC3 FOSC2 FOSC1 FOSC0 00-- 0111
300002h CONFIG2L — — — BORV1 BORV0 BOREN1 BOREN0 PWRTEN ---1 1111
300003h CONFIG2H — — — WDTPS3 WDTPS2 WDTPS1 WDTPS0 WDTEN ---1 1111
300004h CONFIG3L(5) WAIT BW ABW1 ABW0 — — PM1 PM0 1111 --11
300005h CONFIG3H MCLRE — — — — LPT1OSC ECCPMX(5) CCP2MX 1--- -011
300006h CONFIG4L DEBUG XINST BBSIZ1 BBSIZ0 — LVP — STVREN 1000 -1-1
300008h CONFIG5L CP7(1) CP6(1) CP5(2) CP4(2) CP3(3) CP2 CP1 CP0 1111 1111
300009h CONFIG5H CPD CPB — — — — — — 11-- ----
30000Ah CONFIG6L WRT7(1) WRT6(1) WRT5(2) WRT4(2) WRT3(3) WRT2 WRT1 WRT0 1111 1111
30000Bh CONFIG6H WRTD WRTB WRTC — — — — — 111- ----
30000Ch CONFIG7L EBRT7(1) EBRT6(1) EBTR5(2) EBTR4(2) EBTR3(3) EBTR2 EBTR1 EBTR0 1111 1111
30000Dh CONFIG7H — EBTRB — — — — — — -1-- ----
(4)
3FFFFEh DEVID1 DEV2 DEV1 DEV0 REV4 REV3 REV2 REV1 REV0 xxxx xxxx
3FFFFFh DEVID2(4) DEV10 DEV9 DEV8 DEV7 DEV6 DEV5 DEV4 DEV3 xxxx xxxx
Legend: x = unknown, u = unchanged, - = unimplemented, q = value depends on condition.
Shaded cells are unimplemented, read as ‘0’.
Note 1: Unimplemented in PIC18F6527/6622/6627/8527/8622/8627 devices.
2: Unimplemented in PIC18F6527/6622/8527/8622 devices.
3: Unimplemented in PIC18F6527/8527 devices.
4: See Register 25-13 for DEVID1 values. DEVID registers are read-only and cannot be programmed by the user.
5: Unimplemented in PIC18F6527/6622/6627/6722 devices.
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
Note 1: See Section 28.1 “DC Characteristics: Supply Voltage” for specifications.
2: The Power-up Timer is decoupled from Brown-out Reset, allowing these features to be independently con-
trolled.
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
Note 1: These values for DEV<10:3> may be shared with other devices. The specific device is always identified by
using the entire DEV<10:0> bit sequence.
WDTPS<4:1> 4
Sleep
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
Note 1: This bit has no effect if the Configuration bit, WDTEN, is enabled.
OSC1
TOST(1) TPLL(1)
1 2 n-1 n
PLL Clock
Output
Clock
Transition(2)
CPU Clock
Peripheral
Clock
Program
Counter PC PC + 2 PC + 4 PC + 6
Note 1: TOST = 1024 TOSC; TPLL = 2 ms (approx). These intervals are not shown to scale.
2: Clock transition typically occurs within 2-4 TOSC.
Sample Clock
Device Oscillator
Clock Failure
Output
CM Output
(Q)
Failure
Detected
OSCFIF
00BFFFh
00C000h
Configuration Block 3 Block 3 Block 3
and ID
Space 00FFFFh
010000h
Block 4 Block 4
013FFFh
014000h
Unimplemented
Block 5 Block 5
Read ‘0’s
3FFFFFh Unimplemented 017FFFh
Read ‘0’s 018000h
Block 6
Unimplemented 01BFFFh
Read ‘0’s 01C000h
Block 7
01FFFFh
25.5.1 PROGRAM MEMORY not allowed to read and will result in reading ‘0’s.
CODE PROTECTION Figures 25-6 through 25-8 illustrate table write and table
read protection.
The program memory may be read to or written from
any location using the table read and table write Note: Code protection bits may only be written to
instructions. The device ID may be read with table a ‘0’ from a ‘1’ state. It is not possible to
reads. The Configuration registers may be read and write a ‘1’ to a bit in the ‘0’ state. Code
written with the table read and table write instructions. protection bits are only set to ‘1’ by a full
In normal execution mode, the CPn bits have no direct chip erase or block erase function. The full
effect. CPn bits inhibit external reads and writes. A block chip erase and block erase functions can
of user memory may be protected from table writes if the only be initiated via ICSP or an external
WRTn Configuration bit is ‘0’. The EBTRn bits control programmer. Refer to the device
table reads. For a block of user memory with the EBTRn programming specification for more
bit set to ‘0’, a table read instruction that executes from information.
within that block is allowed to read. A table read instruc-
tion that executes from a location outside of that block is
TBLPTR = 0008FFh
WRT0, EBTR0 = 01
00FFFFh
000000h
WRTB, EBTRB = 11
0007FFh
000800h
TBLPTR = 0008FFh
WRT0, EBTR0 = 10
003FFFh
004000h
PC = 007FFEh TBLRD* WRT1, EBTR1 = 11
007FFFh
008000h
WRT2, EBTR2 = 11
00BFFFh
00C000h
WRT3, EBTR3 = 11
00FFFFh
Results: All table reads from external blocks to Blockn are disabled whenever EBTRn = 0.
TABLAT register returns a value of ‘0’.
00FFFFh
Literal operations
15 8 7 0
OPCODE k (literal) MOVLW 7Fh
Control operations
CALL, GOTO and Branch operations
15 8 7 0
OPCODE n<7:0> (literal) GOTO Label
15 12 11 0
1111 n<19:8> (literal)
15 8 7 0
OPCODE S n<7:0> (literal) CALL MYFUNC
15 12 11 0
1111 n<19:8> (literal)
S = Fast bit
15 11 10 0
OPCODE n<10:0> (literal) BRA MYFUNC
15 8 7 0
OPCODE n<7:0> (literal) BC MYFUNC
BYTE-ORIENTED OPERATIONS
ADDWF f, d, a Add WREG and f 1 0010 01da ffff ffff C, DC, Z, OV, N 1, 2
ADDWFC f, d, a Add WREG and Carry bit to f 1 0010 00da ffff ffff C, DC, Z, OV, N 1, 2
ANDWF f, d, a AND WREG with f 1 0001 01da ffff ffff Z, N 1,2
CLRF f, a Clear f 1 0110 101a ffff ffff Z 2
COMF f, d, a Complement f 1 0001 11da ffff ffff Z, N 1, 2
CPFSEQ f, a Compare f with WREG, Skip = 1 (2 or 3) 0110 001a ffff ffff None 4
CPFSGT f, a Compare f with WREG, Skip > 1 (2 or 3) 0110 010a ffff ffff None 4
CPFSLT f, a Compare f with WREG, Skip < 1 (2 or 3) 0110 000a ffff ffff None 1, 2
DECF f, d, a Decrement f 1 0000 01da ffff ffff C, DC, Z, OV, N 1, 2, 3, 4
DECFSZ f, d, a Decrement f, Skip if 0 1 (2 or 3) 0010 11da ffff ffff None 1, 2, 3, 4
DCFSNZ f, d, a Decrement f, Skip if Not 0 1 (2 or 3) 0100 11da ffff ffff None 1, 2
INCF f, d, a Increment f 1 0010 10da ffff ffff C, DC, Z, OV, N 1, 2, 3, 4
INCFSZ f, d, a Increment f, Skip if 0 1 (2 or 3) 0011 11da ffff ffff None 4
INFSNZ f, d, a Increment f, Skip if Not 0 1 (2 or 3) 0100 10da ffff ffff None 1, 2
IORWF f, d, a Inclusive OR WREG with f 1 0001 00da ffff ffff Z, N 1, 2
MOVF f, d, a Move f 1 0101 00da ffff ffff Z, N 1
MOVFF fs, fd Move fs (source) to 1st word 2 1100 ffff ffff ffff None
fd (destination) 2nd word 1111 ffff ffff ffff
MOVWF f, a Move WREG to f 1 0110 111a ffff ffff None
MULWF f, a Multiply WREG with f 1 0000 001a ffff ffff None 1, 2
NEGF f, a Negate f 1 0110 110a ffff ffff C, DC, Z, OV, N
RLCF f, d, a Rotate Left f through Carry 1 0011 01da ffff ffff C, Z, N 1, 2
RLNCF f, d, a Rotate Left f (No Carry) 1 0100 01da ffff ffff Z, N
RRCF f, d, a Rotate Right f through Carry 1 0011 00da ffff ffff C, Z, N
RRNCF f, d, a Rotate Right f (No Carry) 1 0100 00da ffff ffff Z, N
SETF f, a Set f 1 0110 100a ffff ffff None 1, 2
SUBFWB f, d, a Subtract f from WREG with 1 0101 01da ffff ffff C, DC, Z, OV, N
Borrow
SUBWF f, d, a Subtract WREG from f 1 0101 11da ffff ffff C, DC, Z, OV, N 1, 2
SUBWFB f, d, a Subtract WREG from f with 1 0101 10da ffff ffff C, DC, Z, OV, N
Borrow
SWAPF f, d, a Swap Nibbles in f 1 0011 10da ffff ffff None 4
TSTFSZ f, a Test f, Skip if 0 1 (2 or 3) 0110 011a ffff ffff None 1, 2
XORWF f, d, a Exclusive OR WREG with f 1 0001 10da ffff ffff Z, N
Note 1: When a PORT register is modified as a function of itself (e.g., MOVF PORTB, 1, 0), the value used will be that
value present on the pins themselves. For example, if the data latch is ‘1’ for a pin configured as input and is
driven low by an external device, the data will be written back with a ‘0’.
2: If this instruction is executed on the TMR0 register (and where applicable, d = 1), the prescaler will be cleared if
assigned.
3: If Program Counter (PC) is modified or a conditional test is true, the instruction requires two cycles. The second
cycle is executed as a NOP.
4: Some instructions are two-word instructions. The second word of these instructions will be executed as a NOP
unless the first word of the instruction retrieves the information embedded in these 16 bits. This ensures that all
program memory locations have a valid instruction.
BIT-ORIENTED OPERATIONS
BCF f, b, a Bit Clear f 1 1001 bbba ffff ffff None 1, 2
BSF f, b, a Bit Set f 1 1000 bbba ffff ffff None 1, 2
BTFSC f, b, a Bit Test f, Skip if Clear 1 (2 or 3) 1011 bbba ffff ffff None 3, 4
BTFSS f, b, a Bit Test f, Skip if Set 1 (2 or 3) 1010 bbba ffff ffff None 3, 4
BTG f, b, a Bit Toggle f 1 0111 bbba ffff ffff None 1, 2
CONTROL OPERATIONS
BC n Branch if Carry 1 (2) 1110 0010 nnnn nnnn None
BN n Branch if Negative 1 (2) 1110 0110 nnnn nnnn None
BNC n Branch if Not Carry 1 (2) 1110 0011 nnnn nnnn None
BNN n Branch if Not Negative 1 (2) 1110 0111 nnnn nnnn None
BNOV n Branch if Not Overflow 1 (2) 1110 0101 nnnn nnnn None
BNZ n Branch if Not Zero 1 (2) 1110 0001 nnnn nnnn None
BOV n Branch if Overflow 1 (2) 1110 0100 nnnn nnnn None
BRA n Branch Unconditionally 2 1101 0nnn nnnn nnnn None
BZ n Branch if Zero 1 (2) 1110 0000 nnnn nnnn None
CALL n, s Call Subroutine 1st word 2 1110 110s kkkk kkkk None
2nd word 1111 kkkk kkkk kkkk
CLRWDT — Clear Watchdog Timer 1 0000 0000 0000 0100 TO, PD
DAW — Decimal Adjust WREG 1 0000 0000 0000 0111 C
GOTO n Go to Address 1st word 2 1110 1111 kkkk kkkk None
2nd word 1111 kkkk kkkk kkkk
NOP — No Operation 1 0000 0000 0000 0000 None
NOP — No Operation 1 1111 xxxx xxxx xxxx None 4
POP — Pop Top of Return Stack (TOS) 1 0000 0000 0000 0110 None
PUSH — Push Top of Return Stack (TOS) 1 0000 0000 0000 0101 None
RCALL n Relative Call 2 1101 1nnn nnnn nnnn None
RESET Software Device Reset 1 0000 0000 1111 1111 All
RETFIE s Return from Interrupt Enable 2 0000 0000 0001 000s GIE/GIEH,
PEIE/GIEL
RETLW k Return with Literal in WREG 2 0000 1100 kkkk kkkk None
RETURN s Return from Subroutine 2 0000 0000 0001 001s None
SLEEP — Go into Standby mode 1 0000 0000 0000 0011 TO, PD
Note 1: When a PORT register is modified as a function of itself (e.g., MOVF PORTB, 1, 0), the value used will be that
value present on the pins themselves. For example, if the data latch is ‘1’ for a pin configured as input and is
driven low by an external device, the data will be written back with a ‘0’.
2: If this instruction is executed on the TMR0 register (and where applicable, d = 1), the prescaler will be cleared if
assigned.
3: If Program Counter (PC) is modified or a conditional test is true, the instruction requires two cycles. The second
cycle is executed as a NOP.
4: Some instructions are two-word instructions. The second word of these instructions will be executed as a NOP
unless the first word of the instruction retrieves the information embedded in these 16 bits. This ensures that all
program memory locations have a valid instruction.
LITERAL OPERATIONS
ADDLW k Add Literal and WREG 1 0000 1111 kkkk kkkk C, DC, Z, OV, N
ANDLW k AND Literal with WREG 1 0000 1011 kkkk kkkk Z, N
IORLW k Inclusive OR Literal with WREG 1 0000 1001 kkkk kkkk Z, N
LFSR f, k Move Literal (12-bit) 2nd word 2 1110 1110 00ff kkkk None
to FSR(f) 1st word 1111 0000 kkkk kkkk
MOVLB k Move Literal to BSR<3:0> 1 0000 0001 0000 kkkk None
MOVLW k Move Literal to WREG 1 0000 1110 kkkk kkkk None
MULLW k Multiply Literal with WREG 1 0000 1101 kkkk kkkk None
RETLW k Return with Literal in WREG 2 0000 1100 kkkk kkkk None
SUBLW k Subtract WREG from Literal 1 0000 1000 kkkk kkkk C, DC, Z, OV, N
XORLW k Exclusive OR Literal with WREG 1 0000 1010 kkkk kkkk Z, N
DATA MEMORY ↔ PROGRAM MEMORY OPERATIONS
TBLRD* Table Read 2 0000 0000 0000 1000 None
TBLRD*+ Table Read with Post-Increment 0000 0000 0000 1001 None
TBLRD*- Table Read with Post-Decrement 0000 0000 0000 1010 None
TBLRD+* Table Read with Pre-Increment 0000 0000 0000 1011 None
TBLWT* Table Write 2 0000 0000 0000 1100 None 5
TBLWT*+ Table Write with Post-Increment 0000 0000 0000 1101 None 5
TBLWT*- Table Write with Post-Decrement 0000 0000 0000 1110 None 5
TBLWT+* Table Write with Pre-Increment 0000 0000 0000 1111 None 5
Note 1: When a PORT register is modified as a function of itself (e.g., MOVF PORTB, 1, 0), the value used will be that
value present on the pins themselves. For example, if the data latch is ‘1’ for a pin configured as input and is
driven low by an external device, the data will be written back with a ‘0’.
2: If this instruction is executed on the TMR0 register (and where applicable, d = 1), the prescaler will be cleared if
assigned.
3: If Program Counter (PC) is modified or a conditional test is true, the instruction requires two cycles. The second
cycle is executed as a NOP.
4: Some instructions are two-word instructions. The second word of these instructions will be executed as a NOP
unless the first word of the instruction retrieves the information embedded in these 16 bits. This ensures that all
program memory locations have a valid instruction.
Note: All PIC18 instructions may take an optional label argument preceding the instruction mnemonic for use in
symbolic addressing. If a label is used, the instruction format then becomes: {label} instruction argument(s).
Words: 1
Cycles: 1
Q Cycle Activity:
Q1 Q2 Q3 Q4
Decode Read Process Write to
register ‘f’ Data destination
Cycles: 1 No No No No
operation operation operation operation
Q Cycle Activity:
If No Jump:
Q1 Q2 Q3 Q4
Q1 Q2 Q3 Q4
Decode Read Process Write to
Decode Read literal Process No
register ‘f’ Data destination
‘n’ Data operation
Words: 1 Q1 Q2 Q3 Q4
Decode Read literal Process Write to PC
Cycles: 1
‘n’ Data
Q Cycle Activity: No No No No
Q1 Q2 Q3 Q4 operation operation operation operation
Decode Read Process Write If No Jump:
register ‘f’ Data register ‘f’ Q1 Q2 Q3 Q4
Decode Read literal Process No
Example: BTG PORTC, 4, 0 ‘n’ Data operation
Before Instruction:
PORTC = 0111 0101 [75h] Example: HERE BOV Jump
After Instruction:
Before Instruction
PORTC = 0110 0101 [65h]
PC = address (HERE)
After Instruction
If Overflow = 1;
PC = address (Jump)
If Overflow = 0;
PC = address (HERE + 2)
Words: 1
Example: CLRWDT
Cycles: 1
Before Instruction
Q Cycle Activity:
WDT Counter = ?
Q1 Q2 Q3 Q4 After Instruction
Decode Read Process Write WDT Counter = 00h
register ‘f’ Data register ‘f’ WDT Postscaler = 0
TO = 1
Example: CLRF FLAG_REG,1 PD = 1
Before Instruction
FLAG_REG = 5Ah
After Instruction
FLAG_REG = 00h
Q1 Q2 Q3 Q4 Q Cycle Activity:
Decode Read Process Write to Q1 Q2 Q3 Q4
register ‘f’ Data destination Decode Read Process Write to
If skip: register ‘f’ Data destination
Q1 Q2 Q3 Q4 If skip:
No No No No Q1 Q2 Q3 Q4
operation operation operation operation No No No No
If skip and followed by 2-word instruction: operation operation operation operation
Q1 Q2 Q3 Q4 If skip and followed by 2-word instruction:
No No No No Q1 Q2 Q3 Q4
operation operation operation operation No No No No
No No No No operation operation operation operation
operation operation operation operation No No No No
operation operation operation operation
Example: HERE DECFSZ CNT, 1, 1
GOTO LOOP Example: HERE DCFSNZ TEMP, 1, 0
CONTINUE ZERO :
NZERO :
Before Instruction
PC = Address (HERE) Before Instruction
After Instruction TEMP = ?
CNT = CNT – 1 After Instruction
If CNT = 0; TEMP = TEMP – 1,
PC = Address (CONTINUE) If TEMP = 0;
If CNT ≠ 0; PC = Address (ZERO)
PC = Address (HERE + 2) If TEMP ≠ 0;
PC = Address (NZERO)
Words: 1 C register f
Cycles: 1
Words: 1
Q Cycle Activity:
Cycles: 1
Q1 Q2 Q3 Q4
Decode Read Process Write to Q Cycle Activity:
register ‘f’ Data destination Q1 Q2 Q3 Q4
Decode Read Process Write to
Example: RLNCF REG, 1, 0 register ‘f’ Data destination
Before Instruction
REG = 1010 1011 Example: RRCF REG, 0, 0
After Instruction Before Instruction
REG = 0101 0111 REG = 1110 0110
C = 0
After Instruction
REG = 1110 0110
W = 0111 0011
C = 0
ADDFSR Add Literal to FSR ADDULNK Add Literal to FSR2 and Return
Syntax: ADDFSR f, k Syntax: ADDULNK k
Operands: 0 ≤ k ≤ 63 Operands: 0 ≤ k ≤ 63
f ∈ [ 0, 1, 2 ] Operation: FSR2 + k → FSR2,
Operation: FSR(f) + k → FSR(f) (TOS) → PC
Status Affected: None Status Affected: None
Encoding: 1110 1000 ffkk kkkk Encoding: 1110 1000 11kk kkkk
Description: The 6-bit literal ‘k’ is added to the Description: The 6-bit literal ‘k’ is added to the
contents of the FSR specified by ‘f’. contents of FSR2. A RETURN is then
Words: 1 executed by loading the PC with the
Cycles: 1 TOS.
Q Cycle Activity: The instruction takes two cycles to
Q1 Q2 Q3 Q4 execute; a NOP is performed during
the second cycle.
Decode Read Process Write to
literal ‘k’ Data FSR This may be thought of as a special
case of the ADDFSR instruction,
where f = 3 (binary ‘11’); it operates
Example: ADDFSR 2, 23h only on FSR2.
Before Instruction Words: 1
FSR2 = 03FFh Cycles: 2
After Instruction Q Cycle Activity:
FSR2 = 0422h Q1 Q2 Q3 Q4
Decode Read Process Write to
literal ‘k’ Data FSR
No No No No
Operation Operation Operation Operation
Note: All PIC18 instructions may take an optional label argument preceding the instruction mnemonic for use in
symbolic addressing. If a label is used, the instruction format then becomes: {label} instruction argument(s).
MOVSS Move Indexed to Indexed PUSHL Store Literal at FSR2, Decrement FSR2
Syntax: MOVSS [zs], [zd] Syntax: PUSHL k
Operands: 0 ≤ zs ≤ 127 Operands: 0 ≤ k ≤ 255
0 ≤ zd ≤ 127
Operation: k → (FSR2),
Operation: ((FSR2) + zs) → ((FSR2) + zd) FSR2 – 1→ FSR2
Status Affected: None
Status Affected: None
Encoding:
Encoding: 1111 1010 kkkk kkkk
1st word (source) 1110 1011 1zzz zzzzs
2nd word (dest.) 1111 xxxx xzzz zzzzd Description: The 8-bit literal ‘k’ is written to the data
memory address specified by FSR2.
Description The contents of the source register are
FSR2 is decremented by 1 after the
moved to the destination register. The
operation.
addresses of the source and destination
registers are determined by adding the This instruction allows users to push
7-bit literal offsets ‘zs’ or ‘zd’, values onto a software stack.
respectively, to the value of FSR2. Both
Words: 1
registers can be located anywhere in
the 4096-byte data memory space Cycles: 1
(000h to FFFh). Q Cycle Activity:
The MOVSS instruction cannot use the Q1 Q2 Q3 Q4
PCL, TOSU, TOSH or TOSL as the Decode Read ‘k’ Process Write to
destination register. data destination
If the resultant source address points to
an Indirect Addressing register, the
value returned will be 00h. If the Example: PUSHL 08h
resultant destination address points to Before Instruction
an Indirect Addressing register, the FSR2H:FSR2L = 01ECh
instruction will execute as a NOP. Memory (01ECh) = 00h
Words: 2
After Instruction
Cycles: 2 FSR2H:FSR2L = 01EBh
Q Cycle Activity: Memory (01ECh) = 08h
Q1 Q2 Q3 Q4
Decode Determine Determine Read
source addr source addr source reg
Decode Determine Determine Write
dest addr dest addr to dest reg
SUBFSR Subtract Literal from FSR SUBULNK Subtract Literal from FSR2 and Return
Syntax: SUBFSR f, k Syntax: SUBULNK k
Operands: 0 ≤ k ≤ 63 Operands: 0 ≤ k ≤ 63
f ∈ [ 0, 1, 2 ] Operation: FSR2 – k → FSR2
Operation: FSRf – k → FSRf (TOS) → PC
Status Affected: None Status Affected: None
Encoding: 1110 1001 ffkk kkkk Encoding: 1110 1001 11kk kkkk
Description: The 6-bit literal ‘k’ is subtracted from Description: The 6-bit literal ‘k’ is subtracted from the
the contents of the FSR specified contents of the FSR2. A RETURN is then
by ‘f’. executed by loading the PC with the
Words: 1 TOS.
Cycles: 1 The instruction takes two cycles to
Q Cycle Activity: execute; a NOP is performed during the
second cycle.
Q1 Q2 Q3 Q4
Decode Read Process Write to This may be thought of as a special case
register ‘f’ Data destination of the SUBFSR instruction, where f = 3
(binary ‘11’); it operates only on FSR2.
Words: 1
Example: SUBFSR 2, 23h Cycles: 2
Before Instruction Q Cycle Activity:
FSR2 = 03FFh
Q1 Q2 Q3 Q4
After Instruction
Decode Read Process Write to
FSR2 = 03DCh
register ‘f’ Data destination
No No No No
Operation Operation Operation Operation
† NOTICE: Stresses above those listed under “Absolute Maximum Ratings” may cause permanent damage to the
device. This is a stress rating only and functional operation of the device at those or any other conditions above those
indicated in the operation listings of this specification is not implied. Exposure to maximum rating conditions for
extended periods may affect device reliability.
6.0V
5.5V
5.0V PIC18F6627/6622/6627/6722
PIC18F8527/8622/8627/8722
4.5V
Voltage
4.2V
4.0V
3.5V
3.0V
2.5V
2.0V
FMAX
Frequency
6.0V
5.5V
5.0V PIC18F6627/6622/6627/6722
PIC18F8527/8622/8627/8722
4.5V
Voltage
4.2V
4.0V
3.5V
3.0V
2.5V
2.0V
FMAX
Frequency
FMAX = 20 MHz in 8-bit External Memory mode.
FMAX = 25 MHz in all other modes.
6.0V
5.5V
5.0V PIC18LF6627/6622/6627/6722
PIC18LF8527/8622/8627/8722
4.5V
Voltage
4.2V
4.0V
3.5V
3.0V
2.5V
2.0V
4 MHz FMAX
Frequency
In 8-bit External Memory mode:
FMAX = (9.55 MHz/V) (VDDAPPMIN – 2.0V) + 4 MHz, if VDDAPPMIN ≤ 4.2V;
FMAX = 25 MHz, if VDDAPPMIN > 4.2V.
Note: VDDAPPMIN is the minimum voltage of the PIC® device in the application.
Param
Symbol Characteristic Min Typ Max Units Conditions
No.
Param
Device Typ Max Units Conditions
No.
Param
Device Typ Max Units Conditions
No.
Param
Device Typ Max Units Conditions
No.
Param
Device Typ Max Units Conditions
No.
Param
Device Typ Max Units Conditions
No.
Param
Device Typ Max Units Conditions
No.
Param
Device Typ Max Units Conditions
No.
Param
Device Typ Max Units Conditions
No.
Param
Device Typ Max Units Conditions
No.
Param
Device Typ Max Units Conditions
No.
Param
Device Typ Max Units Conditions
No.
Param
Device Typ Max Units Conditions
No.
Param
Symbol Characteristic Min Max Units Conditions
No.
VIL Input Low Voltage
I/O Ports:
D030 with TTL Buffer VSS 0.15 VDD V VDD < 4.5V
D030A — 0.8 V 4.5V ≤ VDD ≤ 5.5V
D031 with Schmitt Trigger Buffer VSS 0.2 VDD V
D032 MCLR VSS 0.2 VDD V
D033 OSC1 VSS 0.3 VDD V HS, HSPLL modes
D033A OSC1 VSS 0.2 VDD V RC, EC modes(1)
D033B OSC1 VSS 0.3 V XT, LP modes
D034 T13CKI VSS 0.3 V
VIH Input High Voltage
I/O Ports:
D040 with TTL Buffer 0.25 VDD + 0.8V VDD V VDD < 4.5V
D040A 2.0 VDD V 4.5V ≤ VDD ≤ 5.5V
D041 with Schmitt Trigger Buffer 0.8 VDD VDD V
D042 MCLR 0.8 VDD VDD V
D043 OSC1 0.7 VDD VDD V HS, HSPLL modes
D043A OSC1 0.8 VDD VDD V EC mode
D043B OSC1 0.9 VDD VDD V RC mode(1)
D043C OSC1 1.6 VDD V XT, LP modes
D044 T13CKI 1.6 VDD V
IIL Input Leakage Current(2,3)
D060 I/O Ports — ±200 nA VDD < 5.5V
VSS ≤ VPIN ≤ VDD,
Pin at high-impedance
— ±50 nA VDD < 3V
VSS ≤ VPIN ≤ VDD,
Pin at high-impedance
D061 MCLR — ±1 μA Vss ≤ VPIN ≤ VDD
D063 OSC1 — ±1 μA Vss ≤ VPIN ≤ VDD
IPU Weak Pull-up Current
D070 IPURB PORTB Weak Pull-up Current 50 400 μA VDD = 5V, VPIN = VSS
Note 1: In RC oscillator configuration, the OSC1/CLKI pin is a Schmitt Trigger input. It is not recommended that the
PIC® device be driven with an external clock while in RC mode.
2: The leakage current on the MCLR pin is strongly dependent on the applied voltage level. The specified
levels represent normal operating conditions. Higher leakage current may be measured at different input
voltages.
3: Negative current is defined as current sourced by the pin.
Param
Sym Characteristics Min Typ Max Units Comments
No.
D300 VIOFF Input Offset Voltage — ±5.0 ±10 mV
D301 VICM Input Common Mode Voltage 0 — VDD – 1.5 V
D302 CMRR Common Mode Rejection Ratio 55 — — dB
300 TRESP Response Time(1) — 150 400 ns PIC18FXXXX
300A — 150 600 ns PIC18LFXXXX,
VDD = 2.0V
301 TMC2OV Comparator Mode Change to — — 10 μs
Output Valid
Note 1: Response time measured with one comparator input at (VDD – 1.5)/2, while the other input transitions
from VSS to VDD.
VHLVD
VHLVD
HLVDIF
Param
Sym Characteristic Min Typ Max Units Conditions
No.
D420 HLVD Voltage on VDD HLVDL<3:0> = 0000 2.06 2.17 2.28 V
Transition High-to-Low HLVDL<3:0> = 0001 2.12 2.23 2.34 V
HLVDL<3:0> = 0010 2.24 2.36 2.48 V
HLVDL<3:0> = 0011 2.32 2.44 2.56 V
HLVDL<3:0> = 0100 2.47 2.60 2.73 V
HLVDL<3:0> = 0101 2.65 2.79 2.93 V
HLVDL<3:0> = 0110 2.74 2.89 3.04 V
HLVDL<3:0> = 0111 2.96 3.12 3.28 V
HLVDL<3:0> = 1000 3.22 3.39 3.56 V
HLVDL<3:0> = 1001 3.37 3.55 3.73 V
HLVDL<3:0> = 1010 3.52 3.71 3.90 V
HLVDL<3:0> = 1011 3.70 3.90 4.10 V
HLVDL<3:0> = 1100 3.90 4.11 4.32 V
HLVDL<3:0> = 1101 4.11 4.33 4.55 V
HLVDL<3:0> = 1110 4.36 4.59 4.82 V
VDD/2
RL Pin CL
VSS
CL
Pin
RL = 464Ω
VSS CL = 50 pF for all pins except OSC2/CLKO
and including D and E outputs as ports
OSC1
1 3 3 4 4
2
CLKO
Param
Device Min Typ Max Units Conditions
No.
INTOSC Accuracy @ Freq = 8 MHz, 4 MHz, 2 MHz, 1 MHz, 500 kHz, 250 kHz, 125 kHz(1)
PIC18LF6X27/6X22/8X27/8X22 -2 +/-1 2 % +25°C VDD = 2.7-3.3V
-5 +/-1 5 % -40°C to +85°C VDD = 2.7-3.3V
PIC18F6X27/6X22/8X27/8X22 -2 +/-1 2 % +25°C VDD = 4.5-5.5V
-5 +/-1 5 % -40°C to +85°C VDD = 4.5-5.5V
INTRC Accuracy @ Freq = 31 kHz
PIC18LF6X27/6X22/8X27/8X22 26.562 — 35.938 kHz -40°C to +85°C VDD = 2.7-3.3V
PIC18F6X27/6X22/8X27/8X22 26.562 +/-8 35.938 kHz -40°C to +85°C VDD = 4.5-5.5V
Legend: Shading of rows is to assist in readability of the table.
Note 1: Frequency calibrated at 25°C. OSCTUNE register can be used to compensate for temperature drift.
OSC1
10 11
CLKO
13 12
14 19 18
16
I/O pin
(Input)
17 15
20, 21
Note: Refer to Figure 28-5 for load conditions.
Q1 Q2 Q3 Q4 Q1 Q2
OSC1
167
ALE 168
164
169
171
CE
171A
OE
165
Operating Conditions: 2.0V < VCC < 5.5V, -40°C < TA < +125°C unless otherwise stated.
Q1 Q2 Q3 Q4 Q1 Q2
OSC1
A<19:16>
Address Address
BA0
166
153
150
156
151
ALE
171
CE
171A
154
WRH or
WRL
157 157A
UB or
LB
Operating Conditions: 2.0V < VCC < 5.5V, -40°C < TA < +125°C unless otherwise stated.
VDD
MCLR
30
Internal
POR
33
PWRT
Time-out 32
Oscillator
Time-out
Internal
Reset
Watchdog
Timer
Reset 31
34 34
I/O pins
BVDD
VDD 35
VBGAP = 1.2V
VIRVST
Enable Internal
Reference Voltage
Internal Reference 36
Voltage Stable
TABLE 28-12: RESET, WATCHDOG TIMER, OSCILLATOR START-UP TIMER, POWER-UP TIMER
AND BROWN-OUT RESET REQUIREMENTS
Param.
Symbol Characteristic Min Typ Max Units Conditions
No.
T0CKI
40 41
42
T1OSO/T13CKI
45 46
47 48
TMR0 or
TMR1
CCPx
(Capture Mode)
50 51
52
CCPx
(Compare or PWM Mode)
53 54
RE2/CS
RE0/RD
RE1/WR
65
RD7:RD0
62
64
63
Note: Refer to Figure 28-5 for load conditions.
SSx
70
SCKx
(CKP = 0)
71 72
78 79
SCKx
(CKP = 1)
79 78
80
75, 76
SSx
81
SCKx
(CKP = 0)
71 72
79
73
SCKx
(CKP = 1)
80
78
75, 76
74
Note: Refer to Figure 28-5 for load conditions.
SSx
70
SCKx
(CKP = 0) 83
71 72
78 79
SCKx
(CKP = 1)
79 78
80
75, 76 77
SDI
SDIx MSb In bit 6 - - - - 1 LSb In
74
73
TABLE 28-18: EXAMPLE SPI MODE REQUIREMENTS (SLAVE MODE TIMING, CKE = 0)
Param
Symbol Characteristic Min Max Units Conditions
No.
70
SCKx
83
(CKP = 0)
71 72
SCKx
(CKP = 1)
80
75, 76 77
SDIx
SDI
MSb In bit 6 - - - - 1 LSb In
74
Note: Refer to Figure 28-5 for load conditions.
SCLx
91 93
90 92
SDAx
Start Stop
Condition Condition
91 92
SDAx
In
110
109 109
SDAx
Out
100 THIGH Clock High Time 100 kHz mode 4.0 — μs PIC18FXXXX must operate at
a minimum of 1.5 MHz
400 kHz mode 0.6 — μs PIC18FXXXX must operate at
a minimum of 10 MHz
SSP Module 1.5 TCY —
101 TLOW Clock Low Time 100 kHz mode 4.7 — μs PIC18FXXXX must operate at
a minimum of 1.5 MHz
400 kHz mode 1.3 — μs PIC18FXXXX must operate at
a minimum of 10 MHz
SSP Module 1.5 TCY —
102 TR SDAx and SCLx Rise Time 100 kHz mode — 1000 ns
400 kHz mode 20 + 0.1 CB 300 ns CB is specified to be from
10 to 400 pF
103 TF SDAx and SCLx Fall Time 100 kHz mode — 300 ns
400 kHz mode 20 + 0.1 CB 300 ns CB is specified to be from
10 to 400 pF
90 TSU:STA Start Condition Setup Time 100 kHz mode 4.7 — μs Only relevant for Repeated
400 kHz mode 0.6 — μs Start condition
91 THD:STA Start Condition Hold Time 100 kHz mode 4.0 — μs After this period, the first clock
400 kHz mode 0.6 — μs pulse is generated
SCLx
91 93
90 92
SDAx
Start Stop
Condition Condition
SDAx
Out
CKx/TXx
pin
121 121
DTx/RXx
pin
122
120
CKx/TXx
pin 125
DTx/RXx
pin
126
BSF ADCON0, GO
(Note 1, 2)
131
Q4
130
A/D CLK 132
ADIF TCY
GO DONE
SAMPLING STOPPED
SAMPLE
Note 1: If the A/D clock source is selected as RC, a time of TCY is added before the A/D clock starts.
This allows the SLEEP instruction to be executed.
2: This is a minimal RC delay (typically 100 ns), which also disconnects the holding capacitor from the analog input.
XXXXXXXXXX PIC18F6722
XXXXXXXXXX -I/PT e3
XXXXXXXXXX 0810017
YYWWNNN
XXXXXXXXXXXX PIC18F8722-E
XXXXXXXXXXXX /PT e3
YYWWNNN 0810017
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be carried over to the next line, thus limiting the number of available
characters for customer-specific information.
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01/02/08