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Desgin and verification of axi apb bridge using system verilog

Article  in  Journal of Advanced Research in Dynamical and Control Systems · June 2018

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Jour of Adv Research in Dynamical & Control Systems, Vol. 10, 06-Special Issue, 2018

DESGIN AND VERIFICATION OF AXI APB

BRIDGE USING SYSTEM VERILOG
G.R.K.Prasad1, Damarla Paradhasaradhi1, G. Madan Sankar Reddy2*,K.Srinivasa Rao3,V.S.V.Prabhakar4
1
Assistant Professor,2 PG Student,3Professor,4Professor and Head of the Department
Department of ECE, Koneru Lakshmaiah Education Foundation, Vaddeswaram, Guntur, Andhra Pradesh ,India -522502
Mail: ramguda1978@gmail.com,madanasnkarreddy@gmail.com

ABSTRACT:

In this paper, the design and verification of an AXI-APB bridge is proposed by focusing on getting high
functional coverage for both the AXI and APB buses.AXI3 consists of five independent channels namely write
data, read data, read address, write address, response channel. In APB it consists of only single channel, and the
interface bridge is designed using three FIFOS. The Effective testbench for AXI-APB bridge is developed using
System Verilog language and the modular architecture of the test bench environment helps in effective utilization
of the features of System Verilog. In this work, the verification of different modes like fixed, wrapping and
incremental modes for read and write transaction and functional verification also performed using Synopsys
VCMX and VERDI simulator.

Key words: AMBA Family,FIFO , AXI-APB Bridge, Functional Coverage

1. INTRODUCTION:

In a complex SoC,there are two types of peripherals namely on-chip and off-chip all are operating at
different operating frequencies to stabilize the communication between the on-chip and off-chip peripherals we
need some common buses. In the present communication purpose there are many buses namely AMBA (Advanced
Microcontroller Bus Architecture), OCP (open core protocol),etc., are used. In all these cases, these standards
purportedly decoupled the interface choice from the interconnects, this is an advancement in these busses. In this
paper we focused on AXI3 (Advanced Extensible interface) and APB (Advanced Peripheral Bus) which belong to
the AMBA family. A bridge is designed to communicate between AXI and APB using FIFOS namely write read
address FIFO, data (write, read)FIFOS are used, and to communicate between SRAM and APB a SRAM interface
is used. All the inputs are driven by test bench and the outputs are sampled at the output of SRAM.

2.ARCHITECTURE OF APB AND AXI PROTOCOL

The ARM AMBA protocols are an open standard and on-chip interconnect specification and it is used for
development of firs time microprocessor designs with large number of peripherals and controllers. The architecture
of AMBA APB and AMBA AXI interconnect protocols are discussed below:

2.1. Advanced Peripheral Bus (APB):

Advanced Peripheral Bus is belonging to the AMBA family and applicable for a single master and slave
principle.It is optimized for low power, reduced complexity interface and low bandwidth operations which is
unpipelined protocol. It is supported only for a single master and multiple slaves and contains only single channel to
communicate between master and slave usually done by PSELx signal. PSELx signal is a master signal which is
used to decide the number of slaves are used, PWRITE is a signal from master which decides Read or write
operation if PWRITE =1, for write operation and 0 for Read operation. For any operation PADDR, PWDATA
1401

*Corresponding Author: G.R.K.Prasad Mail: ramguda1978@gmail.com

Article History: Received: April 15, 2018, Revised: May 10, 2018, Accepted: June 18, 2018
 DESGIN AND VERIFICATION OF AXI APB BRIDGE USING SYSTEM VERILOG

which is an address and data signal is set on the bus, PSEL is high, PENABLE is master is signal is high for the next
clock cycle, when PREADY which is from Slave is high indicating data transfer is completed.

PSLVERR is a master signal indicates an error condition on Read and Write operations.The transaction of APB is
illustrated by the state machine and is shown in the Figure1.

Figure 1. Transaction diagram of APB

2.2 Advanced extensible peripheral (AXI):

AXI3 refers to advance extensible peripheral bus it supports for out of order response, multiple outstanding
transactions, burst operations and disjoint operations along with advanced peripheral bus. It consists of five
independent channels namely Address Write, Write Data, Address Read, Read and write Response channel. The
signaldescription of each channel isshown in Figure 2.

Address write Write data Write Response Address Read

Read Channel
Channel Channel Channel Channel
AWID WID BID ARID RID
AWADDR WDATA BRESP ARLEN RDATA
AWBRUST WSTRB BVALID ARBRUST RESP
AWLEN WLAST BREADY AWVALID RLAST
AWVALID WVALID -NA- ARLEN RVALID
AWREADY WREADY -NA- ARREADY RREADY

Figure 2. Signal Description of AXI

Write Transaction:

In the write transaction, addresssignal AWADDR and WDATA signal is set on the channel from the master and
AWVALID signal which is master to slave goes high, and after one clock cycle a signal AWREADY from slave to
master goes to high. whenever a valid data is transmitted WVALID signal from master to slave goes high and after
one clock cycle WREADY signal which is a slave to master signal goes high indicating that a successful transaction
is completed. BRESP is a signal from slave to master is set to OKAY after completion of data transfer. BVALID
signal is becomes high indicating successfully transferring of data, and BREADY is a master to slave signal is high
throughout the transaction. The architecture of write transaction is as shown in the Figure 3.
Jour of Adv Research in Dynamical & Control Systems, Vol. 10, 06-Special Issue, 2018

Figure 3.Write Transaction mechanism

Read Transaction:

In Read Transaction, read address signal ARADDR is set on channel, ARVALID signal which is master to slave
becomes high, and in the next clock cycle ARREADY which is a master to slave signal becomes high indicating a
valid address, and rad channel data signal RDATA which data presents that is to be read by master and RREADY is
slave to master signal becomes high after completion of each transaction, RVALID is high which is a master to
slave signal indicating successful read transaction, RLAST is a is high for last read burst , the mechanism for read
transaction is as shown in the below Figure 4.

Figure 4. ReadTransaction Mechanism

3.Prposed model:

In the prosed model a bridge is designed to connect the AXI and APB, using synchronous FIFOS. The bridge
consists of 3 FIFOS namely request FIFO, write FIFO and READ FIFO. The architecture of AXI-APB Bridge is
shown Figure 5. In the next sections each type of FIFO that are used in the AXI-APB bridge are discussed.

1403

*Corresponding Author: G.R.K.Prasad Mail: ramguda1978@gmail.com

Article History: Received: April 15, 2018, Revised: May 10, 2018, Accepted: June 18, 2018
 DESGIN AND VERIFICATION OF AXI APB BRIDGE USING SYSTEM VERILOG

Figure 5. Architecture of AXI-APB Bridge

Request FIFO:

The Request FIFO of width is 43 bits and depth is 8 bit wide, the request FIFO mainly consist of the signals namely
A(W/R) ID[3:0] , A(W/R) addr [31:0] , A(W/R) Burst [1:0] , A(W/R)VALID, A(W/R)LEN[3:0].

As AXI is multiple channel bus and APB is single channeled bus to select the operation either read or write
operation an arbitration is required. The arbitration mechanism is used to ensure that only one request(read/write)
has access to the bus at any one time.The arbiter performs this function by observing a few different requests to use
the bus and decide which is currently the highest priority requesting the bus. The inputs of Arbitration are write
address channel for example last written is read operation i.e AWREADY =1 followed by AWVALID and AWID,
AWADDR, AWLEN, AWBRUST are the outputs to the Arbiter.

Data FIFOS:

In the data FIFOS it consists of two types namely write FIFO and read FIFO in the write FIFO the write operation is
to be done from AXI master to the APB slave the write FIFO of 41-bit width and 42-bit depth. The Read FIFO is
used to read the data from APB slave to AXI master the read FIFO of width 37-bit and depth is 32-bit. The data
FIFOs are used to synchronize the read and write transactions.

4. RESULTS:

To verify the functionality of AXI and APB bridge an effective System Verilog testbench is designed and the data is
written from AXI master to APB slave and read the data from APB slave to AXI master for successful
transformation of data their AWID, WID, RID , type of BURST is matched, The block diagram of Test Bench is
shown in the below figure.
Jour of Adv Research in Dynamical & Control Systems, Vol. 10, 06-Special Issue, 2018

TOP.SV

Figure 5. Test Bench model

From the generator length, id , burst type ,addr and data are generated in the form of packets to driver and score
board as shown in the above figure, the driver drives the signals to the DUT and the outputs are sampled at driver
and to the score board , in the score board the inputs and outputs are compared .The output wave forms of write and
read transactions is as shown in the below waveforms.

1405

*Corresponding Author: G.R.K.Prasad Mail: ramguda1978@gmail.com

Article History: Received: April 15, 2018, Revised: May 10, 2018, Accepted: June 18, 2018
 DESGIN AND VERIFICATION OF AXI APB BRIDGE USING SYSTEM VERILOG

Figure 6: Read and Write Transaction Output wave forms

Coverage:

In the coverage it observes the execution of test plan and checks the valid and invalid scenarios of the test plan.
They are two types of coverages:

1. Code coverage
2. Functional coverage

Code coverage:

It is a statistical analysis derived from instrumentation/analysis of executing code which includes how many times
each line of code is executed and paths decisions, loops, procedures etc.… The statistical analysis of code coverage
is as shown in the below fig. The code coverage is purely depending upon the tool.
Jour of Adv Research in Dynamical & Control Systems, Vol. 10, 06-Special Issue, 2018

Figure 7. code coverage

Functional coverage:

Functional coverage perceives the design from the user point of view, wither all the valid and invalid scenarios are
covered or not. In this paper we monitor the functional coverage mainly on length, burst type and transaction type
and achieved 100% functional coverage as shown in the below figure 8,9,10.

Figure 8. functional coverage for Length

1407

*Corresponding Author: G.R.K.Prasad Mail: ramguda1978@gmail.com

Article History: Received: April 15, 2018, Revised: May 10, 2018, Accepted: June 18, 2018
 DESGIN AND VERIFICATION OF AXI APB BRIDGE USING SYSTEM VERILOG

Figure 9. functional coverage for burst

Figure 10. functional coverage for transaction

CONCLUSION:

AMBA AXI and APB are plug and play IP protocol. Which is released by ARM, in this paper an interface between
AXI and APB is designed and builds an effective system Verilog test bench which checks most of the possible
scenarios, and complete functional coverage analysis during the simulation using VCSMX, VERDI tool. The main
advantage of building system Verilog testbench will reduce the time to verify the design for verification engineers,
and the testbench is reusable.

REFERENCES:

1. http://infocenter.arm.com/help/index.jsp?topic=/com.arm.doc.ihi0022d/index.html
2. http://infocenter.arm.com/help/index.jsp?topic=/com.arm.doc.ihi0024c/index.html
3. https://solvnet.synopsys.com/dow_retrieve/N-2018.03/verdi/verdi_olh/index.htm#page
4. https://solvnet.synopsys.com/dow_retrieve/latest/ni/vcs_mx.html
5. http://www.verificationguide.com/p/systemverilog-testbench-example-00.html
6. http://www.testbench.in/CO_02_COVER_GROUP.html

7.1800-2009 - IEEE Standard for SystemVerilog--Unified Hardware Design, Specification, and Verification
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