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DCS DCE Lect 1 PDF
DCS DCE Lect 1 PDF
DCS DCE Lect 1 PDF
Waqar Hussain
firstname.lastname@tut.fi
Department of Computer Systems
Tampere University of Technology
Lecture Contents
1. Why there was a need for FPGA ?
2. What is the Scope of FPGA usability ?
3. How to Implement a Digital System ?
4. FPGA Architecture
5. The Unit of Structure of FPGA
6. Hardware Description Languages
7. Synthesis / Place and Route
8. Timing, Area and Power Analysis
9. Future of FPGA Technology
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The FPGA industry sprouted from programmable read-only memory (PROM) and
programmable logic devices (PLDs). PROMs and PLDs both had the option of
being programmed in batches in a factory or in the field (field programmable)
• First
st PCI
C Integration
teg at o
• First IP Partner Program
Xilinx Co-Founders, Ross Freeman and
Bernard Vonderschmitt, invented the first
commercially available field programmable
gate array in 1985 – the XC2064
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• With FPGAs
o Reprogrammable Logic reusability
o Lower Non-Recurring Engineering (NRE) Cost
o Good for Prototyping
o Less Time to Market
o Can act as a testing device for other digital circuits
o Economical to be used for small volumes of products
o Students can understand digital design concepts in a
better way by designing their custom logic
• Home Appliances
• Communication Systems
• Control Systems and Automation
• Mechanical and Civil Engineering
• Test and Measurement Industry
• Medical Equipment
• Avionics and Aerospace Application
• Academia
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SP
Hardware
Perfo
ASP
HW/SW
CO
DSP GPP
Flexibility
SP
Hardware
ASP
HW/SW
CO
Costs
DSP
GPP
Design effort
7
FPGA Architecture
• An Example of FPGA Prototyping Board
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The unit is
“CLB”
CLB –Xilinx
Xilinx
“LE” - Altera
(Example:
Xilinx XC2000)
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Modern HDL
• Capture Characteristics of a Digital Circuit
Entity & Connectivity
Concurrency & Timing
• Cover Description
In Gate Level and RT Level
In structural view and behavioral view
o Behavioral View
Describe functionalities and I/O behavior
Treat the system as a black box
Corresponds to a sequential PL
o Structural View
Describe the internal implementation (components and
interconnections)
Essentially block diagram
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Generic gate-level
representation
Run on FPGA
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user_logic.vhd
• Synthesis
Creates basic gates and DFFs
from HDL
o Result is so called netlist
synth
A full description of logical ports
and their connections
netlist
(in RTL viewer)
gate-level netlist
x2
x1 m1
x0
• Transforms the basic gates into m2
x1 z
technology specific components x0
x2
m6
x1
• i.e. into logic elements (LE) with
Altera FPGAs
map
LE LE
LE
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place
FPGA
• Other logic may complicate
placement
other functions
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comb logic
comb. D
Q
clk
19
high-freq
signal
multibit
bus
1-bit
signal
Analog view
Monitored Values at of bus
signals cursor Cursor line
Time axis
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