Tools

ARM processor. heads for FPGAs

ACTEL LAUNCHED a soft ARM7 parts although they are physically
family processor core optimised for identical to its existing ProAsic3
use in Actel's low-cost ProAsic3 ch ips .

family of field-programmable gate The ARM7 runs

arrays (FPGAs). Under the at up to 25MHz.

company's agreement with ARM,
CoreMP7 users will not b e r equ ired
to pay royalties to ARM directly;
although the cost of the core has
been built into the pricing for the
ARM-based FPGA. Actel said the
cost of the processor core works out
to about $2.75 in volume based on it
taking up roughly a quarter of a
million-gate ProAsic3.
Yankin Tanurhan, Actel's senior
director of applications and IP, said
the com pa ny decided to offer the
ARM7 because "it is becoming the
8051 of the 32bit processor market".
However, rather than producing a set
of specialised FPGAs with an ARM7
hard core the compa ny decided to
, The release of the CoreMP7
offer it as a pre-synthesised soft IP
core. Locking mechanisms on the
flash-based FPGAs are used to
prevent the core from being copied to
non-MP7 devices. Actel will sell the
ARM7-based FPGAs as separate
Tanurhan said Actel
changed the RTL
code supplied by
ARM to make it
smaller when
implemented on an
FPGA fabric. He added
that some functions such
as the power-an-reset mode
have been designed so that
they remain compatible
with hardwired
implementa tions. "That gives
you the portability to move to
ASICs," he said, adding '�ctel is
currently working with ARM on
future processor possibilities."
coincides with Actel's launch of
the CoreConsole tool. Use of the
CoreMP7 in system-level designs
requires the implementation of a
supporting sub sy stem � inter rupt
controllers, memory controllers, I/O

Linux system split across cores

IGNIOS, WHICH LAUNCHED its
SystemWeaver multicore system
management IP and API last year,
has demonstrated how the
technology can be used to program
a multicore chip using a standard
operating system
The UK start-up has take n a
Xilinx FPGA that integrates two
PowerPCs and added the
SystemWeaver IP core, which acts
as a sort of broker that matches
the needs of the software to the
und erly ing hardware platform.
"We have booted a totally
unmodilled version of Linux onto
one of the PowerPCs. We have then
integrated under the device driver
layer," said Dan Chester, Ignios' vice-
president of business development.
Running a task on hardware
other than the PowerPC hosting
the operating system is apparently
matter of making a library call
through the device driver. In the
device driver, the call is expanded
out through the SystemWeaver API
into the necessary lower level-level
tasks.
'M the software developer sees
is their usual operating system and
they just need to be aware that
there is a devi ce driver that offers
certain services, " explained
ports and so on � aroun d the
microprocessor core. This can be a
tedious and time-consuming process
II done manually, so Actel devised
CoreConsole as a way of reducing
development time.
CoreConsole is a bus-centric tool
that automatically connects IP·cores
to the interconnect bus, allo wing IP
blocks, including user IP, to be
stitched together into synthesisable
RTL. CoreConsole uses methods
defined by the Structure for
Packaging, Integrating and Re-using
IP within Tool-flows (SPIRIT)
initiative, and includes underlying
structures based on XML code,
allowing designers to uses their own
SPIRIT co mpliant cores and
-

installed a device driver into the Chester. ensuring the easy transfer of IP
Linux kernel and our API is www.ignios.com between vendors.
www.acteLcom

lEE Electronics Systems and Software I December/January 2005/06 47