Next we apply a difference or differential input voltage by grounding the gate ofQ2

(i.e., setting
vG2
=0) and applying a signal vid to the gate of Q1, as shown in Fig. 9.4. We can see
that since
vid
= vGS1 � vGS2, if vid is positive, vGS1 will be greater than vGS2 and hence iD1
will be greater
than iD2 and the difference output voltage (vD2 � vD1) will be positive. On the
other hand, when
vid is negative, vGS1 will be lower than vGS2, iD1 will be smaller than iD2, and
correspondingly
vD1 will be higher than vD2; in other words, the difference or differential output
voltage
(vD2 � vD1) will be negative.
From the above, we see that the differential pair responds to difference-mode or
differential input signals by providing a corresponding differential output signal
between
the two drains. At this point, it is useful to inquire about the value of vid that
causes the entire
bias current I to flow in one of the two transistors. In the positive direction,
this happens when
vGS1 reaches the value that corresponds to iD1
= I, and vGS2 is reduced to a value equal to the