1. CMOS operation?

2. Characteristics and various capacitances present in CMOS?

3. What happens to delay if you increase load capacitance?
4. Which is bigger in terms of area NAND or AND?
5. Explain different power dissipation in CMOS
6. Explain LATCHUP?
7. Draw & explain Schematic diagram of AND, NAND, NOR
8. What is Finfet?
9. What is the Shape of your block?
10. What technology have you used in your design?

11. Design goes to which FAB?

12. How many plots in your design?
13. No of macros in Design, Instances?
14. What is HP, NP, NPC, LP, HPC, and HPM?
15. Explain Inputs to PD?
16. What is meant by Drive Strength?
17. Differentiate between metal and via
18. What is FAT table spacing?
19. What is unit Tile?
20. What is via rule?

21. What is single cut via, via array, double cut via?
22. What is meant by Metal density rule?
23. Different views in Physical Libraries? (In LEF)
24. What is Placement grid?
25. What is the standard cell height?
26. What is 8, 10, 12 track?
27. Can use mix or use different track for same design
28. How cell delays calculated?
29. 5*5, 7*7 9*9 why we use it/ (hint delay table)?
30. Explain Cell rise cell fall, rise Tran, fall Tran?

31. What is multi threshold voltage?

32. What is timing arc?
33. What is timing unit?
34. Explain PVT corners?
35. Explain Relation between Delay and PVT corners?
36. What is temperature inversion?
37. Explain sanity checks?
38. What will you do once you get inputs?
39. What happens to output when connected to PG nets?
40. What are multidriven nets?