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DSP Applns Compatibility Mode PDF
DSP Applns Compatibility Mode PDF
DSP Applns Compatibility Mode PDF
Architecture
7/7/2013 TIFAC CORE IN NETWORK 1
ENGINEERING
OVERVIEW OF DSP
PROCESSORS
BY
Computer
Engine Input / Output
Serial ports
Timers
Host ports
I/O
External ports connects
Program Data Link ports
Memory Memory to
outside
world
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ENGINEERING
INSIDE A DSP ENGINE?
Harvard Architecture
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ENGINEERING
• Conventional microprocessors
use:
• Von Neumann architecture
-simple
• -program and data all in a single
memory -effective
• -Address and data buses are
shared between instruction and BUT
data fetches.
performance problems:
Memory
Addre -fetch for next instruction collides
CPU/ALU ss with data fetch/store
Data -Buses may be idle during
instruction decode
P Address
CPU/ALU Program
Instr.
Memory
D1 D1 Data
Address
D2 Address D2 Data
Data
Data
Memory
Memory
#1
#2
TMS320C6000
C62X,C64X,C67X DSPs
TMS320C5000
TMS320C2000 C54X,C55X DSPs
C24X,C28X DSPs High
OMAP Performance
Power C55X+ARM
Control Efficient
Optimized
www.ti.com
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ENGINEERING
TMS320C2000 PLATFORM ROADMAP
SPI & SCI Serial SPI, SCI & CAN SPI, SCI & CAN
ports Serial ports Serial ports
Assembler
Linker
Simulator
C/C++ compiler
Debugger
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ENGINEERING
ANALOG DEVICES
FAMILY
Blackfin processors
Tiger SHARC processors
SHARC DSPs
ADSP-21xx
Mixed signal DSPs
www.analog.com/dsp
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ENGINEERING
NOMENCLATURE OF DSP
PROCESSORS
• TMS 320 C 25 GB L
TMX-Expt. Device C-CMOS
TMP-Prototype Device E-CMOS EPROM
TMS-Qualified Device
TMS320C50PQ57
I/O Ports
D(15-0) CPU 64K X 16
16-bit T-Reg 1,2 16-bit T-Reg0 Software
16 X 16 Multiplier Waitstates
16-bit Barrel
32-bit P-register
Shifter (L or R)
ShiftL(0, 1, 4, -6) Timer
32-bit ALU
32-bit Accumulator and Buffer Serial Port
ShiftL( 0 – 7 ) Sync
8 Auxiliary Registers
8 Level H/W Stack PLU
3 Status Registers BitSet, Clear
Block repeat/Circular Buffer Test, Toggle
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11 Shadow Registers
ENGINEERING
Central Arithmetic Logic Unit (CALU )
16-bit ∗ 16-bit hardware multiplier with a 32-bit
product capability
32-bit arithmetic logic unit (ALU)
PLU-Executes IIy only logical operation –without
affecting Accumulator
32-bit accumulator (ACC)
32-bit accumulator buffer (ACCB)
0- to 16-bit left and right data barrel-shifters
MUX 32
32
32
Arithmetic Logic Unit (ALU)
32
Accumulator Register (32) Accumulator Buffer (32)
16 32
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Left Shifter (0 – 7) ENGINEERING
C50 MEMORY MAPPING
Program Data
0000 0000
INTERNAL
EEPROM
RAM (32KW)
(48KW)
7FFF
8000
BFFF
C000
EXTERNAL
EXTERNAL RAM
RAM (16KW) (32KW)
FFFF
FFFF
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ENGINEERING
TMS320C50 DATA MEMORY
• CBSR-1
• CBSR-2
• CBER-1
• CBER-2
• CBCR
•Assembler/ Compiler :Used to convert the user editor based files into a
machine readable format
Assembler
optimizer
Link.cmd
Cost considerations
-chip size
-pin number
-external memory
Memory organization
-On and Off-chip memory size
-hardware tools
development boards
emulators
1 9
2
3 Clr A ;Clear Accumulator A
Rep N ; Rep N times the next instruction
MAC *(R0)+, *(R1)+, A ; Fetch the two memory locations pointed by R0 and R1, multiply
them together and add the result to A, the final result is stored back
in A
Mov A, *R2 ; Move result to memory
TMS320C50
1. MICRO 50 ST
2. MICRO 50 LC
3. MICRO 50 EB
TMS320VC5416
1. MICRO 5416
2. MICRO 5416 AT
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ENGINEERING
TMS 320C50 STARTER KIT
EXTERNAL
Output
DATA
MEMORY
C50
PROCESSOR
EXTERNAL Analog
PROGRAM Input
MEMORY
HIGH HIGH RESET
SPEED SPEED LOGIC
ADC DAC
BATTERY
BACKUP
(MICRO 50LC)
TMS320C33
1. MICRO 33
TMS320C6713
1. MICRO 6713 AT
MICRO-6713
TMS320F240
1. MICRO 240
TMS320F2407
1. MICRO 2407
2. MICRO 2407 EB
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ENGINEERING
TMS 320F240 TRAINER KIT
ADSP 2181
1. EZ KIT 81
2. MICRO 81 AD
3. MICRO 81 AT
ADSP 2189
1. MICRO 89 ST
2. MICRO 89 AT
ADSP 2191
1. MICRO 91
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ENGINEERING
ADSP 2181 ADVANCED TRAINER KIT