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Digital Logic Technology: Engr. Muhammad Shan Saleem
Digital Logic Technology: Engr. Muhammad Shan Saleem
BMT-264
Lab Instructor:
Name: ____________________
EXPERIMENT No. 03
IMPLEMENTATION OF HALF ADDER AND FULL ADDER
PRE-LAB TASK
Objectives
Introduction
All digital computers execute a variety of information-processing jobs. Among these basic tasks
are the various arithmetic operations. The most basic arithmetic operation is the addition of two
binary digits. The circuit that implements this binary addition is called H-alf Adder. The next
stage to this addition is the addition of three binary numbers. The circuitry for this addition is
called Full Adder.
Theory
Half Adder
Half Adder is a type of combinational logic circuit that produces the sum of two binary digits
(each of 1-bit length). This circuit has two inputs, say x and y, and two outputs i.e. sum and carry
abbreviated as SHA & CHA respectively. First, we will construct Truth Table of Half Adder as:
Inputs Outputs
0 0 0 0
0 1 1 0
1 0 1 0
1 1 0 1
Boolean function for the above-mentioned Truth Table is:
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LAB-03
𝑆𝐻𝐴 = 𝑥 ′ 𝑦 + 𝑥𝑦 ′ = 𝑥 ⊕ 𝑦
𝐶𝐻𝐴 = 𝑥𝑦
x y
SHA= x + y
(To LED)
CHA=x y
(To LED)
Full Adder
Full Adder is combination logic circuit that carry out the sum of three binary numbers, each of
1-bit length. Two of the binary input variables are x and y represent the two significant bits to be
added the third input z, represents the carry from previous lower significant position. Outputs of
Full Adder are Sum and Carry represented as S FA and CFA respectively. Now we will draw the
Truth Table of Full Adder.
Inputs Outputs
x Y z SFA CFA
0 0 0 0 0
0 0 1 1 0
0 1 0 1 0
0 1 1 0 1
1 0 0 1 0
1 0 1 0 1
1 1 0 0 1
1 1 1 1 1
First, we write Boolean expression for Sum of Full Adder.
𝑆𝐹𝐴 = 𝑥 ′ 𝑦 ′ 𝑧 + 𝑥 ′ 𝑦𝑧 ′ + 𝑥𝑦 ′ 𝑧 ′ + 𝑥𝑦𝑧
The above expression can be simplified using Boolean Postulates & theorems/k-map, so we get
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LAB-03
𝑆𝐹𝐴 = (𝑥 ′ 𝑦 + 𝑥𝑦 ′ ). 𝑧 + (𝑥 ′ 𝑦 + 𝑥𝑦 ′ ). 𝑧
𝑆𝐹𝐴 = (𝑥 ⊕ 𝑦) ⊕ 𝑧
𝐶𝐹𝐴 = (𝑥 ′ 𝑦 + 𝑥𝑦 ′ ). 𝑧 + 𝑥𝑦
𝐶𝐹𝐴 = (𝑥 ⊕ 𝑦). 𝑧 + 𝑥𝑦
x y z
HA1 HA2
SFA = (x + y) + z
To LED
CFA = (x + y) z + xy
To LED
LAB SESSION
➢ NI ELVIS II Workstation
➢ 7408 IC
➢ 7432 IC
➢ 7486 IC
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LAB-03
Experimental Procedure
Questions:
1. Can we implement the expressions of SFA and CFA using Basic Gates only?
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2. From the expression of SHA and CHA count the number of gates required to execute these
expressions using basic gates only.
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3. From the expression of SFA and CFA count the number of gates required to execute these
expressions using basic gates only.
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4. From the result of Question 3, give the no. of ICs required.
# of OR Gate ICs: _________________
# of AND Gate ICs: _________________
# of NOT Gate ICs: _________________
LAB REPORT
Discussion of Results
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2. Draw the circuit of Full Adder using Basic Gates only.
Conclusion / Summary:
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