A New Op-amp Noise Model for Switched-Capacitor

Sigma-Delta Modulator in SIMULINK

F. WUI,2, Z.1. Chen*2, M. Zhao2, D.Y. XUI,2, G.C. Shenl,2, W.G. Lu2, Y.C. Zhang2
I
School of Electronic and Computer Engineering, Peking University Shenzhen Graduate School, Shenzhen 518055
2Key Laboratory of Microelectronic Devices and Circuit, Department of Microelectronics, Peking University, Beijing 100871
* Email: chenzj@pku.edu.cn

Abstract-Precise behavioral models are needed to simulate

switched-capacitor sigma-delta modulators more efficiently. This
paper presents a new noise model of the operational amplifier (op­
amp) used in a typical correlated double sampling (CDS)
integrator. Evaluation and validation of the new model are done
via behavioral and transistor-level simulations for a 2-1 MASH
modulator using SIMULINK and SPECTRE with O.35um CMOS
technology. Two sets of results for comparison are obtained and
the biggest difference between the two simulators is around 2dB.

Keywords-sigma delta modulators; correlated double sampling; Fig. 1. Single-ended CDS integrator
non-ideality; op-amp noise; SIMULINK
are calculated only once in a clock period, that's to say, the
I. INTRODUCTION behavioral model wouldn't handle the above relation within one
Switched-capacitor sigma-delta modulators are very suitable period conventionally. So the expression about how the output
for low-frequency high-resolution AID converting applications voltage in phase �2 is affected by the noise in phase �I has to be
in SC circuits. Generally, a large number of parameters have to deduced.
be optimized to achieve the desired signal-to-noise ratio (SNR)
In Fig. 1, Vn represents the noise voltage converted from the
[1]. Considering the large simulating time in transistor level,
output thermal and flicker noise of the integrator. It's substituted
precise behavioral models are needed to estimate the
by Vnl and Vn2 respectively in phase �I and �2. Taking Vn into
performance more efficiently thus making the optimizing work
account, (1) alters to
easier [2]. Non-ideal models of SC modulators are reported in
[1-3] and other papers, however, in these works, the fact that the
fIrst integrator's output voltage is affected by the thermal and
flicker noise in both clock phases rather than one has been (2)
I
ignored. This paper takes this fact into consideration and I
presents a new SIMULINK model of the op-amp noise for a Vn1(z).z--; ·z·(a·z- +b)+Vn2(z)·z·(c·z-1+d)}
widely-used CDS integrator. Two sets of results from behavioral and the coeffIcients
model and transistor-level circuit are obtained to verify the
validation of the model proposed. All the simulations are carried a= 1+Kp I Kds-Kp -Kds
out on a 2-1 MASH SC sigma-delta modulator designed with
b= Kds - (1+Kj +K,)(1+Kp I Kd,)
0.35um CMOS technology.
c= -1- Kp I Kds
II. OP-AMP NOISE MODEL
d= Kp +(l+Kj +Ks)(l+Kp I Kds)
A typical single-ended CDS integrator with a feedback
input is shown in Fig. 1 and its ideal output voltage during the where Kp=Cp/C;, and Cp denotes the op-amp's input parasitic
integrating phase in z-domain is capacitance.
I
--
Z It is seen in (2) that Vnl is delayed half a period and then
Vo2(z)= _ '[�n(z)z z·Ks-Vjb(z)·Kr] (1)
z I together with Vn2 affects the integrated output voltage. As
where Ks=CsIC;, KrClC;. In the case of a non-ideal integrator, mentioned above, in SIMULINK the result is calculated at the
(1) will be altered to a more complex one by many factors among very end of each clock period, so we can simply add the two
which the intrinsic noise of the op-amp is an important one. parts together in the model becauseVnl andVn2 are uncorrelated.
The noise voltage sequences ofVn1 andVn2 can be obtained from
For an SC integrator, its output voltage in the effective phase
their PSDs which can be easily got from transistor-level
(sampling phase of the next stage, assuming it's �2 in Fig. 1) is
simulations [3], and it's easy to ensure that they are uncorrelated.
related with the voltage in phase �I, thus it's surely related with
The noise model is shown in Fig. 2.
the output noise in phase �I. However, in SIMULINK, signals
 TABLE 11 Two Sets of Simulation Results from SIMULINK and SPECTRE
for Comparison

SNR (dB)
Op-amp C; (pF)
SIMULlNK SPECTRE
AMPI 100 1 13.0 1 10.8
AMP2 100 1 15.9 1 14.0
AMP3 100 1 17. 1 1 15.4
AMP3 50 1 12.5 1 10.7
AMP3 25 106.4 107.7
Fig. 2. Op-amp noise model of the CDS integrator

III. SIMULATION RESULTS
A 2-1 MASH low-pass sigma-delta modulator for MEMS
accelerometer interface digitalizing is designed using O.35um
CMOS technology with the parameters listed in Table I. Fully
differential version of the CDS integrator shown in Fig. 1 is used
as the first stage. The behavioral model of the modulator is
shown in Fig. 3. The gray blocks indicate the non-ideal parts and
among them, the KT/C, switch on-resistance, real-INT and jitter
blocks can be referred to [1] and [2], and the block named
'Equivalent OpNoise' represents the model shown in Fig. 2.
For the fust set of results, C, remains unchanged, making
KT/C noise constant, so the SNR alters along with the change of
op-amp noise. And when C, varies and op-amp remains
unchanged, KT/C noise changes, and at the same time, the
output noise of the integrator changes because the op-amp's
GBW alters, resulting in a varying SNR. Obviously, the results
from SIMULINK and SPECTRE show a very good agreement
in both cases, and the biggest difference is around 2dB. For a
more visual comparison, Fig. 4 shows the results from the two
simulators with the combination of AMP3 and C,=IOOpF. It is
seen that noise floors of the two PSDs are almost the same. All
these results indicate that the model proposed can be used to
conduct accurate behavioral simulations. Thus, reliable results
can be obtained from behavior level in just one or two minutes,
without the need to simulate in transistor level for days.

-20

-40

..0
<D
"- -80
0

i('
-100

Fig. 3. SIMULINK model of the 2- 1 MASH sigma-delta modulator

TABLE I Fixed Parameters of the Modulator

Parameters Value Frequency [Hz]

Oversampling Ratio (OSR) 256

Fig. 4. PSD results for AMP3 and C,=IOOpF.
Signal Bandwidth (Hz) 200
Input Sinusoidal Frequency (Hz) 50
IV. SUMMARY
aIlcl 0.2/0.125
a2/c2 0. 16/0.4
This paper presents a new op-amp noise model in
bl/g] 0.2/0.4
SIMULINK for SC sigma-delta modulators. A commonly-used
CDS integrator is modeled through this method and simulations
in SIMULINK and SPECTRE are conducted. The results
To better verify the validation of the noise model, two sets indicate that the proposed model has a good similarity with the
of simulation have been conducted to compare the results from real circuit; thereby efficient simulations can be done when
SIMULINK and SPECTRE. Firstly, keep the integrating designing a needed modulator.
capacitance of the first integrator (C,) fixed and alter the op-amp.
REFERENCES
Secondly, vary the capacitance from IOOpF to 25pF when
keeping the op-amp and the coefficients unchanged. The [I] P. Malcovati, s. Brigati and F. Francesconi, "Behavioral modeling of
switched-capacitor sigma-delta modulators," IEEE Trans. Circuits Syst.,
simulation results of SNR are listed in Table II. vol. 50, no. 3, pp.352-364, Mar 2003.

lt should be noted that other factors are kept sufficient (SR,
GBW) or unchanged Gitter) when conducting the simulations,
and for simplicity, SNR is calculated as the result instead of
SNDR. Thus, the results change mainly due to the change of op­
amp noise or KT/C noise.
[2] A. Dendouga, N.-e. Nouguechal, S. Kouda, S. Barra and B. Lakehal,
"Contribution to the modeling of a non-ideal Sigma-Delta modulator,"
Journal of Computational Electronics, vol. II, pp.32 1-329, June 20 12.
[3] A. Fornasari, P. Malcovati and F. Maloberti, "Improved modeling of
sigma-delta modulator non-idealities in SIMULINK," IEEE Circuits and
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