VLSI Design Cycle

• System Specification: First step is to lay down the specificatio

of the system to be designed.

• Functional Design: Behavioral aspects of the system are consid

• Logic Design: Logic structure that represents the functional de
is delivered and tested.

• Circuit Design: Develop a circuit representation based on logic

design.
• Physical Design: The circuit representation of each component
converted into a geometric representation.
• Design Verification: The layout is verified in this step to ensure
that the layout meets the system specification and the fabricati
requirements.
 • Fabrication : After verification, the layout is ready for
fabrication.
• Packaging, Testing and Debugging: The wafer is
fabricated and diced in a fabrication facility. Each chip is
packaged and tested to ensure that it meets all the
design specifications and functions properly.
 VLSI Physical Design Cycle
• Partitioning: A chip consists of several million transistor. Lay o
the entire circuit layout is not possible to handled due the mem
space limitation. Therefore the circuit lay out is decomposed b
grouping the components into blocks (sub-circuits / modules ).

• Floorplanning and Placement: This step is concerned with

selecting good lay out alternatives for each block, as well as
entire chip.

• Routing: The objective of the routing phase is to complete th

interconnections between blocks according to the specified n

• Compaction: Compaction is simply the task of compressing

lay out in all directions such that the total area is reduced
 Design Styles

 Rent’s rule: IO  t .G r Where IO is the number of IO pins, t

is the number of terminals per gate, G is the number

of gates in the circuit, and ‘r’ is Rent’s exponent which
is a
positive constant less than one.
 Full- Custom
• In general form of design style, the circuit is partitioned into
Collection of subcircuits according to some criteria.
• In full-custom design style, each subcircuit is called a functio
block. Full custom design style allows functional blocks to be o
any size.

• Full custom design is very time consuming ; thus the metho

inappropriate for very large circuits, unless performance is of
utmost importance.

• Full custom is usually used for layout of microprocessor.

 Standard Cell
• This architecture considers the layout to consists of rectangula
of same height.

Gate Arrays
• This design style is a simplification of standard cell design.
standard cell design, all the cells in gate array are identical.

Field Programmable Gate Array

• A FPGA consists of horizontal rows of programmable logic blo
which can be interconnected by programmable routing network
 Design Rules

• The constraints imposed on the geometry of an integrated circ

layout, in order to guarantee that the circuit can be fabricated
an acceptable yield, are called design rule.

• Mead and Conway suggested the use of a single paameter to

design the entire layout. The basic idea is to characterize the p
With a single scalable parameter called lamda  ( ).

Defined as the maximum distance by which a geometrical featu

any layer can stray from another feature, due to over-etching,
Misalignment, distortion, over or underexposure, etc., with a
suitable safety factor included.
 Design rule is classified into three
categories.
Size Rule: Minimum size of a device or interconnection line is
determined by the line patterening capability of lithographic
equipment.

Separation Rule: In ICs, the interconnect line separation is sim

to the size rule.

Overlap Rule: Design rule must protect against fatal errors su

As a short circuited channel caused by the immigration of po
and diffusion.
 Other Rules
1. The size of bonding pads, determined by the diameter of bon
wire and accuracy of the bonding machine.

2. The size of cut in overglass ( final oxide covering) for conta

with pads.

3. The scribe line width.

4. The feature distance from the scribe line to avoid damage

scribing.

5. The feature distance from the bonding pad, to avoid damage t

device during bonding.

6. The bonding pitch, determined by the accuracy of bonding

machine.
 Yield Statistics and Fabrication Costs
• The prediction of the number of good chips per wafer
can be
made on the basis of how many dies ( chips) fit into a
wafer (Nd) and the probability of a die being functional
after C (w)
processing (Y). The Ccost  an untested die C(ud) is
( ud )of
N (d ) * Y
given by,
Where, C(w) is the cost of wafer fabrication. N(d) * Y =
total
number of good dies per wafer, N(Y). N(d) is given by,
(D
2
)
N (d )  2
N (d ) 
(D ) 2
2

4.X 4.X

Where, D is the diameter of the wafer, ( 10 cm approx.) and α

is the
useless scrap edge distance of Aawaferc (mm).
Y  (1  )
c
A = Area of a single chip,   defect density, defect per sq. m
C is parameter that indicates defect clustering. Dissipate
the power generated by the die is the main factor which
determines the cost of material used. Number of gate,

(X
2
P* A ( io ))
N (g) 
A( g )

Where, P is the total number of pads on the chip surface.

A(io) = area of an I/O cell and A(g) = area of the logic gate.

Number of pad required for next level of interconnection

P = 4(X/S - 1), where, S is the minimum pad to pad pitch.
 Delay Computation
The resistance of a uniform slab of conducting material is gi
by:
 .l c
R 
hc .w c
ρ is the resistivity, w is width, h c thickness, l length.
c c
Interconnection capacitance is given by,
w ic

wc hc wc
C  [ 1 . 15 .( )  2 . 80 ( )
0 . 222
 [ 0 . 06 ( ) 
to to to
hc hc hc to
 1 . 66 (  0 . 14 ( ]  s 0 l c
0 . 222 1 . 34
1 . 66 ( ) ) ) ].( )
to to to w ic

C is the capacitance of the conductor,

w ic Is the spacing of chip
Interconnection.
 Basic nMOS design rule
Diffusion region width 3
Polysilicon region width 2λ
Diffusion-diffusion spacing 3
Ply-poly spacing 2λ
Polysilicon gate extension 2λ
Contact extension λ
Metal width 3λ

Let us consider a wire of 2cm long, 0.5 um thick wire having a

1.0 um thick oxide beneath it in an chip fabricated using 2 um
Technology…. Resistance is 600 ohms and capacitance is
approximately 4.0 pF . RC constant 2.4 nsec.
Comparison of wire length

wc Aluminum Poly silicon

2.00 um 44 0.13
1.00 11 .0333
0.75 6.2 .0187
0.50 2.8 .00833
.25 .69 .00208
 Complexity issues and NP- hardness
Various algorithm in physical design:
1. Greedy algorithm
2. Divide and conquer algorithm
3. Dynamic programming algorithm
4. Network flow algorithm
5. Linear / Integer programming techniques
Big-Omega notation: f(n) = Ω(g(n)) if there exist constants
no

n0 and c such that we have f(n) >= c.g(n) for all nn

o > n0 .

Another way to say the same thing is to specify that f(x) is lo

bounded by g(n)
Big-Oh notation: Let f(n) = O(g(n)) if there exist constants
no
and c such that nn>o then f(n) <= c.g(n). F(n) is
upper bounded by g(n).
 Algorithm bubble sort (A[1:n]);
Begin /* Sort Array A[1:n] in ascending order */
Var i , j;
For i= 1 to n Do
For j = I+1 to n Do
If A[i] > A[j] then
Swap ( A[i] , A[j]);
End Algorithm;
2
This algorithm requires O(n) storage ( for the array) and
2
O (n ) O (n )
Running time ( for two nested loops).

Big Theta notation:

Let f(n) = θ(g(n)) if f(n) = Ω(g(n)) . θ(g(n)) is known as tight
Bound.
The class of solvable problems can be partitioned into two gen
classes:- P and NP.
The class P consists of all problems that can be solved by
deterministic turing machine in polynomial time.

NP consists of problems that can be solved in polynomial tim

nondeterministic turing machine.

Algorithm for NP-hard problem: Most optimization problem in

physical design is NP-hard. In such case, there are the followin
four choices.

• Exponential Algorithm

• Special Case Algorithm

• Approximation Algorithm
• Heuristic Algorithm
Depth-First Algorithm:
Algorithm DEPTH-FIRST(v)
begin
MARKED(v) = 1;
For each vertex u, such that (u,v) ε E do
If MARKED(u) = 0 then
DEPTH-FIRST-SEARCH(u);
end.
Breadth-First Search: The basic idea of this algorithm is to exp
All vertices adjacent to a vertex before exploring any other ver
Topological Search: In directed acyclic graph, it is very natural to
the parents, before visiting the children.
 Spanning Tree Algorithm:

lLet G = (V,E) – a graph, select a subset

V V Such that V’
'

L property P. In other way it can be defined as:- A spanning tree

has
e graph G is a set of k-1 edges which form a tree; such a tree
the
t
connects ( or spans) all the k nodes. The minimum spanning tree (
is an edge selection problem. Given an edge weighted graph G = (
select a subset of edges E E such that E’ includes a tree and
'

the total cost of edges wt ( e ) is minimum over all such trees

 i
( ei )

e i E
'

Where wt ( ei ) is the cost or weight of the edge

( ei )

There are three algorithms for finding MST: (i) Boruvka’s Algorithm
(ii) Kruskal’s Algorithm (iii) Prim’s Algorithm.
 Algorithm of Kruskal’s Algorithm

1. Sort the edges by non decreasing weight. Each vertex is assig

a set. Thus for n vertices have n sets. Each set represents a p
spanning tree. All the set together form a spanning forest.
2. For each edge (u,v) from the sort listed , if u and v belong to
same set, the edge is discarded.

3. If u,v belong to disjoint sets, a new set is created by union of th

two sets. This edge is added to the spanning tree.

4. Running time of the algorithm O(E I log I E).

 Shortest Path Algorithms
Single pair shortest path: May be viewed as a vertex or edge se
Given G = (V,E) and two vertices u,v ε V. Select a set of vertices
P V , including u,v such that P induced a path of
minimum
cost in G. Let wt(p,q) be the weight of edge (p,q), assuming tha
wt ( p , q )  0 For each ( p , q )  E

Algorithm SHORTEST-PATH(u)
begin
for I = 1 to n do
If ((u,i) ε E) then D[i] = wt(u,i);
else D[i] = +α;
P[i] = u;
V’ = V-u; D[u] = 0;
while (|V’| > 0) do
Select v such that D [ v ]  min w V D [ w ];
'

V’ = V’ –v;
for w εV’ do
if D[w] > D[v] + wt(u,w)) then
D[w] = D[v] + wt(u,w);
(* D[w] is the length of the shortest path from u to w.*)
P[w] = v;
(*P[w] is the parent of w.*)
for w ε V do
(* print the shortest path from u to v. * )
q = w;
print q;
while ( q ‡ u ) do
q = P[q];
print q;
print q;
end.
 All Pairs Shortest Paths

Floyd-Warshall algorithm - O ( V  )
3 Based on dynamic
Programming.
The algorithm is based on the following:-
Let, G = ( V, E ), V  { v1 , v 2 , v 3 , ..... v n }
Consider a subset
V
'
 { v1 , v 2 ,......
p  ( v1 , v 2 ,...., vl )
vk } V
For any pair of vertices v i , v j
V
Consider all paths from vi , vj with intermediate from V’
Let p be the one with minimum weight
is any vertex
An intermediate vertex of a path p  ( v1 , v 2 ,...., vl )
of p other thanv and v
1 l
Let (k)
d ij Be the weight of a shortest path from
v to vj
i

With the intermediate vertices from'

V  { v1 , v 2 ,...... vk } V
For k=0, a path from v i to vj Is one with no intermediate

vertices, thus having one edge d ij( 0 )  wt ( v i , v j )

For all pairs

d ij
(k)
 wt ( v i , v j ) ifk  0
1 ) 1 )
d ij
(k)
 min{ d ij
(k (k
, d ik  d kj( k 1 ) k  1
Standard Cell: is used if the design of the cells has been standar
in some way.

Macro Cell ( Macro): is a data base is known as the cell library. M

is also known as building block.

Aspect ratio: of a rectangular cell is defined as the ratio h/w.

Signal net or net: is a collection of pins which must be electrica

Connected.
(A. AND[1]. IN1)
(B. AND[1].IN2)
(C.AND[2] . IN1)
(B.AND[2] . IN2)
(A. AND[3] . IN1)
(C. AND[3]. IN2)
(AND[1].OUT , OR3[1]. IN1)
(AND[2].OUT , OR3[1] .IN2)
(AND[3] .OUT , OR3[1].IN3)
(OR3[1].OUT.Z)
(AND[1].Vdd. AND[2]. Vdd, AND[3].Vdd, OR3[1].Vdd
(AND[1].GND. AND[2]. GND, AND[3].GND, OR3[1].GND
 Connectivity Graph from Netlist
• Each net of the form (i,j) …an edge between the module
m i and
mj

• Consider a three pin net (a,b,c) belong to module

m a mb mc