Zilog PDF

Z8018x
Family MPU
User Manual
UM005004-0918
www.zilog.com
Z8018x
Family MPU User Manual
This publication is subject to replacement by a later edition. To determine whether a later edition
exists, or to request copies of publications, go to www.zilog.com
Windows is a registered trademark of Microsoft Corporation.
Document Disclaimer
© 2018 by ZiLOG, Inc. All rights reserved. Information in this publication concerning the devices,
applications, or technology described is intended to suggest possible uses and may be superseded. ZiLOG,
INC. DOES NOT ASSUME LIABILITY FOR OR PROVIDE A REPRESENTATION OF ACCURACY OF
THE INFORMATION, DEVICES, OR TECHNOLOGY DESCRIBED IN THIS DOCUMENT. ZiLOG
ALSO DOES NOT ASSUME LIABILITY FOR INTELLECTUAL PROPERTY INFRINGEMENT
RELATED IN ANY MANNER TO USE OF INFORMATION, DEVICES, OR TECHNOLOGY
DESCRIBED HEREIN OR OTHERWISE. Except with the express written approval ZiLOG, use of
information, devices, or technology as critical components of life support systems is not authorized. No
licenses or other rights are conveyed, implicitly or otherwise, by this document under any intellectual property
rights.
UM005004-0918
Z8018x
iii
MANUAL OBJECTIVES
This user manual describes the features of the Z8018x MPUs.This manual
provides basic programming information for the Z80180/Z8S180/
Z8L180. These cores and base peripheral sets are used in a large family of
ZiLOG products. Below is a list of ZiLOG products that use this class of
processor, along with the associated processor family. This document is
also the core user manual for the following products:
Part Family
Z80180 Z80180
Z8S180 Z8S180
Z8L180 Z8L180
Z80181 Z80180
Z80182 Z80180, Z8S180*
Z80S183 Z8S180
Z80185/195 Z8S180
Z80189 Z8S180
* Part number-dependant
Intended Audience
This manual is written for those who program the Z8018x.
Manual Organization
The Z8018x User Manual is divided into five sections, seven appendices,
and an index.
UM005004-0918
Z8018x
iv
Sections
Z8018X MPU Operation
Presents features, a general description, pins descriptions, block
diagrams, registers, and details of operating modes for the Z8018x MPUs.
Software Architecture
Provides instruction sets and CPU registers for the Z8018x MPUs.
DC Characteristics
Presents the DC parameters and absolute maximum ratings for the
Z8X180 MPUs.
AC Characteristics
Presents the AC parameters for the Z8018x MPUs.
Timing Diagrams
Contains timing diagrams and standard test conditions for the Z8018x
MPUs.
Appendices
The appendixes in this manual provide additional information applicable
to the Z8018x family of ZiLOG MPUs:
• Instruction set
• Instruction summary table
• Op Code map
• Bus Control signal conditions in each machine cycle and interrupt
conditions
• Operating mode summary
• Status signals
• I/O registers and ordering information
UM005004-0918
Z8018x
Table of Contents
Z80180, Z8S180, Z8L180 MPU Operation . . . . . . . . . . . . . . . . . . . .1
Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1
General Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1
Pin Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .7
Architecture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .12
Operation Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .15
CPU Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .18
Wait State Generator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .27
HALT and Low Power Operation Modes
(Z80180-Class Processors Only) . . . . . . . . . . . . . . . . . . . . . . . .31
Low Power Modes
(Z8S180/Z8L180 only) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .36
Add-On Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .36
STANDBY Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .37
STANDBY Mode Exit wiht BUS REQUEST . . . . . . . . . . . . . . . . .38
STANDBY Mode EXit with External Interrupts . . . . . . . . . . . . . . .39
IDLE Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40
STANDBY-QUICK RECOVERY Mode . . . . . . . . . . . . . . . . . . . .41
Internal I/O Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .41
MMU Register Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .60
Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .65
Interrupt Acknowledge Cycle Timings . . . . . . . . . . . . . . . . . . . . . .82
Interrupt Sources During RESET . . . . . . . . . . . . . . . . . . . . . . . . . . .83
Dynamic RAM Refresh Control . . . . . . . . . . . . . . . . . . . . . . . . . . .86
DMA Controller (DMAC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .90
Asynchronous Serial Communication Interface (ASCI) . . . . . . . .115
UM005004-0918
Z8018x
vi
Baud Rate Generator

(Z8S180/Z8L180-Class Processors Only) . . . . . . . . . . . . . . . 143
Clocked Serial I/O Port (CSI/O) . . . . . . . . . . . . . . . . . . . . . . . . . . 146
CSI/O Registers Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 147
Programmable Reload Timer (PRT) . . . . . . . . . . . . . . . . . . . . . . . 156
Miscellaneous . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 172
Software Architecture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 173

Instruction Set . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 173
CPU Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 175
DC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 185
Absolute Maximum Rating . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 185
Z80180 DC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 186
Z8S180 DC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 187
Z8L180 DC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 189
AC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 193
AC Characteristics—Z8S180 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 193
Timing Diagrams . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 197

Standard Test Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 205
Instruction Set . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 207

Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 207
Bit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 207
Condition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 208
Restart Address . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 209
UM005004-0918
Z8018x
vii
Flag . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .209
Miscellaneous . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .210
Data Manipulation Instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .211
Data Transfer Instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .222
Program and Control Instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . .229
Special Control Instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .235
Instruction Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .237

Op Code Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .247
Bus Control Signal Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . .251
Bus and Control Signal Condition in each Machine Cycle . . . . . . . . .251
Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .279
Operating Modes Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .281

Request Acceptances in Each Operating Mode . . . . . . . . . . . . . . . . . .281
Request Priority . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .282
Operation Mode Transition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .283
Other Operation Mode Transitions . . . . . . . . . . . . . . . . . . . . . . . . . . . .285
Status Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .287

Pin Outputs in Each Operating Mode . . . . . . . . . . . . . . . . . . . . . . . . . .287
Pin Status . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .288
I/O Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .293

Internal I/O Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .293
Ordering Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .303
UM005004-0918
Z8018x
viii
List of Figures
Figure 1. 64-Pin DIP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3
Figure 2. 68-Pin PLCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4
Figure 3. 80-Pin QFP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .5
Figure 4. Z80180/Z8S180/Z8L180 Block Diagram . . . . . . . . . . . . . . .6
Figure 5. Operation Mode Control Register . . . . . . . . . . . . . . . . . . . .15
Figure 6. M1 Temporary Enable Timing . . . . . . . . . . . . . . . . . . . . . .16
Figure 7. I/O Read and Write Cycles with IOC = 1
Timing Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .17
Figure 8. I/O Read and Write cycles with IOC = 0
Timing Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .17
Figure 9. Op Code Fetch (without Wait State) Timing Diagram . . . .19
Figure 10. Op Code Fetch (with Wait State) Timing Diagram . . . . . .20
Figure 11. Memory Read/Write (without Wait State)
Timing Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .21
Figure 12. Memory Read/Write (with Wait State)
Timing Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .22
Figure 13. I/O Read/Write Timing Diagram . . . . . . . . . . . . . . . . . . . .23
Figure 14. Instruction Timing Diagram . . . . . . . . . . . . . . . . . . . . . . . .24
Figure 15. RESET Timing Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . .25
Figure 16. Bus Exchange Timing During Memory Read . . . . . . . . . . .26
Figure 17. Bus Exchange Timing During CPU Internal Operation . . .27
Figure 18. WAIT Timing Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . .28
Figure 19. Memory and I/O Wait State Insertion
(DCNTL – DMA/Wait Control Register) . . . . . . . . . . . . . .29
Figure 20. HALT Timing Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . .33
UM005004-0918
Z8018x
ix
Figure 21. SLEEP Timing Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . 35

Figure 22. I/O Address Relocation . . . . . . . . . . . . . . . . . . . . . . . . . . . 43
Figure 23. Logical Address Mapping Examples . . . . . . . . . . . . . . . . . 55
Figure 24. Physical Address Transition . . . . . . . . . . . . . . . . . . . . . . . 56
Figure 25. MMU Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56
Figure 26. I/O Address Translation . . . . . . . . . . . . . . . . . . . . . . . . . . . 57
Figure 27. Logical Memory Organization . . . . . . . . . . . . . . . . . . . . . 58
Figure 28. Logical Space Configuration . . . . . . . . . . . . . . . . . . . . . . . 59
Figure 29. Physical Address Generation . . . . . . . . . . . . . . . . . . . . . . . 64
Figure 30. Physical Address Generation 2 . . . . . . . . . . . . . . . . . . . . . 64
Figure 31. Interrupt Sources . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65
Figure 32. TRAP Timing Diagram -2nd Op Code Undefined . . . . . . 71
Figure 33. TRAP Timing - 3rd Op Code Undefined . . . . . . . . . . . . . 72
Figure 34. NMI Use . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74
Figure 35. NMI Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75
Figure 36. INT0 Mode 0 Timing Diagram . . . . . . . . . . . . . . . . . . . . . 76
Figure 37. INT0 Mode 1 Interrupt Sequence . . . . . . . . . . . . . . . . . . . 77
Figure 38. INT0 Mode 1 Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78
Figure 39. INT0 Mode 2 Vector Acquisition . . . . . . . . . . . . . . . . . . . 79
Figure 40. INT0 Interrupt Mode 2 Timing Diagram . . . . . . . . . . . . . 80
Figure 41. INT1, INT2 Vector Acquisition . . . . . . . . . . . . . . . . . . . . 81
Figure 42. RETI Instruction Sequence . . . . . . . . . . . . . . . . . . . . . . . . 84
Figure 43. INT1, INT2 and Internal Interrupts Timing Diagram . . . . 86
Figure 44. Refresh Cycle Timing Diagram . . . . . . . . . . . . . . . . . . . . . 87
Figure 45. DMAC Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . 93
Figure 46. DMA Timing Diagram-CYCLE STEAL Mode . . . . . . . 106
Figure 47. CPU Operation and DMA Operation DREQ0
is Programmed for Level-Sense . . . . . . . . . . . . . . . . . . . 107
Figure 48. CPU Operation and DMA Operation DREQ0
is Programmed for Edge-Sense . . . . . . . . . . . . . . . . . . . . 108
UM005004-0918
Z8018x
Figure 49. TEND0 Output Timing Diagram . . . . . . . . . . . . . . . . . . .108

Figure 50. DMA Interrupt Request Generation . . . . . . . . . . . . . . . . .114
Figure 51. NMI and DMA Operation Timing Diagram . . . . . . . . . . .115
Figure 52. ASCI Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . .117
Figure 53. DCD0 Timing Diagram . . . . . . . . . . . . . . . . . . . . . . . . . .139
Figure 54. RTS0 Timing Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . .140
Figure 55. ASCI Interrupt Request Circuit Diagram . . . . . . . . . . . . .140
Figure 56. ASCI Clock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .141
Figure 57. CSI/O Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . .147
Figure 58. CSI/O Interrupt Request Generation . . . . . . . . . . . . . . . . .151
Figure 59. Transmit Timing Diagram–Internal Clock . . . . . . . . . . . .153
Figure 60. Transmit Timing–External Clock . . . . . . . . . . . . . . . . . . .154
Figure 61. CSI/O Receive Timing–Internal Clock . . . . . . . . . . . . . . .155
Figure 62. CSI/O Receive Timing–External Clock . . . . . . . . . . . . . .156
Figure 63. PRT Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . .157
Figure 64. Timer Initialization, Count Down, and Reload
Timing Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .163
Figure 65. Timer Output Timing Diagram . . . . . . . . . . . . . . . . . . . . .164
Figure 66. PRT Interrupt Request Generation . . . . . . . . . . . . . . . . . .164
Figure 67. E Clock Timing Diagram (During Read/Write Cycle
and Interrupt Acknowledge Cycle . . . . . . . . . . . . . . . . . .167
Figure 68. E Clock Timing in BUS RELEASE Mode . . . . . . . . . . . .167
Figure 69. E Clock Timing in SLEEP Mode and
SYSTEM STOP Mode . . . . . . . . . . . . . . . . . . . . . . . . . . .168
Figure 70. External Clock Interface . . . . . . . . . . . . . . . . . . . . . . . . . .169
Figure 71. Clock Generator Circuit . . . . . . . . . . . . . . . . . . . . . . . . . .170
Figure 72. Circuit Board Design Rules . . . . . . . . . . . . . . . . . . . . . . .170
Figure 73. Example of Board Design . . . . . . . . . . . . . . . . . . . . . . . . .171
UM005004-0918
Z8018x
xi
Software Architecture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 173

Figure 74. CPU Register Configurations . . . . . . . . . . . . . . . . . . . . . 176
Figure 75. Register Direct — Bit Field Definitions . . . . . . . . . . . . . 181
Figure 76. Register Indirect Addressing . . . . . . . . . . . . . . . . . . . . . . 181
Figure 77. Indexed Addressing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 182
Figure 78. Extended Addressing . . . . . . . . . . . . . . . . . . . . . . . . . . . . 182
Figure 79. Immediate Addressing . . . . . . . . . . . . . . . . . . . . . . . . . . . 183
Figure 80. Relative Addressing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 183
Timing Diagrams . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 197

Figure 81. AC Timing Diagram 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . 197
Figure 82. AC Timing Diagram 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . 198
Figure 83. CPU Timing (IOC = 0) (I/O Read Cycle,
I/O Write Cycle) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 199
Figure 84. DMA Control Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . 200
Figure 85. E Clock Timing (Memory R/W Cycle) (I/O R/W Cycle) 201
Figure 86. E Clock Timing (BUS RELEASE Mode, SLEEP Mode, and
SYSTEM STOP Mode . . . . . . . . . . . . . . . . . . . . . . . . . . 201
Figure 87. E Clock Timing (Minimum Timing Example of PWEL and
PWEH) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 202
Figure 88. Timer Output Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . 202
Figure 89. SLP Execution Cycle Timing Diagram . . . . . . . . . . . . . . 203
Figure 90. CSI/O Receive/Transmit Timing Diagram . . . . . . . . . . . 204
Figure 91. External Clock Rise Time and Fall Time . . . . . . . . . . . . 204
Figure 92. Input Rise Time and Fall Time
(Except EXTAL, RESET) . . . . . . . . . . . . . . . . . . . . . . . . 204
Figure 93. Test Setup . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 205
UM005004-0918
Z8018x
xii
List of Tables
Table 1. Status Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .10
Table 2. Multiplexed Pin Descriptions . . . . . . . . . . . . . . . . . . . . . . .12
Table 3. Memory Wait States . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .29
Table 4. Wait State Insertion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .30
Table 5. Power-Down Modes
(Z8S180/Z8L180-Class Processor Only) . . . . . . . . . . . . . .37
Table 6. I/O Address Map for Z80180-Class Processors Only . . . . .44
Table 7. I/O Address Map
(Z8S180/Z8L180-Class Processors Only) . . . . . . . . . . . . .48
Table 8. State of IEF1 and IEF2. . . . . . . . . . . . . . . . . . . . . . . . . . . . .69
Table 9. Vector Table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .82
Table 10. RETI Control Signal States . . . . . . . . . . . . . . . . . . . . . . . . .85
Table 11. DRAM Refresh Intervals . . . . . . . . . . . . . . . . . . . . . . . . . .89
Table 12. Channel 0 Destination . . . . . . . . . . . . . . . . . . . . . . . . . . . . .98
Table 13. Channel 0 Source . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .99
Table 14. Transfer Mode Combinations . . . . . . . . . . . . . . . . . . . . . . .99
Table 15. Channel 1 Transfer Mode . . . . . . . . . . . . . . . . . . . . . . . . .102
Table 16. DMA Transfer Request . . . . . . . . . . . . . . . . . . . . . . . . . . .110
Table 17. Data Formats . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .131
Table 18. Divide Ratio . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .134
Table 19. ASCI Baud Rate Selection . . . . . . . . . . . . . . . . . . . . . . . . .142
Table 20. Clock Mode Bit Values . . . . . . . . . . . . . . . . . . . . . . . . . . .144
Table 21. 2^ss Values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .145
Table 22. CSI/O Baud Rate Selection . . . . . . . . . . . . . . . . . . . . . . . .150
UM005004-0918
Z8018x
xiii
Table 23. Timer Output Control . . . . . . . . . . . . . . . . . . . . . . . . . . . .163

Table 24. E Clock Timing in Each Condition . . . . . . . . . . . . . . . . . .166
Table 25. Z8X180 Operating Frequencies . . . . . . . . . . . . . . . . . . . .169
Software Architecture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .173

Table 26. Instruction Set Summary . . . . . . . . . . . . . . . . . . . . . . . . . .173
DC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .185
Table 27. Absolute Maximum Rating . . . . . . . . . . . . . . . . . . . . . . . .185
Table 28. Z80180 DC Characteristics . . . . . . . . . . . . . . . . . . . . . . . .186
Table 29. Z8S180 DC Characteristics . . . . . . . . . . . . . . . . . . . . . . . .187
Table 30. Z8L180 DC Characteristics . . . . . . . . . . . . . . . . . . . . . . . .189
AC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .193
Table 31. Z8S180 AC Characteristics . . . . . . . . . . . . . . . . . . . . . . . 193
Instruction Set . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .207

Table 32. Register Values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .207
Table 33. Bit Values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .208
Table 34. Instruction Values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .208
Table 35. Address Values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .209
Table 36. Flag Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .209
Table 37. Operations Mnemonics . . . . . . . . . . . . . . . . . . . . . . . . . . .210
Table 38. Arithmetic and Logical Instructions (8-bit) . . . . . . . . . . . .211
Table 39. Rotate and Shift Instructions . . . . . . . . . . . . . . . . . . . . . . .216
Table 40. Arithmetic Instructions (16-bit) . . . . . . . . . . . . . . . . . . . . .221
Table 41. 8-Bit Load . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .222
Table 42. 16-Bit Load . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .223
UM005004-0918
Z8018x
xiv
Table 43. Block Transfer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 225

Table 44. Stock and Exchange . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 227
Table 45. Program Control Instructions . . . . . . . . . . . . . . . . . . . . . . 229
Table 46. I/O Instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 231
Table 47. Special Control Instructions . . . . . . . . . . . . . . . . . . . . . . . 235
Op Code Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 247

Table 48. 1st Op Code Map Instruction Format: XX . . . . . . . . . . . 247
Table 49. 2nd Op Code Map Instruction Format: CB XX . . . . . . . 249
Table 50. 2nd Op Code Map Instruction Format: ED XX . . . . . . . 250
Bus Control Signal Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . 251

Table 51. Bus and Control Signal Condition in Each
Machine Cycle . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 251
Table 52. Interrupts. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 279
Operating Modes Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 281

Table 53. Request Acceptances in Each Operating Mode . . . . . . . . 281
Table 54. The Z80180 Types of Requests . . . . . . . . . . . . . . . . . . . . 282
Status Signals 287

Table 55. Pin Outputs in Each Operating Mode. . . . . . . . . . . . . . . . 287
Table 56. Pin Status During RESET and
LOW POWER OPERATION Modes. . . . . . . . . . . . . . . . 289
I/O Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 293

Table 57. Internal I/O Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . 293
UM005004-0918
Z8018x
Z80180, Z8S180, Z8L180 MPU Operation

FEATURES
• Operating Frequency to 33 MHz
• On-Chip MMU Supports Extended Address Space
• Two DMA Channels
• On-Chip Wait State Generators
• Two Universal Asynchronous Receiver/Transmitter (UART) Channels
• Two 16-Bit Timer Channels
• On-Chip Interrupt Controller
• On-Chip Clock Oscillator/Generator
• Clocked Serial I/O Port
• Code Compatible with ZiLOG Z80 CPU
• Extended Instructions
GENERAL DESCRIPTION
Based on a microcoded execution unit and an advanced CMOS
manufacturing technology, the Z80180, Z8S180, Z8L180 (Z8X180) is an
8-bit MPU which provides the benefits of reduced system costs and low
power operation while offering higher performance and maintaining
compatibility with a large base of industry standard software written
around the ZiLOG Z8X CPU.
Higher performance is obtained by virtue of higher operating frequencies,
reduced instruction execution times, an enhanced instruction set, and an
UM005004-0918
Z8018x
on-chip memory management unit (MMU) with the capability of

addressing up to 1 MB of memory.
Reduced system costs are obtained by incorporating several key system

functions on-chip with the CPU. These key functions include I/O devices
such as DMA, UART, and timer channels. Also included on-chip are
several glue functions such as dynamic RAM refresh control, wait state
generators, clock oscillator, and interrupt controller.
Not only does the Z8X180 consume a low amount of power during
normal operation, but processors with Z8S180 and Z8L180 class
processors also provides two operating modes that are designed to
drastically reduce the power consumption even further. The SLEEP mode
reduces power by placing the CPU into a stopped state, thereby
consuming less current, while the on-chip I/O device is still operating.
The SYSTEM STOP mode places both the CPU and the on-chip
peripherals into a stopped state, thereby reducing power consumption
even further.
When combined with other CMOS VLSI devices and memories, the
Z8X180 provides an excellent solution to system applications requiring
high performance, and low power operation.
Figures 1 through 3 illustrate the three pin packages in the Z8X180 MPU
family:
• 64-Pin Dual In-line Package (DIP), Figure 1
• 68-Pin Plastic Leaded Chip Carrier (PLCC), Figure 2
• 80-Pin Quad Flat Pack (QFP), Figure 3
Pin out package descriptions for other Z8X180-based products are

covered in their respective product specifications.
Figure 4 depicts the block diagram that is shared throughout all

configurations of the Z8X180.
UM005004-0918
Z8018x
VSS 1 64 Phi
XTAL 2 63 RD
EXTAL 3 62 WR
WAIT 4 61 MI
BUSACK 5 60 E
BUSREQ 6 59 MREQ
RESET 7 58 IORQ
NMI 8 57 RFSH
INT0 9 56 HALT
INT1 10 55 TEND1
INT2 11 54 DREQ1
ST 12 53 CKS
A0 13 52 RXS/CTS1
A1 14 51 TXS
A2 15 50 CKA1/TEND0
A3 16 49 RXA1
A4 17
Z8X180
48 TXA1
A5 18 47 CKA0/DREQ0
A6 19 46 RXA0
A7 20 45 TXA0
A8 21 44 DCO0
A9 22 43 CTS0
A10 23 42 RTS0
A11 24 41 D7
A12 25 40 D6
A13 26 39 D5
A14 27 38 D4
A15 28 37 D3
A16 29 36 D2
A17 30 35 D1
A18/TOUT 31 34 D0
VCC 32 33 VSS
Figure 1. 64-Pin DIP
UM005004-0918
Z8018x
7 BUSREQ
6 BUSACK
8 RESET
EXTAL
63 MREQ
61 RFSH
62 IORQ
XTAL
5 WAIT
VSS
VLS
9 NMI
66 WR
68 Phi
67 RD
65 MI
64 E
2
4
1
3
INT0 10 60 HALT
INT1 11 59 TEND1
INT2 12 58 DREQ1
ST 13 57 CKS
A0 14 56 RXS/CTS1
A1 15 55 TXS
A2 16 54 CKA1/TEND0
A3 17 53 RXA1
VSS 18 Z8X180 52 TEST
A4 19 51 TXA1
A5 20 50 CKA0/DREQ0
A6 21 49 RXA0
A7 22 48 TXA0
A8 23 47 DCD0
A9 24 46 CTS0
A10 25 45 RTS0
A11 26 44 D7
A19 35
VCC 34
A16 31
A18/TOUT 33
A15 30
A17 32
VSS 36
D0 37
D1 38
D2 39
D3 40
D4 41
D5 42
D6 43
A13 28
A14 29
A12 27
Figure 2. 68-Pin PLCC
UM005004-0918
Z8018x
BUSREQ
BUSACK
RESET
EXTAL
MREQ
IORQ
WAIT
XTAL
VSS
VSS
WR
NC
RD
Phi
MI
E
68
67
66
65
80
79
78
77
76
75
74
73
72
71
70
69
NMI 1 64 RFSH
NC 2 63 NC
NC 3 62 NC
INT0 4 61 HALT
INT1 5 60 TEND1
INT2 6 59 DREQ1
ST 7 58 CKS
A0 8 57 RXS/CTS1
A1 9 Z8X180 56 TXS
A2 10 55 CKA1/TEND0
A3 11 54 RXA1
VSS 12 53 TEST
A4 13 52 TXA1
NC 14 51 NC
A5 15 50 CKA0/DREQ0
A6 16 49 RXA0
A7 17 48 TXA0
A8 18 47 DCD0
A9 19 46 CTS
A10 20 45 RTS0
A11 21 44 D7
NC 22 43 NC
NC 23 42 NC
A12 24 41 D6
22
23
24
25
10
11
12
13
14
15
16
17
18
19
20
21
A16
A19
A17
VCC
VSS
NC
A18/TOUT
A15
D3
A13
A14
D5
D2
D4
D0
D1
Figure 3. 80-Pin QFP
UM005004-0918
Z8018x
BUSREQ
BUSACK
RESET
EXTAL
MREQ
RFSH
XTAL
HALT
IORQ
WAIT
INT0
INT1
INT2
NMI
WR
RD
ST
MI
E
Bus State Control Interrupt
Timing
Phi Generator
CPU
(16-bit)
DREQ1
16-bit TEND1
A18/TOUT Programmable DMACs
Reload (2)
Data Bus (8-bit)
Timers
Address Bus
TXA0
TXS
Clocked CKA0/DREQ0
RXS/CTS1 Serial I/O
Port Asynchronous RXA0
CKS SCI
(Channel 0)
RTS0
CTS0
DCD0
TXA1
MMU Asynchronous CKA1/TEND0
SCI
(channel 1)
RXA1
Address Data
Buffer Buffer VCC
VSS
A0–A19 D0–DF
Figure 4. Z80180/Z8S180/Z8L180 Block Diagram
UM005004-0918
Z8018x
PIN DESCRIPTION
A0–A19. Address Bus (Output, Active High, 3-state). A0–A19 form a 20-
bit address bus. The Address Bus provides the address for memory data
bus exchanges, up to 1 MB, and I/O data bus exchanges, up to 64K. The
address bus enters a high impedance state during RESET and external bus
acknowledge cycles. Address line A18 is multiplexed with the output of
PRT channel 1 (TOUT, selected as address output on RESET) and address
line A19 is not available in DIP versions of the Z8X180.
BUSACK. Bus Acknowledge (Output, Active Low). BUSACK indicates
that the requesting device, the MPU address and data bus, and some
control signals, have entered their high impedance state.
BUSREQ. Bus Request (Input, Active Low). This input is used by
external devices (such as DMA controllers) to request access to the
system bus. This request has a higher priority than NMI and is always
recognized at the end of the current machine cycle. This signal stops the
CPU from executing further instructions and places the address and data
buses, and other control signals, into the high impedance state.
CKA0, CKA1. Asynchronous Clock 0 and 1 (Bidirectional, Active High).
These pins are the transmit and receive clocks for the ASCI channels.
CKA0, is multiplexed with DREQ0 and CKA1 is multiplexed with
TEND0.
CKS. Serial Clock (Bidirectional, Active High). This line is the clock for
the CSIO channel.
CLOCK (PHI). System Clock (Output, Active High). The output is used
as a reference clock for the MPU and the external system. The frequency
of this output is equal to one-half that of the crystal or input clock
frequency.
CTS0, CTS1. Clear to Send 0 and 1 (Inputs, Active Low). These lines are
modem control signals for the ASCI channels. CTS1 is multiplexed with RXS.
UM005004-0918
Z8018x
D0–D7. Data Bus (Bidirectional, Active High, 3-state). D0-D7 constitute

an 8-bit bidirectional data bus, used for the transfer of information to and
from I/O and memory devices. The data bus enters the high impedance
state during RESET and external bus acknowledge cycles.
DCD0. Data Carrier Detect 0 (Input, Active Low). This input is a
programmable modem control signal for ASCI channel 0.
DREQ0, DREQ1. DMA Request 0 and 1 (Input, Active Low). DREQ is
used to request a DMA transfer from one of the on-chip DMA channels.
The DMA channels monitor these inputs to determine when an external
device is ready for a read or write operation. These inputs can be
programmed to be either level- or edge-sensed. DREQ0 is multiplexed
with CKA0.
E. Enable Clock (Output, Active High). Synchronous machine cycle clock
output during bus transactions.
EXTAL. External Clock/Crystal (Input, Active High). Crystal oscillator
connection. An external clock can be input to the Z8X180 on this pin
when a crystal is not used. This input is Schmitt-triggered.
HALT. Halt/Sleep Status (Output, Active Low). This output is asserted
after the CPU has executed either the HALT or SLP instruction, and is
waiting for either non-maskable or maskable interrupt before operation
can resume. HALT is also used with the M1 and ST signals to decode
status of the CPU machine cycle.
INT0. Maskable Interrupt Request 0 (Input, Active Low). This signal is
generated by external I/O devices. The CPU honors this request at the end
of the current instruction cycle as long as the NMI and BUSREQ signals
are inactive. The CPU acknowledges this interrupt request with an
interrupt acknowledge cycle. During this cycle, both the M1 and IORQ
signals become Active.
INT1, INT2. Maskable Interrupt Requests 1 and 2 (Inputs, Active Low).
This signal is generated by external I/O devices. The CPU honors these
requests at the end of the current instruction cycle as long as the NMI,
UM005004-0918
Z8018x
BUSREQ, and INT0 signals are inactive. The CPU acknowledges these
interrupt requests with an interrupt acknowledge cycle. Unlike the
acknowledgment for INT0, during this cycle neither the M1 or IORQ
signals become Active.
IORQ. I/O Request (Output, Active Low, 3-state). IORQ indicates that the
address bus contains a valid I/O address for an I/O read or I/O write
operation. IORQ is also generated, along with M1, during the
acknowledgment of the INT0 input signal to indicate that an interrupt
response vector can be placed onto the data bus. This signal is analogous
to the IOE signal of the Z64180.
M1. Machine Cycle 1 (Output, Active Low). Together with MREQ, M1
indicates that the current cycle is the Op Code fetch cycle of an
instruction execution. Together with IORQ, M1 indicates that the current
cycle is for an interrupt acknowledge. It is also used with the HALT and
ST signal to decode status of the CPU machine cycle. This signal is
analogous to the LIR signal of the Z64180.
MREQ. Memory Request (Output, Active Low, 3-state). MREQ indicates
that the address bus holds a valid address for a memory read or memory
write operation. This signal is analogous to the ME signal of the Z64180.
NMI. Non-maskable Interrupt (Input, negative edge triggered). NMI has
a higher priority than INT and is always recognized at the end of an
instruction, regardless of the state of the interrupt enable flip-flops. This
signal forces CPU execution to continue at location 0066H.
RD. Read (Output active Low, 3-state). RD indicates that the CPU wants
to read data from memory or an I/O device. The addressed I/O or memory
device must use this signal to gate data onto the CPU data bus.
RFSH. Refresh (Output, Active Low). Together with MREQ, RFSH
indicates that the current CPU machine cycle and the contents of the
address bus must be used for refresh of dynamic memories. The low order
8 bits of the address bus (A7–A0) contain the refresh address.
This signal is analogous to the REF signal of the Z64180.
UM005004-0918
Z8018x
10
RTS0. Request to Send 0 (Output, Active Low). This output is a

programmable modem control signal for ASCI channel 0.
RXA0, RXA1. Receive Data 0 and 1 (Inputs, Active High). These signals
are the receive data to the ASCI channels.
RXS. Clocked Serial Receive Data (Input, Active High). This line is the
receiver data for the CSIO channel. RXS is multiplexed with the CTS1
signal for ASCI channel 1.
ST. Status (Output, Active High). This signal is used with the M1 and
HALT output to decode the status of the CPU machine cycle. Table 1
provides status summary.
Table 1. Status Summary
ST HALT M1 Operation
0 1 0 CPU operation (1st Op Code fetch)

1 1 0 CPU operation (2nd Op Code and 3rd Op Code fetch)
1 1 1 CPU operation (MC2 except for Op Code fetch)
0 X1 1 DMA operation
0 0 0 HALT mode
1 0 1 SLEEP mode (including SYSTEM STOP mode)
1. X = Don't care
2. MC = Machine cycle
TEND0, TEND1. Transfer End 0 and 1 (Outputs, Active Low). This

output is asserted active during the last write cycle of a DMA operation. It
is used to indicate the end of the block transfer. TEND0 in multiplexed
with CKA1.
TEST. Test (Output, not on DIP version). This pin is for test and must be
left open.
UM005004-0918
Z8018x
11
TOUT. Timer Out (Output, Active High). TOUT is the pulse output from
PRT channel 1. This line is multiplexed with A18 of the address bus.
TXA0, TXA1. Transmit Data 0 and 1 (Outputs, Active High). These
signals are the transmitted data from the ASCI channels. Transmitted data
changes are with respect to the falling edge of the transmit clock.
TXS. Clocked Serial Transmit Data (Output, Active High). This line is
the transmitted data from the CSIO channel.
WAIT. Wait (Input; Active Low). WAIT indicates to the CPU that the
addressed memory or I/O devices are not ready for a data transfer. This
input is used to induce additional clock cycles into the current machine
cycle. The WAIT input is sampled on the falling edge of T2 (and
subsequent Wait States). If the input is sampled Low, then additional Wait
States are inserted until the WAIT input is sampled High, at which time
execution continues.
WR. Write (Output, Active Low, 3-state). WR indicates that the CPU data
bus holds valid data to be stored at the addressed I/O or memory location.
XTAL. Crystal (Input, Active High). Crystal oscillator connection. This
pin must be left open if an external clock is used instead of a crystal. The
oscillator input is not a TTL level (reference DC characteristics).
Multiplexed pins are described in Table 2.
UM005004-0918
Z8018x
12
Table 2. Multiplexed Pin Descriptions
Multiplexed
Pins Descriptions
During RESET, this pin is initialized as A18 pin. If either

TOC1 or TOC0 bit of the Timer Control Register (TCR) is set
A18/TOUT
to 1, TOUT function is selected. If TOC1 and TOC0 bits are
cleared to 0, A18 function is selected.
During RESET, this pin is initialized as CKA0 pin.
CKA0/DREQ0 If either DM1 or SM1 in DMA Mode Register (DMODE) is
set to 1, DREQ0 function is always selected.
During RESET, this pin is initialized as CKA1 pin. If
CKA1D bit in ASCI control register ch 1 (CNTLA1) is set to
CKA1/TEND0
1, TEND0 function is selected. If CKA1D bit is set to 0,
CKA1 function is selected.
During RESET, this pin is initialized as RXS pin. If CTS1E bit
RXS/CTS1 in ASCI status register ch 1 (STAT1) is set to 1, CTS1 function
is selected. If CTS1E bit is 0, RXS function is selected.
ARCHITECTURE
The Z8X180 combines a high performance CPU core with a variety of
system and I/O resources useful in a broad range of applications. The CPU
core consists of five functional blocks: clock generator, bus state controller
(including dynamic memory refresh), interrupt controller, memory
management unit (MMU), and the central processing unit (CPU). The
integrated I/O resources make up the remaining four functional blocks:
• Direct Memory Access (DMA) Control (2 channels)
• Asynchronous Serial Communications Interface (ASCI, 2 channels),
UM005004-0918
Z8018x
13
• Programmable Reload Timers (PRT, 2 channels)
• Clock Serial I/O (CSIO) channel.
Other Z8X180 family members (such as Z80183, Z80S183, Z80185/195)

feature, in addition to these blocks, additional peripherals and are covered
in their associated Product Specification
Clock Generator
This logic generates the system clock from either an external crystal or
clock input. The external clock is divided by two and provided to both
internal and external devices.
Bus State Controller
This logic performs all of the status and bus control activity associated
with both the CPU and some on-chip peripherals. This includes Wait State
timing, RESET cycles, DRAM refresh, and DMA bus exchanges.
Interrupt Controller
This block monitors and prioritizes the variety of internal and external
interrupts and traps to provide the correct responses from the CPU. To
remain compatible with the Z80 CPU, three different interrupt modes are
supported.
Memory Management Unit
The MMU allows the user to map the memory used by the CPU (logically
only 64K) into the 1MB addressing range supported by the Z8X180. The
organization of the MMU object code features compatibility with the Z80
CPU while offering access to an extended memory space. This capability
is accomplished by using an effective common area - banked area
scheme.
UM005004-0918
Z8018x
14
Central Processing Unit

The CPU is microcoded to provide a core that is object code compatible
with the Z80 CPU. It also provides a superset of the Z80 instruction set,
including 8-bit multiply and divide. This core has been enhanced to allow
many of the instructions to execute in fewer clock cycles.
DMA Controller
The DMA controller provides high speed transfers between memory and
I/O devices. Transfer operations supported are memory-to-memory,
memory to/from I/O and I/O to I/O. Transfer modes supported are
REQUEST, BURST, and CYCLE STEAL. DMA transfers can access the
full 1MB addressing range with a block length up to 64KB, and can cross
over 64K boundaries.
Asynchronous Serial Communications Interface (ASCI)

The ASCI logic provides two individual full-duplex UARTs. Each
channel includes a programmable baud rate generator and modem control
signals. The ASCI channels can also support a multiprocessor
communications format.
Programmable Reload Timer (PRT)

This logic consists of two separate channels, each containing a 16-bit
counter (timer) and count reload register. The time base for the counters is
derived from the system clock (divided by 20) before reaching the
counter. PRT channel 1 provides an optional output to allow for
waveform generation.
Clocked Serial I/O (CSIO)

The CSIO channel provides a half-duplex serial transmitter and receiver.
This channel can be used for simple high-speed data connection to
another microprocessor or microcomputer.
UM005004-0918
Z8018x
15
OPERATION MODES
The Z8X180 can be configured to operate like the Hitachi HD64180. This
functionality is accomplished by allowing user control over the M1,
IORQ, WR, and RD signals. The Operation Mode Control Register
(OMCR), illustrated in Figure 5, determines the M1 options, the timing of
the IORQ, RD, and WR signals, and the RETI operation.
Operation Mode Control Register

Bit 7 6 5 4 0
Bit/Field M1E M1TE IOC Reserved
R/W R/W W R/W –
Reset 1 1 1 –
Note: R = Read W = Write X = Indeterminate? = Not Applicable
Figure 5. Operation Mode Control Register
M1E (M1 Enable): This bit controls the M1 output and is set to a 1 during
RESET.
When M1E is 1, the M1 output is asserted Low during the Op Code fetch
cycle, the INT0 acknowledge cycle, and the first machine cycle of the
NMI acknowledge. This action also causes the M1 signal to be Active
during both fetches of the RETI instruction sequence, and may cause
corruption of the external interrupt daisy chain. Therefore, this bit must be
0 for the Z8X180. When M1E is 0 the M1 output is normally inactive and
asserted Low only during the refetch of the RETI instruction sequence
and the INT0 acknowledge cycle (Figure 6).
UM005004-0918
Z8018x
16
T1 T2 T3 T1 T2 T3
Phi
WR
M1
Write into OMCR Op Code Fetch
Figure 6. M1 Temporary Enable Timing
M1TE (M1 Temporary Enable): This bit controls the temporary assertion
of the M1 signal. It is always read back as a 1 and is set to 1 during
RESET. This function is used to arm the internal interrupt structure of the
Z80PIO. When a control word is written to the Z80PIO to enable
interrupts, no enable actually takes place until the PIO sees an active M1
signal. When M1TE is 1, there is no change in the operation of the M1
signal and M1E controls its function. When M1TE is 0, the M1 output is
asserted during the next Op Code fetch cycle regardless of the state
programmed into the M1E bit. This situation is only momentary (one
time) and the user need not reprogram a 1 to disable the function (See
Figure 7).
IOC: This bit controls the timing of the IORQ and RD signals. IOC is set
to 1 by RESET.
When IOC is 1, the IORQ and RD signals function the same as the
HD64180.
UM005004-0918
Z8018x
17
T1 T2 TW T3
Phi
IORQ
RD
WR
Figure 7. I/O Read and Write Cycles with IOC = 1 Timing Diagram
When IOC is 0, the timing of the IORQ and RD signals match the timing
required by the Z80 family of peripherals. The IORQ and RD signals go
active as a result of the rising edge of T2. This timing allows the Z8X180
to satisfy the setup times required by the Z80 peripherals on those two
signals (Figure ).
T1 T2 TW T3
Phi
IORQ
RD
WR
Figure 8. I/O Read and Write cycles with IOC = 0 Timing Diagram
For the remainder of this document, assume that M1E is 0 and IOC is 0.
UM005004-0918
Z8018x
18
The user must program the Operation Mode Control Register

Note:
before the first I/O instruction is executed.
CPU Timing
This section explains the Z8X180 CPU timing for the following operations:
• Instruction (Op Code) fetch timing
• Operand and data read/write timing
• I/O read/write timing
• Basic instruction (fetch and execute) timing
• RESET timing
• BUSREQ/BUSACK bus exchange timing
The basic CPU operation consists of one or more Machine Cycles (MC).
A machine cycle consists of three system clocks, T1, T2, and T3 while
accessing memory or I/O, or it consists of one system clock (T1) during
CPU internal operations. The system clock is half the frequency of the
Crystal oscillator (that is, an 8-MHz crystal produces 4 MHz or 250 nsec).
For interfacing to slow memory or peripherals, optional Wait States (TW)
may be inserted between T2 and T3.
Instruction (Op Code) Fetch Timing

Figure 9 illustrates the instruction (Op Code) fetch timing with no Wait
States. An Op Code fetch cycle is externally indicated when the M1
output pin is Low.
In the first half of T1, the address bus (A0–A19) is driven from the
contents of the Program Counter (PC). This address bus is the translated
address output of the Z8X180 on-chip MMU.
In the second half of T1, the MREQ. (Memory Request) and RD (Read)
signals are asserted Low, enabling the memory.
UM005004-0918
Z8018x
19
The Op Code on the data bus is latched at the rising edge of T3 and the
bus cycle terminates at the end of T3.
T1 T2 T3 T1 T2
Phi
A0–A19
D0–D7
WAIT
M1
MREQ
RD
Figure 9. Op Code Fetch (without Wait State) Timing Diagram
Figure 10 illustrates the insertion of Wait States (TW) into the Op Code
fetch cycle. Wait States (TW) are controlled by the external WAIT input
combined with an on-chip programmable Wait State generator.
At the falling edge of T2 the combined WAIT input is sampled. If WAIT
input is asserted Low, a Wait State (TW) is inserted. The address bus,
MREQ, RD and M1 are held stable during Wait States. When WAIT is
sampled inactive High at the falling edge of TW, the bus cycle enters T3
and completes at the end of T3.
UM005004-0918
Z8018x
20
T1 T2 TW TW T3 T1 T2
Phi
A0–A19
D0–D7
Op Code
WAIT
M1
MREQ
RD
Figure 10. Op Code Fetch (with Wait State) Timing Diagram
Operand and Data Read/Write Timing

The instruction operand and data read/write timing differs from Op Code
fetch timing in two ways:
• The M1 output is held inactive
• The read cycle timing is relaxed by one-half clock cycle because data
is latched at the falling edge of T3
Instruction operands include immediate data, displacement, and extended
addresses, and contain the same timing as memory data reads.
During memory write cycles the MREQ signal goes active in the second
half of T1. At the end of T1, the data bus is driven with the write data.
At the start of T2, the WR signal is asserted Low enabling the memory.
MREQ and WR go inactive in the second half of T3 followed by
disabling of the write data on the data bus.
UM005004-0918
Z8018x
21
Wait States (TW) are inserted as previously described for Op Code fetch
cycles. Figure 11 illustrates the read/write timing without Wait States
(Tw), while Figure 12 illustrates read/write timing with Wait States (TW).
Read Cycle Write Cycle
T1 T2 T3 T1 T2 T3 T1
Phi
A0–A19 Memory address Memory address
D0–D7 Read data Write data
WAIT
MREQ
RD
WR
Figure 11. Memory Read/Write (without Wait State) Timing Diagram
UM005004-0918
Z8018x
22
Read Cycle Write Cycle

T1 T2 TW T3 T1 T2 TW T3
Phi
A0–A19
WAIT
MREQ
RD
WR
Figure 12. Memory Read/Write (with Wait State) Timing Diagram
I/O Read/Write Timing

I/O Read/Write operations differ from memory Read/Write operations in
the following three ways:
• The IORQ (I/O Request) signal is asserted Low instead of the MREQ
signal
• The 16-bit I/O address is not translated by the MMU
• A16–A19 are held Low
At least one Wait State (TW) is always inserted for I/O read and write
cycles (except internal I/O cycles).
Figure 13 illustrates I/O read/write timing with the automatically inserted
Wait State (TW).
UM005004-0918
Z8018x
23
I/O Read Cycle I/O Write Cycle
T1 T2 TW T3 T1 T2 TW T3
Phi
A0–A19 I/O address I/O address

WAIT
IORQ
RD
WR
Figure 13. I/O Read/Write Timing Diagram
Basic Instruction Timing

An instruction may consist of a number of machine cycles including Op
Code fetch, operand fetch, and data read/write cycles. An instruction may
also include cycles for internal processes which make the bus IDLE. The
example in Figure 14 illustrates the bus timing for the data transfer
instruction LD (IX+d),g.
UM005004-0918
Z8018x
24
1st Op Code 2nd Op Code Displacement CPU internal Memory Next instruction
Fetch Cycle Fetch Cycle Read Cycle Operation Write Cycle Fetch Cycle
T1 T2 T3 T1 T2 T3 T1 T2 T3 T1 T1 T1 T1 T2 T3 T1 T2
Phi
A0–A19 PC PC+1 PC+2 IX+d PC+3

(DDH) (7OH–77H) d g
D0–D7
M1
MREQ
RD
WR
Machine Cycle
MC1 MC2 MC3 MC4 MC5 MC6 MC7
NOTE: d = displacement
g = register contents
Figure 14. Instruction Timing Diagram
This instruction moves the contents of a CPU register (g) to the memory
location with address computed by adding a signed 8-bit displacement (d)
to the contents of an index register (IX).
The instruction cycle begins with the two machine cycles to read the two
byte instruction Op Code as indicated by M1 Low. Next, the instruction
operand (d) is fetched.
UM005004-0918
Z8018x
25
The external bus is IDLE while the CPU computes the effective address.
Finally, the computed memory location is written with the contents of the
CPU register (g).
RESET Timing
Figure 15 depicts the Z8X180 hardware RESET timing. If the RESET pin
is Low for six or more clock cycles, processing is terminated and the
Z8X180 restarts execution from (logical and physical) address 00000H.
RESET Start
RESET Op Code Fetch Cycle
T1 T2
Phi
6 or more clocks
RESET
High impedance
A0–A19 Restart address (00000H)
Figure 15. RESET Timing Diagram
BUSREQ/BUSACK Bus Exchange Timing

The Z8X180 can coordinate the exchange of control, address and data bus
ownership with another bus master. The alternate bus master can request
the bus release by asserting the BUSREQ (Bus Request) input Low. After
the Z8X180 releases the bus, it relinquishes control to the alternate bus
master by asserting the BUSACK (Bus Acknowledge) output Low.
The bus may be released by the Z8X180 at the end of each machine cycle.
In this context, a machine cycle consists of a minimum of three clock
cycles (more if wait states are inserted) for Op Code fetch, memory read/
write, and I/O read/write cycles. Except for these cases, a machine cycle
corresponds to one clock cycle.
UM005004-0918
Z8018x
26
When the bus is released, the address (A0–A19), data (D0–D7), and
control (MREQ, IORQ, RD, and WR) signals are placed in the high
impedance state.
Dynamic RAM refresh is not performed when the Z8X180 has released
the bus. The alternate bus master must provide dynamic memory
refreshing if the bus is released for long periods of time.
Figure 16 illustrates BUSREQ/BUSACK bus exchange during a memory
read cycle. Figure 17 illustrates bus exchange when the bus release is
requested during a Z8X180 CPU internal operation. BUSREQ is sampled
at the falling edge of the system clock prior to T3, T1 and Tx (BUS
RELEASE state). If BUSREQ is asserted Low at the falling edge of the
clock state prior to Tx, another Tx is executed.
CPU memory read cycle Bus release cycle CPU cycle
T1 T2 TW T3 TX TX T1 T1
Phi
A0–A19
D0–D7
MREQ
IORQ
RD, WR
BUSREQ
BUSACK
Figure 16. Bus Exchange Timing During Memory Read
UM005004-0918
Z8018x
27
CPU Internal Operation Bus Release Cycle CPU Cycle
T1 T1 T1 T1 TX TX TX T1
Phi
A0–A19
D0–D7
MREQ
IORQ
RD, WR
BUSREQ
BUSACK
Figure 17. Bus Exchange Timing During CPU Internal Operation
Wait State Generator

To ease interfacing with slow memory and I/O devices, the Z8X180 uses
Wait States (TW) to extend bus cycle timing. A Wait State(s) is inserted
based on the combined (logical OR) state of the external WAIT input and
an internal programmable wait state (TW) generator. Wait States (TW)
can be inserted in both CPU execution and DMA transfer cycles.
When the external WAIT input is asserted Low, Wait State(s) (TW) are
inserted between T2 and T3 to extend the bus cycle duration. The WAIT
input is sampled at the falling edge of the system clock in T2 or TW. If the
WAIT input is asserted Low at the falling edge of the system clock in TW,
another TW is inserted into the bus cycle.
Note: WAIT input transitions must meet specified setup and hold
times. This specification can easily be accomplished by
UM005004-0918
Z8018x
28
externally synchronizing WAIT input transitions with the rising

edge of the system clock.
Dynamic RAM refresh is not performed during Wait States (TW) and thus
system designs which use the automatic refresh function must consider
the affects of the occurrence and duration of wait states (TW). Figure 18
depicts WAIT timing.
T1 T2 TW TW T3 T1
Phi
WAIT
Figure 18. WAIT Timing Diagram
Programmable Wait State Insertion

In addition to the WAIT input, Wait States (TW) can also be inserted by
program using the Z8X180 on-chip Wait State generator (see Figure 19.
Wait State (TW) timing applies for both CPU execution and on-chip
DMAC cycles.
By programming the four significant bits of the DMA/Wait Control
Register (DCNTL) the number of Wait States, (TW) automatically
inserted in memory and I/O cycles, can be separately specified. Bits 4 and
5 specify the number of Wait States (TW) inserted for I/O access and bits
6 and 7 specify the number of Wait States (TW) inserted for memory
access. These bit pairs all 0–3 programmed Wait States for either I/O or
memory access.
UM005004-0918
Z8018x
29
Bit 7 6 5 4
MWI1 MWI0 MWI1 MWI0
R/W R/W R/W R/W
Figure 19. Memory and I/O Wait State Insertion (DCNTL – DMA/Wait
Control Register)
The number of Wait States (TW) inserted in a specific cycle is the

maximum of the number requested by the WAIT input, and the number
automatically generated by the on-chip Wait State generator.
Bit 7, 6: MWI1 MWI0, (Memory Wait Insertion)

For CPU and DMAC cycles which access memory (including memory
mapped I/O), zero to three Wait States may be automatically inserted
depending on the programmed value in MWI1 and MWI0 as depicted in
Table 3
Table 3. Memory Wait States
MW11 MWI0 The Number of Wait States
0 0 0
0 1 1
1 0 2
1 1 3
Bit 5, 4: IWI1, IWI0 (I/O Wait Insertion)

For CPU and DMA cycles which access external I/O (and interrupt
acknowledge cycles), one to six Wait States (TW) may be automatically
UM005004-0918
Z8018x
30
inserted depending on the programmed value in IWI1 and IWI0. Refer to

Table 4.
Table 4. Wait State Insertion
The Number of Wait States
For INT1, For NMI

INT2 and interrupt
For INT0 internal acknowledge
For internal interrupt interrupts cycles
For external I/ I/0 acknowledge acknowledge when M1 is
O registers registers cycles when cycles Low
IWI1 IWI0 accesses accesses M1 is Low (Note 2) (Note 2)
0 0 1 0 2 2 0
(Note 1)
0 1 2 4
1 0 3 5
1 1 4 6
Note:
1. For Z8X180 internal I/O register access (I/O addresses 0000H-003FH), IWI1 and IWI0 do not
determine wait state (TW) timing. For ASCI, CSI/O and PRT Data Register accesses, 0 to 4 Wait States
(TW) are generated. The number of Wait States inserted during access to these registers is a function of
internal synchronization requirements and CPU state. All other on-chip I/O register accesses (that is,
MMU, DMAC, ASCI Control Registers, for instance.) have no Wait States inserted and thus require only
three clock cycles.
2. For interrupt acknowledge cycles in which M1 is High, such as interrupt vector table read and PC
stacking cycle, memory access timing applies.
WAIT Input and RESET
During RESET, MWI1, MWI0 IWI1 and IWI0, are all 1, selecting the
maximum number of Wait States (TW) (three for memory accesses, four
for external I/O accesses).
UM005004-0918
Z8018x
31
Also, the WAIT input is ignored during RESET. For example, if RESET
is detected while the Z8X180 is in a Wait State (TW), the Wait Stated
cycle in progress is aborted, and the RESET sequence initiated. Thus,
RESET has higher priority than WAIT.
HALT and Low Power Operation Modes (Z80180-Class

Processors Only)
The Z80180 can operate in two different modes:
• HALT mode
• IOSTOP mode
and two low-power operation modes:
• SLEEP
• SYSTEM STOP
In all operating modes, the basic CPU clock (XTAL, EXTAL) must
remain active.
HALT Mode
HALT mode is entered by execution of the HALT instruction (Op Code
76H) and has the following characteristics:
• The internal CPU clock remains active
• All internal and external interrupts can be received
• Bus exchange (BUSREQ and BUSACK) can occur
• Dynamic RAM refresh cycle (RFSH) insertion continues at the
programmed interval
• I/O operations (ASCI, CSI/O and PRT) continue
• The DMAC can operate
UM005004-0918
Z8018x
32
• The HALT output pin is asserted Low

• The external bus activity consists of repeated dummy fetches of the
Op Code following the HALT instruction.
Essentially, the Z80180 operates normally in HALT mode, except that
instruction execution is stopped.
HALT mode can be exited in the following two ways:
• RESET Exit from HALT Mode
If the RESET input is asserted Low for at least six clock cycles,
HALT mode is exited and the normal RESET sequence (restart at
address 00000H) is initiated.
• Interrupt Exit from HALT mode
When an internal or external interrupt is generated, HALT mode is
exited and the normal interrupt response sequence is initiated.
If the interrupt source is masked (individually by enable bit, or globally
by IEF1 state), the Z80180 remains in HALT mode. However, NMI
interrupt initiates the normal NMI interrupt response sequence
independent of the state of IEF1.
HALT timing is illustrated in Figure 20.
UM005004-0918
Z8018x
33
.
HALT Op Code Interrupt
HALT mode acknowledge cycle
Fetch Cycle
T1 T3 T1 T2 T3 T1 T2
Phi
INT1, NMI
A0–A19 HALT Op Code address HALT Op Code address + 1
HALT
M1
MREQ
RD
Figure 20. HALT Timing Diagram
SLEEP Mode
SLEEP mode is entered by execution of the 2-byte SLP instruction.
SLEEP mode contains the following characteristics:
• The internal CPU clock stops, reducing power consumption
• The internal crystal oscillator does not stop
• Internal and external interrupt inputs can be received
• DRAM refresh cycles stop
• I/O operations using on-chip peripherals continue
• The internal DMAC stop
• BUSREQ can be received and acknowledged
• Address outputs go High and all other control signal outputs become
inactive High
UM005004-0918
Z8018x
34
• Data Bus, 3-state
SLEEP mode is exited in one of two ways as described below.
• RESET Exit from SLEEP mode. If the RESET input is held Low for
at least six clock cycles, it exits SLEEP mode and begins the normal
RESET sequence with execution starting at address (logical and
physical) 00000H.
• Interrupt Exit from SLEEP mode. The SLEEP mode is exited by

detection of an external (NMI, INT0, INT2) or internal (ASCI,
CSI/O, PRT) interrupt.
In case of NMI, SLEEP mode is exited and the CPU begins the normal
NMI interrupt response sequence.
In the case of all other interrupts, the interrupt response depends on the
state of the global interrupt enable flag IEF1 and the individual interrupt
source enable bit.
If the individual interrupt condition is disabled by the corresponding

enable bit, occurrence of that interrupt is ignored and the CPU remains in
the SLEEP mode.
Assuming the individual interrupt condition is enabled, the response to

that interrupt depends on the global interrupt enable flag (IEF1). If
interrupts are globally enabled (IEF1 is 1) and an individually enabled
interrupt occurs, SLEEP mode is exited and the appropriate normal
interrupt response sequence is executed.
If interrupts are globally disabled (IEF1 is 0) and an individually enabled

interrupt occurs, SLEEP mode is exited and instruction execution begins
with the instruction following the SLP instruction. This feature provides a
technique for synchronization with high speed external events without
incurring the latency imposed by an interrupt response sequence.
Figure 21 depicts SLEEP timing.
UM005004-0918
Z8018x
35
SLP 2nd Op Code Op Code Fetch or Interrupt

Fetch Cycle SLEEP mode Acknowledge Cycle
T2 T3 T1 T2 TS TS T1 T2 T3
Phi
INT1, NMI
A0–A19 SLP 2nd Op Code address FFFFFH
HALT
M1
Figure 21. SLEEP Timing Diagram
IOSTOP Mode
IOSTOP mode is entered by setting the IOSTOP bit of the I/O Control
Register (ICR) to 1. In this case, on-chip I/O (ASCI, CSI/O, PRT) stops
operating. However, the CPU continues to operate. Recovery from
IOSTOP mode is by resetting the IOSTOP bit in ICR to 0.
SYSTEM STOP Mode
SYSTEM STOP mode is the combination of SLEEP and IOSTOP modes.

SYSTEM STOP mode is entered by setting the IOSTOP bit in ICR to 1
followed by execution of the SLP instruction. In this mode, on-chip I/O
and CPU stop operating, reducing power consumption. Recovery from
SYSTEM STOP mode is the same as recovery from SLEEP mode, noting
that internal I/O sources, (disabled by IOSTOP) cannot generate a
recovery interrupt.
UM005004-0918
Z8018x
36
Low Power Modes (Z8S180/Z8L180 only)

The following section is a detailed description of the enhancements to the
Z8S180/L180 from the standard Z80180 in the areas of STANDBY, IDLE
and STANDBY QUICK RECOVERY modes.
Add-On Features
There are five different power-down modes. SLEEP and SYSTEM STOP
are inherited from the Z80180. In SLEEP mode, the CPU is in a stopped
state while the on-chip I/Os are still operating. In I/O STOP mode, the on-
chip I/Os are in a stopped state while leaving the CPU running. In
SYSTEM STOP mode, both the CPU and the on-chip I/Os are in the
stopped state to reduce current consumption. The Z8S180 features two
additional power-down modes, STANDBY and IDLE, to reduce current
consumption even further. The differences in these power-down modes
are summarized in Table 5.
UM005004-0918
Z8018x
37
Table 5. Power-Down Modes (Z8S180/Z8L180-Class Processors Only)
Power-
Down On-Chip Recovery Recovery Time
Modes CPU Core I/O Osc. CLKOUT Source (Minimum)
SLEEP Stop Running Running Running RESET, 1.5 Clock

Interrupts
I/O STOP Running Stop Running Running By –
Programming
SYSTEM Stop Stop Running Running RESET, 1.5 Clock
STOP Interrupts
IDLE † Stop Stop Running Stop RESET, 8 + 1.5 Clock
Interrupts,
BUSREQ
STANDBY † Stop Stop Stop Stop RESET, 217 + 1.5 Clock
Interrupts, (Normal
BUSREQ Recovery)
26 + 1.5 Clock
(Quick Recovery)
† IDLE and STANDBY modes are only offered in the Z8S180. The minimum recovery time can
be achieved if INTERRUPT is used as the Recovery Source.
STANDBY Mode
The Z8S180/Z8L180 is designed to save power. Two low-power
programmable power-down modes have been added:
• STANDBY mode
• IDLE mode
The STANDBY/IDLE mode is selected by multiplexing bits 1 and 3 of
the CPU Control Register (CCR, I/O Address = 1FH).
To enter STANDBY mode:
UM005004-0918
Z8018x
38
1. Set bits 6 and 3 to 1 and 0, respectively.

2. Set the I/O STOP bits (bit 5 of ICR, I/O Address = 3FH) to 1.
3. Execute the SLEEP instruction.
When the device is in STANDBY mode, it performs similar to the
SYSTEM STOP mode as it exists on the Z80180-class processors, except
that the STANDBY mode stops the external oscillator, internal clocks and
reduces power consumption to 50 μA (typical).
Because the clock oscillator has been stopped, a restart of the oscillator
requires a period of time for stabilization. An 18-bit counter has been
added in the Z8S180Z8L180 to allow for oscillator stabilization. When
the part receives an external IRQ or BUSREQ during STANDBY mode,
the oscillator is restarted and the timer counts down 217 counts before
acknowledgment is sent to the interrupt source.
The recovery source must remain asserted for the duration of the 217
count, otherwise STANDBY restarts.
STANDBY Mode Exit with BUS REQUEST

Optionally, if the BREXT bit (D5 of CPU Control Register) is set to 1, the
Z8S180 exits STANDBY mode when the BUSREQ input is asserted. The
crystal oscillator is then restarted. An internal counter automatically
provides time for the oscillator to stabilize, before the internal clocking
and the system clock output of the Z8S180 are resumed.
The Z8S180 relinquishes the system bus after the clocking is resumed by:
• 3-State the address outputs A19–A0
• 3-State the bus control outputs MREQ, IORQ, RD, and WR
• Asserting BUSACK
The Z8S180 regains the system bus when BUSREQ is deactivated. The
address outputs and the bus control outputs are then driven High. The
STANDBY mode is exited.
UM005004-0918
Z8018x
39
If the BREXT bit of the CPU Control Register (CCR) is cleared, asserting
the BUSREQ does not cause the Z8S180/Z8L180-class processors to exit
STANDBY mode.
If STANDBY mode is exited because of a reset or an external interrupt,
the Z8S180/Z8L180-class processors remains relinquished from the
system bus as long as BUSREQ is active.
STANDBY Mode EXit with External Interrupts

STANDBY mode can be exited by asserting input NMI. The STANDBY
mode may also exit by asserting INT0. INT1 or INT2, depending on the
conditions specified in the following paragraphs.
INT0 wake-up requires assertion throughout duration of clock
stabilization time (217 clocks).
If exit conditions are met, the internal counter provides time for the
crystal oscillator to stabilize, before the internal clocking and the system
clock output within the Z8S180/Z8L180-class processors resume.
• Exit with Non-Maskable Interrupts
If NMI is asserted, the CPU begins a normal NMI interrupt
acknowledge sequence after clocking resumes.
• Exit with External Maskable Interrupts
If an External Maskable Interrupt input is asserted, the CPU responds
according to the status of the Global Interrupt Enable Flag IEF1
(determined by the ITE1 bit) and the settings of the corresponding
interrupt enable bit in the Interrupt/Trap Control Register (ITC: I/O
Address = 34H).
If an interrupt source is disabled in the ITC, asserting the corresponding
interrupt input does not cause the Z8S180/Z8L180-class processors to
exit STANDBY mode. This condition is true regardless of the state of the
Global Interrupt Enable Flag IEF1.
UM005004-0918
Z8018x
40
If the Global Interrupt Enable Flag IEF1 is set to 1, and if an interrupt

source is enabled in the ITC, asserting the corresponding interrupt input
causes the Z8S180/Z8L180-class processors to exit STANDBY mode.
The CPU performs an interrupt acknowledge sequence appropriate to the
input being asserted when clocking is resumed if:
• The interrupt input follows the normal interrupt daisy-chain protocol
• The interrupt source is active until the acknowledge cycle is complete
If the Global Interrupt Enable Flag IEF1 is disabled (reset to 0) and if an
interrupt source is enabled in the ITC, asserting the corresponding
interrupt input still causes the Z8S180/Z8L180-class processors to exit
STANDBY mode. The CPU proceeds to fetch and execute instructions
that follow the SLEEP instruction when clocking resumes.
If the Extend Maskable Interrupt input is not active until clocking
resumes, the Z8S180/Z8L180-class processors do not exit STANDBY
mode. If the Non-Maskable Interrupt (NMI) is not active until clocking
resumes, the Z8S180/Z8L180-class processors still exits the STANDBY
mode even if the interrupt sources go away before the timer times out,
because NMI is edge-triggered. The condition is latched internally when
NMI is asserted Low.
IDLE Mode
IDLE mode is another power-down mode offered by the Z8S180/
Z8L180-class processors.
2. Set the I/O STOP bit (bit 5 of ICR, I/O Address = 3FH to 1.
3. Execute the SLEEP instruction
When the part is in IDLE mode, the clock oscillator is kept oscillating, but
the clock to the rest of the internal circuit, including the CLKOUT, is
stopped completely. IDLE mode is exited in a similar way as STANDBY
mode, using RESET, BUS REQUEST or EXTERNAL INTERRUPTS,
UM005004-0918
Z8018x
41
except that the 217 bit wake-up timer is bypassed. All control signals are
asserted eight clock cycles after the exit conditions are gathered.
STANDBY-QUICK RECOVERY Mode
STANDBY-QUICK RECOVERY mode is an option offered in

STANDBY mode to reduce the clock recovery time in STANDBY mode
from 217 clock cycles (4 μs at 33 MHz) to 26 clock cycles (1.9 μs at 33
MHz). This feature can only be used when providing an oscillator as
clock source.
To enter STANDBY-QUICK RECOVERY mode:
2. Set the I/O STOP bit (bit 5 of ICR, I/O Address = 3FH) to 1.
3. Execute the SLEEP instruction
When the part is in STANDBY-QUICK RECOVERY mode, the operation

is identical to STANDBY mode except when exit conditions are gathered,
using RESET, BUS REQUEST or EXTERNAL INTERRUPTS. The
clock and other control signals are recovered sooner than the STANDBY
mode.
Note: If STANDBY-QUICK RECOVERY is enabled, the user must

ensure stable oscillation is obtained within 64 clock cycles
Internal I/O Registers
The Z8X180 internal I/O Registers occupy 64 I/O addresses (including

reserved addresses). These registers access the internal I/O modules
(ASCI, CSI/O, PRT) and control functions (DMAC, DRAM refresh,
interrupts, wait state generator, MMU and I/O relocation).
UM005004-0918
Z8018x
42
To avoid address conflicts with external I/O, the Z8X180 internal I/O
addresses can be relocated on 64-byte boundaries within the bottom 256
bytes of the 64KB I/O address space.
I/O Control Register (ICR)

ICR allows relocating of the internal I/O addresses. ICR also controls
enabling/disabling of the IOSTOP mode.
I/O Control Register (ICR: 3FH)

Bit 7 6 5 4 3 2 1 0
Bit/Field IOA7 IOA6 IOSTP — — — — —
R/W R/W R/W R/W
Reset 0 0 0
R = Read W = Write X = Indeterminate ? = Not Applicable
Bit
Position Bit/Field R/W Value Description
7– 6 IOA7:6 R/W IOA7 and IOA6 relocate internal I/O as depicted in

Figure . The high-order 8 bits of 16-bit internal I/O
addresses are always 0. IOA7 and IOA6 are cleared to 0
during RESET.
5 IOSTP R/W IOSTOP mode is enabled when IOSTP is set to 1.
Normal. I/O operation resumes when IOSTP is reset to 0.
UM005004-0918
Z8018x
43
00FFH
IOA7 — IOA6 = 1 1
00C0H
00BFH
IOA7 — IOA6 = 1 0
0080H
007FH
IOA7 — IOA6 = 0 1
0040H
003FH
IOA7 — IOA6 = 0 0
0000H
Figure 22. I/O Address Relocation
Internal I/O Registers Address Map

The internal I/O register addresses are described in Table 6 and Table 7.
These addresses are relative to the 64-byte boundary base address specified
in ICR.
I/O Addressing Notes

The internal I/O register addresses are located in the I/O address space
from 0000H to 00FFH (16-bit I/O addresses). Thus, to access the internal
I/O registers (using I/O instructions), the high-order 8 bits of the 16-bit
I/O address must be 0.
The conventional I/O instructions (OUT (m), A/IN A, (m) / OUTI/INI,
for example) place the contents of a CPU register on the high-order 8 bits
of the address bus, and thus may be difficult to use for accessing internal
I/O registers.
For efficient internal I/O register access, a number of new instructions
have been added, which force the high-order 8 bits of the 16-bit I/O
UM005004-0918
Z8018x
44
address to 0. These instructions are IN0, OUT0, OTIM, OTIMR, OTDM,

OTDMR and TSTIO (see Instruction Set).
When writing to an internal I/O register, the same I/O write occurs on the
external bus. However, the duplicate external I/O write cycle exhibits
internal I/O write cycle timing. For example, the WAIT input and
programmable Wait State generator are ignored. Similarly, internal I/O
read cycles also cause a duplicate external I/O read cycle. However, the
external read data is ignored by the Z8X180.
Normally, external I/O addresses should be chosen to avoid overlap with

internal I/O addresses and duplicate I/O accesses.
Table 6. I/O Address Map for Z80180-Class Processors Only
Address
Register Mnemonic Binary Hex Page
ASCI ASCI Control Register A Ch 0 CNTLA0 XX000000 00H 125

ASCI Control Register A Ch 1 CNTLA1 XX000001 01H 128
ASCI Control Register B Ch 0 CNTLB0 XX000010 02H 132
ASCI Status Register Ch 0 STAT0 XX000100 04H 120
ASCI Transmit Data Register Ch 0 TDR0 XX000110 06H 118
ASCI Receive Data Register Ch 0 RDR0 XX001000 08H 119
CSI/O CSI/O Control Register CNTR XX001010 0AH 147
CSI/O Transmit/Receive Data Register TRD XX1011 0BH 149
UM005004-0918
Z8018x
45
Table 6. I/O Address Map for Z80180-Class Processors Only (Continued)
Address
Timer Data Register Ch 0 L TMDR0L XX001100 0CH 159

Data Register Ch 0 H TMDR0H XX001101 0DH 159
Reload Register Ch 0 L RLDR0L XX001110 0EH 159
Reload Register Ch 0 H RLDR0H XX001111 0FH 159
Timer Control Register TCR XX010000 10H 161
Reserved XX010001 11H
XX010011 13H
Data Register Ch 1 L TMDR1L XX010100 14H 160
Data Register Ch 1 H TMDR1H XX010101 15H 160
Reload Register Ch 1 L RLDR1L XX010110 16H 159
Reload Register Ch 1 H RLDR1H XX010111 17H 159
Others Free Running Counter FRC XX011000 18H 172
Reserved
XX011001 19H
XX011111 1FH
UM005004-0918
Z8018x
46
Address
DMA DMA Source Address Register Ch 0L SAR0L XX100000 20H 93

DMA Source Address Register Ch 0H SAR0H XX100001 21H 93
DMA Source Address Register Ch 0B SAR0B XX100010 22H 93
DMA Destination Address Register Ch DAR0L XX100011 23H 94
0L
DMA Destination Address Register Ch DAR0H XX100100 24H 94
0H
DMA Destination Address Register Ch DAR0B XX100101 25H 94
0B
DMA Byte Count Register Ch 0L BCR0L XX100110 26H 94
DMA Byte Count Register Ch 0H BCR0H XX100111 27H 94
DMA Memory Address Register Ch 1L MAR1L XX101000 28H 94
DMA Memory Address Register Ch 1H MAR1H XX101001 29H 94
DMA Memory Address Register Ch 1B MAR1B XX101010 2AH 94
DMA I/0 Address Register Ch 1L IAR1L XX101011 2BH 102
DMA I/0 Address Register Ch 1H IAR1H XX101100 2CH 102
Reserved XX101101 2DH
DMA Byte Count Register Ch 1L BCR1L XX101110 2EH 94
DMA Byte Count Register Ch 1H BCR1H XX101111 2FH 94
DMA Status Register DSTAT XX110000 30H 95
DMA Mode Register DMODE XX110001 31H 97
DMA/WAIT Control Register DCNTL XX110010 32H 101
UM005004-0918
Z8018x
47
Address
INT IL Register (Interrupt Vector Low IL XX110011 33H 67

Register)
INT/TRAP Control Register ITC XX110100 34H 68
Refresh Refresh Control Register RCR XX110110 36H 88
MMU MMU Common Base Register CBR XX111000 38H 61
MMU Bank Base Register BBR XX111001 39H 62
MMU Common/Bank Area Register CBAR XX111010 3AH 60
I/O Reserved XX111011 3BH
XX111101 3DH
Operation Mode Control Register OMCR XX111110 3EH 15
I/O Control Register ICR XX111111 3FH 42
UM005004-0918
Z8018x
48
Table 7. I/O Address Map (Z8S180/Z8L180-Class Processors Only)
Address
ASCI ASCI Control Register A Ch 0 CNTLA0 XX000000 00H 125

ASCI Control Register A Ch 1 CNTLA1 XX000001 01H 128
ASCI0 Extension Control Register 0 ASEXT0 XX010010 12H 135
ASCI1 Extension Control Register 1 ASEXT1 XX010011 13H 136
ASCI0 Time Constant Low ASTC0L XX011010 1AH 137
ASCI0 Time Constant High ASTC0H XX001011 1BH 137
ASCI1 Time Constant Low ASCT1L XX001100 1CH 138
ASCI1 Time Constant High ASCT1H XX001101 1DH 138
CSI0 CSI0 Control Register CNTR XX001010 0AH 147
CSI0 Transmit/Receive Data Register TRD XX1011 0BH 149
UM005004-0918
Z8018x
49
Table 7. I/O Address Map (Z8S180/Z8L180-Class Processors Only) (Continued)
Address
Timer Data Register Ch 0 L TMDR0L XX001100 0CH 159

Data Register Ch 0 H TMDR0H XX001101 0DH 159
Reload Register Ch 0 L RLDR0L XX001110 0EH 159
Reload Register Ch 0 H RLDR0H XX001111 0FH 159
Timer Control Register TCR XX010000 10H 161
Data Register Ch 1 L TMDR1L XX010100 14H 160
Data Register Ch 1 H TMDR1H XX010101 15H 160
Reload Register Ch 1 L RLDR1L XX010110 16H 160
Reload Register Ch 1 H RLDR1H XX010111 17H 160
Others Free Running Counter FRC XX011000 18H 172
Reserved
XX011001 19H
XX011111 1DH
Clock Multiplier Register CMR XX011110 1EH 52
CPU Control Register CCR XX011111 1FH 53
UM005004-0918
Z8018x
50
Address
DMA DMA Source Address Register Ch 0L SAR0L XX100000 20H 93

DMA Source Address Register Ch 0H SAR0H XX100001 21H 93
DMA Source Address Register Ch 0B SAR0B XX100010 22H 93
DMA Destination Address Register Ch DAR0L XX100011 23H 94
0L
DMA Destination Address Register Ch DAR0H XX100100 24H 94
0H
DMA Destination Address Register Ch DAR0B XX100101 25H 94
0B
DMA Byte Count Register Ch 0L BCR0L XX100110 26H 94
DMA Byte Count Register Ch 0H BCR0H XX100111 27H 94
DMA Memory Address Register Ch 1L MAR1L XX101000 28H 94
DMA Memory Address Register Ch 1H MAR1H XX101001 29H 94
DMA Memory Address Register Ch 1B MAR1B XX101010 2AH 94
DMA I/O Address Register Ch 1L IAR1L XX101011 2BH 102
DMA I/O Address Register Ch 1H IAR1H XX101100 2CH 102
DMA I/O Address Register Ch 1 IAR1B XX101101 2DH 94
DMA Byte Count Register Ch 1L BCR1L XX101110 2EH 94
DMA Byte Count Register Ch 1H BCR1H XX101111 2FH 94
DMA Status Register DSTAT XX110000 30H 95
DMA Mode Register DMODE XX110001 31H 97
DMA/WAIT Control Register DCNTL XX110010 32H 101
UM005004-0918
Z8018x
51
Address
INT IL Register (Interrupt Vector Low IL XX110011 33H 67

Register)
INT/TRAP Control Register ITC XX110100 34H 68
Refresh Refresh Control Register RCR XX110110 36H 88
MMU MMU Common Base Register CBR XX111000 38H 61
MMU Bank Base Register BBR XX111001 39H 62
MMU Common/Bank Area Register CBAR XX111010 3AH 60
I/O Reserved XX111011 3BH
XX111101 3DH
Operation Mode Control Register OMCR XX111110 3EH 15
I/O Control Register ICR XX111111 3FH 42
UM005004-0918
Z8018x
52
Clock Multiplier Register (CMR: 1EH) (Z8S180/L180-Class Processors Only)

Bit 7 6 0
Bit/Field X2 Reserved
R/W R/W ?
Reset 0 1
Note: R = Read W = Write X = Indeterminate ? = Not Applicable
Bit
7 X2 Clock R/W X2 Clock Multiplier Mode

Multiplier 0 Disable
Mode 1 Enable
6– 0 Reserved ? ? Reserved
UM005004-0918
Z8018x
53
CPU Control Register (CCR: 1FH) (Z8S180/L180-Class Processors Only)

Bit 7 6 5 4 3 2 1 0
Bit/Field Clock STAND BREXT LNPHI STAND LNIO LNCPU LNAD/
Divide BY/ BY/ CTL DATA
IDLE IDLE
Enable Enable
R/W R/W R/W R/W R/W R/W R/W R/W R/W
Reset 0 0 0 0 0 0 0 0
Bit
7 Clock R/W 0 XTAL/2

Divide 1 XTAL/1
6 STANDBY R/W In conjunction with Bit 3
/IDLE Mode 00 No STANDBY
01 IDLE after SLEEP
10 STANDBY after SLEEP
11 STANDBY after SLEEP 64 Cycle Exit (Quick
Recovery)
5 BREXT R/W 0 Ignore BUSREQ in STANDBY/IDLE
1 STANDBY/IDLE exit on BUSREQ
4 LNPHI R/W 0 Standard Drive
1 33% Drive on EXTPHI Clock
3 STANDBY R/W In conjunction with Bit 6
/IDLE Mode 00 No STANDBY
01 IDLE after SLEEP
10 STANDBY after SLEEP
11 STANDBY after SLEEP 64 Cycle Exit (Quick
Recovery)
UM005004-0918
Z8018x
54
Bit
2 LNIO R/W 0 Standard Drive

1 33% Drive on certain external I/O
1 LNCPUCTL R/W 0 Standard Drive
1 33% Drive on CPU control signals
0 LNAD/ R/W 0 Standard Drive
DATA 1 33% drive on A10–A0, D7–D0
Memory Management Unit (MMU)

The Z8X180 features an on-chip MMU which performs the translation of
the CPU 64KB (16-bit addresses 0000H to FFFFH) logical memory
address space into a 1024KB (20-bit addresses 00000H to FFFFFH)
physical memory address space. Address translation occurs internally in
parallel with other CPU operation.
Logical Address Spaces

The 64KB CPU logical address space is interpreted by the MMU as
consisting of up to three separate logical address areas, Common Area 0,
Bank Area, and Common Area 1.
As depicted in Figure 23, a variety of logical memory configurations are
possible. The boundaries between the Common and Bank Areas can be
programmed with 4KB resolution.
UM005004-0918
Z8018x
55
Common Common Common

Area 1 Area 1 Area 1
Common
Bank Area Area 1
Bank Common
Area Area 0
Common
Area 0
Figure 23. Logical Address Mapping Examples
Logical to Physical Address Translation

Figure 24 illustrates an example in which the three logical address space
portions are mapped into a 1024KB physical address space. The
important points to note are that Common and Bank Areas can overlap
and that Common Area 1 and Bank Area can be freely relocated (on 4KB
physical address boundaries). Common Area 0 (if it exists) is always
based at physical address 00000H.
UM005004-0918
Z8018x
56
FFFFFH
z
FFFFH
Common Area 1 + Common Base
Bank Area + Bank Base

y
Common Area 0 + 0
0000H
xyz
Logical Address Space x

00000H
Physical Address Space
Figure 24. Physical Address Transition
MMU Block Diagram

The MMU block diagram is depicted in Figure 25. The MMU translates
internal 16-bit logical addresses to external 20-bit physical addresses.
Internal Address/Data Bus

4
LA12—LA15
MMU Common/Bank Area MMU Common Base
Register; CBAR (8) Memory Register; CBR (8)
Management
Unit MMU Bank Base
Register; BBR (8)
8
PA12—PA19
LA: Logical Address
PA: Physical Address
Figure 25. MMU Block Diagram
UM005004-0918
Z8018x
57
Whether address translation (Figure 26) takes place depends on the type
of CPU cycle as follows.
• Memory Cycles
Address Translation occurs for all memory access cycles including
instruction and operand fetches, memory data reads and writes,
hardware interrupt vector fetch, and software interrupt restarts.
• I/O Cycles
The MMU is logically bypassed for I/O cycles. The 16-bit logical I/O
address space corresponds directly with the 16-bit physical I/O
address space. The four high-order bits (A16–A19) of the physical
address are always 0 during I/O cycles.
LA15 LA0
“0000” Logical Address
PA19 PA16 PA15 PA0

Physical Address
Figure 26. I/O Address Translation
• DMA Cycles
When the Z8X180 on-chip DMAC is using the external bus, the
MMU is physically bypassed. The 20-bit source and destination
registers in the DMAC are directly output on the physical address bus
(A0–A19).
MMU Registers
Three MMU registers are used to program a specific configuration of
logical and physical memory.
UM005004-0918
Z8018x
58
• MMU Common/Bank Area Register (CBAR)

• MMU Common Base Register (CBR)
• MMU Bank Base Register (BBR)
CBAR is used to define the logical memory organization, while CBR and
BBR are used to relocate logical areas within the 1024KB physical
address space. The resolution for both setting boundaries within the
logical space and relocation within the physical space is 4KB.
The CA field of CBAR determines the start address of Common Area 1
(Upper Common) and by default, the end address of the Bank Area. The
BA field determines the start address of the Bank Area and by default, the
end address of Common Area 0 (Lower Common).
The CA and BA fields of CBAR may be freely programmed subject only
to the restriction that CA may never be less than BA. Figures 27 and 28
illustrate examples of logical memory organizations associated with
different values of CA and BA.
Common Common Common

Area 1 Area 1 Area 1
Common
Bank Area Area 1
Bank Area Common

Area 0
Common
Area 0
Common Area 1 Common Area 1 Common Area 1 Common Area 1

Lower Limit Address Lower lImit Address Lower Limit Address Lower Limit Address
> > = =
Bank Area Bank Area Bank Area Bank Area
Lower Limit Address Lower lImit Address Lower Limit Address Lower Limit Address
> = > =
0000H 0000H 0000H 0000H
(RESET Condition)
Figure 27. Logical Memory Organization
UM005004-0918
Z8018x
59
FFFFH
MMU Common/Bank Area Register Common Area 1
1 1 0 1 D D000H
CFFFH
D7 D6 D5 D4
Bank Area
MMU Common/Bank Area Register

4000H
0 1 0 0 4 3FFFH
D3 D2 D1 D0 Common Area 0
0000H
Figure 28. Logical Space Configuration (Example)
UM005004-0918
Z8018x
60
MMU Register Description

MMU Common/Bank Area Register (CBAR)
CBAR specifies boundaries within the Z8X180 64KB logical address
space for up to three areas; Common Area 0, Bank Area and Common
Area 1.
MMU Common/Bank Area Register (CBAR: 3AH)

Bit 7 6 5 4 3 2 1 0
Bit/Field CA3 CA2 CA1 CA0 BA3 BA2 BA1 BA0
Reset 1 1 1 1 0 0 0 0
Bit
7– 4 CA7–4 R/W CA specifies the start (low) address (on 4KB boundaries)
for the Common Area 1. This also determines the last
address of the Bank Area.
3–0 BA3–0 R/W BA specifies the start (low) address (on 4KB boundaries)
for the Bank Area. This also determines the last address
of the Common Area 0.
UM005004-0918
Z8018x
61
MMU Common Base Register (CBR)

CBR specifies the base address (on 4K boundaries) used to generate a 20-
bit physical address for Common Area 1 accesses. All bits of CBR are
reset to 0 during RESET.
MMU Common Base Register (CBR: 38H)

Bit 7 6 5 4 3 2 1 0
Bit/Field CB7 CB6 CB5 CB4 CB3 CB2 CB1 CB0
Reset 0 0 0 0 0 0 0 0
Bit
7–0 CB7–0 R/W CBR specifies the base address (on 4KB boundaries) used
to generate a 20-bit physical address for Common Area 1
accesses.
UM005004-0918
Z8018x
62
MMU Bank Base Register (BBR)
BBR specifies the base address (on 4KB boundaries) used to generate a
20-bit physical address for Bank Area accesses. All bits of BBR are reset
to 0 during RESET.
MMU Bank Base Register (BBR: 39H)

Bit 7 6 5 4 3 2 1 0
Bit/Field BB7 BB6 BB5 BB4 BB3 BB2 BB1 BB0
Reset 0 0 0 0 0 0 0 0
Bit
7– 0 BB7–0 R/W BBR specifies the base address (on 4KB boundaries) used
to generate a 20-bit physical address for Bank Area
accesses.
Physical Address Translation
Figure 29 illustrates the way in which physical addresses are generated

based on the contents of CBAR, CBR and BBR. MMU comparators
classify an access by logical area as defined by CBAR. Depending on
which of the three potential logical areas (Common Area 1, Bank Area, or
Common Area 0) is being accessed, the appropriate 8- or 7-bit base
address is added to the high-order 4 bits of the logical address, yielding a
19- or 20-bit physical address. CBR is associated with Common Area 1
accesses. Common Area 0, if defined, is always based at physical address
00000H.
UM005004-0918
Z8018x
63
MMU and RESET

During RESET, all bits of the CA field of CBAR are set to 1 while all bits
of the BA field of CBAR, CBR and BBR are reset to 0. The logical 64KB
address space corresponds directly with the first 64KB 0000H to FFFFH)
of the 1024KB 00000H. to FFFFFH) physical address space. Thus, after
RESET, the Z8X180 begins execution at logical and physical address 0.
MMU Register Access Timing

When data is written into CBAR, CBR or BBR, the value is effective
from the cycle immediately following the I/O write cycle which updates
these registers.
During MMU programming insure that CPU program execution is not
disrupted. The next cycle following MMU register programming is
normally an Op Code fetch from the newly translated address. One
technique is to localize all MMU programming routines in a Common
Area that is always enabled.
UM005004-0918
Z8018x
64
MMU Common/ 4 12 11 0
Bank Area 15
Register
Logical
Address
D7 — D4 4
Comparator (64K)
MMU Common/ 4
Bank Area
Register
D3 — D0
MMU Common Base Reg.

MMU Bank Base Reg.
8 4
0 0 0 0 0 0 0 0
Adder
8
(19) 18 12 11 0
Physical
Address
(512 k or 1 M)
Figure 29. Physical Address Generation

15 12 11 0
Logical
Address
(64 k)
(7) 43 0
Base Register
(8 bit)
(1 M)
Physical (19) 18 16 15 12 11 0
Address
Figure 30. Physical Address Generation 2
UM005004-0918
Z8018x
65
Packages not containing an A19 pin or situations using TOUT

Note:
instead of A18 yield an address capable of only addressing 512K
of physical space.
Interrupts
The Z8X180 CPU has twelve interrupt sources, 4 external and 8 internal,
with fixed priority. (Reference Figure 31.)
This section explains the CPU registers associated with interrupt
processing, the TRAP interrupt, interrupt response modes, and the
external interrupts. The detailed discussion of internal interrupt
generation (except TRAP) is presented in the appropriate hardware
section (that is, PRT, DMAC, ASCI, and CSI/O).
Higher (1) TRAP (Undefined Op Code Trap) Internal Interrupt

Priority (2) NMI (Non Maskable Interrupt)
(3) INT0 (Maskable Interrupt Level 0) External Interrupt
(4) INT1 (Maskable Interrupt Level 1)
(5) INT2 (Maskable Interrupt Level 2)
(6) Timer 0
(7) Timer 1
(8) DMA channel 0
(9) DMA channel 1 Internal Interrupt
(10) Clocked Serial I/O Port
Lower (11) Asynchronous SCI channel 0
Priority (12) Asynchronous SCI channel 1
Figure 31. Interrupt Sources
Interrupt Control Registers and Flags. The Z8X180 has three registers and
two flags which are associated with interrupt processing.
UM005004-0918
Z8018x
66
Function Name Access Method
Interrupt Vector High I LD A,I and LD I, A instructions

Interrupt Vector Low IL I/O instruction (addr = 33H)
Interrupt/Trap Control ITC I/O instruction (addr = 34H)
Interrupt Enable Flag 1,2 IEF1, IEF2 El and DI
Interrupt Vector Register (I)

Mode 2 for INT0 external interrupt, INT1 and INT2 external interrupts,
and all internal interrupts (except TRAP) use a programmable vectored
technique to determine the address at which interrupt processing starts. In
response to the interrupt a 16-bit address is generated. This address
accesses a vector table in memory to obtain the address at which
execution restarts.
While the method for generation of the least significant byte of the table
address differs, all vectored interrupts use the contents of I as the most
significant byte of the table address. By programming the contents of I,
vector tables can be relocated on 256 byte boundaries throughout the
64KB logical address space.
Note: I is read/written with the LD A, I and LD I, A instructions rather

than I/O (IN, OUT) instructions. I is initialized to 00H during
RESET.
Interrupt Vector Low Register

This register determines the most significant three bits of the low-order
byte of the interrupt vector table address for external interrupts INT1 and
INT2 and all internal interrupts (except TRAP). The five least significant
bits are fixed for each specific interrupt source. By programming IL, the
UM005004-0918
Z8018x
67
vector table can be relocated on 32 byte boundaries. IL is initialized to

00H during RESET.
Interrupt Vector Low Register (IL: 33H)

Bit 7 6 5 4 3 2 1 0
Bit/Field IL7 IL6 IL5 ?
R/W R/W R/W R/W ?
Reset 00H 00H 00H ?
Bit
7–5 IL7–5 R/W The IL register is an internal I/O register which is

programmed with the OUT0 instruction and can be read
using the IN0 instruction.
4– 0 ? N/A Interrupt source dependent code
INT/TRAP Control Register (ITC)

ITC is used to handle TRAP interrupts and to enable or disable the
external maskable interrupt inputs INT0, INT1 and INT2.
UM005004-0918
Z8018x
68
INT/TRAP Control Register (ITC: 34H)

Bit 7 6 5 4 3 2 1 0
Bit/Field TRAP UFO ? ITE2 ITE1 ITE0
R/W R/W R N/A R/W R/W R/W
Reset 0 0 0 0 0 1
Bit
7 TRAP R/W This bit is set to 1 when an undefined Op Code is fetched.

TRAP can be reset under program control by writing it
with 0, however, it cannot be written with 1 under
program control.
6 UFO R Undefined Fetch Object (bit 6).
When a TRAP interrupt occurs the contents of UFO allow
determination of the starting address of the undefined
instruction. This action is necessary since the TRAP may
occur on either the second or third byte of the Op Code.
UFO allows the stacked PC value to be correctly adjusted.
If UFO = 0, the first Op Code should be interpreted as the
stacked PC-1. If UFO = 1, the first Op Code address is
stacked PC-2.
2– 0 ITE2–0 R/W Interrupt Enable — ITE2, ITE1 and ITE0 enable and
disable the external interrupt inputs INT2, INT1 and
INT0, respectively. If reset to 0, the interrupt is masked.
Interrupt Enable Flag 1,2 (IEF1, IEF2)

IEF1 controls the overall enabling and disabling of all internal and
external maskable interrupts (that is, all interrupts except NMI and TRAP.
UM005004-0918
Z8018x
69
If IEF1 is 0, all maskable interrupts are disabled. IEF1 can be reset to 0 by

the DI (Disable Interrupts) instruction and set to 1 by the El (Enable
Interrupts) instruction.
The purpose of IEF2 is to correctly manage the occurrence of NMI.
During NMI, the prior interrupt reception state is saved and all maskable
interrupts are automatically disabled (IEF1 copied to IEF2 and then IEF1
cleared to 0). At the end of the NMI interrupt service routine, execution of
the RETN (Return from Non-maskable Interrupt) automatically restores
the interrupt receiving state (by copying IEF2 to IEF1) prior to the
occurrence of NMI.
Table 8 describes how the IEF2 state can be reflected in the P/V bit of the
CPU Status Register by executing LD A, I or LD A, R instructions.
Table 8. State of IEF1 and IEF2
CPU
Operation IEF1 IEF2 REMARKS
RESET 0 0 Inhibits the interrupt except NMI

and TRAP.
NMI 0 IEF1 Copies the contents of IEF1 to
IEF2
RETN IEF2 not affected Returns from the NMI service
routine.
Interrupt except 0 0 Inhibits the interrupt except NMI
NMI end TRAP end TRAP
RETI not affected not affected
TRAP not affected not affected
EI 1 1
UM005004-0918
Z8018x
70
Table 8. State of IEF1 and IEF2 (Continued)
CPU
Operation IEF1 IEF2 REMARKS
DI 0 0
LD A, I not affected not affected Transfers the contents of IEF2 to
P/V
LID A, R not affected not affected Transfers the contents of IEF2 to
P/V
TRAP Interrupt
The Z8X180 generates a non-maskable (not affected by the state of IEF1)
TRAP interrupt when an undefined Op Code fetch occurs. This feature
can be used to increase software reliability, implement an extended
instruction set, or both. TRAP may occur during Op Code fetch cycles
and also if an undefined Op Code is fetched during the interrupt
acknowledge cycle for INT0 when Mode 0 is used.
When a TRAP interrupt occurs the Z8X180 operates as follows:
1. The TRAP bit in the Interrupt TRAP/Control (ITC) register is set to 1.
2. The current PC (Program Counter) value, reflecting location of the
undefined Op Code, is saved on the stack.
3. The Z8X180 vectors to logical address 0. Note that if logical address
0000H is mapped to physical address 00000H. the vector is the same
as for RESET. In this case, testing the TRAP bit in ITC reveals
whether the restart at physical address 00000H was caused by
RESET or TRAP.
The state of the UFO (Undefined Fetch Object) bit in ITC allows TRAP
manipulation software to correctly adjust the stacked PC, depending on
whether the second or third byte of the Op Code generated the TRAP. If
UFO is 0, the starting address of the invalid instruction is equal to the
UM005004-0918
Z8018x
71
stacked PC-1. If UFO is 1, the starting address of the invalid instruction is

equal to the stacked PC-2.
Bus Release cycle, Refresh cycle, DMA cycle, and WAIT cycle cannot be
inserted just after TTP state which is inserted for TRAP interrupt
sequence. Figure depicts TRAP Timing - 2nd Op Code undefined and
Figure illustrates Trap Timing - 3rd Op Code undefined.
Restart from 0000H
2nd Op Code Op Code

Fetch Cycle PC Stacking Fetch Cycle
T1 T2 T3 Ti Ti Ti Ti Ti T1 T2 T3 T1 T2 T3 T1 T2 T3
Phi
A0–A19 PC SP-1 SP-2 0000H
D0–D7 PCH PCL

Undefined
Op Code
MI
MREQ
RD
WR
Figure 32. TRAP Timing Diagram -2nd Op Code Undefined
UM005004-0918
Z8018x
72
Restart from 0000H

3rd Op Code Memory
Fetch Cycle Read Cycle PC stacking
Op Code
fetch cycle
T1 T2 T3 T1 T2 TTP T3 T1 Ti Ti Ti T1 T2 T3 T1 T2 T3 T1 T2 T3
Phi
A0–A19 PC IX+d, IY+d SP-1 SP-2 0000H
D0–D7 PCH PCL
Undefined
Op Code
MI
MREQ
RD
WR
Figure 33. TRAP Timing - 3rd Op Code Undefined
External Interrupts
The Z8X180 features four external hardware interrupt inputs:
• NMI–Non-maskable interrupt
• INT0–Maskable Interrupt Level 0
NMI, INT1, and INT2 feature fixed interrupt response modes. INT0 has 3
different software programmable interrupt response modes—Mode 0,
Mode 1 and Mode 2.
NMI - Non-Maskable Interrupt

The NMI interrupt input is edge-sensitive and cannot be masked by
software. When NMI is detected, the Z8X180 operates as follows:
UM005004-0918
Z8018x
73
1. DMAC operation is suspended by the clearing of the DME (DMA

Main Enable) bit in DCNTL.
2. The PC is pushed onto the stack.
3. The contents of IEF1 are copied to IEF2. This saves the interrupt
reception state that existed prior to NMI.
4. IEF1 is cleared to 0. This disables all external and internal maskable

interrupts (that is, all interrupts except NMI and TRAP).
5. Execution commences at logical address 0066H.
The last instruction of an NMI service routine must be RETN (Return

from Non-maskable Interrupt). This restores the stacked PC, allowing the
interrupted program to continue. Furthermore, RETN causes IEF2 to be
copied to IEF1, restoring the interrupt reception state that existed prior to
NMI.
Note: NMI, because it can be accepted during Z8X180 on-chip

DMAC operation, can be used to externally interrupt DMA
transfer. The NMI service routine can reactivate or abort the
DMAC operation as required by the application.
For NMI, take special care to insure that interrupt inputs do not overrun
the NMI service routine. Unlimited NMI inputs without a corresponding
number of RETN instructions eventually cause stack overflow.
Figure 34 depicts the use of NMI and RETN while Figure 35 details NMI
response timing. NMI is edge sensitive and the internally latched NMI
falling edge is held until it is sampled. If the falling edge of NMI is
latched before the falling edge of the clock state prior to T3 or T1 in the
last machine cycle, the internally latched NMI is sampled at the falling
edge of the clock state prior to T3 or T1 in the last machine cycle and
NMI acknowledge cycle begins at the end of the current machine cycle.
UM005004-0918
Z8018x
74
EF1 → EF2
0 → EF1
Main 0066H
PCH → (SP-1)
Program
PCL → (SP-2)
NMI
NMI Interrupt Service
Program
EF1 ← EF2
PCL ← (SP)
PCH ← (SP+1) RETN
Figure 34. NMI Use
Last MC NMI acknowledge cycle
PC is pushed onto stack Restart from 0066H
Op Code fetch
T1 T1 T3 Ti T1 T1 T2 T3 T1 T2 T3 T1 T2 T3
Phi
NMI
A0–A19 PC SP-1 SP-2 0066H
Instruction
D0–D7 PCH PCL
MI
MREQ
RD
WR
UM005004-0918
Z8018x
75
Figure 35. NMI Timing
INT0 - Maskable Interrupt Level 0

The next highest priority external interrupt after NMI is INT0. INT0 is
sampled at the falling edge of the clock state prior to T3 or T1 in the last
machine cycle. If INT0 is asserted LOW at the falling edge of the clock
state prior to T3 or T1 in the last machine cycle, INT0 is accepted. The
interrupt is masked if either the IEF1 flag or the ITEO (Interrupt Enable
0) bit in ITC are reset to 0. After RESET the state is as follows:
1. IEF1 is 0, so INT0 is masked
2. ITE0 is 1, so INT0 is enabled by execution of the El (Enable
Interrupts) instruction
The INT0 interrupt is unique in that 3 programmable interrupt response
modes are available - Mode 0, Mode 1 and Mode 2. The specific mode is
selected with the IM 0, IM 1 and IM 2 (Set Interrupt Mode) instructions.
During RESET, the Z8X180 is initialized to use Mode 0 for INT0. The 3
interrupt response modes for INT0 are:
• Mode 0–Instruction fetch from data bus
• Mode 1–Restart at logical address 0038H
• Mode 2–Low-byte vector table address fetch from data bus
INT0 Mode 0
During the interrupt acknowledge cycle, an instruction is fetched from the
data bus (DO–D7) at the rising edge of T3. Often, this instruction is one
of the eight single byte RST (RESTART) instructions which stack the PC
and restart execution at a fixed logical address. However, multibyte
instructions can be processed if the interrupt acknowledging device can
provide a multibyte response. Unlike all other interrupts, the PC is not
automatically stacked:
UM005004-0918
Z8018x
76
Last MC INT0 acknowledge cycle RST instruction execution
PC is pushed onto stack
T1 T2 TW* TW* T3 Ti Ti T1 T2 T3 T1 T2 T3
Phi
INT0
A0–A19 PC SP-1 SP-2
M1
MREQ
RD
WR
IORQ
RST instruction
D0–D7 PCH PCL
MC: Machine Cycle
*Two Wait States are automatically inserted
Note: The TRAP interrupt occurs if an invalid instruction is fetched

during Mode 0 interrupt acknowledge. (Reference Figure 36.)
Figure 36. INT0 Mode 0 Timing Diagram
INT0 Mode 1
When INT0 is received, the PC is stacked and instruction execution
restarts at logical address 0038H. Both IEF1 and IEF2 flags are reset to 0,
UM005004-0918
Z8018x
77
disabling all maskable interrupts. The interrupt service routine normally

terminates with the EI (Enable Interrupts) instruction followed by the
RETI (Return from Interrupt) instruction, to reenable the interrupts.
Figure 37 depicts the use of INT0 (Mode 1) and RETI for the Mode 1
interrupt sequence.
Figure 37. INT0 Mode 1 Interrupt Sequence
0 → EF1, EF2 0038H

Main PCH → (SP-1)
Program
PCL → (SP-2)
INT0 (Mode 1)
INT0 Interrupt Service
(Mode 1) Program
PCL ← (SP)
PCH ← (SP+1) E1 (1 → 1EF1, 1EF2)
RETI
Figure 38 illustrates INT0 Mode 1 Timing.
UM005004-0918
Z8018x
78
Last MC INT0 Acknowledge Cycle Op Code Fetch Cycle
PC is pushed onto stack
T1 T2 TW* TW* T3 T1 T2 T3 T1 T2 T3 T1 T2 T3
Phi
INT0
A0–A19 PC SP-1 SP-2 0038H
M1
MREQ
IORQ
RD
WR
D0–D7 PCH PCL
ST
Figure 38. INT0 Mode 1 Timing
INT0 Mode 2
This method determines the restart address by reading the contents of a
table residing in memory. The vector table consists of up to 128 two-byte
restart addresses stored in low byte, high byte order.
UM005004-0918
Z8018x
79
The vector table address is located on 256 byte boundaries in the 64KB
logical address space programmed in the 8-bit Interrupt Vector Register
(1). Figure 39 depicts the INT0 Mode 2 Vector acquisition.
Memory
16-bit Vector
Interrupt Vector 8-bit on

Register I Data Bus
Vector + 1 High-order 8 bits

of starting address 256 Bytes
Vector
Low-order 8 bits Table
Vector
of starting address
Offset
Figure 39. INT0 Mode 2 Vector Acquisition
During the INT0 Mode 2 acknowledge cycle, the low-order 8 bits of the
vector is fetched from the data bus at the rising edge of T3 and the CPU
acquires the 16-bit vector.
Next, the PC is stacked. Finally, the 16-bit restart address is fetched from
the vector table and execution begins at that address.
Note: External vector acquisition is indicated by both MI and IORQ

LOW. Two Wait States (TW) are automatically inserted for
external vector fetch cycles.
During RESET the Interrupt Vector Register (I) is initialized to 00H and,
if necessary, should be set to a different value prior to the occurrence of a
Mode 2 INT0 interrupt. Figure illustrates INT0 interrupt Mode 2 Timing.
UM005004-0918
Z8018x
80
Op Code
Last MC INT0 Acknowledge Cycle Fetch Cycle
Interrupt
Vector Lower Manipulation
Address Read PC is pushed onto stack Cycle
T1 T2 TW* TW* T3 Ti T1 T2 T3 T1 T2 T3 T1 T2 T3 T1 T2 T1 T2 T3
Phi
INT0
Starting address
A0–A19 PC SP-1 SP-2 Vector Vector+1
M1
MREQ
IORQ
RD
WR
Starting Address Starting Address
(Lower Address) (Upper Address)
Lower Vector
D0–D7 PCH PCL
ST
Figure 40. INT0 Interrupt Mode 2 Timing Diagram
INT1, INT2
The operation of external interrupts INT1 and INT2 is a vector mode
similar to INT0 Mode 2. The difference is that INT1 and INT2 generate
the low-order byte of vector table address using the IL (Interrupt Vector
Low) register rather than fetching it from the data bus. This difference is
UM005004-0918
Z8018x
81
also the interrupt response sequence used for all internal interrupts
(except TRAP).
As depicted in Figure 41, the low-order byte of the vector table address
has the most significant three bits of the software programmable IL
register while the least significant five bits are a unique fixed value for
each interrupt (INT1, INT2 and internal) source:
Memory
16-bit Vector
Fixed Code
I IL
(5 bits)
Vector + 1 High-order 8 bits 32 Bytes

of starting address
Vector
Low-order 8 bits Table
Vector
of starting address
Figure 41. INT1, INT2 Vector Acquisition
INT1 and INT2 are globally masked by IEF1 is 0. Each is also

individually maskable by respectively clearing the ITE1 and ITE2 (bits
1,2) of the INT/TRAP control register to 0.
During RESET, IEF1, ITE1 and ITE2 bits are reset to 0.
Internal Interrupts
Internal interrupts (except TRAP) use the same vectored response mode
as INT1 and INT2. Internal interrupts are globally masked by IEF1 is 0.
Individual internal interrupts are enabled/disabled by programming each
UM005004-0918
Z8018x
82
individual I/O (PRT, DMAC, CSI/O, ASCI) control register. The lower
vector of INT1 INT2 and internal interrupt are summarized in Table 9.
Table 9. Vector Table
IL Fixed Code
Interrupt Source Priority b7 b6 b5 b4 b3 b2 b1 b0
INT1 — — — 0 0 0 0 0
Highest
INT2 — — — 0 0 0 1 0
PRT channel 0 — — — 0 0 1 0 0
PRT channel 1 — — — 0 0 1 1 0
DMA channel 0 — — — 0 1 0 0 0
DMA channel 1 — — — 0 1 0 1 0
CSI/O — — — 0 1 1 0 0
ASCI channel 0 Lowest — — — 0 1 1 1 0
ASCI channel 1 — — — 1 0 0 0 0
Interrupt Acknowledge Cycle Timings

Figure 43 illustrates INT1, INT2, and internal interrupts timing. INT1 and
INT2 are sampled at the falling edge of the clock state prior to T2 or T1 in
the last machine cycle. If INT1 or INT2 is asserted Low at the falling
edge of clock state prior to T3 or T1 in the last machine cycle, the
interrupt request is accepted.
UM005004-0918
Z8018x
83
Interrupt Sources During RESET
All bits are reset to 0. Because I = 0 locates the vector tables starting at
logical address 0000H vectored interrupts (INT0 Mode 2, INT1, INT2,
and internal interrupts) overlap with fixed restart interrupts like RESET
(0), NMI (0066H), INT0 Mode 1 (0038H) and RST (0000H-0038H). The
vector table(s) are built elsewhere in memory and located on 256 byte
boundaries by reprogramming I with the LD I, A instruction.
IL Register
Bits 7 - 5 are reset to 0
The IL Register can be programmed to locate the vector table for INT1,
INT2 and internal interrupts on 32-byte subboundaries within the 256
byte area specified by I.
IEF1, IEF2 Flags
Reset to 0. Interrupts other than NMI and TRAP are disabled.
ITC Register
ITE0 set to 1. ITE1, ITE2 reset to 0. INT0 can be enabled by the EI

instruction, which sets IEF1 to 1. Enabling INT1 and INT2 also requires
that the ITE1 and ITE2 bits be respectively set to 1 by writing to ITC.
I/O Control Registers
Interrupt enable bits reset to 0. All Z8X180 on-chip I/O (PRT, DMAC,
CSI/O, ASCI) interrupts are disabled and can be individually enabled by
writing to each I/O control register interrupt enable bit.
UM005004-0918
Z8018x
84
Return from Subroutine (RETI) Instruction Sequence

When the EDH/4DH sequence is fetched by the Z8X180, it is recognized as
the RETI instruction sequence. The Z8X180 then refetches the RETI
instruction with four T-states in the EDH cycle allowing the Z80
peripherals time to decode that cycle (See Figure 42). This procedure
allows the internal interrupt structure of the peripheral to properly decode
the instruction and behave accordingly.
The M1E bit of the Operation Mode Control Register (OMCR) must be
set to 0 so that M1 signal is active only during the refetch of the RETI
instruction sequence. This condition is the desired operation when Z80
peripherals are connected to the Z8018X.
T1 T2 T3 T1 T2 T3 Ti Ti Ti T1 T2 T3 Ti T1 T2 T3 T1
Phi
A0–A18 (A19) PC PC + 1 PC PC + 1
EDH 4DH EDH 4DH
D0–D7
M1 (M1E = 1)
M1 (M1E = 0)
MREQ
RD
ST
Note: RETI machine cycles 9 and 10 not shown.
Figure 42. RETI Instruction Sequence
The RETI instruction takes 22 T-states and 10 machine cycles. Table 10

lists the conditions of all the control signals during this sequence for the
UM005004-0918
Z8018x
85
Z8X180. Figure 43 illustrates the INT1, INT2 and internal interrupts

timing.
Table 10. RETI Control Signal States
MI
Machine
Cycle States Address Data RD WR MREQ IORQ M1E=1 M1E=0 HALT ST
1 T1-T3 1st EDH 0 1 0 1 0 1 1 0

Op Code
2 TI-T3 2nd 4DH 0 1 0 1 0 1 1 1
Op Code
3 T1 Don't 3-state 1 1 1 1 1 1 1 1
Care
4 T1 Don't 3-state 1 1 1 1 1 1 1 1
Care
5 T1 Don't 3-state 1 1 1 1 1 1 1 1
Care
6 T1-T3 1st EDH 0 1 0 1 0 0 1 1
Op Code
7 T1 Don't 3-state 1 1 1 1 1 1 1 1
Care
8 T1-T3 2nd 4DH 0 1 0 1 0 1 1 1
Op Code
9 T1-T3 SP data 0 1 0 1 1 1 1 1
10 T1-T3 SP+1 data 0 1 0 1 1 1 1 1
IOC affects the IORQ/RD signals. M1E affects the assertion of M1. One state also reflects a 1 while
the other reflects a 0
UM005004-0918
Z8018x
86
Op Code
INT1, INT2, internal interrupt acknowledge cycle fetch cycle
Last MC
PC Stacking Vector Table Read
T1 T2 TW* TW* T3 Ti T1 T2 T3 T1 T2 T3 T1 T2 T3 T1 T2 T3 T1 T2 T3
Phi
INT1,2 Starting
Address
A0–A19 PC SP-1 SP-2 Vector Vector+1
M1
MREQ
IORQ
RD
WR Starting Starting
address (L) address (H)
D0–D7 PCH PCL
ST
MC: Machine Cycle * Two Wait States are automatically inserted.
Figure 43. INT1, INT2 and Internal Interrupts Timing Diagram
Dynamic RAM Refresh Control
The Z8X180 incorporates a dynamic RAM refresh control circuit

including 8-bit refresh address generation and programmable refresh
timing. This circuit generates asynchronous refresh cycles inserted at the
programmable interval independent of CPU program execution. For
systems which do not use dynamic RAM, the refresh function can be
disabled.
When the internal refresh controller determines that a refresh cycle should
occur, the current instruction is interrupted at the first breakpoint between
machine cycles. The refresh cycle is inserted by placing the refresh
address on A0–A7 and the RFSH output is driven Low.
UM005004-0918
Z8018x
87
Refresh cycles may be programmed to be either two or three clock cycles

in duration by programming the REFW (Refresh Wait) bit in the Refresh
Control Register (RCR). The external WAIT input and the internal Wait
State generator are not effective during refresh.
Figure 44 depicts the timing of a refresh cycle with a refresh wait (TRW)
cycle.
MCi Refresh cycle MCi+1
TR1 TRW* TR2
Refresh signal
(Internal signal)
Refresh address A0 — A7
MREQ
RFSH
NOTE: * If three refresh cycles are specified, TRW is inserted.

Otherwise, TRW is not inserted
MC: Machine Cycle
Figure 44. Refresh Cycle Timing Diagram
UM005004-0918
Z8018x
88
Refresh Control Register (RCR)

The RCR specifies the interval and length of refresh cycles, while
enabling or disabling the refresh function.
Refresh Control Register (RCR: 36H)

Bit 7 6 5 4 3 2 1 0
Bit/Field REFE REFW ? CYC1 CYC0
R/W R/W R/W ? R/W R/W
Reset 1 1 ? 0 0
Bit
7 REFE R/W REFE: Refresh Enable

0 Disables the refresh controller
1 Enables refresh cycle insertion.
6 REFW R/W Refresh Wait (bit 6)
0 Causes the refresh cycle to be two clocks in duration.
1 Causes the refresh cycle to be three clocks in duration by
adding a refresh wait cycle (TRW).
1– 0 CYC1–0 R/W Cycle Interval — CYC1 and CYC0 specify the interval
(in clock cycles) between refresh cycles. In the case of
dynamic RAMs requiring 128 refresh cycles every 2 ms
(or 256 cycles in every 4 ms), the required refresh interval
is less than or equal to 15.625 μs. Thus, the underlined
values indicate the best refresh interval depending on
CPU clock frequency. CYC0 and CYC1 are cleared to 0
during RESET. Refer to Table 11.
UM005004-0918
Z8018x
89
Table 11. DRAM Refresh Intervals
Time Interval
Insertion
CYC1 CYC0 Interval 10 MHz 8 MHz 6 MHz 4 MHz 2.5 MHz
0 0 10 states (1.0 μs)* (1.25 μs)* 1.66 μs 2.5 μs 4.0 μs

* Calculated interval
Refresh Control And RESET
After RESET, based on the initialized value of RCR, refresh cycles occur
with an interval of ten clock cycles and are three clock cycles in duration.
Dynamic Ram Refresh Operation Notes
1. Refresh Cycle insertion is stopped when the CPU is in the following

states:
– During RESET
– When the bus is released in response to BUSREQ
– During SLEEP mode
– During Wait States
2. Refresh cycles are suppressed when the bus is released in response to

BUSREQ. However, the refresh timer continues to operate. Thus, the
time at which the first refresh cycle occurs after the Z8X180 re-
acquires the bus depends on the refresh timer and has no timing
relationship with the bus exchange.
UM005004-0918
Z8018x
90
3. Refresh cycles are suppressed during SLEEP mode. If a refresh cycle

is requested during SLEEP mode, the refresh cycle request is
internally latched (until replaced with the next refresh request). The
latched refresh cycle is inserted at the end of the first machine cycle
after SLEEP mode is exited. After this initial cycle, the time at which
the next refresh cycle occurs depends on the refresh time and has no
timing relationship with the exit from SLEEP mode.
4. Regarding (2) and (3), the refresh address is incremented by one for
each successful refresh cycle, not for each refresh request. Thus,
independent of the number of missed refresh requests, each refresh
bus cycle uses a refresh address incremented by one from that of the
previous refresh bus cycles.
DMA Controller (DMAC)

The Z8X180 contains a two-channel DMA (Direct Memory Access)
controller which supports high speed data transfer. Both channels
(channel 0 and channel 1) feature the following capabilities:
• Memory Address Space
Memory source and destination addresses can be directly specified
anywhere within the 1024KB physical address space using 20-bit
source and destination memory addresses. In addition, memory
transfers can arbitrarily cross 64KB physical address boundaries
without CPU intervention.
• I/O Address Space
I/O source and destination addresses can be directly specified
anywhere within the 64KB I/O address space (16-bit source and
destination I/O addresses).
• Transfer Length
Up to 64KB are transferred based on a 16- bit byte count register.
UM005004-0918
Z8018x
91
• DREQ Input
Level- and edge-sense DREQ input detection are selectable.
TEND Output Used to indicate DMA completion to external devices.
• Transfer Rate
Each byte transfer occurs every 6 clock cycles. Wait States can be
inserted in DMA cycles for slow memory or I/O devices. At the
system clock (φ) = 6 MHz, the DMA transfer rate is as high as 1.0
megabytes/second (no Wait States).
There is an additional feature disc for DMA interrupt request by DMA
END. Each channel has the following additional specific capabilities:
Channel 0
• Memory to memory
• Memory to I/O
• Memory to memory mapped I/O transfers.
• Memory address increment, decrement, no-change
• Burst or cycle steal memory to/from memory transfers
• DMA to/from both ASCI channels
• Higher priority than DMAC channel 1
Channel 1
• Memory to/from I/O transfer
• Memory address increment, decrement
DMAC Registers
Each channel of the DMAC (channel 0, 1) contains three registers
specifically associated with that channel.
UM005004-0918
Z8018x
92
Channel 0
• SAR0–Source Address Register
• DAR0–Destination Address Register
• BCR0–Byte Count Register
Channel 1
• MAR1–Memory Address Register
• IAR1–I/O Address Register
• BCR1–Byte Count Register
The two channels share the following three additional registers in common:
• DSTAT–DMA Status Register
• DMODE–DMA Mode Register
• DCNTL–DMA Control Register
DMAC Block Diagram

Figure 45 depicts the Z8X180 DMAC Block Diagram.
UM005004-0918
Z8018x
93
DMA Source Address DMA Status

Register ch0 : SAR0 (20) Register : DSTAT (8) DREQ0
Priority &
DMA Destination Address Request
DMA Mode
Register ch0 : DAR0 (20) Control
Register : DMODE (8) DREQ1
DMA Byte Count DMA/WAIT Control
Register ch0 : BCR0 (16) Register : DCNTL (8)
DMA Destination Address

Register ch1 : MAR1 (20)
DMA I/O Address

Register ch1 : IAR1 (16)
Bus & CPU
DMA Byte Count DMA Control
Control
Register ch1 : BCR1 (16)
TEND0
TEND1
Incrementer/Decrementer (16) Interrupt Request
Figure 45. DMAC Block Diagram
DMAC Register Description

DMA Source Address Register Channel 0 (SAR0 I/O Address = 20H
to 22H)
Specifies the physical source address for channel 0 transfers. The register
contains 20 bits and can specify up to 1024KB memory addresses or up to
64KB I/O addresses. Channel 0 source can be memory, I/O, or memory
mapped I/O.
UM005004-0918
Z8018x
94
DMA Destination Address Register Channel 0 (DAR0 I/O Address =

23H to 25H)
Specifies the physical destination address for channel 0 transfers. The
register contains 20 bits and can specify up to 1024KB memory addresses
or up to 64KB I/O addresses. Channel 0 destination can be memory, I/O,
or memory mapped I/O.
DMA Byte Count Register Channel 0 (BCR0 I/O Address = 26H to

27H)
Specifies the number of bytes to be transferred. This register contains 16
bits and may specify up to 64KB transfers. When one byte is transferred,
the register is decremented by one. If n bytes are transferred, n is stored
before the DMA operation.
DMA Memory Address Register Channel 1 (MAR1: I/O Address =

28H to 2AH)
Specifies the physical memory address for channel 1 transfers. This
address may be a destination or source memory address. The register
contains 20 bits and may specify up to 1024KB memory address.
DMA I/O Address Register Channel 1 (IAR1: I/O Address = 2BH to

2CH)
Specifies the I/O address for channel 1 transfers. This address may be a
destination or source I/O address. The register contains 16 bits and may
specify up to 64KB I/O addresses.
DMA Byte Count Register Channel 1 (BCR1: I/O Address = 2EH to

2FH)
Specifies the number of bytes to be transferred. This register contains 16
bits and may specify up to 64KB transfers. When one byte is transferred,
the register is decremented by one.
UM005004-0918
Z8018x
95
DMA Status Register (DSTAT)

DSTAT is used to enable and disable DMA transfer and DMA termination
interrupts. DSTAT also determines DMA transfer status, that is, completed
or in progress.
DMA Status Register (DSTAT: 30H)

Bit 7 6 5 4 3 2 1 0
Bit/Field DE1 DE0 DWE1 DWE0 DIE1 DIE0 ? DME
R/W R/W R/W W W R/W R/W ? R
Reset 0 0 1 1 0 0 ?
Bit
7 DE1 R/W Enable Channel 1 — When DE1 = 1 and DME = 1,

channel 1 DMA is enabled. When a DMA transfer
terminates (BCR1 = 0), DE1 is reset to 0 by the DMAC.
When DE1 = 0 and the DMA interrupt is enabled (DIE1 =
1), a DMA interrupt request is made to the CPU.
To perform a software write to DE1, DWE1 is written with
0 during the same register write access. Writing DE1 to 0
disables channel 1 DMA, but DMA is restartable. Writing
DE1 to 1 enables channel 1 DMA and automatically sets
DME (DMA Main Enable) to 1. DE1 is cleared to 0 during
RESET.
UM005004-0918
Z8018x
96
Bit
6 DE0 R/W Enable Channel 0 — When DE0 = 1 and DME = 1,

channel 0 DMA is enabled. When a DMA transfer
terminates BCR0 = 0), DE0: is reset to 0 by the DMAC.
When DE0 = 0 and the DMA interrupt is enabled (DIE0 =
1), a DMA interrupt request is made to the CPU.
To perform a software write to DE0, DWE0 must be written
with 0 during the same register write access. Writing DE0 to
0 disables channel 0 DMA. Writing DE0 to 1 enables
channel 0 DMA and automatically sets DME (DMA Main
Enable) to 1. DE0 is cleared to 0 during RESET.
5 DWE1 W Bit Write Enable 1 — When performing any software
write to DEI, DWE1 must be written with 0 during the
same access. DWE1 write value of 0 is not held and
DWE1 is always read as 1.
4 DWE0 W Bit Write Enable 0 — When performing any software
write to DE0, DWE0 must be written with 0 during the
same access. DWE0 write value of 0 is not held and
DWE0 is always read as 1.
3 DIE1 R/W DMA Interrupt Enable Channel 1 — When DIE1 is set
to 1, the termination channel 1 DMA transfer (indicated
when DE1 is 0) causes a CPU interrupt request to be
generated. When DIE1 is 0, the channel 1 DMA
termination interrupt is disabled. DIE1 is cleared to 0
during RESET.
2 DIE0 DMA Interrupt Enable Channel 0 — When DIE0 is set
to 1, the termination channel 0 of DMA transfer
(indicated when DE0 is 0) causes a CPU interrupt request
to be generated. When DIE0 is 0, the channel 0 DMA
termination interrupt is disabled. DIE0 is cleared to 0
during RESET.
UM005004-0918
Z8018x
97
Bit
0 DME R DMA Main Enable — A DMA operation is only enabled

when its DE bit DE0 for channel 0, DE1 for channel 1)
and the DME bit are set to 1.
When NMI occurs, DME is reset to 0, thus disabling
DMA activity during the NMI interrupt service
routine. To restart DMA, DE0 and/or DE1 must be
written with 1 (even if the contents are already 1).
This action automatically sets DME to 1, allowing
DMA operations to continue. DME cannot be
directly written. It is cleared to 0 by NMI or
indirectly set to 1 by setting DE0 and/or DE1 to
1.DME is cleared to 0 during RESET.
DMA Mode Register (DMODE)
DMODE is used to set the addressing and transfer mode for channel 0.
DMA Mode Register (DMODE: 31H)
Bit 7 6 5 4 3 2 1 0
Bit/Field ? DM1 DM0 SM1 SM0 MMOD ?
R/W ? R/W R/W R/W R/W R/W ?
Reset ? 0 0 0 0 0 ?
Bit
5–4 DM1:0 R/W Destination Mode Channel 0 — Specifies whether the

destination for channel 0 transfers is memory, I/O or
memory mapped I/O and the corresponding address
modifier. Reference Table 12.
UM005004-0918
Z8018x
98
Bit
3– 2 SM1:0 W Source Mode Channel — Specifies whether the source

for channel 0 transfers is memory, I/O, or memory
mapped I/O and the corresponding address modifier.
Reference Table 13.
1 MMOD R/W DMA Memory Mode Channel 0 — When channel 0 is
configured for memory to/from memory transfers, the
external DREQ0 input is not used to control the transfer
timing. Instead, two automatic transfer timing modes are
selectable - BURST (MMOD is 1) and CYCLE STEAL
(MMOD is 0). For BURST memory to/from memory
transfers, the DMAC takes control of the bus
continuously until the DMA transfer completes (as shown
by the byte count register is 0). In CYCLE STEAL mode,
the CPU is given a cycle for each DMA byte transfer
cycle until the transfer is completed.
For channel 0 DMA with I/O source or destination, the
DREQ0 input times the transfer and thus MMOD is
ignored.
Table 12. Channel 0 Destination
DM1 DM0 Memory/I/O Address Increment/Decrement
0 0 Memory +1
0 1 Memory -1
1 0 Memory fixed
1 1 I/O fixed
UM005004-0918
Z8018x
99
Table 13. Channel 0 Source
SM1 SM0 Memory/I/O Address lncrement/Decrement
0 0 Memory +1
0 1 Memory -1
1 0 Memory fixed
1 1 I/O fixed
Table 14 describes all DMA TRANSFER mode combinations of DM0

DM1, SM0 SM1. Because I/O to/from I/O transfers are not implemented,
12 combinations are available.
Table 14. Transfer Mode Combinations
DM1 DM0 SM1 SM0 Transfer Mode Increment/Decrement
0 0 0 0 Memory to Memory SAR0+1, DAR0+1

0 0 0 1 Memory to Memory SAR0-1, DAR0+1
0 0 1 0 Memory* to Memory SAR0 fixed, DAR0+ 1
0 0 1 1 I/O to Memory SAR0 fixed DAR0+1
0 1 0 0 Memory to Memory SAR0+1, DAR0-1
0 1 0 1 Memory to Memory SAR0-1,DAR0-1
0 1 1 0 Memory to Memory SAR0 fixed, DAR0-1
0 1 1 1 I/O to Memory SAR0 fixed. DAR0-1
1 0 0 0 Memory to Memory* SAR0+ 1, DAR0 fixed
1 0 0 1 Memory to Memory* SAR0-1, DAR0 fixed
1 0 1 0 Reserved
1 0 1 1 Reserved
UM005004-0918
Z8018x
100
Table 14. Transfer Mode Combinations
DM1 DM0 SM1 SM0 Transfer Mode Increment/Decrement
1 1 0 0 Memory to I/O SAR0+1, DAR0 fixed

1 1 0 1 Memory to I/O SAR0-1, DAR0 fixed
1 1 1 0 Reserved
1 1 1 1 Reserved
Note: *: includes memory mapped I/O.
DMA/WAIT Control Register (DCNTL)

DCNTL controls the insertion of Wait States into DMAC (and CPU)
accesses of memory or I/O Also, the DMA request mode for each DREQ
DREQ0 and DREQ1) input is defined as level or edge sense. DCNTL
also sets the DMA transfer mode for channel 1, which is limited to
memory to/from I/O transfers.
UM005004-0918
Z8018x
101
DMA/WAIT Control Register (DCNTL: 32H)

Bit 7 6 5 4 3 2 1 0
Bit/Field MWI1 MWI0 IWI1 IWI0 DMS1 DMS0 DIM1 DIM0
Reset 0 0 0 0 0 0 0 0
Bit
7–6 MWI1–0 R/W Memory Wait Insertion —Specifies the number of wait
states introduced into CPU or DMAC memory access
cycles. MWI1 and MWI0 are set to 1 during RESET. See
section on Wait State Generator for details.
5– 4 IWI1–0 R/W Wait Insertion — Specifies the number of Wait States
introduced into CPU or DMAC I/O access cycles. IWI1
and IWI0 are set to 1 during RESET. See section on Wait
State Generator for details.
3– 2 DMS1–0 R/W DMA Request Sense — Specifies the DMA request
sense for channel 0 (DREQ0) and channel 1 (DREQ1)
respectively. When reset to 0, the input is level-sense.
When set to 1, the input is edge-sense.
1– 0 DIM1–0 R/W DMA Channel 1 I/O and Memory Mode — Specifies
the source/destination and address modifier for channel 1
memory to/from I/O transfer modes. Reference Table 15.
UM005004-0918
Z8018x
102
Table 15. Channel 1 Transfer Mode
DIM1 DIM0 Transfer Mode Address Increment/Decrement
0 0 Memory to I/O MARI +1, IAR1 fixed

0 1 Memory to I/O MARI -1, IAR1 fixed
1 0 I/O to Memory IAR1 fixed, MAR1+1
1 1 I/O to Memory IAR1 fixed, MAR1-1
DMA I/O Address Register Ch. 1 (IAR1B: 2DH) (Z8S180/L180-Class Processor Only)
Bit 7 6 5 4 3 2 1 0
Bit/Field Reserved
R/W R/W R/W R/W R/W R/W
Reset 0 0 0 0 0
Bit
7 R/W Alternating Channels

0 DMA Channels are independent
1 Toggle between DMA channels for same device
6 R/W Currently selected DMA channel when Bit 7 = 1
5– 4 Reserved R/W 0 Reserved. Must be 0.
3 R/W 0 TOUT/DREQ is DREQ In
1 TOUT/DREQ is TOUT Out
UM005004-0918
Z8018x
103
Bit
2-0 R/W 000 DMA1 ext TOUT/DREQ

001 DMA1 ASCI0
010 DMA1 ASCI1
011 DMA1 ESCC
111 DMA1 PIA27-20 (P1284)
DMA Register Description
Bit 7
This bit must be set to 1 only when both DMA channels are set to take
their requests from the same device. If this bit is 1 (it resets to 0), the
TEND output of DMA channel o sets a flip-flop, so that thereafter the
device’s request is visible to channel 1, but not visible to channel 0. The
internal TEND signal of channel 1 clears the FF, so that thereafter, the
device’s request is visible to channel 0, but no visible to channel 1.
If DMA request are from differing sources, DMA channel 0 request is

forced onto DMA channel 1 after TEND output of DMA channel 0 sets
the flop-flop to alternate.
Bit 6
When both DMA channels are programmed to take their requests from
the same device, this bit (FF mentioned in the previous paragraph)
controls which channel the device’s request is presented to: 0 = DMA0, 1
= DMA l. When Bit 7 is 1, this bit is automatically toggled by the channel
end output of the channels.
UM005004-0918
Z8018x
104
Bits 5–3
Reserved. Must be 0.
Bits 2–0
With DIM1, bit 1 of DCNTL, these bits control which request is presented
to DMA channel 1, as described below:
DIM1 IAR18–16 Request Routed to DMA Channel 1
0 000 DREQ1
0 001 ASCI0 Tx
0 010 ASCI1 Tx
0 011 ext CKA0/DREQ0
0 10X Reserved
0 1X0 Reserved
0 111 Reserved
1 000 ext DREQ1
1 001 ASCI0 Rx
1 010 ASCI1 Rx
1 011 ext CKA0/DREQ0
1 10X Reserved
1 1X0 Reserved
1 111 Reserved
DMA Operation
This section discusses the three DMA operation modes for channel 0:
• Memory to/from memory
• Memory to/from I/O
• Memory to/from memory mapped I/O
UM005004-0918
Z8018x
105
In addition, the operation of channel 0 DMA with the on-chip ASCI

(Asynchronous Serial Communication Interface) as well as Channel 1
DMA are described.
Memory to Memory—Channel 0
For memory to/from memory transfers, the external DREQ0 input is not
used for DMA transfer timing. Rather, the DMA operation is timed in one
of two programmable modes – BURST or CYCLE STEAL. In both
modes, the DMA operation automatically proceeds until termination
(shown by byte count-BCR0) = 0.
In BURST mode, the DMA operation proceeds until termination. In this
case, the CPU cannot perform any program execution until the DMA
operation is completed. In CYCLE STEAL mode, the DMA and CPU
operation are alternated after each DMA byte transfer until the DMA is
completed. The sequence:
• 1 CPU Machine Cycle
• DMA Byte Transfer
is repeated until DMA is completed. Figure 46 describes CYCLE STEAL
mode DMA timing.
UM005004-0918
Z8018x
106
DMA cycle CPU cycle DMA cycle (transfer 1 byte) CPU cycle DMA cycle
T1 T2 T3 T1 T2 T3 T1 T2 T3 T1 T2 T3 T1 T2
Phi
LD g,m Source Destination LD g,m
Op Code memory memory operand
address address address address
Address
MREQ
RD
WR
m Read data Write data, m
Data
Figure 46. DMA Timing Diagram-CYCLE STEAL Mode
To initiate memory to/from memory DMA transfer for channel 0, perform

the following operations.
1. Load the memory source and destination address into SAR0 and DAR0
2. Specify memory to/from memory mode and address increment/
decrement in the SM0 SM1, DM0 and DM1 bits of DMODE.
3. Load the number of bytes to transfer in BCR0.
4. Specify burst or cycle steal mode in the MMOD bit of DCNTL.
5. Program DE0 = 1 (with DWE0 = 0 in the same access) in DSTAT and
the DMA operation starts one machine cycle later. If interrupt occurs
at the same time, the DIE0 bit must be set to 1.
UM005004-0918
Z8018x
107
Memory to I/O (Memory Mapped I/O) — Channel 0
For memory to/from I/O (and memory to/from memory mapped I/O) the
DREQ0 input is used to time the DMA transfers. In addition, the TEND0
(Transfer End) output is used to indicate the last (byte count register
BCR0 = 00H) transfer.
The DREQ0 input can be programmed as level- or edge-sensitive.
When level-sense is programmed, the DMA operation begins when

DREQ0 is sampled Low. If DREQ0 is sampled High, after the next DMA
byte transfer, control is relinquished to the Z8X180 CPU. As illustrated in
Figure 47, DREQ0 is sampled at the rising edge of the clock cycle prior to
T3, (that is, either T2 or Tw).
DMA CPU DMA DMA

Write Machine Read Write
Cycle Cycle Cycle Cycle (I/O)
Tw Tw T3 T1 T2 T3 T1 T2 T3 T1 T2 Tw Tw T3 T1 T2
Phi
**
** **
DREQ0
** DREQ0 is sampled at
Figure 47. CPU Operation and DMA Operation DREQ0 is Programmed

for Level-Sense
When edge-sense is programmed, DMA operation begins at the falling

edge of DREQ0 If another falling edge is detected before the rising edge
of the clock prior to T3 during DMA write cycle (that is T2 or Tw), the
DMAC continues operating. If an edge is not detected, the CPU is given
control after the current byte DMA transfer completes. The CPU
continues operating until a DREQ0 falling edge is detected before the
UM005004-0918
Z8018x
108
rising edge of the clock prior to T3 at which time the DMA operation
(re)starts. Figure 48 depicts the edge-sense DMA timing.
DMA CPU DMA DMA CPU

Write Machine Read Write Machine
Cycle Cycle Cycle Cycle Cycle
Tw T3 T1 T2 T3 T1 T2 T3 T1 T2 Tw T3 T1 T2 T3
Phi
** ** ** **
DREQ0
** DREQ0 is sampled at
Figure 48. CPU Operation and DMA Operation DREQ0 is Programmed

for Edge-Sense
During the transfers for channel 0, the TEND0 output goes Low
synchronous with the write cycle of the last (BCR0 = OOH) DMA transfer
(Reference Figure 49).
Last DMA cycle (BCR0 = 00H)
DMA read cycle DMA write cycle
T1 T2 T3 T1 T2 TW T3
Phi
TEND0
Figure 49. TEND0 Output Timing Diagram
The DREQ0 and TEND0 pins are programmably multiplexed with the
CKA0 and CKA1 ASCI clock input/outputs. However, when DMA
channel 0 is programmed for memory to/from I/O (and memory to/from
UM005004-0918
Z8018x
109
memory mapped I/O. transfers, the CKA0/DREQ0 pin automatically

functions as input pin or output pin even if it has been programmed as
output pin for CKA0. And the CKA1/TEND0 pin functions as an input or
an output pin for TEND0 by setting CKA1D to 1 in CNTLA1.
To initiate memory to/from I/O (and memory to/from memory mapped
I/O) DMA transfer for channel 0, perform the following operations:
1. Load the memory and I/O or memory mapped I/O source and
destination addresses into SAR0 and DAR0.
I/O addresses (not memory mapped I/O are limited to 16 bits
(A0–A15). Make sure that bits A16, A17 and A19 are 0 (A18 is a
don't care) to correctly enable the external DREQ0 input.
2. Specify memory to/from I/O or memory to/from memory mapped I/O

mode and address increment/decrement in the SM0, SM1, DM0 and
DM1 bits of DMODE.
3. Load the number of bytes to transfer in BCR0.
4. Specify whether DREQ0 is edge- or level-sense by programming the
DMS0 bit of DCNTL.
5. Enable or disable DMA termination interrupt with the DIE0 bit in
DSTAT.
6. Program DE0: = 1 (with DWEO = 0 in the same access) in DSTAT
and the DMA operation begins under the control of the DREQ0 input.
Memory to ASCI - Channel 0

Channel 0 has extra capability to support DMA transfer to/from the on-
chip two channel ASCI. In this case, the external DREQ0 input is not
used for DMA timing. Rather, the ASCI status bits are used to generate an
internal DREQ0 The TDRE (Transmit Data Register Empty) bit and the
RDRF (Receive Data Register Full) bit are used to generate an internal
UM005004-0918
Z8018x
110
DREQ0 for ASCI transmission and reception respectively. To initiate

memory to/from ASCI DMA transfer, perform the following operations:
1. Load the source and destination addresses into SAR0 and DAR0
Specify the I/O (ASCI) address as follows:
a. Bits A0–A7 must contain the address of the ASCI channel
transmitter or receiver (I/O addresses 6H-9H).
b. Bits A8–A15 must equal 0.
c. Bits SAR17–SAR16 must be set according to Table 16 to enable
use of the appropriate ASCI status bit as an internal DMA
request.
Table 16. DMA Transfer Request
SAR18 SAR17 SAR16 DMA Transfer Request
X 0 0 DREQ0
X 0 1 RDRF (ASCI channel 0)
X 1 0 RDRF (ASCI channel 1)
X 1 1 Reserved
Note: X = Don’t care
DAR18 DAR17 DAR16 DMA Transfer Request
X 0 0 DREQ0
X 0 1 TDRE (ASCI channel O)
X 1 0 TDRE (ASCI channel 1)
X 1 1 Reserved
Note: X = Don’t care
UM005004-0918
Z8018x
111
2. Specify memory ↔ I/O transfer mode and address increment/

decrement in the SM0, SM1, DM0 and DM1 bits of DMODE.
3. Load the number of bytes to transfer in BCR0
4. The DMA request sense mode (DMS0 bit in DCNTL) must be
specified as edge sense.
DSTAT.
6. Program DE0 =1 (with DWE0 = 0 in the same access) in DSTAT and
the DMA operation with the ASCI begins under control of the ASCI
generated internal DMA request.
The ASCI receiver or transmitter using DMA is initialized to allow the
first DMA transfer to begin.
The ASCI receiver must be empty as shown by RDRF = 0.
The ASCI transmitter must be full as shown by TDRE = 0. Thus, the first
byte is written to the ASCI Transmit Data Register under program
control. The remaining bytes are transferred using DMA.
Channel 1 DMA
DMAC Channel 1 performs memory to/from I/O transfers. Except for
different registers and status/control bits, operation is exactly the same as
described for channel 0 memory to/from I/O DMA.
To initiate a DMA channel 1 memory to/from I/O transfer, perform the
following operations:
1. Load the memory address (20 bits) into MAR1.
2. Load the I/O address (16 bits) into IAR1.
3. Program the source/destination and address increment/decrement
mode using the DIM1 and DIM0 bits in DCNTL.
UM005004-0918
Z8018x
112
4. Specify whether DREQ1 is level- or edge- sense in the DMS1 bit in

DCNTL.
DSTAT.
6. Program DE1 = 1 (with DWE1 = 0 in the same access) in DSTAT
and the DMA operation with the external I/O device begins using the
external DREQ1 input and TEND1 output.
DMA Bus Timing

When memory (and memory mapped I/O) is specified as a source or
destination, MREQ goes Low during the memory access. When I/O is
specified as a source or destination, IORQ goes Low during the I/O access.
When I/O (and memory mapped I/O) is specified as a source or
destination, the DMA timing is controlled by the external DREQ input
and the TEND output indicates DMA termination
Note: External I/O devices may not overlap addresses with internal I/O
and control registers, even using DMA.
For I/O accesses, one Wait State is automatically inserted. Additional

Wait States can be inserted by programming the on-chip wait state
generator or using the external WAIT input.
Note: For memory mapped I/O accesses, this automatic I/O Wait State
is not inserted.
For memory to memory transfers (channel 0 only), the external DREQ0

input is ignored. Automatic DMA timing is programmed as either
BURST or CYCLE STEAL.
When a DMA memory address carry/borrow between bits A15 and A16
of the address bus occurs (crossing 64KB boundaries), the minimum bus
UM005004-0918
Z8018x
113
cycle is extended to 4 clocks by automatic insertion of one internal Ti

state.
DMAC Channel Priority

For simultaneous DREQ0 and DREQ1 requests, channel 0 has priority
over channel 1. When channel 0 is performing a memory to/from memory
transfer, channel 1 cannot operate until the channel 0 operation has
terminated. If channel 1 is operating, channel 0 cannot operate until
channel 1 releases control of the bus.
DMAC and BUSREQ, BUSACK

The BUSREQ and BUSACK inputs allow another bus master to take
control of the Z8X180 bus. BUSREQ and BUSACK take priority over the
on-chip DMAC and suspends DMAC operation. The DMAC releases the
bus to the external bus master at the breakpoint of the DMAC memory or
I/O access. Since a single byte DMAC transfer requires a read and a write
cycle, it is possible for the DMAC to be suspended after the DMAC read,
but before the DMAC write. Hence, when the external master releases the
Z8X180 bus (BUSREQ High), the on-chip DMAC correctly continues
the suspended DMA operation.
UM005004-0918
Z8018x
114
DMAC Internal Interrupts

Figure 50 illustrates the internal DMA interrupt request generation circuit.
IEF1
DE1 DMA ch1 Interrupt

Request
DIE1
DE0 DMA ch0 Interrupt

Request
DIE0
Figure 50. DMA Interrupt Request Generation
DE0 and DE1 are automatically cleared to 0 by the Z8X180 at the

completion (byte count is 0) of a DMA operation for channel 0 and
channel 1, respectively. They remain 0 until a 1 is written. Because DE0:
and DE1 use level sense, an interrupt occurs if the CPU IEF1 flag is set to
1. Therefore, the DMA termination interrupt service routine disables
further DMA interrupts (by programming the channel DIE bit is 0) before
enabling CPU interrupts (for example, IEF1 is set to 1). After reloading
the DMAC address and count registers, the DIE bit can be set to 1 to
reenable the channel interrupt, and at the same time DMA can resume by
programming the channel DE bit = 1.
DMAC and NMI

NMI, unlike all other interrupts, automatically disables DMAC operation
by clearing the DME bit of DSTAT. Thus, the NMI interrupt service
routine responds to time-critical events without delay due to DMAC bus
usage. Also, NMI can be effectively used as an external DMA abort input,
recognizing that both channels are suspended by the clearing of DME.
UM005004-0918
Z8018x
115
If the falling edge of NMI occurs before the falling clock of the state prior
to T3 (T2 or Tw) of the DMA write cycle, the DMAC is suspended and
the CPU starts the NMI response at the end of the current cycle. By
setting a channel's DE bit to 1, the channel's operation is restarted and
DMA correctly resumes from its suspended point by NMI. (Reference
Figure 51.)
DMA read cycle DMA write cycle NMI acknowledge cycle
T1 T2 T3 T1 T2 T3 T1
Phi
NMI
DME = “0” (DMA Stop)
Figure 51. NMI and DMA Operation Timing Diagram
DMAC and RESET

During RESET the bits in DSTAT, DMODE, and DCNTL are initialized
as stated in their individual register descriptions. Any DMA operation in
progress is stopped, allowing the CPU to use the bus to perform the
RESET sequence. However, the address register (SAR0, DAR0 MAR1,
IAR1) and byte count register (BCR0 BCR1) contents are not changed
during RESET.
Asynchronous Serial Communication Interface (ASCI)

The Z8X180 on-chip ASCI has two independent full-duplex channels.
Based on full programmability of the following functions, the ASCI
directly communicates with a wide variety of standard UARTs (Universal
Asynchronous Receiver/Transmitter) including the Z8440 SIO and the
Z85C30 SCC.
UM005004-0918
Z8018x
116
The key functions for ASCI on Z80180, Z8S180 and Z8L180 class
processors are listed below. Each channel is independently
programmable.
• Full-duplex communication
• 7- or 8-bit data length
• Program controlled 9th data bit for multiprocessor communication
• 1 or 2 stop bits
• Odd, even, no parity
• Parity, overrun, framing error detection
• Programmable baud rate generator, /16 and /64 modes
• Modem control signals – Channel 0 contains DCD0, CTS0 and RTS0;
Channel 1 contains CTS1
• Programmable interrupt condition enable and disable
• Operation with on-chip DMAC
ASCI Block Diagram for the Z8S180/Z8L180-Class

Processors
Figure 52 illustrates the ASCI block diagram.
UM005004-0918
Z8018x
117
Interrupt Request
ASCI Transmit Data Register ASCI Transmit Data Register

ch 0 : TDR0 ch 1 : TDR1
TXA0 ASCI Transmit Shift Register* ASCI Transmit Shift Register* TXA1
ch 0 : TSR0 ch 1 : TSR1
ASCI Receive Data Register ASCI Receive Data Register

ch 0 : RDR0 ch 1 : RDR1
RXA0 ASCI Receive Shift Register* ASCI Receive Shift Register* RXA1
ASCI ch 1 : RSR1 (8)
ch 0 : RSR0 (8) Control
ASCI Control Register A ASCI Control Register A
RTS0 ch 0 : CNTLA0 (8) ch 1 : CNTLA1 (8)
ASCI Control Register B ASCI Control Register B CTS1

CTS0
ch 0 : CNTLB0 (8) ch 1 : CNTLB1 (8)
DCD0 ASCI Status Register ASCI Status Register

ch 0 : STAT0 (8) ch 1 : STAT1 (8)
CKA0 Baud Rate

Generator 0 Phi
* Not program Accessible
CKA1 Baud Rate
Generator 1
Figure 52. ASCI Block Diagram
ASCI Register Description

The following subparagraphs explain the various functions of the ASCI
registers.
ASCI Transmit Shift Register 0, 1 (TSR0, 1)

When the ASCI Transmit Shift Register receives data from the ASCI
Transmit Data Register (TDR), the data is shifted out to the TXA pin.
UM005004-0918
Z8018x
118
When transmission is completed, the next byte (if available) is

automatically loaded from TDR into TSR and the next transmission
starts. If no data is available for transmission, TSR idles by outputting a
continuous High level. The TSR is not program-accessible.
ASCI Transmit Data Register 0, 1(TDR0,1:I/O Address = 06H, 07H)
Data written to the ASCI Transmit Data Register is transferred to the TSR
as soon as TSR is empty. Data can be written while TSR is shifting out the
previous byte of data. Thus, the ASCI transmitter is double buffered. Data
can be written into and read from the ASCI Transmit Data Register.
If data is read from the ASCI Transmit Data Register, the ASCI data
transmit operation is not affected by this read operation.
ASCI Transmit Data Register Ch. 0 (TDR0: 06H)

Bit 7 6 5 4 3 2 1 0
Bit/Field ASCI Transmit Channel 0
R/W R/W
Reset 0
ASCI Transmit Data Register Ch. 1 (TDR1: 07H)

Bit 7 6 5 4 3 2 1 0
Bit/Field ASCI Transmit Channel 1
R/W R/W
Reset 0
UM005004-0918
Z8018x
119
ASCI Receive Shift Register 0,1(RSR0, 1)

This register receives data shifted in on the RXA pin. When full, data is
automatically transferred to the ASCI Receive Data Register (RDR) if it
is empty. If RSR is not empty when the next incoming data byte is shifted
in, an overrun error occurs. The RSR is not program-accessible.
ASCI Receive Data Register 0,1 (RDR0, 1: I/O Address = 08H, 09H)
When a complete incoming data byte is assembled in RSR, it is
automatically transferred to the RDR if RDR is empty. The next incoming
data byte can be shifted into RSR while RDR contains the previous
received data byte. Thus, the ASCI receiver on Z80180 is double-
buffered.
ASCI Receive Data Register Ch. 0 (RDR0: 08H)

Bit 7 6 5 4 3 2 1 0
Bit/Field ASCI Receive Channel 0
R/W R/W
Reset 0
ASCI Receive Data Register Ch. 1 (RDR1: 09H)

Bit 7 6 5 4 3 2 1 0
Bit/Field ASCI Receive Channel 1
R/W R/W
Reset 0
On the Z8S180 and Z8L180-class processors are quadruple buffered. The

ASCI Receive Data Register is a read-only register. However, if RDRF =
UM005004-0918
Z8018x
120
0, data can be written into the ASCII Receive Data Register, and the data
can be read.
ASCI Status Register 0, 1 (STAT0, 1)

Each channel status register allows interrogation of ASCI
communication, error and modem control signal status, and enabling or
disabling of ASCI interrupts.
ASCI Status Register 0 (STAT0: 04H)

Bit 7 6 5 4 3 2 1 0
Bit/Field RDRF OVRN PE FE RIE DCD0 TDRE TIE
R/W R R R R R/W R R R/W
Reset 0 0 0 0 0 0 0 0
Bit
7 RDRF R Receive Data Register Full — RDRF is set to 1 when an

incoming data byte is loaded into RDR. If a framing or
parity error occurs, RDRF remains set and the receive
data (which generated the error) is still loaded into RDR.
RDRF is cleared to 0 by reading RDR, when the DCD0
input is High, in IOSTOP mode, and during RESET.
6 OVRN R Overrun Error — OVRN is set to 1 when RDR is full
and RSR becomes full. OVRN is cleared to 0 when the
EFR bit (Error Flag Reset) of CNTLA is written to 0,
when DCD0 is High, in IOSTOP mode, and during
RESET.
UM005004-0918
Z8018x
121
Bit
5 PE R Parity Error — PE is set to 1 when a parity error is

detected on an incoming data byte and ASCI parity
detection is enabled (the MOD1 bit of CNTLA is set to
1). PE is cleared to 0 when the EFR bit (Error Flag Reset)
of CNTLA is written to 0, when DCD0 is High, in
IOSTOP mode, and during RESET.
4 FE R Framing Error — If a receive data byte frame is
delimited by an invalid stop bit (that is, 0, should be 1),
FE is set to 1. FE is cleared to 0 when the EFR bit (Error
Flag Reset) of CNTLA is written to 0, when DCD0 is
High, in IOSTOP mode, and during RESET.
3 RIE R/W Receive Interrupt Enable — RIE must be set to 1 to
enable ASCI receive interrupt requests. When RIE is 1, if
any of the flags RDRF, OVRN, PE, or FE become set to
1, an interrupt request is generated. For channel 0, an
interrupt is also generated by the transition of the external
DCD0 input from Low to High.
2 DCD0 R Data Carrier Detect — Channel 0 has an external
DCD0 input pin. The DCD0 bit is set to 1 when the
DCD0 input is HIGH. It is cleared to 0 on the first read of
(STAT0, following the DCD0 input transition from
HIGH to LOW and during RESET. When DCD0 is 1,
receiver unit is reset and receiver operation is inhibited.
1 TDRE R Transmit Data Register Empty — TDRE = 1 indicates
that the TDR is empty and the next transmit data byte is
written to TDR. After the byte is written to TDR, TDRE
is cleared to 0 until the ASCI transfers the byte from TDR
to the TSR and then TDRE is again set to 1. TDRE is set
to 1 in IOSTOP mode and during RESET. When the
external CTS input is High, TDRE is reset to 0.
UM005004-0918
Z8018x
122
Bit
0 TIE R/W Transmit Interrupt Enable — TIE must be set to 1 to

enable ASCI transmit interrupt requests. If TIE is 1, an
interrupt is requested when TDRE is 1. TIE is cleared to 0
during RESET.
UM005004-0918
Z8018x
123
ASCI Control Register A0, 1 (CNTLA0, 1)

Each ASCI channel Control Register A configures the major operating modes
such as receiver/transmitter enable and disable, data format, and multiprocessor
communication mode.
ASCI Status Register 1 (STAT1: 05H)

Bit 7 6 5 4 3 2 1 0
Bit/Field RDRF OVRN PE FE RIE CTS1E TDRE TIE
R/W R R R R R/W R/W R R/W
Reset 0 0 0 0 0 0 0 0
Bit
7 RDRF R Receive Data Register Full — RDRF is set to 1 when an

incoming data byte is loaded into RDR. Note that if a
framing or parity error occurs, RDRF is still set and the
receive data (which generated the error) is still loaded
into RDR. RDRF is cleared to 0 by reading RDR, when
the DCD0 input is High, in IOSTOP mode, and during
RESET.
6 OVRN R Overrun Error — OVRN is set to 1 when RDR is full
and RSR becomes full. OVRN is cleared to 0 when the
EFR bit (Error Flag Reset) of CNTLA is written to 0,
when DCD0 is High, in IOSTOP mode, and during
RESET.
5 PE R Parity Error — PE is set to 1 when a parity error is
detected on an incoming data byte and ASCI parity
detection is enabled (the MOD1 bit of CNTLA is set to
1). PE is cleared to 0 when the EFR bit (Error Flag Reset)
of CNTLA is written to 0, when DCD0 is High, in
IOSTOP mode, and during RESET.
UM005004-0918
Z8018x
124
Bit
4 FE R Framing Error — If a receive data byte frame is

delimited by an invalid stop bit (that is, 0, should be 1),
FE is set to 1. FE is cleared to 0 when the EFR bit (Error
Flag Reset) of CNTLA is written to 0, when DCD0 is
High, in IOSTOP mode, and during RESET.
3 RIE R/W Receive Interrupt Enable — RIE must be set to 1 to
enable ASCI receive interrupt requests. When RIE is 1, if
any of the flags RDRF, OVRN, PE, or FE become set to
1, an interrupt request is generated. For channel 0, an
interrupt is also generated by the transition of the external
DCD0 input from Low to High.
2 CTS1E R/W Channel 1 CTS Enable — Channel 1 has an external
CTS1 input which is multiplexed with the receive data
pin (RXS) for the CSI/O (Clocked Serial I/O Port).
Setting CTS1E to 1 selects the CTS1 function and
clearing CTS1E to 0 selects the RXS function.
1 TDRE R Transmit Data Register Empty — TDRE = 1 indicates
that the TDR is empty and the next transmit data byte is
written to TDR. After the byte is written to TDR, TDRE
is cleared to 0 until the ASCI transfers the byte from TDR
to the TSR and then TDRE is again set to 1. TDRE is set
to 1 in IOSTOP mode and during RESET. When the
external CTS input is High, TDRE is reset to 0.
0 TIE R/W Transmit Interrupt Enable — TIE must be set to 1 to
enable ASCI transmit interrupt requests. If TIE is 1, an
interrupt is requested when TDRE is 1. TIE is cleared to 0
during RESET.
UM005004-0918
Z8018x
125
ASCI Control Register A0, 1 (CNTLA0, 1)

Each ASCI channel Control Register A configures the major operating
modes such as receiver/transmitter enable and disable, data format, and
multiprocessor communication mode.
ASCI Control Register A 0 (CNTLA0: 00H)

Bit 7 6 5 4 3 2 1 0
Bit/Field MPE RE TE RTS0 MPBR/ MOD2 MOD1 MOD0
EFR
Reset 0 0 0 1 X 0 0 0
Bit
7 MPE R/W Multi-Processor Mode Enable — The ASCI has a

multiprocessor communication mode which utilizes an
extra data bit for selective communication when a number
of processors share a common serial bus. Multiprocessor
data format is selected when the MP bit in CNTLB is set
to 1. If multiprocessor mode is not selected (MP bit in
CNTLB = 0), MPE has no effect. If multiprocessor mode
is selected, MPE enables or disables the wakeup feature
as follows. If MPE is set to 1, only received bytes in
which the MPB (multiprocessor bit) is 1 can affect the
RDRF and error flags. Effectively, other bytes (with MPB
is 0) are ignored by the ASCI. If MPE is reset to 0, all
bytes, regardless of the state of the MPB data bit, affect
the RDRF and error flags.
UM005004-0918
Z8018x
126
Bit
6 RE R/W Receiver Enable — When RE is set to 1, the ASCI

receiver is enabled. When RE is reset to 0, the receiver is
disabled and any receive operation in progress is
interrupted. However, the RDRF and error flags are not
reset and the previous contents of RDRF and error flags
are held. RE is cleared to 0 in IOSTOP mode, and during
RESET.
5 TE R/W Transmitter Enable — When TE is set to 1, the ASCI
transmitter is enabled. When TE is reset to 0, the
transmitter is disabled and any transmit operation in
progress is interrupted. However, the TDRE flag is not
reset and the previous contents of TDRE are held. TE is
cleared to 0 in IOSTOP mode, and during RESET.
4 RTS0 R/W Request to Send Channel 0 — When RTS0 is reset to 0,
the RTS0 output pin goes Low. When RTS0 is set to 1,
the RTS0 output immediately goes High.
3 MPBR/ R/W Multiprocessor Bit Receive/Error Flag Reset — When
EFR multiprocessor mode is enabled (MP in CNTLB is 1),
MPBR, when read, contains the value of the MPB bit for
the last receive operation. When written to 0, the EFR
function is selected to reset all error flags (OVRN, FE and
PE) to 0. MPBR/EFR is undefined during RESET.
UM005004-0918
Z8018x
127
Bit
2–0 MOD2–0 R/W ASCI Data Format Mode 2, 1, 0 — These bits program
the ASCI data format as follows.
MOD2
0: 7 bit data
1: 8 bit data
MOD1
0: No parity
1: Parity enabled
MOD0
0: 1 stop bit
1: 2 stop bits
The data formats available based on all combinations of

MOD2, MOD1 and MOD0 are described in Table 17.
UM005004-0918
Z8018x
128
ASCI Control Register A 1 (CNTLA1: 01H)

Bit 7 6 5 4 3 2 1 0
Bit/Field MPE RE TE CKA1D MPBR/ MOD2 MOD1 MOD0
EFR
Reset 0 0 0 0 X 0 0 0
Bit
7 MPE R/W Multi-Processor Mode Enable — The ASCI has a

multiprocessor communication mode which utilizes an
extra data bit for selective communication when a number
of processors share a common serial bus. Multiprocessor
data format is selected when the MP bit in CNTLB is set
to 1. If multiprocessor mode is not selected (MP bit in
CNTLB = 0), MPE has no effect. If multiprocessor mode
is selected, MPE enables or disables the wakeup feature as
follows. If MPE is set to 1, only received bytes in which
the MPB (multiprocessor bit) is 1 can affect the RDRF
and error flags. Effectively, other bytes (with MPB = 0)
are ignored by the ASCI. If MPE is reset to 0, all bytes,
regardless of the state of the MPB data bit, affect the
RDRF and error flags.
6 RE R/W Receiver Enable — When RE is set to 1, the ASCI
receiver is enabled. When RE is reset to 0, the receiver is
disabled and any receive operation in progress is
interrupted. However, the RDRF and error flags are not
reset and the previous contents of RDRF and error flags
are held. RE is cleared to 0 in IOSTOP mode, and during
RESET.
UM005004-0918
Z8018x
129
Bit
5 TE R/W Transmitter Enable — When TE is set to 1, the ASCI

transmitter is enabled. When TE is reset to 0, the
transmitter is disabled and any transmit operation in
progress is interrupted. However, the TDRE flag is not
reset and the previous contents of TDRE are held. TE is
cleared to 0 in IOSTOP mode, and during RESET.
4 CKA1D R/W CKA1 Clock Disable — When CKA1D is set to 1, the
multiplexed CKA1/TEND0 pin is used for the TEND0
function. When CKA1 D is 0, the pin is used as CKA1, an
external data dock input/output for channel 1
3 MPBR/ R/W Multiprocessor Bit Receive/Error Flag Reset — When
EFR multiprocessor mode is enabled (MP in CNTLB is 1),
MPBR, when read, contains the value of the MPB bit for
the last receive operation. When written to 0, the EFR
function is selected to reset all error flags (OVRN, FE and
PE) to 0. MPBR/EFR is undefined during RESET.
UM005004-0918
Z8018x
130
Bit
2– 0 MOD2–0 R/W ASCI Data Format Mode 2, 1, 0 — These bits program

the ASCI data format as follows.
MOD2
0: 7 bit data
1: 8 bit data
MOD1
0: No parity
1: Parity enabled
MOD0
0: 1 stop bit
1: 2 stop bits
The data formats available based on all combinations of

MOD2, MOD1 and MOD0 are described in Table 17.
UM005004-0918
Z8018x
131
Table 17. Data Formats
MOD2 MOD1 MOD0 Data Format
0 0 0 Start + 7 bit data + 1 stop

0 0 1 Start + 7 bit date + 2 Stop
0 1 0 Start + 7 bit data + parity + 1 stop
1 1 1 Start + 8 bit date + parity + 2 stop
ASCI Control Register B0, 1 (CNTLB0, 1)

Each ASCI channel control register B configures multiprocessor mode,
parity and baud rate selection.
UM005004-0918
Z8018x
132
ASCI Control Register B 0 (CNTLB0: 02H)

ASCI Control Register B 1 (CNTLB1: 03H)
Bit 7 6 5 4 3 2 1 0
Bit/Field MPBT MP CTS/PS PE0 DR SS2 SS1 SS0
Reset X 0 0 0 0 1 1 1
Bit
7 MPBT R/W Multiprocessor Bit Transmit — When multiprocessor

communication format is selected (MP bit is 1), MPBT is
used to specify the MPB data bit for transmission. If
MPBT is 1, then MPB = 1 is transmitted. If MPBT is 0,
then MPBT = 0 is transmitted. MPBT state is undefined
during and after RESET.
6 MP R/W Multiprocessor Mode — When MP is set to 1, the data
format is configured for multiprocessor mode based on
the MOD2 (number of data bits) and MOD0 (number of
stop bits) bits in CNTLA. The format is as follows.
Start bit + 7 or 8 data bits + MPB bit + 1 or 2 stop bits
Multiprocessor (MP = 1) format has no provision for
parity. If MP is 0, the data format is based on MOD0
MOD1, MOD2, and may include parity. The MP bit is
cleared to 0 during RESET.
UM005004-0918
Z8018x
133
Bit
5 CTS/PS R/W Clear to Send/Prescale — When read, CTS/PS reflects

the state of the external CTS input. If the CTS input pin
is High, CTS/PS is read as 1. When the CTS input pin is
High, the TDRE bit is inhibited (that is, held at 0). For
channel 1, the CTS1 input is multiplexed with RXS pin
(Clocked Serial Receive Data). Thus, CTS/PS is only
valid when read if the channel 1 CTS1E bit is 1 and the
CST1 input pin function is selected. The read data of
CTS/PS is not affected by RESET.
When written, CT /PS specifies the baud rate generator
prescale factor. If CTS/PS is set to 1, the system clock is
prescaled by 30 while if CTS/PS is cleared to 0, the
system clock is prescaled by 10.CTS/PS is cleared to 0
during RESET.
4 PEO R/W Parity Even Odd — PE0 selects even or odd parity. PE0
does not affect the enabling/disabling of parity (MOD1
bit of CNTLA). If PE0 is cleared to 0, even parity is
selected. If PE0 is set to 1, odd parity is selected.PE0 is
cleared to 0 during RESET.
3 DR R/W Divide Ratio — DR specifies the divider used to obtain
baud rate from the data sampling clock If DR is reset to 0,
divide by 16 is used, while if DR is set to 1, divide by 64
is used. DR is cleared to 0 during RESET.
2– 0 SS2–0 R/W Source/Speed Select — Specifies the data clock source
(internal or external) and baud rate prescale factor. SS2,
SS1, and SS0 are all set to 1 during RESET. Table 18
describes the divide ratio corresponding to SS2, SS1 and
SS0
The external ASCI channel 0 data clock pins are multiplexed with DMA
control lines (CKA0/DREQ and CKA1/TEND0). During RESET, these
UM005004-0918
Z8018x
134
pins are initialized as ASCI data clock inputs. If SS2, SS1 and SS0 are
reprogrammed (any other value than SS2, SS1, SS0 = 1) these pins
become ASCI data clock inputs. However, if DMAC channel 0 is
configured to perform memory to/from I/O (and memory mapped I/O)
transfers the CKA0/DREQ0 pin reverts to DMA control signals
regardless of SS2, SS1, SS0 programming.
Also, if the CKA1D bit in the CNTLA register is 1, then the CKA1/
TEND0 reverts to the DMA Control output function regardless of SS2,
SS1 and SS0 programming. Final data clock rates are based on CTS/PS
(prescale), DR, SS2, SS1, SS0 and the Z8X180 system clock frequency
(Reference Table 19).
Table 18. Divide Ratio
SS2 SS1 SS0 Divide Ratio
0 0 0 ÷1
0 0 1 ÷2
0 1 0 ÷4
0 1 1 ÷8
1 0 0 ÷ 16
1 0 1 ÷ 32
1 1 0 ÷ 64
1 1 1 external clock

UM005004-0918
Z8018x
135
ASCI0 Extension Control Register (I/O Address: 12H) (Z8S180/L180-Class Processors

Only)
Bit 7 6 5 4 3 2 1 0
Bit/Field RDRF DCD0 CTS0 X1 Bit BRG0 Break Break Send
Int Disable Disable Clk Mode Feature Detect Break
Inhibit ASCI0 Enable (RO)
Reset 0 0 0 0 0 0 0 0
Bit
7 RDRF R/W 0 RDRF Interrupt Inhibit On

Interrupt 1 RDRF Interrupt Inhibit Off
Inhibit
6 DCD0 R/W 0 DCD0 Auto-enables Rx
Disable 1 DCD0 advisory to SW
5 CTS0 R/W 0 CTS0 Auto-enable Tx
Disable 1 CTS0 advisory to SW
4 X1 Bit R/W 0 CKA0 /16 or /64
Clk 1 CKA0 is bit clock
ASCI0
3 BRG0 R/W 0 As S180
Mode 1 Enable 16-bit BRG counter
2 Break R/W 0 Break Feature Enable On
Feature 1 Break Feature Enable Off
Enable
1 Break R/W 0 Break Detect On
Detect 1 Break Detect Off
(RO)
UM005004-0918
Z8018x
136
Bit
0 Send R/W 0 Normal Xmit

Break 1 Drive TXA Low

ASCI1 Extension Control Register (I/O Address: 13H) (Z8S180/L180-Class Processors

Only)
Bit 7 6 5 4 3 2 1 0
Bit/Field RDRF Reserved X1 Bit BRG1 Break Break Send
Int Clk Mode Feature Detect Break
Inhibit ASCI1 Enable (RO)
R/W R/W ? R/W R/W R/W R/W R/W
Reset 0 0 0 0 0 0 0
Bit
7 RDRF R/W 0 RDRF Interrupt Inhibit On

Interrupt 1 RDRF Interrupt Inhibit Off
Inhibit
6–5 Reserved ? 0 Reserved. Must be 0
4 X1 Bit R/W 0 CKA1 /16 or /64
Clk 1 CKA1 is bit clock
ASCI1
3 BRG1 R/W 0 As S180
Mode 1 Enable 16-bit BRG counter
UM005004-0918
Z8018x
137
Bit
2 Break R/W 0 Break Feature Enable On

Feature 1 Break Feature Enable Off
Enable
1 Break R/W 0 Break Detect On
Detect 1 Break Detect Off
(RO)
0 Send R/W 0 Normal Xmit
Break 1 Drive TXA Low

ASCI0 Time Constant Low Register (I/O Address: 1AH) (Z8S180/L180-Class Processors
Only)
Bit 7 6 5 4 3 2 1 0
Reset 0 0 0 0 0 0 0 0
ASCI0 Time Constant High Register (I/O Address: 1BH) (Z8S180/L180-Class Processors
Only)
Bit 7 6 5 4 3 2 1 0
Reset 0 0 0 0 0 0 0 0
UM005004-0918
Z8018x
138
ASCI1 Time Constant Low Register (I/O Address: 1CH) (Z8S180/L180-Class Processors
Only)
Bit 7 6 5 4 3 2 1 0
Reset 0 0 0 0 0 0 0 0
ASCI1 Time Constant High Register (I/O Address: 1DH) (Z8S180/L180-Class Processors
Only)
Bit 7 6 5 4 3 2 1 0
Reset 0 0 0 0 0 0 0 0
Modem Control Signals

ASCI channel 0 has CTS0, DCD0 and RTS0 external modem control
signals. ASCI channel 1 has a CTS1 modem control signal which is
multiplexed with Clocked Serial Receive Data (RXS).
CTS0: Clear to Send 0 (Input)

The CTS0 input allows external control (start/stop) of ASCI channel 0
transmit operations. When CTS0 is High, the channel 0 TDRE bit is held
at 0 whether or not the TDR0 (Transmit Data Register) is full or empty.
When CTS0 is Low, TDRE reflects the state of TDR0. The actual
transmit operation is not disabled by CT High, only TDRE is inhibited:
DCD0: Data Carrier Detect 0 (Input)

The DCD0 input allows external control (start/stop) of ASCI channel 0
receive operations. When DCD0 is High, the channel 0 RDRF bit is held
at 0 whether or not the RDR0, (Receive Data Register) is full or empty.
UM005004-0918
Z8018x
139
The error flags (PE, FE, and OVRN bits) are also held at 0. Even after the
DCD0 input goes Low, these bits do not resume normal operation until
the status register (STAT0, is read. This first read of (STAT0, while
enabling normal operation, still indicates the DCD0 input is High (DCD0
bit = 1) even though it has gone Low. Thus, the STAT0 register must be
read twice to ensure the DCD0 bit is reset to 0:
RTS0: Request to Send 0 (Output)

RTS0 allows the ASCI to control (start/stop) another communication
devices transmission (for example, by connection to that device's CTS
input). RTS0 is essentially a 1-bit output port, having no side effects on
other ASCI registers or flags.
CTS1: Clear to Send 1 (Input)

Channel 1 CTS1 input is multiplexed with Clocked Serial Receive Data
(RXS). The CTS1 function is selected when the CTS1E bit in STAT1 is
set to 1. When enabled, the CTS1 operation is equivalent to CTS0,
Modem control signal timing is depicted in Figure 53 and Figure 54.
DCD0 Pin
DCD0 Flag
Status Register Read
Figure 53. DCD0 Timing Diagram
UM005004-0918
Z8018x
140
I/O Instruction I/O write cycle
T1 T2 T3 T1
Phi
WR
RTS0 Flag
RTS0 Pin
Figure 54. RTS0 Timing Diagram
Figure 55 illustrates the ASCI interrupt request generation circuit.
IEF1
DCD0
RDRF0
OVRN0
PE0
FE0
RIE0 ASCI0 Interrupt
Request
TDRE0
TIE0
RDRF1
OVRN1
PE1
RIE1 ASCI1 Interrupt
FE1 Request
TDRE1
TIE1
Figure 55. ASCI Interrupt Request Circuit Diagram
UM005004-0918
Z8018x
141
ASCI to/from DMAC Operation

Operation of the ASCI with the on-chip DMAC channel 0 requires that the
DMAC be correctly configured to use the ASCI flags as DMA request signals.
ASCI and RESET

During RESET, the ASCI status and control registers are initialized as
defined in the individual register descriptions.
Receive and Transmit operations are stopped during RESET. However,
the contents of the transmit and receive data registers (TDR and RDR) are
not changed by RESET.
ASCI Clock
When in external clock input mode, the external clock is directly input to
the sampling rate (÷16/÷64) as depicted in Figure 56.
Internal Clock Baud Rate Selection Prescaler Sampling Rate

Phi ÷1 to ÷64 ÷10 ÷ 30 ÷16 ÷64
External Clock
fc ≤ Phi ÷ 40
Figure 56. ASCI Clock
UM005004-0918
Z8018x
142
Table 19. ASCI Baud Rate Selection
Sampling Baud Rate (Example)

Prescaler Rate Baud Rate (BPS) CKA
General
Divide SS2 SS1 SS0 Divide Divide φ = 6.144 φ = 4.608 φ = 3.072 Clock
PS Ratio DR Rate Ratio Ratio MHz MHz MHz I/O Frequency
0 0 0 ÷1 φ ÷ 160 38400 19200 φ ÷ 10
0 0 1 2 320 19200 9600 20
0 1 0 4 640 9600 4800 40

0 16
0 1 1 8 1280 4800 2400 0 80
1 0 0 16 2560 2400 1200 160
1 0 1 32 5120 1200 600 320
1 1 0 64 10240 600 300 640

0 φ ÷ 10 1 1 1 — fc ÷ 16 — — — I fc
0 0 0 ÷1 0÷640 9600 4800 φ ÷ 10
0 0 1 2 1280 4800 2400 20
0 1 0 4 2560 2400 1200 40
1 64 0 1 1 8 5120 1200 600 0 80
1 0 0 16 10240 600 300 160

1 0 1 32 20480 300 150 320
1 1 0 64 40960 150 75 640
1 1 1 — fc ÷ 64 — — — I fc
UM005004-0918
Z8018x
143
Table 19. ASCI Baud Rate Selection (Continued)
Sampling Baud Rate (Example)

Prescaler Rate Baud Rate (BPS) CKA
General
Divide SS2 SS1 SS0 Divide Divide φ = 6.144 φ = 4.608 φ = 3.072 Clock
PS Ratio DR Rate Ratio Ratio MHz MHz MHz I/O Frequency
0 0 0 ÷1 φ ÷ 480 9600 φ ÷ 30
0 0 1 2 960 4800 60
0 1 0 4 1920 2400 120
0 16 0 1 1 8 3840 1200 0 240
1 0 0 16 7680 600 480

1 0 1 32 15360 300 960
1 1 0 64 30720 150 1920

1 φ ÷ 30
1 1 1 — fc ÷ 16 — — — I fc
0 0 0 ÷1 φ ÷ 1920 2400 φ ÷ 30
0 0 1 2 3840 1200 60
0 1 0 4 7680 600 120
1 64 0 1 1 8 15360 300 0 240
1 0 0 16 30720 150 480
1 0 1 32 61440 75 960
1 1 0 64 122880 37.5 1920
1 1 1 — fc ÷ 64 — — — I fc
Baud Rate Generator

(Z8S180/Z8L180-Class Processors Only)
The Z8S180/Z8L180 Baud Rate Generator (BRG) features two modes.

The first is the same as in the Z80180. The second is a 16-bit down
counter that divides the processor clock by the value in a 16-bit time
constant register, and is identical to the DMSCC BRG. This feature allows
UM005004-0918
Z8018x
144
a common baud rate of up to 512 Kbps to be selected. The BRG can also
be disabled in favor of an external clock on the CKA pin.
The Receiver and Transmitter subsequently divide the output of the BRG
(or the signal from the CKA pin) by 1, 16, or 64, under the control of the
DR bit in the CNTLB register, and the X1 bit in the ASCI Extension
Control REgister. To compute baud rate, use the following formulas:
Where:
BRG mode is bit 3 of the ASEXT register
PS is bit 5 of the CNTLB register
TC is the 16-bit value in the ASCI Time Constant register
If ss2.1.0 = 111, baud rate - fCKA/Clock mode
else if BRG mode baud rate = fPHI/(2*(TC+2)*Clock mode)
else baud rate -fPHI/((10 + 20*PS) * 2^ss*Clock mode)
The TC value for a given baud rate is:
TC = (fPHI/*2*baud rate*Clock mode)) -2
Clock mode depends on bit 4 in ASEXT and bit 3 in CNTLB, as

described in Table 20.
Table 20. Clock Mode Bit Values
X1 DR Clock Mode
0 0 16
0 1 64
1 0 1
1 1 Reserved, do not use
UM005004-0918
Z8018x
145
2^ss depends on the three least significant bits of the CNTLB register, as
described in Table 21.
Table 21. 2^ss Values
ss2 ss1 ss0 2^ss
0 0 0 1
0 0 1 2
0 1 0 4
0 1 1 8
1 0 0 16
1 0 1 32
1 1 0 64
1 1 1 External Clock from CKA0
The ASCIs require a 50% duty cycle when CKA is used as an input.
Minimum High and Low times on CKA0 are typical of most CMOS
devices.
RDRF is set, and if enabled, an Rx Interrupt or DMA REquest is
generated when the receiver transfers a character from the Rx Shift
Register to the RX FIFO. The FIFO provides a margin against overruns.
When the is more than one character in the FIFO, and software or a DMA
channel reads a character, RDRF either remains set or is cleared and then
immediately set again. For example, if a receive interrupt service routine
does not real all the characters in the RxFIFO, RDRF and the interrupt
request remain asserted.
The Rx DMA request is disabled when any of the error flags PE or FE or
OVRN are set, so that software can identify with which character the
problem is associated.
If Bit 7, RDRF Interrupt Inhibit, is set to 1, the ASCI does not request a
Receive interrupt when its RDRF flag is 1. Set this bit when programming
a DMA channel to handle the receive data from an ASCI. The other
UM005004-0918
Z8018x
146
causes for an ASCI Receive interrupt (PE, FE, OVRN, and for ASCI0,
DCD) continue to request RX interrupt if the RIE bit is 1. The Rx DMA
request is inhibited if PE or FE or OVRN is set, so that software can
detect where an error occurred. When the RIE bit is 0, as it is after a
Reset, RDRF causes an ASCI interrupt if RIE is 1.
Clocked Serial I/O Port (CSI/O)

The Z8X180 includes a simple, high-speed clock, synchronous serial I/O
port. The CSI/O includes transmit/receive (half-duplex), fixed 8-bit data,
and internal or external data clock selection. High-speed operation (baud
rate 200Kbps at fC = 4 MHz) is provided. The CSI/O is ideal for
implementing a multiprocessor communication link between multiple
Z8X180s. These secondary devices may typically perform a portion of the
system I/O processing, (that is, keyboard scan/decode, LDC interface, for
instance).
CSI/O Block Diagram

The CSI/O block diagram is illustrated in Figure 57. The CSI/O consists
of two registers–the Transmit/Receive Data Register (TRDR) and Control
Register (CNTR).
UM005004-0918
Z8018x
147
Phi
TXS CSI/O Transmit/Receive CKS

Baud Rate
Data Register: Generator
RXS TRDR (8)
CSI/O Control Register:

CNTR (8)
Interrupt Request
Figure 57. CSI/O Block Diagram
CSI/O Registers Description
CSI/O Control/Status Register (CNTR: I/O Address 0AH)
CNTR is used to monitor CSI/O status, enable and disable the CSI/O,
enable and disable interrupt generation, and select the data clock speed
and source.
CSI/O Control/Status Register (CNTR: 0AH)

Bit 7 6 5 4 3 2 1 0
Bit/Field EF EIE RE TE — SS2 SS1 SS0
R/W R R/W R/W R/W R/W R/W R/W
Reset 0 0 0 0 1 1 1
UM005004-0918
Z8018x
148
Bit
7 EF R End Flag — EF is set to 1 by the CSI/O to indicate

completion of an 8-bit data transmit or receive operation.
If EIE (End Interrupt Enable) bit = 1 when EF is set to 1, a
CPU interrupt request is generated. Program access of
TRDR only occurs if EF is 1. The CSI/O clears EF to 0
when TRDR is read or written. EF is cleared to 0 during
RESET and IOSTOP mode.
6 EIE R/W End Interrupt Enable — EIE is set to 1 to enable EF = 1
to generate a CPU interrupt request. The interrupt request
is inhibited if EIE is reset to 0. EIE is cleared to 0 during
RESET.
5 RE R/W Receive Enable — A CSI/O receive operation is started
by setting RE to 1. When RE is set to 1, the data clock is
enabled. In internal clock mode, the data clock is output
from the CKS pin. In external dock mode, the dock is
input on the CKS pin. In either case, data is shifted in on
the RXS pin in synchronization with the (internal or
external) data clock. After receiving 8 bits of data, the
CSI/O automatically clears RE to 0, EF is set to 1, and an
interrupt (if enabled by EIE = 1) is generated. RE and TE
are never both set to 1 at the same time. RE is cleared to 0
during RESET and ISTOP mode.
RXS is multiplexed with CTS1 modem control input of
ASCI channel 1. In order to enable the RXS function, the
CTS1E bit in CNTA1 must be reset to 0.
UM005004-0918
Z8018x
149
Bit
4 TE R/W Transmit Enable — A CSI/O transmit operation is

started by setting TE to 1. When TE is set to 1, the data
clock is enabled. When in internal clock mode, the data
clock is output from the CKS pin. In external clock mode,
the clock is input on the CKS pin. In either case, data is
shifted out on the TXS pin synchronous with the (internal
or external) data clock. After transmitting 8 bits of data,
the CSI/O automatically clears TE to 0, EF is set to 1, and
an interrupt (if enabled by EIE = 1) is generated. TE and
RE are never both set to 1 at the same time. TE is cleared
to 0 during RESET and IOSTOP mode.
2–0 SS2–0 R/W Speed Select — Selects the CSI/O transmit/receive clock
source and speed. SS2, SS I and SS0 are all set to 1 during
RESET. Table 22 shows CSI/O Baud Rate Selection.
CSI/O Transmit/Receive Data Register (TRDR: I/O

Address = 0BH).
TRDR is used for both CSI/O transmission and reception. Thus, the
system design must insure that the constraints of half-duplex operation
are met (Transmit and receive operation cannot occur simultaneously).
For example, if a CSI/O transmission is attempted while the CSI/O is
receiving data, the CSI/O does not work.
TRDR is not buffered. Attempting to perform a CSI/O transmit while the

previous transmit data is still being shifted out causes the shift data to be
immediately updated, thereby corrupting the transmit operation in
progress. Similarly, reading TRDR during a transmit or receive must be
avoided.
UM005004-0918
Z8018x
150
CSI/O Transmit/Receive Register (TRDR: 0BH)

Bit 7 6 5 4 3 2 1 0
Bit/Field CSI/O Transmit/Receive Data
R/W R/W
Reset 0
Table 22. CSI/O Baud Rate Selection
SS2 SS1 SS0 Divide Ratio Baud Rate
0 0 0 ÷ 20 (200000)
0 0 1 ÷ 40 (100000)
0 1 0 ÷ 80 (50000)
0 1 1 ÷ 160 (25000)
1 0 0 ÷ 320 (12500)
1 0 1 ÷ 640 (6250)
1 1 0 ÷ 1280 (3125)
1 1 1 External Clock input (less than ÷ 20)
Note: ( ) indicates the baud rate (BPS) at Phi = 4 MHz.
After RESET, the CKS pin is configured as an external clock input (SS2,
SS1, SS0 = 1). Changing these values causes CKS to become an output pin
and the selected clock is output when transmit or receive operations are
enabled.
CSI/O Interrupts
The CSI/O interrupt request circuit is shown in Figure 58.
UM005004-0918
Z8018x
151
IEF1
EF CSI/O
Interrupt Request
EIE
Figure 58. CSI/O Interrupt Request Generation
CSI/O Operation
The CSI/O is operated using status polling or interrupt driven algorithms.
• Transmit–Polling
a. Poll the TE bit in CNTR until TE = 0.
b. Write the transmit data into TRDR.
c. Set the TE bit in CNTR to 1.
d. Repeat steps 1 to 3 for each transmit data byte.
• Transmit–Interrupts
a. Poll the TE bit in CNTR until TE = 0.
b. Write the first transmit data byte into TRDR.
c. Set the TE and EIE bits in CNTR to 1.
d. When the transmit interrupt occurs, write the next transmit data
byte into TRDR.
e. Set the TE bit in CNTR to 1.
f. Repeat steps 4 and 5 for each transmit data byte.
• Receive –Polling
a. Poll the RE bit in CNTR until RE = 0.
b. Set the RE bit in CNTR to 1.
UM005004-0918
Z8018x
152
c. Poll the RE bit in CNTR until RE = 0.

d. Read the receive data from TRDR.
e. Repeat steps 2 to 4 for each receive data byte.
• Receive–Interrupts
a. Poll the RE bit in CNTR until RE is 0.
b. Set the RE and EIE bits in CNTR to 1.
c. When the receive interrupt occurs read the receive data from
TRDR.
d. Set the RE bit in CNTR to 1.
e. Repeat steps 3 and 4 for each receive data byte.
CSI/O Operation Timing Notes

• Transmitter clocking and receiver sampling timings are different from
internal and external clocking modes. Figure 59 to Figure 62 illustrate
CSI/O Transmit/Receive Timing.
• The transmitter and receiver is disabled TE and RE = 0) when
initializing or changing the baud rate.
CSI/O Operation Notes

• Disable the transmitter and receiver (TE and RE = 0) before
initializing or changing the baud rate. When changing the baud rate
after completion of transmission or reception, a delay of at least one
bit time is required before baud rate modification.
• When RE or TE is cleared to 0 by software, a corresponding receive
or transmit operation is immediately terminated. Normally, TE or RE
is only cleared to 0 when EF is 1.
• Simultaneous transmission and reception is not possible. Thus, TE
and RE are not both 1 at the same time.
UM005004-0918
Z8018x
153
CSI/O and RESET

During RESET each bit in the CNTR is initialized as defined in the
CNTR register description. CSI/O transmit and receive operations in
progress are aborted during RESET. However, the contents of TRDR are
not changed.
CKS
TXS LSB MSB
TE
EF
Read or write of CSI/O

Transmit/Receive
Data Register
Figure 59. Transmit Timing Diagram–Internal Clock
UM005004-0918
Z8018x
154
CKS
TXS LSB MSB

2.5φ 2.5φ 2.5φ 2.5φ
7.5φ 7.5φ 7.5φ 7.5φ
TE
EF

Transmit/Receive
Data Register
Figure 60. Transmit Timing–External Clock
UM005004-0918
Z8018x
155
CKS
RXS LSB MSB
11φ 11φ 11φ 11φ
Sampling
RE
17φ
EF

Transmit/Receive
Data Register
Figure 61. CSI/O Receive Timing–Internal Clock
UM005004-0918
Z8018x
156
CKS
RXS LSB MSB
11.5φ 11.5φ 11.5φ 11.5φ

16.5φ 16.5φ 16.5φ 16.5φ
Sampling
RE
EF

Transmit/Receive
Data Register
Figure 62. CSI/O Receive Timing–External Clock
Programmable Reload Timer (PRT)

The Z8X180 contains a two channel 16-bit Programmable Reload Timer.
Each PRT channel contains a 16-bit down counter and a 16-bit reload
register. The down counter is directly read and written and a down counter
overflow interrupt can be programmably enabled or disabled. Also, PRT
channel 1 features a TOUT output pin (multiplexed with A18) which can be
set High, Low, or toggled. Thus, PRT1 can perform programmable output
waveform generation.
PRT Block Diagram

The PRT block diagram is depicted in Figure 63. The two channels
feature separate timer data and reload registers and a common status/
UM005004-0918
Z8018x
157
control register. The PRT input clock for both channels is equal to the
system clock divided by 20.
Phi ÷ 20 Phi ÷ 20
Timer Data Timer Data Timer Data Timer Data

Register 0L Register 0H Register 1L Register 1H
: TMDR0L (8) : TMDR0H (8) Timer Control : TMDR1L (8) : TMDR1H (8) TOUT
Register
: TCR (8)
Timer Reload Timer Reload Timer Reload Timer Reload
Register 0L Register 0H Register 1L Register 1H
: RLDR0L (8) : RLDR0H (8) : RLDR1L (8) : RLDR1H (8)
Interrupt Register
Figure 63. PRT Block Diagram
PRT Register Description
Timer Data Register (TMDR: I/O Address - CH0: 0CH, 0DH; CH1: 15H,
14H). PRT0 and PRT1 each contain 16-bit timer Data Registers (TMDR).
TMDR0 and TMDR1 are each accessed as low and high byte registers
(TMDR0H, TMDR0L and TMDR1H, TMDR1L). During RESET,
TMDR0 and TMDR1 are set to FFFFH.
TMDR is decremented once every twenty clocks. When TMDR counts

down to 0, it is automatically reloaded with the value contained in the
Reload Register (RLDR).
TMDR is read and written by software using the following procedures.

The read procedure uses a PRT internal temporary storage register to
UM005004-0918
Z8018x
158
return accurate data without requiring the timer to be stopped. The write
procedure requires the PRT to be stopped.
For reading (without stopping the timer), TMDR is read in the order of
lower byte - higher byte (TMDRnL, TMDRnH). The lower byte read
(TMDRnL) stores the higher byte value in an internal register. The
following higher byte read (TMDRnH) accesses this internal register.
This procedure insures timer data validity by eliminating the problem of
potential 16-bit timer updating between each 8-bit read. Specifically,
reading TMDR in higher byte–lower byte order may result in invalid data.
Note the implications of TMDR higher byte internal storage for
applications which may read only the lower and/or higher bytes. In
normal operation all TMDR read routines must access both the lower and
higher bytes, in that order. For writing, the TMDR down counting must be
inhibited using the TDE (Timer Down Count Enable) bits in the TCR
(Timer Control Register). Then, any or both higher and lower bytes of
TMDR can be freely written (and read) in any order.
CSI/O Transmit/Receive Data Register (TRDR: I/O

Address = 0BH).
TRDR is used for both CSI/O transmission and reception. Thus, the
system design must insure that the constraints of half-duplex operation
are met (Transmit and receive operation cannot occur simultaneously).
For example, if a CSI/O transmission is attempted while the CSI/O is
receiving data, the CSI/O does not work.
TRDR is not buffered. Attempting to perform a CSI/O transmit while the

previous transmit data is still being shifted out causes the shift data to be
immediately updated, thereby corrupting the transmit operation in
progress. Similarly, reading TRDR during a transmit or receive must be
avoided.
UM005004-0918
Z8018x
159
Timer Data Register 0L (TMDR0L: 0CH)

Bit 7 6 5 4 3 2 1 0
Bit/Field Timer Data
R/W R/W
Reset 0
Timer Data Register 0H (TMDR0H: 0DH)

Bit 7 6 5 4 3 2 1 0
R/W R/W
Reset 0
Timer Reload Register (RLDR: I/O Address = CH0: 0EH,

0FH, CHI, 16H, 17H)
PRT0 and PRT1 each contain 16-bit Timer Reload Registers (RLDR).
RLDR0 and RLDR1 are each accessed as low and high byte registers
(RLDR0H, RLDR0L and RLDR1H, RLDR1L). During RESET, RLDR0
and RLDR1 are set to FFFFH
When the TMDR counts down to 0, it is automatically reloaded with the
contents of RLDR.
UM005004-0918
Z8018x
160
Timer Reload Register Channel 0L (RLDR0L: 0EH)

Bit 7 6 5 4 3 2 1 0
Bit/Field Timer Reload Data
R/W R/W
Reset 0
Timer Reload Register Channel 0H (RLDR0L: 0FH)

Bit 7 6 5 4 3 2 1 0
R/W R/W
Reset 0
Timer Data Register 1L (TMDR1L: 14H)

Bit 7 6 5 4 3 2 1 0
R/W R/W
Reset 0
Timer Data Register 1H (TMDR1H: 15H)

Bit 7 6 5 4 3 2 1 0
R/W R/W
Reset 0
UM005004-0918
Z8018x
161
Timer Reload Register Channel 1L (RLDR1L: 16H)

Bit 7 6 5 4 3 2 1 0
R/W R/W
Reset 0
Timer Reload Register Channel 1H (RLDR1H: 17H)

Bit 7 6 5 4 3 2 1 0
R/W R/W
Reset 0
Timer Control Register (TCR)

TCR monitors both channels (PRT0, PRT1) TMDR status. It also controls
enabling and disabling of down counting and interrupts along with
controlling output pin A18/TOUT for PRT1.
Timer Control Register (TCR: 10H)

Bit 7 6 5 4 3 2 1 0
Bit/Field TIF1 TIF0 TIE1 TIE0 TOC1 TOC0 TDE1 TDE0
R/W R R R/W R/W R/W R/W R/W R/W
Reset 0 0 0 0 0 0 0 0
UM005004-0918
Z8018x
162
Bit
7– 6 TIF1–0 R TIF1: Timer Interrupt Flag — When TMDR1

decrements to 0, TIF1 is set to 1. This generates an
interrupt request if enabled by TIE1 = 1. TIF1 is reset to 0
when TCR is read and the higher or lower byte of
TMDR1 is read. During RESET, TIF1 is cleared to 0.
When TMDR0 decrements to 0, TIF0 is set to 1. This
generates an interrupt request if enabled by TIE0 = 1.
TIF0 is reset to 0 when TCR is read and the higher or
lower byte of TMDR0 is read. During RESET, TIF0 is
cleared to 0.
5–4 TIE1–0 R/W Timer Interrupt Enable — When TIE1 is set to 1, TIF1
= 1 generates a CPU interrupt request. When TIE1 is reset
to 0, the interrupt request is inhibited. During RESET,
TIE1 is cleared to 0.
When TIE0 is set to 1, TIF0 = 1 generates a CPU interrupt
request. When TIE0 is reset to 0, the interrupt request is
inhibited. During RESET, TIE0 is cleared to 0.
3–2 TOC1–0 R/W Timer Output Control — TOC1, and TOC0 control the
output of PRT1 using the multiplexed A18/TOUT pin as
shown in Table 23. During RESET, TOC1 and TOC0 are
cleared to 0. This selects the address function for A18/
TOUT. By programming TOC1 and TOC0 the A18/
TOUT pin can be forced HIGH, LOW, or toggled when
TMDR1 decrements to 0. Reference Table 23.
1– 0 TDE1–0 R/W Timer Down Count Enable — TDE1 and TDE0 enable
and disable down counting for TMDR1 and TMDR0
respectively. When TDEn (n = 0, 1) is set to 1, down
counting is executed for TMDRn. When TDEn is reset to
0, down counting is stopped and TMDRn is freely read or
written. TDE1 and TDE0 are cleared to 0 during RESET
and TMDRn does not decrement until TDEn is set to 1.
UM005004-0918
Z8018x
163
Table 23. Timer Output Control
TOC1 TOC0 OUTPUT
0 0 Inhibited (A18/TOUT pin is selected as an

address output function.)
0 1 Toggled
1 0 0 A18/TOUT pin is selected as a
PRT1 output function!
1 1 1
Figure 64 illustrates timer initialization, count down, and reload timing.

Figure 65 depicts timer output (A18/TOUT) timing.
Timer Data Register 0 < + < 20

write (0004H)
RESET 20 φ 20 φ 20 φ 20 φ 20 φ 20 φ 20 φ 20 φ 20φ
Timer Data FFFFH 0004H 0003H 0002H 0001H 0000H 0003H 0002H 0001H 0000H 0003H
Register
Timer Reload Register Write (0003H) Reload Reload
Timer Reload FFFFH 0003H

Register
Write 1 to TDE
TDE Flag
TIF Flag
Timer Data Register Read
Timer Control
Register Read
Figure 64. Timer Initialization, Count Down, and Reload Timing Diagram
UM005004-0918
Z8018x
164
Timer Data Timer Data

Reg. = 0001H Reg. = 0000H
Phi
TOUT
Figure 65. Timer Output Timing Diagram
PRT Interrupts
The PRT interrupt request circuit is illustrated in Figure 66.
IEF1
TIF1 PRT1 Interrupt

Request
TIE1
TIF0 PRT0 Interrupt

Request
TIE0
Figure 66. PRT Interrupt Request Generation
PRT and RESET

During RESET, the bits in TCR are initialized as defined in the TCR
register description. Down counting is stopped and the TMDR and RLDR
registers are initialized to FFFFH. The A18/TOUT pin reverts to the
address output function.
UM005004-0918
Z8018x
165
PRT Operation Notes
• TMDR data is accurately read without stopping down counting by

reading the lower (TMDRnL*) and higher (TMDRnH*) bytes in that
order. Also, TMDR is read or written by stopping the down
counting.1
Take care to ensure that a timer reload does not occur during or
between lower (RLDRnL*) and higher (RLDRnH*) byte writes. This
may be guaranteed by system design/timing or by stopping down
counting (with TMDR containing a non-zero value) during the RLDR
updating. Similarly, in applications where TMDR is written at each
TMDR overflow, the system/software design must guarantee that
RLDR can be updated before the next overflow occurs. Otherwise,
time base inaccuracy occurs.
• During RESET, the multiplexed A18/TOUT pin reverts to the address

output. By reprogramming the TOC1 and TOC0 bits, the timer output
function for PRT channel 1 is selected. The following paragraph
describes the initial state of the TOUT pin after TOC1 and TOC0 are
programmed to select the PRT channel 1 timer output function.
PRT (channel 1) has not counted down to 0.
If the PRT has not counted down to 0 (timed out), the initial state of
TOUT depends on the programmed value in TOC1 and TOC0.
Secondary Bus Interface
E clock Output Timing

The Z8X180 also has a secondary bus interface that allows it to easily
interface with other peripheral families.
1. *n = 0, 1
UM005004-0918
Z8018x
166
These devices require connection with the Z8X180 synchronous E clock

output. The speed (access time) required for the peripheral devices are
determined by the Z8X180 clock rate. Table 24, and Figure 67 through
Figure 70 define E clock output timing.
Wait States are inserted in Op Code fetch, memory read/write, and I/O
read/write cycles which extend the duration of E clock output High.
During I/O read/write cycles with no Wait States (only occurs during on-
chip I/O register accesses), E does not go High.
Table 24. E Clock Timing in Each Condition
Condition Duration of E Clock Output High
Op Code Fetch Cycle T2 rise - T3 fall (1.5 Phi + nw x Phi)

Memory Read/Write Cycle
I/O read Cycle 1st Tw rise - T3 fall (0.5Phi + nw x Phi)
I/O Write Cycle 1st Tw rise - T3 rise Inw x Phi)
NMI Acknowledge 1st MC T2 rise - T3 fall (1.5 Phi)
INT0 Acknowledge 1st MC 1st Tw rise - T3 fall (0.50 + nw x Phi)
BUS RELEASE mode
SLEEP mode Phi fall - Phi fall (2 Phi or 1 Phi)
SYSTEM STOP mode
Note: nw = the number of Wait States; MC: Machine Cycle
UM005004-0918
Z8018x
167
NMI
Op Code Memory Read/ Acknowledge INT0 Acknowledge
Fetch Cycle Write Cycle I/O Read Cycle I/O Write Cycle 1st MC 1st MC
T1 T2 T3 T1 T2 T3 T1 T2 Tw T3 T1 T2 T3 T1 T2 T3 T1 T2 Tw*Tw* T3
Phi
E
M1
MREQ
IORQ
NOTE : MC = Machine Cycle * Two wait states are automatically inserted
Figure 67. E Clock Timing Diagram (During Read/Write Cycle and

Interrupt Acknowledge Cycle
Last BUS RELEASE mode

state TX TX TX TX
Phi
BUSREQ
BUSACK
E
E
E
E
Figure 68. E Clock Timing in BUS RELEASE Mode
UM005004-0918
Z8018x
168
SLP
Instruction
2nd Op Code Op Code
Fetch Cycle SLEEP mode or SYSTEM STOP mode Fetch Cycle
T1 T2 T3 T1 T2 Ts Ts Ts Ts T1 T2
Phi
D0– D7
76H
INT, NMI
E
E
Figure 69. E Clock Timing in SLEEP Mode and SYSTEM STOP Mode
On-Chip Clock Generator

The Z8X180 contains a crystal oscillator and system clock generator. A
crystal can be directly connected or an external clock input can be
provided. In either case, the system clock is equal to one-half the input
clock. For example, a crystal or external clock input of 8 MHz
corresponds with a system clock rate of 4 MHz.
Z8S180 and Z8L180-class processors also have the ability to run at X1
and X2 input clock.
Table 25 describes the AT cut crystal characteristics (Co, Rs) and the load
capacitance (CL1, CL2) required for various frequencies of Z8X180
operation.
UM005004-0918
Z8018x
169
Table 25. Z8X180 Operating Frequencies
Clock
Frequency
Item 4MHz 4MHz < f ≤ 12MHz 12MHz < f ≤ 33MHz
Co < 7 pF < 7 pF < 7 pF

Rs <60Ω <60Ω <60Ω
CL1, CL2 10 to 22 pF ± 10% 10 to 22 pF ± 10% 10 to 22 pF ± 10%
If an external clock input is used instead of a crystal, the waveform (twice

the clock rate) must exhibit a 50% ± 10% duty cycle.
Note: The minimum clock input High voltage level is VCC –0.6V. The
external clock input is connected to the EXTAL pin, while the
XTAL pin is left open. Figure 70 depicts the external clock
interface.
EXTAL 3 External Clock Input
2
XTAL Open
Figure 70. External Clock Interface
Figure 71 illustrates the Z8X180 clock generator circuit while Figures 72

and 72 specify circuit board design rules.
UM005004-0918
Z8018x
170
CL XTAL
2 64
CL EXTAL
3
Z8X180
Note: Pin numbers are valid only for DIP configuration
Figure 71. Clock Generator Circuit
Must be avoided
A B A, B Signal
Signal C
CL
2
CL
3
Z8X180
Figure 72. Circuit Board Design Rules
UM005004-0918
Z8018x
171
20 mm max Signal line layout must

avoid shaded areas
Crystal GND
20 mm max
CL CL
1
64
2 Phi
3
Z8X180
Note: Pin mumbers valid only

for DIP configuration
Top View
Figure 73. Example of Board Design
Circuit Board design should observe the following parameters.

• Locate the crystal and load capacitors as close to the IC as physically
possible to reduce noise.
• Signal lines must not run parallel to the clock oscillator inputs. In
particular, the clock input circuitry and the system clock output (pin 64)
must be separated as much as possible.
• VCC power lines must be separated from the clock oscillator input
circuitry.
• Resistivity between XTAL or EXTAL and the other pins must be
greater than 10M ohms.
Signal line layout must avoid areas marked with the shaded area of Figure
73.
UM005004-0918
Z8018x
172
Miscellaneous
Free Running Counter (I/O Address = 18H)
If data is written into the free running counter, the interval of DRAM
refresh cycle and baud rates for the ASCI and CSI/O are not guaranteed.
In IOSTOP mode, the free running counter continues counting down. It is
initialized to FFH during RESET.
Free Running counter (FRC: 18H)

Bit 7 6 5 4 3 2 1 0
Bit/Field Counting Data
R/W R
Reset ?
UM005004-0918
Z8018x
173
Software Architecture
INSTRUCTION SET
The Z80180 is object code-compatible with the Z80 CPU. Refer to the
Z80 CPU Technical Manual or the Z80 Assembly Language
Programming Manual for further details.
Table 26. Instruction Set Summary
New Instructions Operation

SLP Enter SLEEP mode
MLT 8-bit multiply with 16-bit result
INO g, (m) Input contents of immediate I/O address
OUT0 (m), g Output register contents to immediate I/O address
OTIM Block output - increment
OTIMR Block output - increment and repeat
OTDM Block output - decrement
OTDMR Block output - decrement and repeat
TSTIO m Non-destructive AND, I/O port, and accumulator
TST g Non-destructive AND, register, and accumulator
TST m Non-destructive AND, immediate data, and accumulator
TST (HL) Non-destructive AND, memory data, and accumulator
SLP - Sleep
The SLP instruction causes the Z80180 to enter the SLEEP low power
consumption mode. See page 32 for a complete description of the SLEEP
state.
UM005004-0918
Z8018x
174
MLT- Multiply
The MLT performs unsigned multiplication on two 8-bit numbers yielding a
16-bit result. MLT may specify BC, DE, HL, or SP registers. The 8-bit
operands are loaded into each half of the 16-bit register and the 16-bit result
is returned in that register.
OTIM, OTIMR, OTDM, OTDMR - Block I/O

The contents of memory pointed to by HL is output to the I/O address in (C).
The memory address (HL) and I/O address (C) are incremented in OTIM
and OTIMR and decremented in OTDM and OTDMR, respectively. The B
register is decremented. The OTIMR and OTDMR variants repeat the above
sequence until register B is decremented to 0. Since the I/O address (C) is
automatically incremented or decremented, these instructions are useful for
block I/O (such as Z80180 on-chip I/O) initialization. When I/O is accessed,
00H is output in high-order bits of address automatically.
TSTIO m - Test I/O Port

The contents of the I/O port addressed by C are ANDed with immediately
specified 8-bit data and the status flags are updated. The I/O port contents
are not written (non-destructive AND). When I/O is accessed, 00H is
output in higher bits of address automatically.
TST g - Test Register

Perform an AND instruction on the contents of the specified register with
the accumulator (A) and the status flags are updated. The accumulator
and specified register are not changed (non-destructive AND).
TST m - Test Immediate

Perform an AND instruction on the contents of the immediately specified
8-bit data with the accumulator (A) and the status flags are updated. The
accumulator is not changed (non-destructive AND).
UM005004-0918
Z8018x
175
TST (HL) - Test Memory

The contents of memory pointed to by HL are ANDed with the accumulator
(A) and the status flags are updated. The memory contents and accumulator
are not changed (non-destructive AND).
INO g, (m) - Input, Immediate I/O address

The contents of immediately specified 8-bit I/O address are input into the
specified register. When I/O is accessed, 00H is output in high-order bits
of the address automatically.
OUTO (m), g - Output, Immediate I/O address

The contents of the specified register are output to the immediately
specified 8-bit I/O address. When I/O is accessed, 00H is output in high-
order bits of the address automatically.
CPU REGISTERS
The Z80180 CPU registers consist of Register Set GR, Register Set GR'
and Special Registers.
The Register Set GR consists of 8-bit Accumulator (A), 8-bit Flag Register
(F), and three General Purpose Registers (BC, DE, and HL) which may be
treated as 16-bit registers (BC, DE, and HL) or as individual 8-bit registers
(B, C, D, E, H, and L) depending on the instruction to be executed. The
Register Set GR' is alternate register set of Register Set GR and also contains
Accumulator (A'), Flag Register (F') and three General Purpose Registers
(BC', DE', and HL'). While the alternate Register Set GR' contents are not
directly accessible, the contents can be programmably exchanged at high
speed with those of Register Set GR.
The Special Registers consist of 8-bit Interrupt Vector Register (I), 8-bit R
Counter (R), two 16-bit Index Registers (IX and IY), 16-bit Stack Pointer
(SP), and 16-bit Program Counter (PC)
UM005004-0918
Z8018x
176
Figure 74 depicts CPU register configurations.
Register Set GR
Accumulator A Flag Register F
B Register C Register
General
D Register E Register Purpose
Registers
H Register L Register
Register Set GR'

Accumulator A' Flag Register F'
B' Register C' Register

General
D' Register E' Register Purpose
Registers
H' Register L' Register
Special Register
Interrupt R Counter
Vector Register
I R
Index Register IX
Index Register IY
Stack Pointer SP
Program Counter PC
Figure 74. CPU Register Configurations
Accumulator (A, A')

The Accumulator (A) is the primary register used for many arithmetic,
logical, and I/O instructions.
UM005004-0918
Z8018x
177
Flag Registers (F, F')

The flag registers store status bits (described in the next section) resulting
from executed instructions.
General Purpose Registers (BC, BC', DE, DE', HL, HL')

The General Purpose Registers are used for both address and data
operation. Depending on the instruction, each half (8 bits) of these
registers (B, C, D, E, H, and I) may also be used.

For interrupts that require a vector table address to be calculated (INT0
Mode 2, INT1, INT2, and internal interrupts), the Interrupt Vector
Register (I) provides the most significant byte of the vector table address.
I is cleared to 00H during reset.
R Counter (R)
The least significant seven bits of the R counter (R) count the number of
instructions executed by the Z80180. R increments for each CPU Op Code
fetch cycle (each M1 cycle). R is cleared to 00H during reset.
Index Registers (IX, and IY)

The Index Registers are used for both address and data operations. For
addressing, the contents of a displacement specified in the instruction are
added to or subtracted from the Index Register to determine an effective
operand address.
UM005004-0918
Z8018x
178
Stack Pointer (SP)

The Stack Pointer (SP) contains the memory address based LIFO stack.
SP is cleared to 0000H during reset.
Program Counter (PC)

The Program Counter (PC) contains the address of the instruction to be
executed and is automatically updated after each instruction fetch. PC is
cleared to 0000H during reset.
Flag Register (F)

The Flag Register stores the logical state reflecting the results of instruction
execution. The contents of the Flag Register are used to control program
flow and instruction operation.
Flag Register
Bit 7 6 5 4 3 2 1 0
Bit/Field S Z Not Used H Not Used P/V N C
R/W R/W R/W ? R/W ? R/W R/W R/W
Reset 0 0 ? 0 ? 0 0 0
Bit
7 S R/W 0 Sign. S stores the state of the most significant bit

(bit 7) of the result. This is useful for operations with
signed numbers in which values with bit 7 = 1 are
interpreted as negative.
UM005004-0918
Z8018x
179
Bit
6 Z R/W 0 Zero.
Z is set to 1 when instruction execution produces 0 result.
Otherwise, Z is reset to 0.
5 Not Used ? ? Not used
4 H R/W 0 Half Carry.
H is used by the DAA (Decimal Adjust Accumulator)
instruction to reflect borrow or carry from the least
significant 4 bits and thereby adjust the results of BCD
addition and subtraction.
3 Not Used ? ? Not used.
2 P/V R/W 0 P/V: Parity/Overflow.
P/V serves a dual purpose. For logical operations P/V is
set to 1 if the number of 1 bit in the result is even and P/V
is reset to 0 if the number of 1 in the result is odd. For two
complement arithmetic, P/V is set to 1 if the operation
produces a result which is outside the allowable range
(+ 127 to -128 for 8-bit operations, + 32767 to - 32768 for
16-bit operations).
1 N R/W 0 Negative.
N is set to 1 if the last arithmetic instruction was a subtract
operation (SUB, DEC, CP, etc.) and N is reset to 0 if the
last arithmetic instruction was an addition operation (ADD,
INC, etc.).
0 C R/W 0 Carry.
C is set to 1 when a carry (addition) or borrow (subtraction)
from the most significant bit of the result occurs. C is also
affected by Accumulator logic operations such as shifts
and rotates.
UM005004-0918
Z8018x
180
Addressing Modes
The Z80180 instruction set includes eight addressing modes.
• Implied Register
• Register Direct
• Register Indirect
• Indexed
• Extended
• Immediate
• Relative
• IO
Implied Register (IMP)

Certain Op Codes automatically imply register usage, such as the
arithmetic operations that inherently reference the Accumulator, Index
Registers, Stack Pointer, and General Purpose Registers.
Register Direct (REG)

Many Op Codes contain bit fields specifying registers used for operation.
The exact bit field definitions vary depending on instruction depicted in
Figure 75.
UM005004-0918
Z8018x
181
8-bit Register
g or g field ' Register ww field Register
0 B 0 0 B C
0 0 1 C 0 1 D E
0 1 0 D 1 0 H L
0 1 1 E 1 1 S P
1 0 0 H
1 0 1 L xx field Register
1 1 0 — 0 0 B C
1 1 1 A 0 1 D E
1 0 I X
1 1 S P
16-bit Register
zz field Register yy field Register
0 0 B C 0 0 B C
0 1 D E 0 1 D E
1 0 H L 1 0 I Y
1 1 A F 1 1 S P
Suffixed H and L ww,xx,yy,zz (ex. wwH,IXL) indicate upper and
lower 8-bit of the 16-bit register respectively.
Figure 75. Register Direct — Bit Field Definitions
Register Indirect (REG)

The memory operand address is contained in one of the 16-bit General
Purpose Registers (BC, DE, and HL) as illustrated in Figure 76.
B C
D E
H L Operand
Memory
Figure 76. Register Indirect Addressing
UM005004-0918
Z8018x
182
Indexed (INDX)
The memory operand address is calculated using the contents of an Index
Register (IX or IY) and an 8-bit signed displacement specified in the
instruction. Refer to Figure 77
Op Code 1
Op Code 2
displacement (d)
Operand
IX or IY Memory
Figure 77. Indexed Addressing
Extended (EXT)
The memory operand address is specified by two bytes contained in the
instruction, as depicted in Figure 78.
Op Code
n
m
m n Operand
Memory
Figure 78. Extended Addressing
UM005004-0918
Z8018x
183
Immediate (IMMED)
The memory operands are contained within one or two bytes of the
instruction, as depicted in Figure 79.
Op Code Op Code
m 8-bit
operand n 16-bit
m operand
Figure 79. Immediate Addressing
Relative (REL)
Relative addressing mode is only used by the conditional and unconditional
branch instructions (refer to Figure 80). The branch displacement (relative to
the contents of the program counter) is contained in the instruction.
Op Code
displacement (d)
Program Counter (PC)
Figure 80. Relative Addressing
UM005004-0918
Z8018x
184
IO (I/O)
IO addressing mode is used only by I/O instructions. This mode specifies
I/O address (IORQ is 0) and outputs them as follows.
1. An operand is output to A0–A7. The contents of accumulator is
output to A8–A15.
2. The contents of Register B is output to A0–A7. The contents of
Register C is output to A8–A15.
3. An operand is output to A0–A7. 00H is output to A8–A15 (useful for
internal I/O register access)
4. The contents of Register C is output to A0–A7. 00H is output to
A8–A15 (useful for internal I/O register access).
UM005004-0918
Z8018x
185
DC Characteristics
This section describes the DC characteristics of the Z8X180 family and
absolute maximum rating for these products.
ABSOLUTE MAXIMUM RATING
Table 27. Absolute Maximum Rating
Item Symbol Value Unit

Supply Voltage Vcc - 0.3 ∼ + 7.0 V
Input Voltage Vin -0.3 ∼ Vcc+0.3 V
Operating Temperature Topr 0 ∼ 70 °C
Extended Temperature Text -40 ∼ 85 °C
Storage Temperature Tstg - 55 ∼ +150 °C
Permanent IC damage may occur if maximum ratings are exceeded.

Normal operation should be under recommended operating conditions. If
these conditions are exceeded, it could affect reliability of IC.
UM005004-0918
Z8018x
186
Z80180 DC CHARACTERISTICS
VCC = 5V ± 10%, VSS = OV, Ta = 0° to +70°C, unless otherwise noted.)
Table 28. Z80180 DC Characteristics
Symbol Item Condition Minimum Typical Maximum Unit
VIH1 Input High Voltage VCC –0.6 – VCC +0.3 V

RESET, EXTAL NMI
VIH2 Input High Voltage 2.0 VCC +0.3 V
except RESET, EXTAL
NMI
VIL1 Input Low Voltage –0.3 0.6 V
RESET, EXTAL NMI
except RESET, EXTAL Standard
NMI 7 TLVIL
VOH Output High Voltage IOH = –200 μA 2.4 – – V
all outputs IOH = –20 μA VCC –1.2 – – V
VOL Output Low Voltage IOL = 2.2 mA – – 0.45 V
all outputs
IIL Input Leakage Current VIN = 0.5~ – – 1.0 μA
all inputs except XTAL, VCC –0.5
EXTAL
ITL Three-State Leakage – – 1.0 μA
Current
ICC Power Dissipation* f = 6 MHz – 15 40 mA
(Normal Operation) f = 8 MHz – 20 50 mA
f = 33 MHz – 25 60 mA
UM005004-0918
Z8018x
187
Table 28. Z80180 DC Characteristics (Continued)
Power Dissipation* f = 6 MHz – 3.8 12.5 mA

(SYSTEM STOP mode) f = 8 MHz – 5 15.0 mA
f = 33 MHz – 6.3 17.5 mA
CP Pin Capacitance VIN = 0V, f = 1MHz – – 12 pF
TA = 25°C
Notes: * VIN min = VCC –1.0V. VIL max = 0.8V (All output terminals are a no load.)
VCC = 5.0V
Z8S180 DC CHARACTERISTICS
VCC = 5V ± 10%, VSS = OV, Ta = 0° to +70°C, unless otherwise noted.
Table 29. Z8S180 DC Characteristics

RESET, EXTAL NMI
except RESET, EXTAL
NMI
VIH3 Input High Voltage 2.4 VDD + 0.3 V
CKS, CKA0, CKA1
RESET, EXTAL NMI
except RESET, EXTAL
NMI
UM005004-0918
Z8018x
188
Table 29. Z8S180 DC Characteristics (Continued)
VOH1 Output High Voltage IOH = –200 μA 2.4 – – V

All outputs IOH = –20 μA VCC –1.2 – – V
VOH2 Output High Voltage IOH = –200 μA VCC –0.6
Output High Phi
VOL1 Output Low Voltage IOL = 2.2 mA – – 0.45 V
All outputs
VOL2 Output Low Voltage IOL = 2.2 mA – – 0.45 V
Output Low Phi
IIL Input Leakage Current VIN = 0.5 ~ VCC –0.5 – – 1.0 μA
all inputs except XTAL,
ETAL
ITL Three-State Leakage VIN = 0.5 ~ VCC –0.5 – – 1.0 μA
Current
ICC Power Dissipation* f = 10 MHz – 15 – mA
(Normal Operation) f = 20 MHz 30 50
f = 33 MHz 60 100
Power Dissipation* f = 10 MHz – 1.5 – mA
(SYSTEM STOP f = 20 MHz 3 6
Mode) f = 33 MHz 5 9
Power Dissipation* f = 20 MHz – 4 10 mA
(IDLE Mode) f = 33 MHz
Power Dissipation* External Oscillator, – 5 10 μA
(STANDBY Mode) Internal Clock Stops
CP Pin Capacitance VIN = 0V, – – 12 pF
f = 1MHz
TA = 25°C
VCC = 5.0V
UM005004-0918
Z8018x
189
Z8L180 DC CHARACTERISTICS
VCC = 3.3V ± 10%, VSS = OV, Ta = 0° to +70°C, unless otherwise noted.)
Table 30. Z8L180 DC Characteristics

RESET, EXTAL NMI
except RESET, EXTAL
NMI
RESET, EXTAL NMI
except RESET, EXTAL
NMI
VOH1 Output High Voltage IOH = –200 μA 2.4 V
all outputs
VOH2 Output High Voltage IOH = –200 μA VCC –0.6 V
Output High Phi
VOL Output Low Voltage IOL = 4 mA – – 0.4 V
all outputs
VOL2 Output Low Voltage IOL = 4 mA – – 0.4 V
Output Low Phi
IIL Input Leakage Current VIN = 0.5 ~ VCC –0.5 – – 1.0 μA
all inputs except XTAL,
EXTAL
ITL Three-State Leakage VIN = 0.5 ~ VCC –0.5 – – 1.0 μA
Current
UM005004-0918
Z8018x
190
Table 30. Z8L180 DC Characteristics (Continued)
ICC Power Dissipation* f = 20 MHz 20 100 mA

(Normal Operation)
Power Dissipation* f = 20 MHz 2 10 mA
(SYSTEM STOP
Mode)
Power Dissipation* f = 20 MHz 3 10 mA
(IDLE Mode)
Power Dissipation* External Oscillator, 4 10 μA
(STANDBY Mode) Internal Clock Stops
CP Pin Capacitance VIN = 0V, – – 12 pF
f = 1MHz
TA = 25°C
VCC = 3.3V
UM005004-0918
Z8018x
191
Z8L180
Typical ICCA at 4 MHz
5
ICC Active (mA.)
2.7 3.0 3.3

VDD (Volts)
Z8S180
Typical ICCA at 20 MHz
50
ICC Active (mA.)
40
30
20
10
2 3 4 5
VDD (Volts)
UM005004-0918
Z8018x
192
UM005004-0918
Z8018x
193
AC Characteristics
This section describes the AC characteristics of the Z8X180 family and
absolute maximum rating for these products.
AC CHARACTERISTICS—Z8S180
Table 31. Z8S180 AC Characteristics VDD = 5V ±10% or VDD = 3.3V

±10%; 33-MHz Characteristics Apply Only to 5V Operation
Z8S180—20 Z8S180—33
MHz MHz
No. Symbol Item Min Max Min Max Unit
1 tCYC Clock Cycle Time 50 DC 30 DC ns
2 tCHW Clock “H” Pulse Width 15 — 10 — ns
3 tCLW Clock “L” Pulse Width 15 — 10 — ns
4 tCF Clock Fall Time — 10 — 5 ns
5 tCR Clock Rise Time — 10 — 5 ns
6 tAD PHI Rise to Address Valid Delay — 30 — 15 ns
7 tAS Address Valid to MREQ Fall or 5 — 5 — ns
IORQ Fall)
8 tMED1 PHI Fall to MREQ Fall Delay — 25 — 15 ns
9 tRDD1 PHI Fall to RD Fall Delay IOC = 1 — 25 — 15 ns
PHI Rise to RD Rise Delay IOC = — 25 — 15
0
10 tM1D1 PHI Rise to M1 Fall Delay — 35 — 15 ns
11 tAH Address Hold Time from 5 — 5 — ns
MREQ, IOREQ, RD, WR High
12 tMED2 PHI Fall to MREQ Rise Delay — 25 — 15 ns
UM005004-0918
Z8018x
194
Table 31. Z8S180 AC Characteristics (Continued) VDD = 5V ±10% or

VDD = 3.3V ±10%; 33-MHz Characteristics Apply Only to 5V
Z8S180—20 Z8S180—33
MHz MHz
13 tRDD2 PHI Fall to RD Rise Delay — 25 — 15 ns
14 tM1D2 PHI Rise to M1 Rise Delay — 40 — 15 ns
15 tDRS Data Read Set-up Time 10 — 5 — ns
16 tDRH Data Read Hold Time 0 — 0 — ns
17 tSTD1 PHI Fall to ST Fall Delay — 30 — 15 ns
18 tSTD2 PHI Fall to ST Rise Delay — 30 — 15 ns
19 tWS WAIT Set-up Time to PHI Fall 15 — 10 — ns
20 tWH WAIT Hold Time from PHI Fall 10 — 5 — ns
21 tWDZ PHI Rise to Data Float Delay — 35 — 20 ns
22 tWRD1 PHI Rise to WR Fall Delay — 25 — 15 ns
23 tWDD PHI Fall to Write Data Delay Time — 25 — 15 ns
24 tWDS Write Data Set-up Time to WR Fall 10 — 10 — ns
25 tWRD2 PHI Fall to WR Rise Delay — 25 — 15 ns
26 tWRP WR Pulse Width (Memory Write 80 — 45 — ns
Cycle)
26a WR Pulse Width (I/O Write Cycle) 150 — 70 — ns
27 tWDH Write Data Hold Time from WR Rise 10 — 5 — ns
28 tIOD1 PHI Fall to IORQ Fall Delay IOC — 25 — 15 ns
=1
PHI Rise to IORQ Fall Delay IOC — 25 — 15
=0
29 tIOD2 PHI Fall to IORQ Rise Delay — 25 — 15 ns
30 tIOD3 M1 Fall to IORQ Fall Delay 125 — 80 — ns
31 tINTS INT Set-up Time to PHI Fall 20 — 15 — ns
32 tINTH INT Hold Time from PHI Fall 10 — 10 — ns
UM005004-0918
Z8018x
195

Z8S180—20 Z8S180—33
MHz MHz
33 tNMIW NMI Pulse Width 35 — 25 — ns
34 tBRS BUSREQ Set-up Time to PHI Fall 10 — 10 — ns
35 tBRH BUSREQ Hold Time from PHI Fall 10 — 10 ns
36 tBAD1 PHI Rise to BUSACK Fall Delay — 25 — 15 ns
37 tBAD2 PHI Fall to BUSACK Rise Delay — 25 — 15 ns
38 tBZD PHI Rise to Bus Floating Delay Time — 40 — 30 ns
39 tMEWH MREQ Pulse Width (High) 35 — 25 — ns
40 tMEWL MREQ Pulse Width (Low) 35 — 25 — ns
41 tRFD1 PHI Rise to RFSH Fall Delay — 20 — 15 ns
42 tRFD2 PHI Rise to RFSH Rise Delay — 20 — 15 ns
43 tHAD1 PHI Rise to HALT Fall Delay — 15 — 15 ns
44 tHAD2 PHI Rise to HALT Rise Delay — 15 — 15 ns
45 tDRQS DREQ1 Set-up Time to PHI Rise 20 — 15 — ns
46 tDRQH DREQ1 Hold Time from PHI Rise 20 — 15 — ns
47 tTED1 PHI Fall to TENDi Fall Delay — 25 — 15 ns
48 tTED2 PHI Fall to TENDi Rise Delay — 25 — 15 ns
49 tED1 PHI Rise to E Rise Delay — 30 — 15 ns
50 tED2 PHI Fall or Rise to E Fall Delay — 30 — 15 ns
51 PWEH E Pulse Width (High) 25 — 20 — ns
52 PWEL E Pulse Width (Low) 50 — 40 — ns
53 tEr Enable Rise Time — 10 — 10 ns
54 tEf Enable Fall Time — 10 — 10 ns
55 tTOD PHI Fall to Timer Output Delay — 75 — 50 ns
UM005004-0918
Z8018x
196

Z8S180—20 Z8S180—33
MHz MHz
56 tSTDI CSI/O Transmit Data Delay Time — 2 — 2 tcyc
(Internal Clock Operation)
57 tSTDE CSI/O Transmit Data Delay Time — 7.5 tCY — 75 tCYC ns
(External Clock Operation) C +60
+75
58 tSRSI CSI/O Receive Data Set-up Time 1 — 1 — tcyc
59 tSRHI CSI/O Receive Data Hold Time 1 — 1 — tcyc
60 tSRSE CSI/O Receive Data Set-up Time 1 — 1 — tcyc
(External Clock Operation)
61 tSRHE CSI/O Receive Data Hold Time 1 — 1 — tcyc
(External Clock Operation)
62 tRES RESET Set-up Time to PHI Fall 40 — 25 — ns
63 tREH RESET Hold Time from PHI Fall 25 — 15 — ns
64 tOSC Oscillator Stabilization Time — 20 — 20 ns
65 tEXR External Clock Rise Time (EXTAL) — 5 — 5 ns
66 tEXF External Clock Fall Time (EXTAL) — 5 — 5 ns
67 tRR RESET Rise Time — 50 — 50 ms
68 tRF RESET Fall Time — 50 — 50 ms
69 tIR Input Rise Time (except EXTAL, — 50 — 50 ns
RESET)
70 tIF Input Fall Time (except EXTAL, — 50 — 50 ns
RESET)
UM005004-0918
Z8018x
197
Timing Diagrams
I/O Write Cycle*
Opcode Fetch Cycle I/O Read Cycle*
T1 T2 TW T3 T1 T2 TW T3 T1
2 3
4 5
PHI
1
6
ADDRESS
20 20
19 19
WAIT
7 12 11
MREQ
7
8 29 11
IORQ
11
28 13
13
RD
9
9 11
22 25
WR
26
14
M1
10 18
ST
17 21
15
15 16
16
Data IN
23 24 27
Data OUT
62
63 62
RESET 63
68 67 67 68
Figure 81. AC Timing Diagram 1

UM005004-0918
Z8018x
198
Memory Read/Write Cycle timing is the sam as I/O Read/Write Cycle

except there are no automatica Wait States (TW), and MREQ is active
instead of IORQ.
PHI
32
31
INT0,1,2
33
NMI
M1
30
10
28 14
IORQ
15 29
16
Data IN
39
MREQ 40
41 42
RFSH
35 34
34 35
BUSREQ
36 37
BUSACK
38 38
A19–0, D7–0
MREQ, RD
WR, IORQ Output Buffer Off
43 44
HALT
Figure 82. AC Timing Diagram 2
UM005004-0918
Z8018x
199
I/O Read Cycle I/O Write Cycle
T1 T2 Tw T3 T1 T2 Tw T3
PHI
ADDRESS
28 29 28 29
IORQ
9 13
RD
22 25
WR
I/O Read Cycle

CPU Timing (IOC = 0)
I/O Write Cycle
Figure 83. CPU Timing (IOC = 0) (I/O Read Cycle, I/O Write Cycle)
UM005004-0918
Z8018x
200
CPU or DMA Read/Write Cycle (Only DMA Write Cycle for TENDi)
T1 T2 TW T3 T1
PHI
46 *
45
DREQ1
(level sense)
45 46 **
DREQ1
(edge sense)
CPU Cycle
Starts
47 18
48
TENDi DMA Cycle 17

Starts
ST
Notes:
*TDRQS and TDRQH are specified for the rising edge of the clock followed by T3.
**TDRQS and TDRQH are specified for the rising edge of the clock.
Figure 84. DMA Control Signals
UM005004-0918
Z8018x
201
T1 T2 TW TW T3
PHI
~
~
49 50
~
~
E
(Memory Read/Write)
49 50
~
~
E
(I/O Read)
49 50
E ~
~
(I/O Write) 15 16
~
~
D0–D7
~
~
Figure 85. E Clock Timing (Memory R/W Cycle) (I/O R/W Cycle)
PHI
E 49 50
BUS RELEASE mode
SLEEP mode
SYSTEM STOP mode
Figure 86. E Clock Timing (BUS RELEASE Mode, SLEEP Mode, and
SYSTEM STOP Mode
UM005004-0918
Z8018x
202
T2 TW T3 T1 T2
PHI
E 50 52 49
Example 50
I/O Read 49 54 53
→ Opcode Fetch 51
E
(I/O Write) 53 54
Figure 87. E Clock Timing (Minimum Timing Example of PWEL and

PWEH)
PHI
Timer Data
Reg. = 0000H
A18/TOUT
55
Figure 88. Timer Output Timing
UM005004-0918
Z8018x
203
SLP Instruction Fetch Next Opcode Fetch

T3 T1 T2 TS TS T1 T2
~
~
PHI
31
32
INTi
~
~
NMI ~~
33
~
~
A19–A0
~
~
~~
MREQ, M1
43
RD 44
HALT
~
~
Figure 89. SLP Execution Cycle Timing Diagram
UM005004-0918
Z8018x
204
CSI/O Clock
56 56
Transmit Data
(Internal Clock)
57 57
Transmit Data
(External Clock)
11tcyc 11tcyc
58 59 58 59
Receive Data
(Internal Clock)
11.5tcyc 16.5tcyc 11.5tcyc 16.5tcyc
Receive Data
(External Clock)
60 61 60 61
Figure 90. CSI/O Receive/Transmit Timing Diagram
65 66
EXTAL VIL1 VIH1 VIH1 VIL1
Figure 91. External Clock Rise Time and Fall Time
70 69
Figure 92. Input Rise Time and Fall Time (Except EXTAL, RESET)
UM005004-0918
Z8018x
205
STANDARD TEST CONDITIONS

The previous DC Characteristics and Capacitance sections apply to the
following standard test conditions, unless otherwise noted. All voltages
are referenced to GND (0V). Positive current flows in to the referenced
pin.
All AC parameters assume a load capacitance of 100 pF. Add 10 ns delay
for each 50 pF increase in load up to a maximum of 200 pF for the data
bus and 100 pF for the address and control lines. AC timing
measurements are referenced to 1.5 volts (except for CLOCK, which is
referenced to the 10% and 90% points).
The Ordering Information section lists temperature ranges and product
numbers. Package drawings are in the Package Information section. Refer
to the Literature List for additional documentation.
+5V
2.1KΩ
From Output
Under Test
100 pf v 200
μA
Figure 93. Test Setup
UM005004-0918
Z8018x
206
UM005004-0918
Z8018x
207
Instruction Set
This section explains the symbols in the instruction set.
REGISTER
g, g', ww, xx, yy, and zz specify a register to be used. g and g' specify an
8-bit register. ww, xx, yy, and zz specify a pair of 8-bit registers. Table 32
describes the correspondence between symbols and registers.
Table 32. Register Values
g,g' Reg. ww Reg. xx Reg. yy Reg. zz Reg.

000 B 00 BC 00 BC 00 BC 00 BC
001 C 01 DE 01 DE 01 DE 01 DE
010 D 10 HL 10 IX 10 IY 10 HL
011 E 11 SP 11 SP 11 SP 11 AF
100 H
101 L
111 A
Note: Suffixed H and L to ww, xx, yy, zz (ex. wwH, IXL) indicate upper and lower
8-bit of the 16-bit register respectively.
BIT
b specifies a bit to be manipulated in the bit manipulation instruction.
Table 33 indicates the correspondence between b and bits.
UM005004-0918
Z8018x
208
Table 33. Bit Values
b Bit
000 0
001 1
010 2
011 3
100 4
101 5
110 6
111 7
CONDITION
f specifies the condition in program control instructions. Table 34
describes the correspondence between f and conditions.
Table 34. Instruction Values
f Condition
000 NZ Nonzero
001 Z Zero
010 NC Non Carry
011 C Carry
100 PO Parity Odd
101 PE Parity Even
110 P Sign Plus
111 M Sign Minus
UM005004-0918
Z8018x
209
RESTART ADDRESS
v specifies a restart address. Table 35 describes the correspondence
between v and restart addresses.
Table 35. Address Values
v Address
000 00H
001 08H
010 l0H
011 18H
100 20H
101 28H
110 30H
111 38H
FLAG
The symbols listed in Table 36 indicate the flag conditions.
Table 36. Flag Conditions

• Not Affected
↑ Affected
x Undefined
S Set to 1
R Reset to 0
P Parity
V Overflow
UM005004-0918
Z8018x
210
MISCELLANEOUS
Table 37 lists the operations mnemonics.
Table 37. Operations Mnemonics
( )M Data in the memory address

( )I Data in the I/O address
m or n 8-bit data
mn 16-bit data
r 8-bit register
R 16-bit register
b.( )M A content of bit b in the memory address
b.gr A content of bit b in the register gr
d or j 8-bit signed displacement
S Source
D Destination
• AND operation
+ OR operation
⊕ EXCLUSIVE OR operation
** Added new instructions to Z80
UM005004-0918
Z8018x
211
DATA MANIPULATION INSTRUCTIONS
Table 38. Arithmetic and Logical Instructions (8-bit)
Flags
Addressing 7 6 4 2 1 0
Operation
Name Mnemonics Op Code Immed Ext Ind Reg RegI Imp Rel Bytes States Operation S Z H P/V N C
ADD ADD A,g 10 000 g S D 1 4 Ar + gr→Ar ↑ ↑ ↑ V R ↑
ADD A, (HL) 10 000 110 S D 1 6 Ar + (HL)M→Ar ↑ ↑ ↑ V R ↑
ADD A, m 11 000 110 S D 2 6 Ar + m→Ar ↑ ↑ ↑ V R ↑
<m>
ADD A,(IX + d) 11 011 101 S D 3 14 Ar + (IX + d)M→Ar ↑ ↑ ↑ V R ↑
10 000 110
<d>
ADD A,(IY + d) 11 111 101 S D 3 14 Ar + (IY + d))M→Ar ↑ ↑ ↑ V R ↑
10 000 I10
<d>
ADC ADC A,g 10 001 g S D 1 4 Ar + gr + c→Ar ↑ ↑ ↑ V R ↑
ADC A,(HL) 10 001 110 S D 1 6 Ar + (HL)M + c→Ar ↑ ↑ ↑ V R ↑
ADC A,m 11 001 110 S D 2 6 Ar + m + c→Ar ↑ ↑ ↑ V R ↑
<m>
ADC A,(IX + d) 11 011 101 S D 3 14 Ar + (lX + d))M + ↑ ↑ ↑ V R ↑

c→Ar
10 001 110
<d>
ADC A,(IY + d) 11 111 101 S D 3 14 Ar + (IY + d))M + ↑ ↑ ↑ V R ↑

c→Ar
10 001 110
<d>
UM005004-0918
Z8018x
212
Table 38. Arithmetic and Logical Instructions (8-bit) (Continued)
Flags
Operation
AND AND g 10 100 g S D 1 4 Ar*gr→Ar ↑ ↑ S P R R
AND (HL) 10 100 110 S D 1 6 Ar*(HL)M→Ar ↑ ↑ S P R R
AND m 11 100 110 S D 2 6 Ar*m→Ar ↑ ↑ S P R R
<m>
AND (IX + d) 11 011 101 S D 3 14 Ar*(1X + d))M→Ar ↑ ↑ S P R R
10 100 110
<d>
AND (IY + d) 11 111 101 S D 3 14 Ar*(1Y + d)v→Ar ↑ ↑ S P R R
10 100 110
<d>
Compare CP g 10 111 g S D 1 4 Ar-gr ↑ ↑ ↑ V S ↑
CP (HL) 10 111 110 S D 1 6 Ar-(HL)M ↑ ↑ ↑ V S ↑
CP m 11 111 110 S D 2 6 Ar-m ↑ ↑ ↑ V S ↑
<m>
CP (IX + d) 11 011 101 S D 3 14 Ar-(IX + d))M ↑ ↑ ↑ V S ↑
10 111 110
<d>
CP (IY + d) 11 111 101 S D 3 14 Ar-(IY + d))M ↑ ↑ ↑ V S ↑
10 111 110
<d>
Compleme CPL 00 101 111 S/D 1 3 Ar→Ar • • S • S •

nt
UM005004-0918
Z8018x
213
Flags
Operation
DEC DEC g 00 g 101 S/D 1 4 gr-1→gr ↑ ↑ ↑ V S •
DEC (HL) 00 110 101 S/D 1 10 (HL)M-1→(HL)M ↑ ↑ ↑ V S •
DEC (IX + d) 11 011 101 S/D 3 18 (IX + d))M-I→ ↑ ↑ ↑ V S •
00 110 101 (IX + d))M
<d>
DEC (IY + d) 11 111 101 S/D 3 18 (IY + d)M-1→ ↑ ↑ ↑ V S •
00 1101 01 (IY + d)M
<d>
INC INC g 00 g 100 S/D 1 4 gr + I→gr ↑ ↑ ↑ V R •
INC (HL) 00 110 100 S/D 1 10 (HL)M + I→(HL)M ↑ ↑ ↑ V R •
INC (IX + d) 11 011 101 S/D 3 18 (IX + d))M + 1→ ↑ ↑ ↑ V R •
00 110 100 (1X + d))M
<d>
INC (IY + d) 11 111 101 S/D 3 18 (IY + d)v + 1→ ↑ ↑ ↑ V R •
00 110 100 (IY + d)v
<d>
MULT MLT ww** 11 101 101 S/D 2 17 wwHr→wwLr→wwI • • • • • •
01 WWI
100
NEGATE NEG 11 101 101 S/D 2 6 0-Ar→Ar ↑ ↑ ↑ Y S ↑
01 000 100
UM005004-0918
Z8018x
214
Flags
Operation
OR OR g 10 110 g S D 1 4 Ar + gr→Ar ↑ ↑ R P R R
OR (HL) 10 110 110 S D 1 6 Ar + (HL)M→Ar ↑ ↑ R P R R
OR m 11 110 110 S D 2 6 Ar + m→Ar ↑ ↑ R P R R
<m>
OR (IX + d) 11 011 101 S D 3 14 Ar + (IX + d)M→Ar ↑ ↑ R P R R
10 110 110
<d>
OR (IY + d) 11 111 101 S D 3 14 Ar + (IY + d)M→Ar ↑ ↑ R P R R
10 110 110
<d>
SUB SUB g 10 010 g S D 1 4 Ar-gr→Ar ↑ ↑ ↑ V S ↑
SUB (HL) 10 010 110 S D 1 6 Ar-(HL)M→Ar ↑ ↑ ↑ V S ↑
SUB m 11 010 110 S D 2 6 Ar-m→Ar ↑ ↑ ↑ V S ↑
<m>
SUB (IX + d) 11 011 101 S D 3 14 Ar-(IX + d)M-c→Ar ↑ ↑ ↑ V S ↑
10 011 110
<d>
SUB (IY + d) 11 111 101 S D 3 14 Ar-(IY + d)M-c→Ar ↑ ↑ ↑ V S ↑
10 010 110
<d>
UM005004-0918
Z8018x
215
Flags
Operation
SUBC SBC A,g 10 011 g S D 1 4 Ar-gr-c→Ar ↑ ↑ ↑ V S ↑
SBC A,(HL) 10 011 110 S D 1 6 Ar-(HL)M-c→Ar ↑ ↑ ↑ V S ↑
SBC A,m 11 011 110 S D 2 6 Ar-m-c→Ar ↑ ↑ ↑ V S ↑
<m>
SBC A,(IX + d) 11 011 101 S D 3 14 Ar-(IX + d)M-c→Ar ↑ ↑ ↑ V S ↑
10 011 110
<d>
SBC A,(IY + d) 11 111 101 S D 3 14 Ar-(IY + d)M-c→Ar ↑ ↑ ↑ V S ↑
10 011 110
<d>
TEST TST g** 11 101 101 S 2 7 Ar•gr ↑ ↑ S P R R
00 g 100
TST {HL)** 11101101 S 2 10 Ar•(HL)M ↑ ↑ S P R R
00 110 100
TST m** 11 101 101 S 3 9 Ar•m ↑ ↑ S P R R
01 100 100
<m>
XOR XOR g 10 101 g S D 1 4 Ar⊕ + gr→Ar ↑ ↑ R P R R
XOR (HL) 10 101 110 S D 1 6 Ar⊕ + (HL)M→Ar ↑ ↑ R P R R
XOR m 11 101 110 S D 2 6 Ar⊕ + m→Ar ↑ ↑ R P R R
<m>
XOR (IX + d) 11 011 101 S D 3 14 Ar⊕ + (IX + d))M→Ar ↑ ↑ R P R R
10 101 110
<d>
UM005004-0918
Z8018x
216
Flags
Operation
XOR (IY + d) 11 111 101 S D 3 14 Ar⊕ + (IY + d))M→Ar ↑ ↑ R P R R
10 101 110
<d>
Table 39. Rotate and Shift Instructions

Flags
Operation State
Name Mnemonics Op Code Immed Ext Ind Reg Regi Imp Rel Bytes s Operation S Z H P/V N C
Rotate RL A 00 010 1111 S/D 1 3 • • R • R ↑

and
RL g 11 001 011 S/D 2 7 ↑ ↑ R P R ↑
Shift
Data 00 010 g
C b7 b0
RL (HL) 11 001 011 S/D 2 13 ↑ ↑ R P R ↑
00 010 110
RL (IX + d) 11 011 101 S/D 4 19 ↑ ↑ R P R ↑
11 001 011
<d>
00 010 110
RL (IY + d) 11 111 101 S/D 4 19 Ar ↑ ↑ R P R ↑
11 001 011 b7 b0
<d>
00 010 110 (HL)M
RLC A 00 000 111 S/D 1 3 b7 b0 • • R • R ↑
RLC g 11 001 011 S/D 2 7 ↑ ↑ R P R ↑
00 000 g
RLC (HL) 11 001 011 S/D 2 13 b7 b0 C ↑ ↑ R P R ↑
00 000 110
UM005004-0918
Z8018x
217
Table 39. Rotate and Shift Instructions (Continued)

Flags
Operation State
RLC (IX + d) 11 011 101 S/D 4 19 ↑ ↑ R P R ↑

11 001 011
<d>
00 000 110
RLC (IY + d) 11 111 101 S/D 4 19 ↑ ↑ R P R ↑
11 001 011
<d>
00 000 110
RLD 11 101 101 S/D 2 16 ↑ ↑ R P R •
01 101 111 C b7 b0
RRA 00 011 111 S/D 1 3 • • R • R ↑
RRg 11 001 011 S/D 2 7 ↑ ↑ R P R ↑
00 011 g
RR (HL) 11 001 011 S/D 2 13 ↑ ↑ R P R ↑
00 011 110
RR (IX + d) 11 011 101 S/D 4 19 ↑ ↑ R P R ↑
11 001 011
<d>
00 011 110
b0 b7 C
RR (IY + d) 11 111 101 S/D 4 19 ↑ ↑ R P R ↑
11 001 011
<d>
00 011 110
RRCA 00 001 111 S/D 1 3 • • R • R ↑
RRC g 11 001 011 S/D 2 7 ↑ ↑ R P R ↑
00 001 g
RRC (HL) 11 001 011 S/D 2 13 ↑ ↑ R P R ↑
00 001 110
RRC (IX + d) 11 011 101 S/D 4 19 ↑ ↑ R P R ↑
11 001 011
<d>
00 001 110
RRC (IY + d) 11 111 101 S/D 4 19 ↑ ↑ R P R ↑
UM005004-0918
Z8018x
218

Flags
Operation State
11 001 011
<d>
00 001 110
RRD 11 101 101 S/D 2 16 ↑ ↑ R P R •
01 100 111 Ar
SLA g 11 001 011 S/D 2 7 b7 b0 ↑ ↑ R P R ↑
00 100 g
(HL)M
SLA (HL) 11 001 011 S/D 2 13 b7 b0 ↑ ↑ R P R ↑
00 100 110
SLA (IX + d) 11 011 101 S/D 4 19 ↑ ↑ R P R ↑
0
11 001 011 C b7 b0
<d>
00 100 110
SLA (IY + d) 11 111 101 S/D 4 19 ↑ ↑ R P R ↑
11 001 011
<d>
00 100 110
SRA g 11 001 011 S/D 2 7 ↑ ↑ R P R ↑
00 101 g
SRA (HL) 11 001 011 S/D 2 13 ↑ ↑ R P R ↑
b7 b0 C
00 101 110
SRA (IX + d) 11 011 101 S/D 4 19 ↑ ↑ R P R ↑
11 001 011
<d>
00 101 110
SRA (IY + d) 11 111 101 S/D 4 19 ↑ ↑ R P R ↑
11 001 011
<d>
00 101 110
SRL g 11 001 011 S/D 2 7 0 ↑ ↑ R P R ↑
00 111 g b7 b0 C
UM005004-0918
Z8018x
219

Flags
Operation State
SRL (HL) 11 001 011 S/D 2 3 ↑ ↑ R P R ↑

00 111 110
SRL (IX + d) 11 011 101 S/D 4 19 ↑ ↑ R P R ↑
11 001 011
<d>
00 111 110
SRL (IY + d) 11 111 101 S/D 4 19 ↑ ↑ R P R ↑
11 001 011
<d>
00 111 110
Bit Set SET b,g 11 001 011 S/D 2 7 1→b•gr • • • • • •
11 b g
SET b,(HL) 11 001 011 S/D 2 13 1→b•(HL)M • • • • • •
11 b 110
SET b,(IX + d) 11 011 101 S/D 4 19 1→b•(IX + d)M • • • • • •
11 001 011
<d>
11 b 110
SET b,(IY + d) 11 111 101 S/D 4 19 l →b•(IY + d)M • • • • • •
11 001 011
<d>
11 b 110
Bit Reset RES b,g 11 001 011 S/D 2 7 0 →b•gr • • • • • •
10 b g
RES b,(HL) 11 001 011 S/D 2 13 0 →6*b•(HL)M • • • • • •
10 b 110
RES b,(IX + d) 11 011 101 S/D 4 19 0 →•b•(IX + d)M • • • • • •
11 001 011
<d>
10 b 110
UM005004-0918
Z8018x
220

Flags
Operation State
Bit Reset RES b,(IY + d) 11 011 101 S/D 4 19 0→b•(IY + d)M • • • • • •

11 001 01l
<d>
10 b 110
Bit Test BIT b, g 11 001 011 S 2 6 b•gr→z X ↑ S X R •
01bg
BIT b,(HL) 11 001 011 S 2 9 b•(HL)M→z X ↑ S X R •
01 b 110
BIT b,(IX + d) 11 011 101 S 4 15 b•(IX + d)M→z X ↑ S X R •
11 001 011
<d>
01 b 110
BIT b,(IY + d) 11 111 101 S 4 15 b•(IY + d)M→z X ↑ S X R •
11 001 011
<d>
01 b 110
UM005004-0918
Z8018x
221
Table 40. Arithmetic Instructions (16-bit)

Flags
Operation
ADD ADD HL,ww 00 ww1 001 S D 1 7 HLR + wwR→HLR • • X • R ↑

ADD IX,xx 11 011 101 S D 2 10 IXR + xxR→*IXR • • X • R ↑
00 xx1 001
ADD IY,yy 11 111 101 S D 2 10 IYR + yyR→IYR • • X • R ↑
00 yy1 001
ADC ADC HL,ww 11 101 101 S D 2 10 HLR + wwR + ↑ ↑ X V R ↑
c→HLR
01 ww1 010
DEC DEC ww 00 ww1 011 S/D 1 4 wwR -1→•wwR • • • • • •
DEC IX 11 011 101 S/D 2 7 1XR -1→IXR • • • • • •
00 101 011
DEC IY 11 111 101 S/D 2 7 1YR -1→IYR • • • • • •
00 101 011
INC INC ww 00 ww 0011 S/D 1 4 wwR + 1→wwR • • • • • •
INC IX 11 011 101 S/D 2 7 1XR + 1→IXR • • • • • •
00 100 011
INC IY 11 111 101 S/D 2 7 1YR + 1→IYR • • • • • •
00 100 011
SBC SBC HL ww 11 101 101 S D 2 10 HLR-wwR-c→HLR ↑ ↑ X V S ↑
01 ww0 010
UM005004-0918
Z8018x
222
DATA TRANSFER INSTRUCTIONS

Table 41. 8-Bit Load
Flags
Operation
Load LD A,I 11 101 101 S/D 2 6 1r→Ar ↑ ↑ R IEF2 R •

8-Bit
01 010 111
Data
LD A,R 11 101 101 S/D 2 6 Rr→Ar ↑ ↑ R IEF2 R •
01 011 111
LD A,(BC) 00 001 010 S D 1 6 (BC)M→Ar • • • • • •
LD A,(DE) 00 011 010 S D 1 6 (DE)M→Ar • • • • • •
LD A,(mn) 00 111 010 S D 3 12 (mn)M→Ar • • • • • •
<n>
<m>
LD L,A 11 101 101 S/D 2 6 Ar→Ir • • • • • •
01 000 111
LD R,A 11 101 101 S/D 2 6 Ar→Rr • • • • • •
01 001 111
LD (BC),A 00 000 010 D S 1 7 Ar→(BC)M • • • • • •
LD(DE),A 00 010 010 D S 1 7 Ar→(DE)M • • • • • •
LD (mn),A 00 110 010 D S 3 13 Ar→(mn)M • • • • • •
<n>
<m>
LD gg’ 01 g g’ S/D 1 4 gr’→gr • • • • • •
LD g,(HL) 01 g 110 D S 1 6 (HL)M→gr • • • • • •
LD g,m 00 g 110 S D 2 6 m→gr • • • • • •
<m>
LD g,(IX + d) 11 011 101 S D 3 14 (IX + d)Mgr • • • • • •
01 g 110
<d>
LD g,(IY + d) 11 111 101 S D 3 14 (IY + d)M→gr • • • • • •
01 g 110
<d>
LD (HL),m 00 110 110 S D 2 9 m→(HL)M • • • • • •
<m>
UM005004-0918
Z8018x
223
Table 41. 8-Bit Load (Continued)

Flags
Operation
Load LD (IX + d),m 11 011 101 S D 4 15 m→(IX + d)M • • • • • •

8-Bit
00 110 110
Data
<d>
LD (IY + d),m 11 111 101 S D 4 15 m→(IY + d)M • • • • • •
01 110 g
<d>
<m>
LD (HL),g 01 110 g S D 1 7 gr→(HL)M • • • • • •
LD (IX + d),g 11 011 101 D S 3 15 gr→(IX+d)M • • • • • •
01 110 g
<d>
LD (IY + d),g 11 111 101 D S 3 15 gr→(IY + d)M • • • • • •
01 110 g
<d>
(1) In the case of R1 and Z Mask, interrupts are not sampled at the end of LD A, I or LD A,R.
Table 42. 16-Bit Load

Flags
Operation
Load LD ww,mn 00 ww0 001 S D 3 9 mn→wwR • • • • • •

16-Bit
<n>
Data
<m>
LD IX,mn 11 011 101 S D 4 12 mn→IXR • • • • • •
00 100 001
<n>
<m>
UM005004-0918
Z8018x
224

Flags
Operation
Load LD IY,mn 11 111 101 S D 4 12 mn→IYR • • • • • •

16-Bit
00 100 001
Data
<n>
<m>
LD SP,HL 11 111 001 S/D 1 4 HIR→SPR • • • • • •
LD SP,IX 11 011 101 S/D 2 7 IXR-SPR • • • • • •
11 111 001
LD SP,IY 11 111 101 S/D 2 7 IYR→SPR • • • • • •
11 111 001
LD ww,(mn) 11 101 101 S D 4 18 (mn + 1)M→wwHr • • • • • •
01 ww1 011 (mn)M→wwLr
<n>
<m>
LD HL,(mn) 00 101 010 S D 3 15 (mn + 1)M→Hr • • • • • •
<n> (mn)M→Lr
<m>
LD IX,(mn) 11 011 101 S D 4 18 (mn + 1)M→IXHr • • • • • •
00 101 010 (mn)M→IXLr
<n>
<m>
LD IY,(mn) 11 111 101 S D 4 18 (mn + 1)M→IYHr • • • • • •
00 101 010 (mn)M →IYLr
<n>
<m>
LD (mn),ww 11 101 101 D S 4 19 wwHr→(mn + 1)M • • • • • •
01 ww0 011 wwLr→(mn)M
<n>
<m>
UM005004-0918
Z8018x
225

Flags
Operation
Load LD (mn),HL 00 100 010 D S 3 16 Hr→(mn + 1)M • • • • • •

16-bit
<n> Lr→(mn)M
Data
<m>
LD (mn),IX 11 011 101 D S 4 19 IXHr-(mn + 1)M • • • • • •
00 100 010 IXLr→(mn)M
<n>
<m>
LD (mn),IY 11 111 101 D S 4 19 IYHr→(mn + 1)M • • • • • •
00 100 010 IYLr→(mn)M
<n>
<m>
Table 43. Block Transfer

Flags
Operation
Block (3) (2)

Transfer
CPD 11 101 101 S S 2 12 Ar = (HL)M ↑ ↑ ↑ ↑ S •
Search
Data 10 101 001 BCR-1→BCR
HLR-1→HLR (3) (2)
CPDR 11 101 101 S S 2 14 BCR ≠ 0 Ar ≠ (HL)M ↑ ↑ ↑ ↑ S •
10 111 001 12 BCR = 0 or Ar = (HL)M
Ar-(HL)R
Q BCR-1-BCR
HLR-1→HLR
Repeat Q until
Ar = (HL)M or BCR = 0 (3) (2)
UM005004-0918
Z8018x
226
Table 43. Block Transfer (Continued)

Flags
Operation
CPI 11101101 S S 2 12 Ar-(HL)M ↑ ↑ ↑ ↑ S •

10100001 BCR-1→BCR
HLR + 1→HLR (3) (2)
CPIR 11101101 S S 2 14 BCR ≠ 0 Ar*(HL)M ↑ ↑ ↑ ↑ S •
10110001 12 BCR = 0 or Ar = (HL)M
Ar-(HL)M
Q BCR-1→BCR
HLR + 1→HLR
Repeat Q until
Ar = (HL)M or BCR = 0 (2)
LDD 11 101 101 S/D 2 12 (HL)M → (DE)M • • R ↑ R •
10 101 000 BCR -1→BCR
DER-1→DER
HLR-1→HLR
LDDR 11 101 101 S/D 2 14(BCR ≠ 0) (HL)M → (DE)M • • R R R •
BCR -1 → BCR
10 111 000 12(BCR = 0)
Q DER -1 → DER
HLR -1 → HLR
Repeat Q until
BCR = 0 (2)
LDI 11 101 101 S/D 2 12 (HL)M→DE)R • • R ↑ R •
10 100 000 BCR-1→BCR
DER + 1→DER
HLR + 1→HLR
LDIR 11 101 101 S/D 2 14(BCR≠0) (HL)M→(DE)M • • R R R •
Q BCR-1→BCR
10 110 000 12(BCR = 0)
DER + 1→DER
HLR + 1→HLR
Repeat Q until
BCR = 0
(2) P/V = 0: BCR-1 = 0
P/V = 1: BCR-1 ≠ 0
(3) Z = 1: Ar = (HL)M
Z = 0 :Ar ≠ (HL)M
UM005004-0918
Z8018x
227
Table 44. Stock and Exchange

Flags
Operation
PUSH PUSH zz 11zz 0101 S D 1 11 zzLr→(SP-2)M • • • • • •

zzHr→(SP-1)M
SPR-2→SPR
PUSH IX 11 011 101 S/D 2 14 IXLr→(SP-2)M • • • • • •
11 100 101 IXHr→(SP-1)M
SPR-2→SPR
PUSH PUSH IY 11 111 101 S/D 2 14 IYLr→(SP-2)M • • • • • •
11 100 101 IYHr→(SP-1)M
SPR-2→SPR
POP POP zz 11 zz0 001 D S 1 9 (SP + 1)M→xxHr(4) • • • • • •
(SP)M→zzLx
SPR + 2→SPR
POP IX 11 011 101 S/D 2 12 (SP + 1)M→IXHr • • • • • •
11 100 001 (SP)M→IXLr
SPR + 2→SPR
POP IY 11 111 101 S/D 2 12 (SP + 1)M→IYHr • • • • • •
11 100 001 (SP)M-IYLr
SPR + 2→SPR
UM005004-0918
Z8018x
228
Table 44. Stock and Exchange (Continued)

Flags
Operation
Exchange EX AFAF’ 00 001 000 S/D 1 4 AFR-AFR' • • • • • •

EX DE, HL 11 101 011 S/D 1 3 DER-HLR • • • • • •
EX X 11 011 001 S/D 1 3 BCR-BCR' • • • • • •
DER→DER'
HLR→HLR'
EX (SP),HL 11 100 011 S/D 1 16 Hr→(SP + 1)M • • • • • •
Lr→(SP)M
EX (SP),IX 11 011 101 S/D 2 19 IXHr→(SP + 1)M • • • • • •
IXLr-(SP)M
EX (SP),IY 11 111 101 S/D 2 19 IYHr-(SP + 1)M • • • • • •
11 100 011 IYLr→(SP)M
(4) In the case of POP AF, Flag is written as current contents of the stack
UM005004-0918
Z8018x
229
PROGRAM AND CONTROL INSTRUCTIONS
Table 45. Program Control Instructions

Flags
Operation
Call CALL mn 11 001 101 D 3 16 PCHr→(SP-1)M • • • • • •

<n> PCLr→(SP-2)M
<m> mn→PCR
SPR-2→SPR
CALL f,mn 11 f 100 D 3 6 (f : false) continue : f is false • • • • • •
<n> 16 (f: true) CALL mn: f is true
<m>
Jump DJNZj 00 010 000 D 2 9 (Br ≠ 0) Br-1→Br • • • • • •
<j-2> 2 7 (Br = 0) continue: Br = 0
PCR + j→PCR: Br ≠ 0
JP f,mn 11 f 010 D 3 6 (f: false) mn→PCR: f is true • • • • • •
<n> 3 9 (f: true) continue: f is false
<m>
JP mn 11 000 011 D 3 9 mn→PCR • • • • • •
<n>
<m>
JP (HL) 11 101 001 D 1 3 HLR→PCR • • • • • •
JP (IX) 11 011 101 D 2 6 IXR→PCR • • • • • •
11 101 001
JP (IY) 11 111 101 D 2 6 IYR→PCR • • • • • •
11 101 001
JR j 00 011 000 D 2 8 PCR + j→PCR • • • • • •
<j-2>
JR Cj 00 111 000 D 2 6 continue: C = 0 • • • • • •
<j-2> 2 8 PCR + j→PCR: C = 1
JR NCj 00 110 000 D 2 6 continue : C = 1 • • • • • •
<j-2> 2 8 PCR + j→PCR : C = 0
UM005004-0918
Z8018x
230
Table 45. Program Control Instructions (Continued)

Flags
Operation
Jump JR Zj 00 101 000 D 2 6 continue : Z = 0 • • • • • •

<j-2> 2 8 PCR, + j→PCR : Z = 1
JR NZj 00 100 000 D 2 6 continue : Z = 1
<j-2> 2 8 PCR + j→PCR : Z = 0
Return RET 11001001 D 1 9 (SP)M→PCLr • • • • • •
(SP + 1)M→PCHr
SPR + 2→SPR
RET f 11f 000 D 1 5 (f : false) continue : f is false • • • • • •
1 10 (f : true) RET : f is true
RETI 11101101 D 2 12 (R0,R1) (SP)M→PCLr • • • • • •
01001101 ZZ(z) (SP + 1)M→PCHr
SPR + 2→SPR
RETN 11101101 D 2 12 (SP)M→PCLr • • • • • •
01000101 (SP + 1)M→PCHr
SPR + 2→SPR
IEF2→IEF1
Restart RST v 11 v 111 D 1 11 PCHr→(SP-1)M • • • • • •
PCLr→(SP-2)M
0→PCHr
v→PCLr
SPR-2→SPR
UM005004-0918
Z8018x
231
Table 46. I/O Instructions

Flags
Operation
INPUT IN A,(m) 11 011 011 D S 2 9 (Am)1,→Ar • • • • • •

<m> m→A0~A7
Ar→A8~A16
IN g,(C) 11 101 101 D S 2 9 (BC)1→gr
01 g 000 g = 110 : Only the ↑ ↑ R P R •
flags change
Cr→A0~A7
Br→A8~16
IN0 g,(m)** 11 101 101 D S 3 12 (00m)g→gr ↑ ↑ R P R •
00 g 000 g = 110 : Only the
flags change
<m> m→A0~A7
(00)→A8~A16 (5) (6)
IND 11 101 101 D S 2 12 (BC)M→(HL)M X ↑ X X ↑ X
10 101 010 Hl2→1→Hl2
Br→1→Br
Cr→A0~A7 (6)
INDR 11 101 101 D S 2 14 (Br ≠ 0) (BC)1→(HL)M X S X X ↑ X
Q HL2→1→HL8
10 111 010 12 (BR =
Br-1→Br
0)
Repeat Q until
Br = 0
Cr→A0~A7
Br→A8∼A16
(5) (6)
INI 11 101 101 D S 2 12 (BC)1→(HL)M X ↑ X X ↑ X
10 100 010 HLR + 1→HLR
Br-1→Br
Cr→A0~A7
Br→A8~A16 (6)
UM005004-0918
Z8018x
232
Table 46. I/O Instructions (Continued)

Flags
Operation
INPUT INIR 11 101 101 D S 2 14 (Br ≠ 0) (BC)I→(HL)M X S X X ↑ X

Q HLR + 1→HLR
10 110 010 12 (Br = 0)
Br-f→Br
Repeat Q until
Br = 0
Cr→A0~A7
Br→A8→A16
OUTPUT OUT (m)A 11 010 011 S D 2 10 Ar→(Am)1 • • • • • •
<m> m→A0~A7
Ar→A8~A16
OUT (C),g 11 101 101 S D 2 10 gr→(BC)1 • • • • • •
01 g 001 Cr→A0~A7
Br→A8~A16
OUT0(m),g** 11 101 101 S D 3 13 gr→(00m)1 • • • • • •
00 g 001 m→A0~A7
<m> 00→A8~A16 (5) (6)
OTDM** 11 101 101 S D 2 14 (HL)M→(00C)1 ↑ ↑ ↑ P ↑ ↑
10 001 011 HLR-1→HLR
Cr-1→Cr
Br-1→Br
Cr→A0~A7
00→A8~A16 (6)
OTDMR** 11 101 101 S D 2 16 (Br ≠ 0) (HL)M→(00C)1 R S R S ↑ R
HLR-1-HLR
10 011 011 14 (Br = 0)
Q Cr~1→Cr
Br-1→Br
Repeat Q until
Br = 0
Cr→A0~A7
00→A8~A16 (6)
UM005004-0918
Z8018x
233

Flags
Operation
OUTPUT OTDR 11 101 101 S D 2 14 (Br ≠ 0) (HL)M→(BC)M1 X S X X ↑ X

Q HLR-1→HLR
10 111 011 12 (Br = 0)
Br-1Βr
Repeat Q until
Br = 0
Cr→A0~A7
Br→A8~A16 (5) (6)
Q (HL)M→(BC)M
OUTI 11 101 101 S D 2 12 X ↑ X X ↑ X
HLR + 1→HLR
10 100 011
Br-1→Br
Repeat Q until
BR = 0
Cr→A0~A7
Br→A8~A16 (6)
OTIR 11 101 101 S D 2 14 (Br ≠ 0) (HL)M→(BC)M X S X X ↑ X
Q HLR + 1→HLR
10 110 011 12 (Br = 0)
Br-1→Br
Repeat Q until
Br = 0
Cr→A0~A7
Br→A8~A16
TSTIOm** 11 101 101 S S 3 12 (00C)1*m ↑ ↑ S P R R
01 110 100 Cr→A0~A7
<m> 00→A8~A16 (5) (6)
OTIM** 11 101 101 S D 2 14 (HL)M→(00C)I ↑ ↑ ↑ P ↑ ↑
10 000 011 HLR + 1→HLR
Cr + 1→Cr
Br-1→Br
Cr→A0~A7
00→A8~A16 (6)
UM005004-0918
Z8018x
234

Flags
Operation
OTIMR** 11 101 101 S D 2 16 (Br ≠ 0) (HL)M→(00C)I R S R S ↑ R

HLR + 1→HLR
10 010 011 14 (Br = 0)
Q Cr + 1→Cr
Br-1→Br
Repeat Q until
Br = 0
Cr→A0~A7
00→A8~A16 (5) (6)
OUTD 11 101 101 S D 2 12 (HL)M→(BC)1 X ↑ X X ↑ X
10 101 011 HLR-1→ΗLR
Br-1→Br
Cr→A0~A7
Br→A8~A16
(5) Z = 1 : Br-1 = 0
Z = 0 : Br-1 ≠ 0
(6) N = 1: MSB of Data = 1
N = 0 : MSB of Data = 0
UM005004-0918
Z8018x
235
Special Control Instructions
Table 47. Special Control Instructions

Flags
Operation
Name Mnemonics Op Code Immed Ext Ind Reg Regi Imp Rel Bytes States Operation S Z H P/V N C
Special DAA 00 100 111 S/D 1 4 Decimal ↑ ↑ ↑ P • ↑

Function Adjust
Accumulator
Carry CCF 00 111 111 1 3 C→C • • R • R ↑
Control
SCF 00 110 111 1 3 1→C • • R • R S
CPU DI 11 110 011 1 3 0→IEF1,0→IEF2 (7) • • • • • •
Control
EI 11 111 011 1 3 1→IEF1,1→ΙEF2 (7) • • • • • •
HALT 01 110 110 1 3 CPU halted • • • • • •
IM0 11 101 101 2 6 Interrupt • • • • • •
01 000 110 Mode 0
IM1 11 101 101 2 6 Interrupt • • • • • •
01 010 110 Mode 1
IM2 11 101 101 2 6 Interrupt • • • • • •
01 011 110 Mode 2
NOP 00 000 000 1 3 No operation • • • • • •
SLP** 11 101 101 2 8 Sleep • • • • • •
01 110 110
7) Interrupts are not sampled at the end of DI or EI.
UM005004-0918
Z8018x
236
UM005004-0918
Z8018x
237
Instruction Summary
** : Added new instructions to Z80
Machine
MNEMONICS Bytes Cycles States
ADC A,m 2 2 6
ADC A,g 1 2 4
ADC A, (HL) 1 2 6
ADC A, (IX+d) 3 6 14
ADC A, (IY+d) 3 6 14
ADD A,m 2 2 6
ADD A,g 1 2 4
ADD A, (HL) 1 2 6
ADD A, (IX+d) 3 6 14
ADD A, (IY+d) 3 6 14
ADC HL,ww 2 6 10
ADD HL,ww 1 5 7
ADD IX,xx 2 6 10
ADD IY,yy 2 6 10
AND m 2 2 6
AND g 1 2 4
AND (HL) 1 2 6
AND (IX+d) 3 6 14
AND (IY+d) 3 6 14
BIT b, HU 2 3 9
BIT b, (IX+d) 4 5 15
BIT b, (IY+d) 4 5 15
BIT b,g 2 2 6
CALL f,mn 3 2 6
(If condition is false)
UM005004-0918
Z8018x
238
Machine
3 6 16
(If condition is true)
CALL mn 3 6 16
CCF 1 1 3
CPD 2 6 12
CPDR 2 8 14
(If BCR ≠ 0 and Ar ≠ (HL)M
2 6 12
(If BCR = 0 or Ar = (HL)M
CP (HL) 1 2 6
CPI 2 6 12
CPIR 2 8 14
(If BCR ≠ 0 and Ar ≠ (HL)M
2 6 12
(If BCR = 0 or Ar = (HL)M
CP (IX+d) 3 6 14
CP (IY+d) 3 6 14
CPL 1 1 3
CP m 2 2 6
CP g 1 2 4
DAA 1 2 4
DEC (HL) 1 4 10
DEC IX 2 3 7
DEC IY 2 3 7
DEC (IX+d) 3 8 18
DEC (IY+d) 3 8 18
DEC g 1 2 4
DEC ww 1 2 4
DI 1 1 3
DJNZ j 2 5 9 (if Br ≠ 0)
UM005004-0918
Z8018x
239
Machine
2 3 7 (if Br = 0)
EI 1 1 3
EX AF,AF' 1 2 4
EX DE,HL 1 1 3
EX (SP),HL 1 6 16
EX (SP)I,IX 2 7 19
EX (SP),IY 2 7 19
EXX 1 1 3
HALT 1 1 3
IM 0 2 2 6
IM 1 2 2 6
IM 2 2 2 6
INC g 1 2 4
INC (HL) 1 4 10
INC (IX+d) 3 8 18
INC (IY+d) 3 8 18
INC ww 1 2 4
INC IX 2 3 7
INC IY 2 3 7
IN A,(m) 2 3 9
IN g,(C) 2 3 9
INI 2 4 12
INIR 2 6 14 (if Br ≠ 0)
2 4 12 (If Br = 0)
IND 2 4 12
INDR 2 6 14 (If Br ≠ 0)
INDR 2 4 12 (If Br = 0)
IN0 g,(m)** 3 4 12
JP f,mn 3 2 6
(If f is false)
UM005004-0918
Z8018x
240
Machine
3 3 9
(If f is true)
JP (HL) 1 1 3
JP (IX) 2 2 6
JP (IY) 2 2 6
JP mn 3 3 9
JR j 2 4 8
JR C,j 2 2 6
2 4 8
JR NC,j 2 2 6
(if condition is false)
2 4 8
JR Z,j 2 2 6
2 4 8
If condition is true)
JR NZ,j 2 2 6
2 4 8
LD A, (BC) 1 2 6
LD A, (DE) 1 2 6
LD A,I 2 2 6
LD A, (mn) 3 4 12
LD A,R 2 2 6
LD (BC),A 1 3 7
LDD 2 4 12
UM005004-0918
Z8018x
241
Machine
LD (DE),A 1 3 7
LD ww,mn 3 3 9
LD ww,(mn) 4 6 18
LDDR 2 6 14 (If BCR ≠ 0)
2 4 12 (If BCR = 0
LD (HL),m 2 3 9
LD HL,(mn) 3 5 15
LD (HL),g 1 3 7
LDI 2 4 12
LDI,A 2 2 6
LDIR 2 6 14 (If BCR ≠ 0)
2 4 12 (If BCR = 0)
LD IX,mn 4 4 12
LID IX,(mn) 4 6 18
LD (IX+d),m 4 5 15
LD (IX+ d),g 3 7 15
LD IY,mn 4 4 12
LD IY,(mn) 4 6 18
LD (IY+d),m 4 5 15
LD (IY+d),g 3 7 15
LD (mn),A 3 5 13
LD (mn),ww 4 7 19
LD (mn),HL 3 6 16
LD (mn),IX 4 7 19
LD (mn),IY 4 7 19
LD R,A 2 2 6
LD g,(HL) 1 2 6
LD g,(IX+d) 3 6 14
LD g,(IY+d) 3 6 14
LD g,m 2 2 6
UM005004-0918
Z8018x
242
Machine
LD g,g' 1 2 4
LD SP,HL 1 2 4
LD SP,IX 2 3 7
LD SP,IY 2 3 7
MLT ww" 2 13 17
NEG 2 2 6
NOP 1 1 3
OR (HL) 1 2 6
OR (IX+d) 3 6 14
OR (IY+d) 3 6 14
OR m 2 2 6
OR g 1 2 4
OTDM** 2 6 14
OTDMR** 2 8 16 (If Br ≠ 0)
2 6 14 (If Br = 0)
OTDR 2 6 14 (If Br ≠ 0)
2 4 12 (If Br = 0
OTIM** 2 6 14
OTIMR** 2 8 16 (If Br ≠ 0)
2 6 14 (If Br = 0)
OTIR 2 6 14 (If Br ≠ 0)
2 4 12 (If Br = 0)
OUTD 2 4 12
OUTI 2 4 12
OUT (m),A 2 4 10
OUT (C),g 2 4 10
OUT0 (m),g ** 3 5 13
POP IX 2 4 12
POP IY 2 4 12
POP zz 1 3 9
UM005004-0918
Z8018x
243
Machine
PUSH IX 2 6 14
PUSH IY 2 6 14
PUSH zz 1 5 11
RES b,(HL) 2 5 13
RES b,(IX+d) 4 7 19
RES b,(IY+d) 4 7 19
RES b,g 2 3 7
RET 1 3 9
RET f 1 3 5
1 4 10
RETI 2 4 (R0, R1) 12 (R0, R1)
10 (Z) 22 (Z)
RETN 2 4 12
RLA 1 1 3
RLCA 1 1 3
RLC (HL) 2 5 13
RLC (IX-1-dl 4 7 19
RLC (IY+d) 4 7 19
RLC g 2 3 7
RLD 2 8 16
RL (HL) 2 5 13
RL (IX+d) 4 7 19
RL (IY+d) 4 7 19
RL g 2 3 7
RRA 1 1 3
RRCA 1 1 3
RRC (HL) 2 5 13
RRC (IX+d) 4 7 19
UM005004-0918
Z8018x
244
Machine
RRC (IY+d) 4 7 19
RRC g 2 3 7
RRD 2 8 16
RR (HL) 2 5 13
RR (IX+d) 4 7 19
RR (IY+d) 4 7 19
RR g 2 3 7
RST v 1 5 11
SBC A,(HL) 1 2 6
SBC A, (IX+d) 3 6 14
SBC A,(IY+d) 3 6 14
SBC A,m 2 2 6
SBC A,g 1 2 4
SBC HL,ww 2 6 10
SCF 1 1 3
SET b,(HL) 2 5 13
SET b,(IX+d) 4 7 19
SET b,(IY+d) 4 7 19
SET b,g 2 3 7
SLA (HL) 2 5 13
SLA (IX+d) 4 7 19
SLA (IY+d) 4 7 19
SLA g 2 3 7
SLP** 2 2 8
SRA (HL) 2 5 13
SRA (IX+d) 4 7 19
SRA (IY+d) 4 7 19
SRA g 2 3 7
SRL (HL) 2 5 13
SRL (IX+d) 4 7 19
UM005004-0918
Z8018x
245
Machine
SRL (IY+d) 4 7 19
SRL g 2 3 7
SUB (HL) 1 2 6
SUB (IX+d) 3 6 14
SUB (IY+d) 3 6 14
SUB m 2 2 6
SUB g 1 2 4
**TSTIO m 3 4 12
**TST g 2 3 7
TST m** 3 3 9
TST (HL)** 2 4 10
XOR (HL) 1 2 6
XOR (IX+d) 3 6 14
XOR (IY+d) 3 6 14
XOR m 2 2 6
XOR g 1 2 4
UM005004-0918
Z8018x
246
UM005004-0918
Z8018x
247
Op Code Map
Table 48. 1st Op Code Map Instruction Format: XX
ww (L0 = ALL) L0 = 0~7

BC DE HL SP BC DE HL AF zz
g (LO = 0~7) NZ NC P0 P f
B D H (HL) B D H (HL) 00H 10H 20H 30H v
0000 0001 0010 0011 0100 0101 0110 0111 1000 1001 1010 1011 1100 1101 1110 1111
HI
LO 0 1 2 3 4 5 6 7 8 9 A B C D E F
B 0000 0 N0P DJNZj JR JR note 1) RET f 0
NZ,j NC,j
C 0001 1 LD ww, mn POP zz 1
LD g, s ADD SUB s AND s OR s
D 0010 2 LD (ww), A LD LD A,s JP f, mn 2
(mn) (mn),
,HL A
E 0011 3 INC ww JP mn OUT EX(SP), DI 3
(m),A HL
H 0100 4 INC g note1 CALL f, mn 4
L 0101 5 DEC g note1 PUSH zz 5
(HL) 0110 6 LD g,m note1 note2 HALT note2 note2 note2 note2 ADD SUB m AND m OR m 6
A,m
A 0111 7 RLCA RLA DAA SCF RST v 7
S (HI = ALL)
B 1000 8 EXAF,A JR j JR Z,j JR C,j RET f

F’ 8
C 1001 9 ADD HL, ww RET EXX JP(HL) LD 9
SP,
LD g, s ADC SBC XOR s CP s HL
D 1010 A LD A,(ww) LD LD A, A,s A,s JP f, mn A
HL, (mn)
(mn)
E 1011 B DEC ww Table2 IN A(m) EXDE,H EI B
L
H 1100 C INC g CALL f, mn C
L 1101 D DEC g CALL note3 Table3 note3 D
mn
(HL) 1110 E LD g,m note2 note2 note2 note2 note2 ADC SBC A,m XOR m CP m E
A,m
A 1111 F RRCA RRA CPL CCF RST v F
0 1 2 3 4 5 6 7 8 9 A B C D E F
C E L A C E L A Z C PE M f
g(L0 = 8~F) 08H 18H 28H 3BH v
LO = 8~F
UM005004-0918
Z8018x
248
Note 1: (HL) replaces g.

Note 2: (HL) replaces s.
Note 3: If DDH is supplemented as first Op Code for the instructions
which have HL or (HL) as an operand in Table 48, the instructions are
executed replacing HL with IX and (HL) with (IX+d).
ex. 22H : LD (mn), HL
DDH 22H : LD (mn), IX
If FDH is supplemented as 1st Op Code for the instructions which have
HL or (HL) as an operand in Table 48, the instructions are executed
replacing HL with IY and (HL) with (IY+d).
ex. 34H : INC (HL)
FDH 34H : INC (IY+d)
However, JP (HL) and EX DE, HL are exceptions and note the following.
• If DDH is supplemented as 1st Op Code for JP (HL), (IX) replaces
(HL) as operand and JP (IX) is executed
• If FDH is supplemented as 1st Op Code for JP (HL), (IY) replaces
(HL) as operand and JP (IY) is executed
• Even if DDH or FDH is supplemented as 1st Op Code for EX DE,
HL, HL is not replaced and the instruction is regarded as illegal
instruction.
UM005004-0918
Z8018x
249
Table 49. 2nd Op Code Map Instruction Format: CB XX
b (L0 = 0~7)
0 2 4 6 0 2 4 6 0 2 4 6
HI 0000 0001 0010 0011 0100 0101 0110 0111 1000 1001 1010 1011 1100 1101 1110 1111
LO 0 1 2 3 4 5 6 7 8 9 A B C D E F
B 0000 0 0
C 0001 1 1
D 0010 2 RLC g RL g SLA g 2
E 0011 3 3
H 0100 4 BIT b,g RES b,g SET b,g 4
L 0101 5 5
(HL 0110 6 NOTE NOTE NOTE NOTE1) NOTE1) NOTE1) 6
) 1) 1) 1)
g (HI = ALL)
A 0111 7 7
B 1000 8 8
C 1001 9 RRC g RR g SRA g SRL g 9
D 1010 A BIT b,g RES b,g SET b,g A
E 1011 B B
H 1100 C C
L 1101 D D
(HL 1110 E NOTE NOTE NOTE NOTE NOTE1) NOTE1) NOTE 1) E
) 1) 1) 1) 1)
A 1111 F F
0 1 2 3 4 5 6 7 8 9 A B C D E F
1 3 5 7 1 3 5 7 1 3 5 7
b (LO = 8 ~ F)
UM005004-0918
Z8018x
250
Table 50. 2nd Op Code Map Instruction Format: ED XX
ww (L0 = ALL)
BC DE HL SP
G (L0 = 0~7)
B D H B D H
HI 0000 0001 0010 0011 0100 0101 0110 0111 1000 1001 1010 1011 1100 1101 1110 1111
LO 0 1 2 3 4 5 6 7 8 9 A B C D E F
0000 0 IN0 g, (m) IN g, (C) LDI LDIR 0
0001 1 OUT0 (m),g OUT (C),g CPI CPIR 1
0010 2 SBC HL, ww INI INIR 2
0011 3 LD (mn), ww OTIM OTIM OUTI OTIR 3
R
0100 4 TST g TST NEG TST m TSTIO 4
(HL) m
0101 5 RETN 5
0110 6 IM 0 IM 1 SLP 6
0111 7 LD I,A LD A,I RRD 7
1000 8 IN0 g, (m) IN g, (C) LDD LDDR 8
1001 9 OUT0 (m), g OUT (C) , g CPD CPDR 9
1010 A ADC HL,ww IND INDR A
1011 B LD ww, (mn) OTD OTD OUTD OTDR B
M MR
1100 C TST g MLT ww C
1101 D RETI D
1110 E IM 2 E
1111 F LDR, LD A,R RLD F
A
0 1 2 3 4 5 6 7 8 9 A B C D E F
C E L A C E L A
g (L0 = 8~F)
UM005004-0918
Z8018x
251
Bus Control Signal Conditions

BUS AND CONTROL SIGNAL CONDITION IN EACH MACHINE
CYCLE
* (ADDRESS) invalid
Z (DATA) high impedance.
** added new instructions to Z80
Table 51. Bus and Control Signal Condition in Each Machine Cycle
Machine
Instruction Cycle States Address Data RD WR MREQ IORQ M1 HALT ST
MC1 T1T2T3 1st Op Code 1st Op 0 1 0 1 0 1 0

Address Code
ADD HL,ww
MC2 TiTiTiTi * Z 1 1 1 1 1 1 1
~MC5

Address Code
ADD IX,xx
ADD IY,yy MC2 T1T2T3 2nd Op Code 2nd Op 0 1 0 1 0 1 1
Address Code
MC3 TiTiTiTi * Z 1 1 1 1 1 1 1
~MC6

ADC HL,ww Address Code
SBC HL,ww
MC2 T1T2T3 2nd Op Code 2nd Op 0 1 0 1 0 1 1
Address Code
MC3 TiTiTiTi * Z 1 1 1 1 1 1 1
~MC6
UM005004-0918
Z8018x
252
Table 51. Bus and Control Signal Condition in Each Machine Cycle (Continued)
Machine
ADD A,g MC1 T1T2T3 1st Op Code 1st Op 0 1 0 1 0 1 0

ADC A,g Address Code
SUB g
MC2 Ti * Z 1 1 1 1 1 1 1
SBC A,g
AND g
OR g
XOR g
CP g
ADD A,m MC1 T1T2T3 1st Op Code 1st Op 0 1 0 1 0 1 0

ADC A,m Address Code
SUB m
SBC A,m MC2 T1T2T3 1st operand m 0 1 0 1 1 1 1
Address
AND m
OR m
XOR m
CP m
ADD A, (HL) MC1 T1T2T3 1st Op Code 1st Op 0 1 0 1 0 1 0

ADC A, (HL) Address Code
SUB (HL)
MC2 T1T2T3 HL DATA 0 1 0 1 1 1 1
SBC A, (HL)
AND HU
OR (HL)
XOR (HL)
CP (HL)
ADD A, (IX+ d) MC1 T1T2T3 1st Op Code 1st Op 0 1 0 1 0 1 0

ADD A, (IY+d) Address Code
ADC A, (IX+d)
ADC A, (IY+d)
Address Code
SUB (lX+d)
SUB (IY+d)
SBC A, (IX+ d)
SBC A, (IY+ d) MC3 T1T2T3 1st operand d 0 1 0 1 1 1 1

AND (IX+d) Address
UM005004-0918
Z8018x
253
Machine
AND (IY+ d) MC4 TiTiTi * Z 1 1 1 1 1 1 1

OR (IX + d) ~MC6
OR (IY+d)
XOR (IX + d)
XOR (IY+d)
CP (IX+d) MC6 T1T2T3 IX+d DATA 0 1 0 1 1 1 1

CP (IY+d) IY+d
MC1 T1T2T3 1st Op Code 1st 0 1 0 1 0 1 0

Address Op Code
BIT b,g
MC2 T1T2T3 2nd Op Code 2nd 0 1 0 1 0 1 1
Address Op Code
Address Op Code
BIT b, (HL)
MC2 T1T2T3 2nd Op Code 2nd 0 1 0 1 0 1 1
Address Op Code
MC3 T1T2T3 HL DATA 0 1 0 1 1 1 1

Address Code

BIT b, (IX+d) Address Code
BIT b, (IY+d) MC3 T1T2T3 1st operand d 0 1 0 1 1 1 1
Address
MC4 T1T2T3 3rd Op Code 3rd Op 0 1 0 1 0 1 1

Address Code
MC5 T1T2T3 IX+ d DATA 0 1 0 1 1 1 1

IY+d
UM005004-0918
Z8018x
254
Machine

Address Code
MC2 T1T2T3 1st operand n 0 1 0 1 1 1 1

Address
CALL mn MC3 T1T2T3 2nd operand m 0 1 0 1 1 1 1
Address
MC4 Ti * Z 1 1 1 1 1 1 1
MC5 T1T2T3 SP-1 PCH 1 0 0 1 1 1 1

MC6 T1T2T3 SP-2 PCL 1 0 0 1 1 1 1
CALL f,mn (If MC1 T1T2T3 1st Op Code 1st Op 0 1 0 1 0 1 0

condition is false) Address Code

Address

Address Code

CALL f,mn Address
if condition is MC3 T1T2T3 2nd operand m 0 1 0 1 1 1 1
true) Address
MC4 Ti * Z 1 1 1 1 1 1 1
MC5 T1T2T3 SP-1 PCH 1 0 0 1 1 1 1
MC6 T1T2T3 SP-2 PCL 1 0 0 1 1 1 1
CCF MC1 T1T2T3 1st Op Code 1st Op 0 1 0 1 0 1 0

Address Code
UM005004-0918
Z8018x
255
Machine

Address Code

CPI
CPD Address Code
MC3 T1T2T3 HL DATA 0 1 0 1 1 1 1
MC4 TiTiTi * Z 1 1 1 1 1 1 1
~MC6

Address Code
CPIR
CPDR
(If BCR ≠ 0 and Address Code
Ar = (HL)M) MC3 T1T2T3 HL DATA 0 1 0 1 1 1 1
MC4~M TiTiTi * Z 1 1 1 1 1 1 1
C8 TiTi
Address Code
CPIR
CPDR MC2 T1T2T3 2nd Op Code 2nd Op 0 1 0 1 0 1 1
Address Code
(If BCR=0 or
Ar=(HL)M) MC3 T1T2T3 HL DATA 0 1 0 1 1 1 1
MC4~M TiTiTi * Z 1 1 1 1 1 1 1
C6
CPL MC1 T1T2T3 1st Op Code 1st Op 0 1 0 1 0 1 0

Address Code
DAA Address Code
MC2 Ti * Z 1 1 1 1 1 1 1
DI*1 MC1 T1T2T3 1st Op Code 1st Op 0 1 0 1 0 1 0
Address Code
* 1 Interrupt request is not sampled.
UM005004-0918
Z8018x
256
Machine

Address Code
DJNZ j
MC2 Ti*2 * Z 1 1 1 1 1 1 1
(If Br ≠ 0)
MC3 T1T2T3 1st operand j-2 0 1 0 1 1 1 1
Address
MC4~M TiTi * Z 1 1 1 1 1 1 1
C5

Address Code
DJNZ j
MC2 Ti*1 * Z 1 1 1 1 1 1 1
(If Br=0)
Address
EI*3 MC1 T1T2T3 1st Op Code 1st Op 0 1 0 1 0 1 0

Address Code
EX DE, HL MC1 T1T2T3 1st Op Code 1st Op 0 1 0 1 0 1 0

EXX Address Code

EX AF, AF’ Address Op Code
MC2 Ti * Z 1 1 1 1 1 1 1

Address Code
MC2 T1T2T3 SP DATA 0 1 0 1 1 1 1

EX (SP), HL
MC3 T1T2T3 SP+1 DATA 0 1 0 1 1 1 1
MC4 Ti * Z 1 1 1 1 1 1 1
MC5 T1T2T3 SP+1 H 1 0 0 1 1 1 1
MC6 T1T2T3 SP L 1 0 0 1 1 1 1
*2 DMA,REFRESH, or BUS RELEASE cannot be executed after this state. (Request is ignored)
*3 Interrupt request is not sampled.
UM005004-0918
Z8018x
257
Machine

Address Code

EX (SP),IX
EX (SP),IY Address Code
MC3 T1T2T3 SP DATA 0 1 0 1 1 1 1
MC4 T1T2T3 SP+1 DATA 0 1 0 1 1 1 1
MC5 Ti * Z 1 1 1 1 1 1 1
MC6 T1T2T3 SP+1 IXH 1 0 0 1 1 1 1

IYH
MC7 T1T2T3 SP IXL 1 0 0 1 1 1 1

IYL
Address Code
HALT
— — Next Op Code Next Op 0 1 0 1 0 0 0
Address Code
IM0 MC1 T1T2T3 1st Op Code 1st Op 0 1 0 1 0 1 0

IM1 Address Code
IM2
Address Code

INC g Address Code
DEC g
MC2 Ti * Z 1 1 1 1 1 1 1

Address Code
INC (HL)
MC2 T1T2T3 HL DATA 0 1 0 1 1 1 1
DEC (HL)
MC3 Ti * Z 1 1 1 1 1 1 1
MC4 T1T2T3 HL DATA 1 0 0 1 1 1 1
UM005004-0918
Z8018x
258
Machine

Address Code

INC (IX+ d)
INC (IY+d) Address Code
MC3 T1T2T3 1st operand d 0 1 0 1 1 1 1

Address
DEC (IX+d) MC4~M TiTi * Z 1 1 1 1 1 1 1

DEC (IY+d) C5
MC6 T1T2T3 X+ d DATA 0 1 0 1 1 1 1
IY+ d
MC7 T1 * Z 1 1 1 1 1 1 1
MC8 T1T2T3 IX+ d DATA 1 0 0 1 1 1 1
IY+d

INC ww Address Code
DEC ww
MC2 Ti * Z 1 1 t 1 1 1 1

INC IX Address Code
INC IY
DEC IX
DEC IY Address Code
MC3 Ti * Z 1 1 1 1 1 1 1

Address Code
MC2 T1T2T3 1st operand m 0 1 0 1 1 1 1
IN A,(m)
Address
MC3 T1T2T3 m to A0~A7 DATA 0 1 1 0 1 1 1

A to A8~A15
UM005004-0918
Z8018x
259
Machine

Address Code

IN g,(C)
Address Code
MC3 T1T2T3 BC DATA 0 1 1 0 1 1 1

Address Code

Address Code
INO g,(m)**
Address
MC4 T1T2T3 m to A0~A7 DATA 0 1 1 0 1 1 1
00H to
A8~A15

Address Code
INI MC2 T1T2T3 2nd Op Code 2nd Op 0 1 0 1 0 1 1

Address Code
IND
MC3 T1T2T3 BC DATA 0 1 1 0 1 1 1
MC4 T1T2T3 HL DATA 1 0 0 1 1 1 1

Address Code

Address Code
INIR
INDR MC3 T1T2T3 BC DATA 0 1 1 0 1 1 1
(If Br≠0)
MC4 T1T2T3 HL DATA 1 0 0 1 1 1 1
MC5~M TiTi * Z 1 1 1 1 1 1 1
C6
UM005004-0918
Z8018x
260
Machine

Address Code
INIR
INDR
(If Br=0) Address Code
MC3 T1T2T3 BC DATA 0 1 1 0 1 1 1
MC4 T1T2T3 HL DATA 1 0 0 1 1 1 1

Address Code
JP mn
Address
MC3 T1T2T3 2nd operand m 0 1 0 1 1 1 1

Address

JP f,mn Address Code
(if is false)
Address

Address Code
JP f,mn
(If f is true)
Address
Address
JP (HL) MC1 T1T2T3 1st Op Code 1st Op 0 1 0 1 0 1 0

Address Code

JP (IX) Address Code
JP (IY)
Address Code
UM005004-0918
Z8018x
261
Machine

Address Code

JR j
Address
MC3~M TiTi * Z 1 1 1 1 1 1 1
C4
JR C,j JR NC,j MC1 T1T2T3 1st Op Code 1st Op 0 1 0 1 0 1 0

JR Z,j JR NZ,j Address Code
(if condition
is false)
Address

JR C,j JR NC,j Address Code
JR Z,j JR NZ,j
(if condition
is true) Address
MC3~M TiTi * Z 1 1 1 1 1 1 1
C4

LD g,g' Address Code
MC2 Ti * Z 1 1 1 1 1 1 1

Address Code
LD g,m
Address
LD g, (HL) Address Code
MC2 T1T2T3 HL DATA 0 1 0 1 1 1 1
UM005004-0918
Z8018x
262
Machine

Address Code

LD g, (IX+d) Address Code
LD g, (IY+d) MC3 T1T2T3 1st operand d 0 1 0 1 1 1 1
Address
MC4~M TiTi * Z 1 1 1 1 1 1 1
C5
MC6 T1T2T3 IX+d DATA 0 1 0 1 1 1 1
IY+d

Address Code
LD (HL),g
MC2 Ti * Z 1 1 1 1 1 1 1
MC3 T1T2T3 HL g 1 0 0 1 1 1 1

Address Code

Address Code
LD (IX + d),g
LD (IY + d),g MC3 T1T2T3 1st operand d 0 1 0 1 1 1 1
Address
MC4~ TiTiTi * Z 1 1 1 1 1 1 1
MC6
MC7 T1T2T3 IX+d g 1 0 0 1 1 1 1

IY+d

Address Code
LD (HL),m
Address
MC3 T1T2T3 HL DATA 1 0 0 1 1 1 1
UM005004-0918
Z8018x
263
Machine

Address Code

LD (IX+d),m Address Code
LD (IY+d),m MC3 T1T2T3 1st operand d 0 1 0 1 1 1 1
Address

Address
MC5 T1T2T3 IX+ d DATA 1 0 0 1 1 1 1
IY+d

LD A, (BC) Address Code
LD A, (DE)
MC2 T1T2T3 BC DATA 0 1 0 1 1 1 1
DE
Address Code
LD A,(mn) MC2 T1T2T3 1st operand n 0 1 0 1 1 1 1

Address

Address
MC4 T1T2T3 mn DATA 0 1 0 1 1 1 1

Address Code
LD (BC),A
MC2 Ti * Z 1 1 1 1 1 1 1
LD (DE),A
MC3 T1T2T3 BC A 1 0 0 1 1 1 1
DE
UM005004-0918
Z8018x
264
Machine

Address Code

LD (mn),A Address
Address
MC4 Ti * Z 1 1 1 1 1 1 1
MC5 T1T2T3 mn A 1 0 0 1 1 1 1
LD A,I MC1 T1T2T3 1st Op Code 1st Op 0 1 0 1 0 1 0
*4
LD A,R Address Code
LD I,A
LD R,A MC2 T1T2T3 2nd Op Code 2nd Op 0 1 0 1 0 1 1
Address Code

Address Code
LD ww, mn
Address

Address

Address Code

LD IX,mn
Address Code
LD IY,mn
Address

Address
*4 In the case of R1 and Z MASK, interrupt request is not sampled.
UM005004-0918
Z8018x
265
Machine

Address Code

LD HL, (mn) Address
Address
MC4 T1T2T3 mn DATA 0 1 0 1 1 1 1
MC5 T1T2T3 mn+1 DATA 0 1 0 1 1 1 1

Address Code

Address Code
LD ww,(mn) MC3 T1T2T3 1st operand n 0 1 0 1 1 1 1
Address
Address
MC5 T1T2T3 mn DATA 0 1 0 1 1 1 1

MC6 T1T2T3 mn+ 1 DATA 0 1 0 1 1 1 1

Address Code

Address Code
LD IX,(mn)
LD IY,(mn) MC3 T1T2T3 1st operand n 0 1 0 1 1 1 1
Address

Address
MC5 T1T2T3 mn DATA 0 1 0 1 1 1 1
MC6 T1T2T3 mn+1 DATA 0 1 0 1 1 1 1
UM005004-0918
Z8018x
266
Machine

Address Code

LD (mn),HL Address
Address
MC4 Ti * Z 1 1 1 1 1 1 1
MC5 T1T2T3 mn L 1 0 0 1 1 1 1
MC6 T1T2T3 mn+1 H 1 0 0 1 1 1 1

Address Code

Address Code

LD (mn),ww Address

Address
MC5 Ti * Z 1 1 1 1 1 1 1
MC6 T1T2T3 mn wwL 1 0 0 1 1 1 1
MC7 T1T2T3 mn+1 wwH 1 0 0 1 1 1 1
UM005004-0918
Z8018x
267
Machine

Address Code

Address Code
LD (mn),IX Address
LD (mn),IY
Address
MC5 Ti * Z 1 1 1 1 1 1 1
MC6 T1T2T3 mn IXL 1 0 0 1 1 1 1

IYL
MC7 T1T2T3 mn+1 IXH 1 0 0 1 1 1 1

IYH

LD SP, HL Address Code
MC2 Ti * Z 1 1 1 1 1 1 1

Address Code
LD SP,IX
LD SP,IY
Address Code
MC3 Ti * Z 1 1 1 1 1 1 1

Address Code
LDI
LDD
Address Code
MC3 T1T2T3 HL DATA 0 1 0 1 1 1 1

MC4 T1T2T3 DE DATA 1 0 0 1 1 1 1
UM005004-0918
Z8018x
268
Machine

Address Code

LDIR
LDDR Address Code
(If BCR≠0) MC3 T1T2T3 HL DATA 0 1 0 1 1 1 1
MC4 T1T2T3 DE DATA 1 0 0 1 1 1 1
MC5~M TiTi * Z 1 1 1 1 1 1 1
C6

Address Code
LDIR
LDDR MC2 T1T2T3 2nd Op Code 2nd Op 0 1 0 1 0 1 1
Address Code
(If BCR=0)
MC3 T1T2T3 HL DATA 0 1 0 1 1 1 1
MC4 T1T2T3 DE DATA 1 0 0 1 1 1 1

Address Code
MLT ww** MC2 T1T2T3 2nd Op Code 2nd Op 0 1 0 1 0 1 1

Address Code
MC3 TiTiTTi * Z 1 1 1 1 1 1 1
~MC13 TiTiTiTi
TiTiTi

NEG Address Code
Address Code
NOP MC1 T1T2T3 1st Op Code 1st Op 0 1 0 1 0 1 0

Address Code
UM005004-0918
Z8018x
269
Machine

Address Code

OUT (m),A
Address
MC3 Ti * Z 1 1 1 1 1 1 1
MC4 T1T2T3 m to A0~A7 A 1 0 1 0 1 1 1

A to A8~A15

Address Code

OUT (C),g
Address Code
MC3 Ti * Z 1 1 1 1 1 1 1
MC4 T1T2T3 BC g 1 0 1 0 1 1 1

Address Code

OUT0 (m),g** Address Code

Address
MC4 Ti * Z 1 1 1 1 1 1 1
MC5 T1T2T3 m to A0~A7 g 1 0 1 0 1 1 1

00H to
A8~A15
UM005004-0918
Z8018x
270
Machine

Address Code

OTIM** Address Code
OTDM** MC3 Ti * Z 1 1 1 1 1 1 1
MC4 T1T2T3 HL DATA 0 1 0 1 1 1 1
MC5 T1T2T3 C to A0~A7 DATA 1 0 1 0 1 1 1

00H to
A8~A15
MC6 Ti * Z 1 1 1 1 1 1 1

Address Code

OTIMR** Address Code
OTDMR** MC3 Ti * Z 1 1 1 1 1 1 1
(If Br≠0)
MC4 T1T2T3 HL DATA 0 1 0 1 1 1 1
MC5 T1T2T3 C to A0~A7 DATA 1 0 1 0 1 1 1

00H to
A8~A15
MC6~M TiTiTi * Z 1 1 1 1 1 1 1
C8
UM005004-0918
Z8018x
271
Machine

Address Code

OTIMR** Address Code
OTDMR** MC3 Ti * Z 1 1 1 1 1 1 1
(if Br= 0)
MC4 T1T2T3 HL DATA 0 1 0 1 1 1 1
MC5 T1T2T3 C to A0~A7 DATA 1 0 1 0 1 1 1

00H to
A8~A15
MC6 Ti * Z 1 1 1 1 1 1 1

Address Code
OUTI
OUTD
Address Code
MC3 T1T2T3 HL DATA 0 1 0 1 1 1 1
MC4 T1T2T3 BC DATA 1 0 1 0 1 1 1

Address Code

OTIR
OTDR Address Code
(If Br`≠ 0) MC3 T1T2T3 HL DATA 0 1 0 1 1 1 1
MC4 T1T2T3 BC DATA 1 0 1 0 1 1 1
MC5~M TiTi * Z 1 1 1 1 1 1 1
C6
UM005004-0918
Z8018x
272
Machine

Address Code
OTIR
OTDR
(if Br=0) Address Code
MC3 T1T2T3 HL DATA 0 1 0 1 1 1 1
MC4 T1T2T3 BC DATA 1 0 1 0 1 1 1

Address Code
POP zz
MC2 T1T2T3 SP DATA 0 1 0 1 1 1 1
MC3 T1T2T3 SP+1 DATA 0 1 0 1 1 1 1

Address Code
POP IX
POP IY
Address Code
MC3 T1T2T3 SP DATA 0 1 0 1 1 1 1
MC4 T1T2T3 SP+1 DATA 0 1 0 1 1 1 1
PUSH zz MC1 T1T2T3 1st Op Code 1st Op 0 1 0 1 0 1 0

Address Code
MC2 TiTi * Z 1 1 1 1 1 1 1
~MC3
MC4 T1T2T3 SP-1 zzH 1 0 0 1 1 1 1
MC5 T1T2T3 SP-2 zzL 1 0 0 1 1 1 1
UM005004-0918
Z8018x
273
Machine

Address Code

Address Code
PUSH IX MC3~M TiTi * Z 1 1 1 1 1 1 1
PUSH IY C4
MC5 T1T2T3 SP-1 IXH 1 0 0 1 1 1 1

IYH
MC6 T1T2T3 SP-2 IXL 1 0 0 1 1 1 1

IYL

Address Code
RET
MC2 T1T2T3 SP DATA 0 1 0 1 1 1 1
MC3 T1T2T3 SP+1 DATA 0 1 0 1 1 1 1

RET f Address Code
(If condition
is false) MC2~M TiTi * Z 1 1 1 1 1 1 1
C3

Address Code
RET f
MC2 Ti * Z 1 1 1 1 1 1 1
(If condition
is true) MC3 T1T2T3 SP DATA 0 1 0 1 1 1 1
MC4 T1T2T3 SP+1 DATA 0 1 0 1 1 1 1

Address Code
RETI (R0, R1) MC2 T1T2T3 2nd Op Code 2nd Op 0 1 0 1 0 1 1

Address Code
RETN
MC3 T1T2T3 SP DATA 0 1 0 1 1 0 1
MC4 T1T2T3 SP+1 DATA 0 1 0 1 1 1 1
UM005004-0918
Z8018x
274
Machine
MC1 T1T2T3 1st Op Code 1st Op 0 1 0 1 0*5 1 0

Address Code 1
MC2 T1T2T3 2nd Op Code 2nd Op 0 1 0 1 0*5 1 1

Address Code 1
MC3 TiTiTi * Z 1 1 1 1 1*5 1 1

~MC5 1
MC6 T1T2T3 1st Op Code 1st Op 0 1 0 1 0*5 1 1

RETI (Z) Address Code 0
MC7 Ti * Z 1 1 1 1 1*5 1 1
1
MC8 T1T2T3 2nd Op Code 2nd Op 0 1 0 1 0*5 1 1

Address Code 0
MC9 T1T2T3 SP data 0 1 0 1 1*5 1 1

1
MC10 T1T2T3 SP+1 data 0 1 0 1 1*5 1 1
1
RLCA MC1 T1T2T3 1st Op Code 1st Op 0 1 0 1 0 1 0

RLA Address Code
RRCA
RRA
RLC g MC1 T1T2T3 1st Op Code 1st Op 0 1 0 1 0 1 0

RL g Address Code
RRC g MC2 T1T2T3 2nd Op Code 2nd Op 0 1 0 1 0 1 1

RR g Address Code
SLA g
MC3 Ti * Z 1 1 1 1 1 1 1
SRA g
SRL g
*5 The upper and lower data show the state of M1 when IOC = 1 and IOC = 0 respectively.
UM005004-0918
Z8018x
275
Machine

RLC (HL) Address Code
RL (HL)
RRC (HL)
RR (HL) Address Code
SLA (HL) MC3 T1T2T3 HL DATA 0 1 0 1 1 1 1
SRA (HL)
SRL (HL) MC4 Ti * Z 1 1 1 1 1 1 1
MC5 T1T2T3 HL DATA 1 0 0 1 1 1 1
RLC (IX + d) MC1 T1T2T3 1st Op Code 1st Op 0 1 0 1 0 1 0

RLC (IY + d) Address Code
RL (IX + d)
MC2 T1T2T3 2nd Op Code 2ndOp 0 1 0 1 0 1 1
RL (IY + d)
RRC (IX + d) Address Code
RRC (IY + d) MC3 T1T2T3 1st operand d 0 1 0 1 1 1 1
RR (IX + d) Address
RR (IY + d)
SLA (IX + d) MC4 T1T2T3 3rd Op Code 3rd Op 0 1 0 1 0 1 1
SLA (IY + d) Address Code
SRA (IX + d)
MC5 T1T2T3 IX+d DATA 0 1 0 1 1 1 1
SRA (IY + d)
IY+d
SRL (IX + d)
SRL (IY + d) MC6 Ti * Z 1 1 1 1 1 1 1
MC7 T1T2T3 IX+d DATA 1 0 0 1 1 1 1

IY+d
Address Code

Address Code
RLD
RRD MC3 T1T2T3 HL DATA 0 1 0 1 1 1 1
MC4~M TiTiTiTi Z 1 1 1 1 1 1 1
C7 *
MC8 T1T2T3 HL DATA 1 0 0 1 1 1 1
UM005004-0918
Z8018x
276
Machine

Address Code
MC2 TiTi * Z 1 1 1 1 1 1 1
RST v
~MC3
MC4 T1T2T3 SP-1 PCH 1 0 0 1 1 1 1
MC5 T1T2T3 SP-2 PCL 1 0 0 1 1 1 1
SCF MC1 T1T2T3 1st Op Code 1st Op 0 1 0 1 0 1 0

Address Code
Address Code
SET b,g
RES b,g MC2 T1T2T3 2nd Op Code 2nd Op 0 1 0 1 0 1 1
Address Code
MC3 Ti * Z 1 1 1 1 1 1 1

Address Code
MC2 T1T2T3 2nd Op Code 2ndOp 0 1 0 1 0 1 1

SET b. (HL)
RES b, (HL) Address Code
MC3 T1T2T3 HL DATA 0 1 0 1 1 1 1
MC4 Ti * Z 1 1 1 1 1 1 1
MC5 T1T2T3 HL DATA 1 0 0 1 1 1 1
UM005004-0918
Z8018x
277
Machine

Address Code

Address Code
SET b, (IX+d) MC3 T1T2T3 1st operand d 0 1 0 1 1 1 1
SET b, (IY+d) Address
RES b, (IX+d)
RES b, (IY+d) MC4 T1T2T3 3rd Op Code 3rd Op 0 1 0 1 0 1 1
Address Code
MC5 T1T2T3 IX+d DATA 0 1 0 1 1 1 1

IY+d
MC6 Ti * Z 1 1 1 1 1 1 1
MC7 T1T2T3 IX+ d DATA 1 0 0 1 1 1 1

IY+d
MC1 T1T2T3 1st Op Code 1stOp 0 1 0 1 0 1 0

Address Code
SLP**
Address Code
— — 7FFFFH Z 1 1 1 1 1 0 1

Address Code
Address Code
TSTIO m**
Address
MC4 T1T2T3 C to A0~A7 DATA 0 1 1 0 1 1 1

00H to
A8~A15
UM005004-0918
Z8018x
278
Machine

Address Code
TST g**
Address Code
MC3 Ti * Z 1 1 1 1 1 1 1

Address Code
TST m** MC2 T1T2T3 2nd Op Code 2nd Op 0 1 0 1 0 1 1

Address Code

Address
TST (HL)** MC1 T1T2T3 1st Op Code 1st Op 0 2 0 2 0 2 0

Address Code

Address Code
MC3 Ti * Z 1 1 1 1 1 1 1
MC4 T1T23 HL Data 0 1 0 1 1 1 1
UM005004-0918
Z8018x
279
INTERRUPTS
Table 52. Interrupts
Machine
MC1 T1T2T3 Next Op 0 1 0 1 0 1 0

Code
Address (PC)
NMI
MC2 T1T1 * Z 1 1 1 1 1 1 1
~MC3
MC4 T1T2T3 SP-1 PCH 1 0 0 1 1 1 1

MC5 T1T2T3 SP-2 PCL 1 0 0 1 1 1 1
MC1 T1T2TW Next Op 1st (PC) 1 1 1 0 0 1 0

TWT3 Code Op Code
INT0 Mode 0 Address
(RST Inserted)
MC2 T1T1 * Z 1 1 1 1 1 1 1
~MC3
MC4 T1T2T3 SP-1 PCH 1 0 0 1 1 1 1
MC5 T1T2T3 SP-2 PCL 1 0 0 1 1 1 1
MC1 T1T2Tw Next Op 1st 1 1 1 0 0 1 0

TWT3 Code Op Code
Address (PC)
INT0 Mode 0 MC2 T1T2T3 PC n 0 1 0 1 1 1 1

(Call MC3 T1T2T3 PC+1 m 0 1 0 1 1 1 1
Inserted)
MC4 Ti * Z 1 1 1 1 1 1 1
MC5 T1T2T3 SP-1 PC+2(H) 1 0 0 1 1 1 1
MC6 T1T2T3 SP-2 PC+2(L) 1 0 0 1 1 1 1
MC1 T1T2TW Next 1 1 1 0 0 1 0

TWT3 Op Code
INT0 Mode 1 Address (PC)
MC2 T1T2T3 SP-1 PCH 1 0 0 1 1 1 1
MC3 T1T2T3 SP-2 PCL 1 0 0 1 1 1 1
UM005004-0918
Z8018x
280
Table 52. Interrupts (Continued)
Machine
MC1 T1T2TW Next Vector 1 1 1 0 0 1 0

TWT3 Op Code
Address (PC)
INT0 Mode 2
MC2 Ti * Z 1 1 1 1 1 1 1
MC3 T1T2T3 SP-1 PCH 1 0 0 1 1 1
MC4 T1T2T3 SP-2 PCL 1 0 0 1 1 1 1
MC5 T1T2T3 I, Vector DATA 0 1 0 1 1 1 1
MC6 T1T2T3 I, Vector+1 DATA 0 1 0 1 1 1 1

T1T2,TW
MC1 T1T2,TW Next 1 1 1 1 1 1 0

TWT3 Op Code
INT1 Address (PC)
INT2
MC2 Ti * Z 1 1 1 1 1 1 1
Internal
Interrupts MC3 T1T2T3 SP-1 PCH 1 0 0 1 1 1 1
MC4 T1T2T3 SP-2 PCL 1 0 0 1 1 1 1
MC5 T1T2T3 I, Vector DATA 0 1 0 1 1 1 1
MC6 T1T2T3 I, Vector+1 DATA 0 1 0 1 1 1 1
UM005004-0918
Z8018x
281
Operating Modes Summary

REQUEST ACCEPTANCES IN EACH OPERATING MODE
Table 53. Request Acceptances in Each Operating Mode
Current Normal
Status Operation
(CPU mode Interrupt BUS SYSTEM
and IOSTOP Refresh Acknowledge RELEASE SLEEP STOP
Request Mode) WAIT State Cycle Cycle DMA Cycle Mode Mode Mode
WAIT Acceptable Acceptable Not Acceptable Acceptable Not Not Not

acceptable acceptable acceptable acceptable
Refresh Request Refresh cycle Not Not Refresh cycle Refresh cycle Not Not Not
Request of Refresh begins at the acceptable acceptable begins at the begins at the acceptable acceptable acceptable
by the on-chip end of Machine end MC end of MC
Refresh Controller Cycle (MC)
DREQ0 DMA cycle DMA cycle Acceptable Acceptable Acceptable Acceptable Not Not
DREQ1 begins at the begins at the Refresh cycle DMA cycle Refer to *After BUS acceptable acceptable
end of MC end of MC precedes. begins at the “DMA RELEASE
DMA cycle end of MC. Controller” cycle, DMA
begins at the for details. cycle begins
end of one at the end of
MC one MC
BUSREQ Bus is released Not Not Bus is released Bus is Continue Acceptable Acceptable
at the end of acceptable acceptable at the end of released at the BUS
MC MC end of MC RELEASE
mode
Interrupt INT0, Accepted after Accepted Not Not Not Not Acceptable Acceptable
INT1, executing the after acceptable acceptable acceptable acceptable Return from Return from
1NT2 current executing the SLEEP SYSTEM
instruction. current mode to STOP mode
instruction normal to normal
operation. operation
UM005004-0918
Z8018x
282
Table 53. Request Acceptances in Each Operating Mode
Current Normal
Status Operation
(CPU mode Interrupt BUS SYSTEM
and IOSTOP Refresh Acknowledge RELEASE SLEEP STOP
Request Mode) WAIT State Cycle Cycle DMA Cycle Mode Mode Mode
Internal ↑ ↑ ↑ ↑ ↑ ↑ ↑ Not
I/O acceptable
Interrupt
NMI ↑ ↑ ↑ Not acceptable Acceptable Acceptable

Interrupt DMA cycle Return from
acknowledge stops SYSTEM
cycle precedes. STOP mode
NMI is accepted to normal
after executing operation
Note: * Not acceptable when DMA Request is in level-sense.

↑: Same as above.
MC: Machine Cycle
REQUEST PRIORITY
The Z80180 features three types of requests.

.
Table 54. The Z80180 Types of Requests
Type 1 Accepted in specified state WAIT
Type 2 Accepted in each machine cycle Refresh Request, DMA
Request, and Bus Request.
Type 3 Accepted in each instruction Interrupt Request
Type 1, Type 2, and Type 3 requests priority as follows.

• Highest priority Type 1 > Type 2 > Type 3 lowest priority
• Each request priority in Type 2 is shown as follows. highest priority
Bus Req. > Refresh Req. > DMA Request lowest priority
UM005004-0918
Z8018x
283
Note: If Bus Request and Refresh Request occur simultaneously,

Bus Request is accepted but Refresh Request is cleared.
OPERATION MODE TRANSITION
NORMAL *1 HAL
T In
stru
ctio
T =0 n
SE Inte
RE 0 rru
T= pt
SE
RE
RESET RESET = 0 HALT

SL
P
Ins
RE
SE
tru
Int
T=
0
cti
err
on
up
RESET = 0
t
RE
SE
T
=0
IOSTOP = 0
IOSTOP = 1
SYSTEM
SLEEP
STOP Inte
rru
pt
SL
PI
nst
ruc
tion
IOSTOP
UM005004-0918
Z8018x
284
NORMAL *1 DM
AR
equ
=0 est
En *2
ET d
R ES 1
of D
MA
T= *3
SE
RE
RESET = 0
RESET DMA
R E uest
End
R eq
RE
FR
SE
of R
ES
T
=0
=0
E FR
H
=1
REQ
ESH
RE
Re q ESH
ESH
REQ
t
SE
ues
BUS
EF R
R
0
=
BUS
T=
REF
Q
RE
of R
1
0
B US Q
=
RE
End
B US
BUS REFRESH
RELEASE
Figure 94. Operation Mode Transition
* 1. NORMAL: CPU executes instructions normally in NORMAL mode.

* 2. DMA request: DMA is requested in the following cases.
– DREQ0, DREQ1 = 0
memory to/from (memory mapped) I/0 DMA transfer
– b. DEO = 1 (memory to/from memory DMA transfer)
* 3. DMA end: DMA ends in the following cases:
UM005004-0918
Z8018x
285
– DREQ0, DREQ1 = 1
memory to/from (memory mapped)
I/O DMA transfer
– BCR0, BCR1 = 0000H (all DMA transfers)
– NMI = 0 (all DMA transfers)
OTHER OPERATION MODE TRANSITIONS

The following operation mode transitions are also possible.
1. HALT
{ DMA
REFRESH
BUS RELEASE
}
IOSTOP
{ DMA
REFRESH
BUS RELEASE
}
2. SLEEP BUS RELEASE
SYSTEM STOP BUS RELEASE
UM005004-0918
Z8018x
286
UM005004-0918
Z8018x
287
Status Signals
PIN OUTPUTS IN EACH OPERATING MODE
Table 55 describes pin outputs in each operating mode.
Table 55. Pin Outputs in Each Operating Mode
Address Data
Mode M1 MREQ IORQ RD WR RFSH HALT BUSACK ST BUS BUS
CPU Op Code Fetch 0 0 1 0 1 1 1 1 0 A IN

Operation (1st Op Code)
Op Code Fetch 0 0 1 0 1 1 1 1 1 A IN
(except 1 st Op
Code)
MemRead 1 0 1 0 1 1 1 1 1 A IN
Memory Write 1 0 1 1 0 1 1 1 1 A OUT
I/O Read 1 1 0 0 1 1 1 1 1 A IN
I/O Write 1 1 0 1 0 1 1 1 1 A OUT
Internal 1 1 1 1 1 1 1 1 1 A IN
Operation
Refresh 1 0 1 1 1 0 1 1 * A IN
Interrupt NMI 0 0 1 0 1 1 1 1 0 A IN
Acknowledge
INT0 0 1 0 1 1 1 1 1 0 A IN
Cycle
(1st Machine INT1, INT2 & 1 1 1 1 1 1 1 1 0 A IN
Cycle) Internal
Interrupts
BUS RELEASE 1 Z Z Z Z 1 1 0 * Z IN
HALT 0 0 1 0 1 1 0 1 0 A IN
SLEEP 1 1 1 1 1 1 0 1 1 1 IN
UM005004-0918
Z8018x
288
Table 55. Pin Outputs in Each Operating Mode (Continued)
Address Data
Mode M1 MREQ IORQ RD WR RFSH HALT BUSACK ST BUS BUS
Memory Read 1 0 1 0 1 1 * 1 0 A IN
Internal
Memory Write 1 0 1 1 0 1 * 1 0 A OUT
DMA
I/O Read 1 1 0 0 1 1 * 1 0 A IN
I/O Write 1 1 0 1 0 1 * 1 0 A OUT
RESET 1 1 1 1 1 1 1 1 1 Z IN
• 1 : High
• 0 : Low
• A : Programmable
• Z : High Impedance
• IN : Input
• OUT : Output
• * : Invalid
PIN STATUS
Tables 56 describes the status of each ping during RESET and LOW
POWER OPERATION modes.
UM005004-0918
Z8018x
289
Table 56. Pin Status During RESET and LOW POWER OPERATION Modes
Pin Status in Each Operation Mode
SYSTEM
Symbol Pin Function RESET SLEEP IOSTOP STOP
WAIT — IN (N) IN (N) IN (A) IN (N)

BUSACK — 1 OUT OUT OUT
BUSREQ — IN (N) IN (A) IN (A) IN (A)
RESET — 0 IN (A) IN (A) IN (A)
NMI — IN (N) IN (A) IN (A) IN (A)
INT0 — IN (N) IN (A) IN (A) IN (A)
ST — 1 1 OUT 1
A0–A17, A19 — Z 1 A 1
A18/TOUT A18 Z 1 A 1
TOUT Z OUT H H
D0–D7 — Z Z A Z
RTS0 — 1 H OUT H
CTS0 — IN (N) IN (A) IN (N) N (N)
DCD0 — IN (N) IN (A) IN (N) IN (N)
TXA0 — 1 OUT H H
RXA0 — IN (N) IN (A) IN (N) IN (N)
CKA0/DREQ0 CKA0 Z OUT Z Z
(Internal Clock Mode)
UM005004-0918
Z8018x
290
Table 56. Pin Status During RESET and LOW POWER OPERATION Modes (Continued)
SYSTEM
CKA0 Z IN (A) IN (N) IN (N)

(External Clock Mode)
DREQ0 Z IN (N) IN (A) IN (N)
TXA1 — 1 OUT H H
RXA1 — IN (N) IN (A) IN (N) IN (N)
CKA1/TEND0 CKA1 Z OUT Z Z
CKA1 Z IN (A) IN (N) IN (N)
TEND0 Z 1 OUT 1
TXS — 1 OUT H H
RXS/CTS1 RXS IN (N) IN (A) IN (N) IN (N)
CTS1 IN (N) IN (A) IN (N) IN (N)
CKS CKS Z OUT 1 1
CKS Z IN (A) Z Z
DREQ1 — IN (N) IN (N) IN (A) IN (N)
TEND1 — 1 1 OUT 1
HALT — 1 0 OUT 0
RFSH — 1 1 OUT 1
IORQ — 1 1 OUT 1
UM005004-0918
Z8018x
291
Table 56. Pin Status During RESET and LOW POWER OPERATION Modes (Continued)
SYSTEM
MREQ — 1 1 OUT 1
E — 0 E Clock ← ←
Output
M1 — 1 1 OUT 1
WR — 1 1 OUT 1
RD — 1 1 OUT 1
Phi — Phi Clock ← ← ←
Output
• 1: HIGH 0: LOW A: Programmable Z: High Impedance

• IN (A): Input (Active) IN (N): Input (Not active) OUT: Output
• H: Holds the previous state
• ←: same as the left
UM005004-0918
Z8018x
292
UM005004-0918
Z8018x
293
I/O Registers
INTERNAL I/O REGISTERS
By programming IOA7 and IOA6 as the I/O control register, internal I/O
register addresses are relocatable within ranges from 0000H to 00FFH in
the I/O address space.
Table 57. Internal I/O Registers
Register Mnemonics Address Remarks

ASCI Control Register A CNTLA0 0 0 MPBR/
MPE RE TE RTS0 MOD2 MOD1 MOD0
Channel 0: bit EFR
during RESET 0 0 0 1 invalid 0 0 0
MODE Selection
Multi Processor Bit Receive/
1 Reset
Error Flag
Request to Send
Transmit Enable
Receive Enable
Multi Processor Enable
ASCI Control Register A CNTLA1 0 1 MPBR/

bit MPE RE TE CKA1D MOD2 MOD1 MOD0
Channel 1: EFR
during RESET 0 0 0 1 invalid 0 0 0
MODE Selection
Multi Processor Bit Receive/
Error Flag Reset
CKA1 Disable
Transmit Enable
Receive Enable
Multi Processor Enable
MOD 2 1 0
0 0 0 Start + 7 bit Data + 1 Stop
0 1 0 Start + 7 bit Data + Parity + 1 Stop
UM005004-0918
Z8018x
294
Table 57. Internal I/O Registers (Continued)

ASCI Control Register B CNTLB0 0 2 CTS/
MPBT MP PEO DR SS2 SS1 SS0
Channel 0: bit PS
during RESET invalid 0 0 0 1 1 1
*
Clock Source and

Divide Ratio Speed Select
Parity Even or Odd

Clear to send/Prescale
Multi Processor
Multi Processor Bit Transmit
* CTS: Depending on the condition 0f CTS Pin.

PS: Cleared to 0.
ASCI Control Register B CNTLB1 0 3

Channel 1: CTS/
bit MPBT MP PEO DR SS2 SS1 SS0
PS
during RESET invalid 0 0 0 0 1 1 1
Clock Source and

Speed Select
Divide Ratio
Parity Even or Odd

Clear to Send/Prescale
Multi Processor
Multi Processor Bit Transmit
General PS=0 PS=1

divide ratio (divide ratio=10) (divide ratio=30)
SS2 1 0 DR=0 (X 16) DR=1 (X 64) DR=0 (X 16) DR=1 (X 64)
0 0 0 φ ÷ 160 φ ÷ 640 φ ÷ 480 φ ÷ 1920
0 0 1 ÷ 320 ÷ 1280 ÷ 960 ÷ 3840
0 1 0 ÷ 640 ÷ 2560 ÷ 1920 ÷ 7680
0 1 1 ÷ 1280 ÷ 5120 ÷ 3840 ÷ 15360
1 0 0 ÷ 2560 ÷ 10240 ÷ 7680 ÷ 30720
1 0 1 ÷ 5120 ÷ 20480 ÷ 15360 ÷ 61440
1 1 0 ÷ 10240 ÷ 40960 ÷ 30720 ÷ 122880
1 1 1 External clock (frequency < φ ÷ 40)
UM005004-0918
Z8018x
295

ASCI Status Channel 0: STAT0 0 4
RDRF OVRN PE FE RIE DCD0 TDRE TIE
bit
during RESET 0 0 0 0 invalid * ** 0

Transmit Interrupt Enable

Transmit Data Register Empty
Data Carrier Detect
Receive Interrupt Enable
Framing Error
Parity Error
Overrun Error TDRE
** CTS0 Pin
Receive Data Register Full
L 1
* DCD0: Depending on the condition of DCD0 Pin. H 0
ASCI Status Channel 1: STAT1 0 5

RDRF OVRN PE FE RIE CTS1E TDRE TIE
bit
during RESET 0 0 0 0 0 0 1 0
Transmit Interrupt Enable

Transmit Data Register Empty
CTS1 Enable
Receive Interrupt Enable
Framing Error
Parity Error
Overrun Error
Receive Data Register Full
UM005004-0918
Z8018x
296

ASCI Transmit Data TDR0 0 6
Register Channel 0:
ASCI Transmit Data TDR1 0 7

Register Channel 1:
ASCI Receive Data TSR0 0 8

Register Channel 0:
ASCI Receive Data TSR1 0 9

Register Channel 1:
CSI/O Control Register: CNTR 0 A bit EF EIE RE TE — SS2 SS1 SS0
during RESET 0 0 0 0 1 1 1 1
R/W R R/W R/W R/W R/W R/W R/W
Speed Select
Transmit Enable
Receive Enable
End Interrupt Enable
End Flag
SS2 1 0 Baud Rate SS2 1 0 Baud Rate

0 0 0 Phi ÷ 20 1 0 0 Phi ÷ 320
0 0 1 ÷ 40 1 0 1 ÷ 640
0 1 0 ÷ 80 1 1 0 ÷ 1280
0 1 1 ÷ 160 1 1 1 External
frequency < ÷ 20)
UM005004-0918
Z8018x
297

CSI/O Transmit/ TRDR 0 B
Receive Data Register:
Timer Data Register TMDR0L 0 C

Channel 0L:
Timer Data Register TMDR0H 0 D

Channel 0H:
Timer Reload Register RLDR0L 0 E

Channel 0L:
Timer Reload Register RLDR0H 0 F

Channel 0H:
Timer Control Register TCR 1 0 bit

TF1 TF0 TE1 TE0 TOC1 TOC0 TDE1 TDE0
Channel 0L: 0 0 0 0 0 0 0 0
during RESET
R/W R R R/W R/W R/W R/W R/W R/W
Timer Down
Count Enable 1,0
Timer Output Control 1,0
Timer Interrupt Enable 1,0
Timer Interrupt Flag 1,0
TOC1,0 A18/TOUT
00 Inhibited
01 Toggle
10 0
11 1
UM005004-0918
Z8018x
298

Timer Data Register TMDR1L 1 4
Channel 1L:
Timer Data Register TMDR1H 1 5
Channel 1H:
Timer Reload Register RLDR1L 1 6
Channel 1L
Timer Reload Register RLDR1H 1 7
Channel 1H:
Free Running Counter: FRC 1 8 Read only
DMA Source Address SAR0L 2 0
Register Channel 0L:
DMA Source Address SAR0H 2 1
Register Channel 0H:
DMA Source Address SAR0B 2 2 Bits 0-2 (3) are used for SAR0B DMA Transfer Request
A19*, A18, A17, A16
Register Channel 0B:
X X 0 0 DREQ0 (external)
DMA Destination Address DAR0L 2 3 X X 0 1 RDR0 (ASCI0)
Register Channel 0L: X X 1 0 RDR1 (ASCI1)
X X 1 1
DMA Destination Address DAR0H 2 4 Not used
Register Channel 0H:

DMA Destination Address DAR0B 2 5 Bits 0-2 (3) are used for DAR0B DMA Transfer Request
A19*, A18, A17, A16
Register Channel 0B:
X X 0 0 DREQ0 (external)
DMA Byte Count Register BCROL 2 6 X X 0 1 TDR0 (ASCI0)
Channel 0L: X X 1 0 TDR1 (ASCI1)
X X 1 1 Not used
DMA Byte Count Register BCROH 2 7
Channel 0H:
DMA Memory Address MAR1L 2 8
Register
Channel 1L:
DMA Memory Address MAR1H 2 9
Register
Channel 1H:
* In the R1 and Z mask, these DMAC registers are expanded from 4 bits to 3 bits in the
package version of CP-68.
UM005004-0918
Z8018x
299

DMA Memory Address MAR1B 2 A Bits 0 - 2 are used for MAR1B
Register
Channel 1B:
DMA I/O Address Register IAR1L 2 B

Channel 1L:
DMA I/O Address Register IAR1H 2 C

Channel 1H
DMA Byte Count Register BCR1L 2 E

Channel 1L:
DMA Byte Count Register

Channel 1H: BCR1H 2 F
DMA Status Register: DSTAT 3 0 bit DE1 DE0 DWE1 DWE0 DIE1 DIE0 — DME
during RESET 0 R/W

0 1 1 0 0 1 0
R/W R/W R/W W W R/W R
DMA Master enable
DMA Interrupt Enable 1,0
DMA Enable Bit Write Enable 1,0

DMA enable ch 1,0
DMA Mode Register: DMODE 3 1
bit — — DM1 DM0 SM1 SM0 MMOD —
during RESET 1 1 0 0 0 0 0 1
R/W R/W R/W R/W R/W R/W
Memory MODE select
Ch 0 Source Mode 1,0

Ch 0 Destination Mode 1,0
DM1,0 Destination Address SM1,0 Source Address

0 0 M DAR0+1 0 0 M SAR0+1
0 1 M DAR0-1 0 1 M SAR0-1
1 0 M DAR0 fixed 1 0 M SAR0 fixed
1 1 I/O DAR0 fixed 1 1 I/O SAR0 fixed
MMOD Mode
0 Cycle Steal Mode
1 Burst Mode
UM005004-0918
Z8018x
300

MMU Common Base CBR 3 8
CB7 CB6 CB5 CB4 CB3 CB2 CB1 CB0
Register: bit
during RESET 0 0 0 0 0 0 0 0
MMU Common Base Register
MMU Bank Base Register BBR 3 9

BB7 BB6 BB5 BB4 BB3 BB2 BB1 BB0
bit
during RESET 0 0 0 0 0 0 0 0
MMU Bank Base Register
MMU Common/Bank CBAR 3 A

CA3 CA2 CA1 CA0 BA3 BA2 BA1 BA0
Register bit
during RESET 1 1 1 1 0 0 0 0
MMU Bank
Area Register
MMU Common Area Register
Operation Mode Control OMCR 3 E bit

MIE MITE IOC — — — — —
Register 1 1 1 1 1 1 1 1
during RESET
R/W R/W W R/W
I/O Compatibility
M1 Temporary Enable
M1 Enable
I/O Control Register: ICR 3 F

IOA7 IOA6 IOSTP — — — — —
bit
during RESET 0 0 0 1 1 1 1 1
R/W R/W R/W R/W

I/O Stop
I/O Address
UM005004-0918
Z8018x
301

DMA/WAIT Control DCNTL 3 2
Register: MWI1 MWI0 IWI1 IWI0 DMS1 DMS0 DIMA1 DIMA0
bit
during RESET 1 1 1 1 0 0 0 0
DMA Ch 1
I/O Memory
Mode Select
DREQi Select, i=1,0
I/O Wait Insertion
Memory Wait Insertion
The number of The number of

MWI1,0 wait states IWI1,0 wait states
00 0 00 0
01 1 01 2
10 2 10 3
11 3 11 4
DMSi Sense
1 Edge sense
0 Level sense
DIM1,0 Transfer Mode Address Increment/Decrement
00 M→I/O MAR1+1 IAR1 fixed

01 M→I/O MAR1-1 IAR1 fixed
10 I/O→M IAR1 fixed MAR1+1
11 I/O→M IAR1 fixed MAR1-1
UM005004-0918
Z8018x
302

Interrupt Vector Low IL 3 3
IL7 —
Register bit
IL6 IL5 — — — —
during RESET 0 0 0 0 0 0 0 0
R/W R/W R/W R/W
Interrupt Vector Low
INT/TRAP Control ITC 3 4 TRAP UF0 — — — ITE2 ITE1 ITE0

bit
Register
during RESET 0 0 1 1 1 0 0 0
R/W R/W R R/W R/W R/W
INT Enable 2,1,0

Unidentified Fetch Object
TRAP
REFE — — — —
Refresh Control Register: RCR 3 6 bit
REFW CYC1 CYC0
during RESET 1 1 1 1 1 1 0 0
R/W R/W R/W R/W R/W
Cycle select
Refresh Wait State
Refresh Enable
Interval of Refresh Cycle

00 10 states
01 20
10 40
11 80
UM005004-0918
Z8018x
303
ORDERING INFORMATION
Codes
• Package
P = Plastic Dip
V = Plastic Chip Carrier
F = Quad Flat Pack
• Temperature
S = 0°C to +70°C
E = -40°C to 100°C
• Speed
06 = 6 MHz
08 = 8 MHz
10 = 10 MHz
• Environmental
C = Plastic Standard
• Example
Z8018008PSC is an 80180 8 MHz, Plastic DIP, 0°C to
70°C, Plastic Standard Flow.
Z 80180 08 P S C
Environmental Flow
Temperature
Package
Speed
Product Number
ZiLOG Prefix
UM005004-0918
Z80 Microprocessors
Z80 CPU
User Manual
UM008011-0816
Copyright ©2016 Zilog, Inc. All rights reserved.

www.zilog.com
Z80 CPU
User Manual
ii
Warning: DO NOT USE THIS PRODUCT IN LIFE SUPPORT SYSTEMS.
LIFE SUPPORT POLICY

ZILOG’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE
SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS PRIOR WRITTEN APPROVAL OF
THE PRESIDENT AND GENERAL COUNSEL OF ZILOG CORPORATION.
As used herein
Life support devices or systems are devices which (a) are intended for surgical implant into the body, or (b)
support or sustain life and whose failure to perform when properly used in accordance with instructions for
use provided in the labeling can be reasonably expected to result in a significant injury to the user. A criti-
cal component is any component in a life support device or system whose failure to perform can be reason-
ably expected to cause the failure of the life support device or system or to affect its safety or effectiveness.
Document Disclaimer
©2016 Zilog, Inc. All rights reserved. Information in this publication concerning the devices, applications,
or technology described is intended to suggest possible uses and may be superseded. ZILOG, INC. DOES
NOT ASSUME LIABILITY FOR OR PROVIDE A REPRESENTATION OF ACCURACY OF THE
INFORMATION, DEVICES, OR TECHNOLOGY DESCRIBED IN THIS DOCUMENT. ZILOG ALSO
DOES NOT ASSUME LIABILITY FOR INTELLECTUAL PROPERTY INFRINGEMENT RELATED
IN ANY MANNER TO USE OF INFORMATION, DEVICES, OR TECHNOLOGY DESCRIBED
HEREIN OR OTHERWISE. The information contained within this document has been verified according
to the general principles of electrical and mechanical engineering.
Z80, Z180, Z380 and Z80382 are trademarks or registered trademarks of Zilog, Inc. All other product or
service names are the property of their respective owners.
UM008011-0816
Z80 CPU
User Manual
iii
Revision History
Each instance in the following revision history table reflects a change to this document
from its previous version. For more details, refer to the corresponding pages provided in
the table.
Revision
Date Level Description Page
Aug 11 Made formatting changes for better readability. 39, 40, 41
2016
Aug 10 Added Instruction Notation Summary; corrected typos and 39, 42, 123, 126, 136,
2016 errors 242,
May 09 Corrected typos and errors. 126, 132, 133, 136, 141,
2016 192, 317
Jan 08 Corrected typos and errors. 46, 77, 103, 112, 122,
2016 130, 132, 138, 161,
207,221, 224, 227, 233,
253, 255, 263, 296
Jul 07 Corrected typos in POP qq description. 119
2015
Jul 06 Updated to Zilog style and to incorporate customer 65, 126
2014 suggestions, including a correction to the Z80 Status
Indicator Flags table, bit 4, and a correction to the EXX
instruction at bit 0.
Feb 05 Corrected the hex code for the RLCA instruction; 55, 205
2005 corrected illustration for the Rotate and Shift Group RLCA
instruction.
Dec 04 Corrected discrepancies in the bit patterns for IM 0, IM 1 184, 185, 186
2004 and IM 2 instructions.
UM008011-0816 Revision History

Z80 CPU
User Manual
iv
Revision History UM008011-0816

Z80 CPU
User Manual
Table of Contents
Revision History. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .iii
Table of Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . v
List of Figures. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . xi
List of Tables . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .xiii
Architectural Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
CPU Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2
Special-Purpose Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2
General Purpose Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
Arithmetic Logic Unit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
Instruction Register and CPU Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
Pin Functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
Instruction Fetch . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
Memory Read Or Write . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
Input or Output Cycles . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
Bus Request/Acknowledge Cycle . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
Interrupt Request/Acknowledge Cycle . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
Nonmaskable Interrupt Response . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
HALT Exit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
Power-Down Acknowledge Cycle . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
Power-Down Release Cycle . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
Interrupt Response . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
Interrupt Enable/Disable . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
CPU Response . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
Hardware and Software Implementation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
Minimum System Hardware . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
Adding RAM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
Memory Speed Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
Interfacing Dynamic Memories . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
Software Implementation Examples . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
Specific Z80 Instruction Examples . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
Programming Task Examples . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
Z80 CPU Instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
Instruction Types . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
UM008011-0816 Table of Contents

Z80 CPU
User Manual
vi
Addressing Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
Immediate Addressing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
Immediate Extended Addressing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
Modified Page Zero Addressing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
Relative Addressing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
Extended Addressing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
Indexed Addressing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
Register Addressing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
Implied Addressing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
Register Indirect Addressing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
Bit Addressing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38
Addressing Mode Combinations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38
Instruction Notation Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
Instruction Op Codes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40
Load and Exchange . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41
Block Transfer and Search . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47
Arithmetic and Logical . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49
Rotate and Shift . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53
Bit Manipulation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55
Jump, Call, and Return . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58
Input/Output . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61
CPU Control Group . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63
Z80 Instruction Set . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65
Z80 Assembly Language . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65
Z80 Status Indicator Flags . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65
Carry Flag . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66
Add/Subtract Flag . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66
Decimal Adjust Accumulator Flag . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67
Parity/Overflow Flag . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67
Half Carry Flag . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68
Zero Flag . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68
Sign Flag . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69
Z80 Instruction Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69
LD r, r' . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71
LD r,n . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72
LD r, (HL) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74
LD r, (IX+d) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75
LD r, (IY+d) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77
LD (HL), r . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79
LD (IX+d), r . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81
Table of Contents UM008011-0816

Z80 CPU
User Manual
vii
LD (IY+d), r . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83
LD (HL), n . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85
LD (IX+d), n . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86
LD (IY+d), n . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87
LD A, (BC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88
LD A, (DE) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89
LD A, (nn) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90
LD (BC), A . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 91
LD (DE), A . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 92
LD (nn), A . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 93
LD A, I . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 94
LD A, R . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 95
LD I,A . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96
LD R, A . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 97
LD dd, nn . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 99
LD IX, nn . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100
LD IY, nn . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 101
LD HL, (nn) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 102
LD dd, (nn) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 103
LD IX, (nn) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 105
LD IY, (nn) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 106
LD (nn), HL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 107
LD (nn), dd . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 108
LD (nn), IX . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 110
LD (nn), IY . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 111
LD SP, HL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 112
LD SP, IX . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 113
LD SP, IY . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 114
PUSH qq . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 115
PUSH IX . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 117
PUSH IY . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 118
POP qq . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 119
POP IX . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 121
POP IY . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 122
EX DE, HL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 124
EX AF, AF′ . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 125
EXX . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 126
EX (SP), HL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 127
EX (SP), IX . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 128
EX (SP), IY . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 129
LDI . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 130

Z80 CPU
User Manual
viii
LDIR . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 132
LDD . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 134
LDDR . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 136
CPI . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 138
CPIR . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 139
CPD . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 141
CPDR . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 142
ADD A, r . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 145
ADD A, n . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 147
ADD A, (HL) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 148
ADD A, (IX + d) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 149
ADD A, (IY + d) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 150
ADC A, s . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 151
SUB s . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 153
SBC A, s . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 155
AND s . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 157
OR s . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 159
XOR s . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 161
CP s . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 163
INC r . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 165
INC (HL) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 167
INC (IX+d) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 168
INC (IY+d) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 169
DEC m . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 170
DAA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 173
CPL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 175
NEG . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 176
CCF . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 178
SCF . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 179
NOP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 180
HALT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 181
DI . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 182
EI . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 183
IM 0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 184
IM 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 185
IM 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 186
ADD HL, ss . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 188
ADC HL, ss . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 190
SBC HL, ss . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 192
ADD IX, pp . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 194
ADD IY, rr . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 196

Z80 CPU
User Manual
ix
INC ss . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 198
INC IX . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 199
INC IY . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 200
DEC ss . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 201
DEC IX . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 202
DEC IY . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 203
RLCA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 205
RLA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 207
RRCA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 209
RRA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 211
RLC r . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 213
RLC (HL) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 215
RLC (IX+d) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 217
RLC (IY+d) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 219
RL m . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 221
RRC m . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 224
RR m . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 227
SLA m . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 230
SRA m . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 233
SRL m . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 236
RLD . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 238
RRD . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 240
BIT b, r . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 243
BIT b, (HL) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 245
BIT b, (IX+d) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 247
BIT b, (IY+d) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 249
SET b, r . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 251
SET b, (HL) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 253
SET b, (IX+d) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 255
SET b, (IY+d) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 257
RES b, m . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 259
JP nn . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 262
JP cc, nn . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 263
JR e . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 265
JR C, e . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 267
JR NC, e . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 269
JR Z, e . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 271
JR NZ, e . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 273
JP (HL) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 275
JP (IX) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 276
JP (IY) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 277

Z80 CPU
User Manual
DJNZ, e . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 278
CALL nn . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 281
CALL cc, nn . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 283
RET . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 285
RET cc . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 286
RETI . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 288
RETN . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 290
RST p . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 292
IN A, (n) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 295
IN r (C) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 296
INI . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 298
INIR . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 300
IND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 302
INDR . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 304
OUT (n), A . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 306
OUT (C), r . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 307
OUTI . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 309
OTIR . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 311
OUTD . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 313
OTDR . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 315
Customer Support. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 317

Z80 CPU
User Manual
xi
List of Figures
Figure 1. Z80 CPU Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
Figure 2. CPU Register Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2
Figure 3. Z80 CPU I/O Pin Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
Figure 4. Basic CPU Timing Example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
Figure 5. Instruction Op Code Fetch . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
Figure 6. Memory Read or Write Cycle . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
Figure 7. Input or Output Cycles . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
Figure 8. Bus Request/Acknowledge Cycle . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
Figure 9. Interrupt Request/Acknowledge Cycle . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
Figure 10. Nonmaskable Interrupt Request Operation . . . . . . . . . . . . . . . . . . . . . . . . . 14
Figure 11. HALT Exit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
Figure 12. Power-Down Acknowledge . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
Figure 13. Power-Down Release Cycle, #1 of 3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
Figure 16. Interrupt Enable Flip-Flops . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
Figure 17. Mode 2 Interrupt Response Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
Figure 18. Minimum Z80 Computer System . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
Figure 19. ROM and RAM Implementation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
Figure 20. RAM Memory Space Organization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
Figure 21. Adding One Wait State to an M1 Cycle . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
Figure 22. Adding One Wait State to Any Memory Cycle . . . . . . . . . . . . . . . . . . . . . . 24
Figure 23. Interfacing Dynamic RAM Memory Spaces . . . . . . . . . . . . . . . . . . . . . . . . 25
Figure 24. Shifting of BCD Digits/Bytes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
Figure 25. Immediate Addressing Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
Figure 26. Immediate Extended Addressing Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
Figure 27. Modified Page Zero Addressing Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
Figure 28. Relative Addressing Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
UM008011-0816 List of Figures

Z80 CPU
User Manual
xii
Figure 29. Extended Addressing Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36

Figure 30. Indexed Addressing Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
Figure 31. Register Indirect Addressing Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
Figure 32. Example of a 3-Byte Load Indexed Instruction Sequence . . . . . . . . . . . . . 43
Figure 33. Example of a 3-Byte Load Extended Instruction Sequence . . . . . . . . . . . . 44
Figure 34. Example of a 2-Byte Load Immediate Instruction Sequence . . . . . . . . . . . 44
Figure 35. Example of a 4-Byte Load Indexed/Immediate Instruction Sequence . . . . 44
Figure 36. Example of a 16-Bit Load Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46
Figure 37. Example of a 2-Byte Load Indexed/Immediate Instruction Sequence . . . . 47
Figure 38. Example of an AND Instruction Sequence . . . . . . . . . . . . . . . . . . . . . . . . . 51
Figure 39. Rotates and Shifts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54
Figure 40. Example of an Unconditional Jump Sequence . . . . . . . . . . . . . . . . . . . . . . 58
Figure 41. Mode 2 Interrupt Command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64
List of Figures UM008011-0816

Z80 CPU
User Manual
xiii
List of Tables
Table 1. Interrupt Enable/Disable, Flip-Flops . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
Table 2. Bubble Listing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
Table 3. Multiply Listing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
Table 4. Instruction Notation Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
Table 5. Hex, Binary, Decimal Conversion Table . . . . . . . . . . . . . . . . . . . . . . . . . . . 40
Table 6. 8-Bit Load Group LD . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42
Table 7. 16-Bit Load Group LD, PUSH, and POP . . . . . . . . . . . . . . . . . . . . . . . . . . 45
Table 8. Exchanges EX and EXX . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47
Table 9. Block Transfer Group . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48
Table 10. Block Search Group . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49
Table 11. 8-Bit Arithmetic and Logic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50
Table 12. General-Purpose AF Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51
Table 13. 16-Bit Arithmetic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52
Table 14. Bit Manipulation Group . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55
Table 15. Jump, Call, and Return Group . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59
Table 16. Example Usage of the DJNZ Instruction . . . . . . . . . . . . . . . . . . . . . . . . . . . 60
Table 17. Restart Group . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61
Table 18. Input Group . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62
Table 19. 8-Bit Arithmetic and Logic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63
Table 20. Miscellaneous CPU Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64
Table 21. Flag Register Bit Positions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65
Table 22. Flag Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66
Table 23. Half Carry Flag Add/Subtract Operations . . . . . . . . . . . . . . . . . . . . . . . . . . 68
UM008011-0816 List of Tables

Z80 CPU
User Manual
xiv
List of Tables UM008011-0816

Z80 CPU
User Manual
Architectural Overview
Zilog’s Z80 CPU family of components are fourth-generation enhanced microprocessors
with exceptional computational power. They offer higher system throughput and more
efficient memory utilization than comparable second and third-generation microproces-
sors. The speed offerings from 6–20 MHz suit a wide range of applications which migrate
software. The internal registers contain 208 bits of read/write memory that are accessible
to the programmer. These registers include two sets of six general-purpose registers which
can be used individually as either 8-bit registers or as 16-bit register pairs. In addition,
there are two sets of Accumulator and Flag registers.
The Z80 CPU also contains a Stack Pointer, Program Counter, two index registers, a
refresh register, and an interrupt register. The CPU is easy to incorporate into a system
because it requires only a single +5V power source. All output signals are fully decoded
and timed to control standard memory or peripheral circuits; the Z80 CPU is supported by
an extensive family of peripheral controllers.
Figure 1 shows the internal architecture and major elements of the Z80 CPU.
Data Bus
Control
Inst. Internal Data Bus

Register ALU
I
n
13
CPU and
System CPU CPU
Control Control Registers
Signals
Address
Control
16-Bit
+5V GND CLK Address Bus
Figure 1. Z80 CPU Block Diagram
UM008011-0816 Architectural Overview

Z80 CPU
User Manual
CPU Register
The Z80 CPU contains 208 bits of read/write memory that are available to the program-
mer. Figure 2 shows how this memory is configured to eighteen 8-bit registers and four
16-bit registers. All Z80 CPU’s registers are implemented using static RAM. The registers
include two sets of six general-purpose registers that can be used individually as 8-bit reg-
isters or in pairs as 16-bit registers. There are also two sets of Accumulator and Flag regis-
ters and six special-purpose registers.
Main Register Set Alternate Register Set
Accumulator Flags Accumulator Flags

A F A' F'
B C B' B' General
D E D' E' Purpose
Registers
H L H' L'
Interrupt Vector Memory Refresh

I R
Index Register IX Special
Index Register IY Purpose
Registers
Stack Pointer SP
Program Counter PC
Figure 2. CPU Register Configuration
Special-Purpose Registers
Program Counter (PC). The program counter holds the 16-bit address of the current
instruction being fetched from memory. The Program Counter is automatically incre-
mented after its contents are transferred to the address lines. When a program jump occurs,
the new value is automatically placed in the Program Counter, overriding the incrementer.
Stack Pointer (SP). The stack pointer holds the 16-bit address of the current top of a stack
located anywhere in external system RAM memory. The external stack memory is orga-
nized as a last-in first-out (LIFO) file. Data can be pushed onto the stack from specific
CPU registers or popped off of the stack to specific CPU registers through the execution of
PUSH and POP instructions. The data popped from the stack is always the most recent
data pushed onto it. The stack allows simple implementation of multiple level interrupts,
unlimited subroutine nesting and simplification of many types of data manipulation.
Architectural Overview UM008011-0816

Z80 CPU
User Manual
Two Index Registers (IX and IY). The two independent index registers hold a 16-bit base
address that is used in indexed addressing modes. In this mode, an index register is used as
a base to point to a region in memory from which data is to be stored or retrieved. An addi-
tional byte is included in indexed instructions to specify a displacement from this base.
This displacement is specified as a two’s complement signed integer. This mode of
addressing greatly simplifies many types of programs, especially when tables of data are
used.
Interrupt Page Address (I) Register. The Z80 CPU can be operated in a mode in which
an indirect call to any memory location can be achieved in response to an interrupt. The I
register is used for this purpose and stores the high-order eight bits of the indirect address
while the interrupting device provides the lower eight bits of the address. This feature
allows interrupt routines to be dynamically located anywhere in memory with minimal
access time to the routine.
Memory Refresh (R) Register. The Z80 CPU contains a memory refresh counter,
enabling dynamic memories to be used with the same ease as static memories. Seven bits
of this 8-bit register are automatically incremented after each instruction fetch. The eighth
bit remains as programmed, resulting from an LD R, A instruction. The data in the refresh
counter is sent out on the lower portion of the address bus along with a refresh control sig-
nal while the CPU is decoding and executing the fetched instruction. This mode of refresh
is transparent to the programmer and does not slow the CPU operation. The programmer
can load the R register for testing purposes, but this register is normally not used by the
programmer. During refresh, the contents of the I Register are placed on the upper eight
bits of the address bus.
Accumulator and Flag Registers. The CPU includes two independent 8-bit Accumula-
tors and associated 8-bit Flag registers. The Accumulator holds the results of 8-bit arith-
metic or logical operations while the Flag Register indicates specific conditions for 8-bit
or 16-bit operations, such as indicating whether or not the result of an operation is equal to
0. The programmer selects the Accumulator and flag pair with a single exchange instruc-
tion so that it is possible to work with either pair.
General Purpose Registers

Two matched sets of general-purpose registers, each set containing six 8-bit registers, can
be used individually as 8-bit registers or as 16-bit register pairs. One set is called BC, DE,
and HL while the complementary set is called BC', DE', and HL'. At any one time, the pro-
grammer can select either set of registers to work through a single exchange command for
the entire set. In systems that require fast interrupt response, one set of general-purpose
registers and an Accumulator/Flag Register can be reserved for handling this fast routine.
One exchange command is executed to switch routines. This process greatly reduces inter-
rupt service time by eliminating the requirement for saving and retrieving register contents
in the external stack during interrupt or subroutine processing. These general-purpose reg-
UM008011-0816 General Purpose Registers

Z80 CPU
User Manual
isters are used for a wide range of applications. They also simplify programing, specifi-
cally in ROM-based systems in which little external read/write memory is available.
Arithmetic Logic Unit

The 8-bit arithmetic and logical instructions of the CPU are executed in the Arithmetic
Logic Unit (ALU). Internally, the ALU communicates with the registers and the external
data bus by using the internal data bus. Functions performed by the ALU include:
• Add
• Subtract
• Logical AND
• Logical OR
• Logical exclusive OR
• Compare
• Left or right shifts or rotates (arithmetic and logical)
• Increment
• Decrement
• Set bit
• Reset bit
• Test bit
Instruction Register and CPU Control

As each instruction is fetched from memory, it is placed in the Instruction Register and
decoded. The control sections performs this function and then generates and supplies the
control signals necessary to read or write data from or to the registers, control the ALU,
and provide required external control signals.
Pin Description
The Z80 CPU I/O pins are shown in Figure 3. The function of each pin is described in the
section that follows.

Z80 CPU
User Manual
27 30 A0
M1
31 A1
19 32
MREQ A2
20 33
System IORQ A3
21 34
Control RD A4
22 35 A5
WR
36 A6
28 37
RFSH A7 Address
38 A8 Bus
18 39 A9
HALT
40 A10
24 1
WAIT A11
2 A12
CPU Z80 CPU
Control 16 3 A13
INT
17 4 A14
NMI
5 A15
26
RESET
CPU 25
BUSRQ
Bus 23
Control BUSACK
14
D0
15 D1
CLK 6 12
D2
+5V 11 8
D3 Data
29 7 D4
GND Bus
9
D5
10 D6
13
D7
Figure 3. Z80 CPU I/O Pin Configuration
Pin Functions
A15–A0. Address Bus (output, active High, tristate). A15–A0 form a 16-bit Address Bus,
which provides the addresses for memory data bus exchanges (up to 64 KB) and for I/O
device exchanges.
BUSACK. Bus Acknowledge (output, active Low). Bus Acknowledge indicates to the
requesting device that the CPU address bus, data bus, and control signals MREQ, IORQ,
UM008011-0816 Pin Functions

Z80 CPU
User Manual
RD, and WR have entered their high-impedance states. The external circuitry can now
control these lines.
BUSREQ. Bus Request (input, active Low). Bus Request contains a higher priority than
NMI and is always recognized at the end of the current machine cycle. BUSREQ forces
the CPU address bus, data bus, and control signals MREQ, IORQ, RD, and WR to enter a
high-impedance state so that other devices can control these lines. BUSREQ is normally
wired OR and requires an external pull-up for these applications. Extended BUSREQ peri-
ods due to extensive DMA operations can prevent the CPU from properly refreshing
dynamic RAM.
D7–D0. Data Bus (input/output, active High, tristate). D7–D0 constitute an 8-bit bidirec-
tional data bus, used for data exchanges with memory and I/O.
HALT. HALT State (output, active Low). HALT indicates that the CPU has executed a
HALT instruction and is waiting for either a nonmaskable or a maskable interrupt (with
the mask enabled) before operation can resume. During HALT, the CPU executes NOPs to
maintain memory refreshes.
INT. Interrupt Request (input, active Low). An Interrupt Request is generated by I/O
devices. The CPU honors a request at the end of the current instruction if the internal soft-
ware-controlled interrupt enable flip-flop (IFF) is enabled. INT is normally wired-OR and
requires an external pull-up for these applications.
IORQ. Input/Output Request (output, active Low, tristate). IORQ indicates that the lower
half of the address bus holds a valid I/O address for an I/O read or write operation. IORQ
is also generated concurrently with M1 during an interrupt acknowledge cycle to indicate
that an interrupt response vector can be placed on the data bus.
M1. Machine Cycle One (output, active Low). M1, together with MREQ, indicates that the
current machine cycle is the op code fetch cycle of an instruction execution. M1, when
operating together with IORQ, indicates an interrupt acknowledge cycle.
MREQ. Memory Request (output, active Low, tristate). MREQ indicates that the address
bus holds a valid address for a memory read or a memory write operation.
NMI. Nonmaskable Interrupt (input, negative edge-triggered). NMI contains a higher pri-
ority than INT. NMI is always recognized at the end of the current instruction, indepen-
dent of the status of the interrupt enable flip-flop, and automatically forces the CPU to
restart at location 0066h.
RD. Read (output, active Low, tristate). RD indicates that the CPU wants to read data from
memory or an I/O device. The addressed I/O device or memory should use this signal to
gate data onto the CPU data bus.
RESET. Reset (input, active Low). RESET initializes the CPU as follows: it resets the
interrupt enable flip-flop, clears the Program Counter and registers I and R, and sets the
interrupt status to Mode 0. During reset time, the address and data bus enter a high-imped-
ance state, and all control output signals enter an inactive state. RESET must be active for
a minimum of three full clock cycles before a reset operation is complete.

Z80 CPU
User Manual
RFSH. Refresh (output, active Low). RFSH, together with MREQ, indicates that the lower
seven bits of the system’s address bus can be used as a refresh address to the system’s
dynamic memories.
WAIT. WAIT (input, active Low). WAIT communicates to the CPU that the addressed
memory or I/O devices are not ready for a data transfer. The CPU continues to enter a
WAIT state as long as this signal is active. Extended WAIT periods can prevent the CPU
from properly refreshing dynamic memory.
WR. Write (output, active Low, tristate). WR indicates that the CPU data bus contains
valid data to be stored at the addressed memory or I/O location.
CLK. Clock (input). Single-phase MOS-level clock.
Note: All signals with an overline are active Low. For example, B/W, in which word is active
Low, or B/W, in which byte is active Low.
Timing
The Z80 CPU executes instructions by stepping through a precise set of basic operations.
These operations include:
• Memory read or write
• I/O device read or write
• Interrupt acknowledge
All instructions are a series of basic operations. Each of these operations can take from
three to six clock periods to complete, or they can be lengthened to synchronize the CPU
to the speed of external devices. These clock periods are referred to as time (T) cycles, and
the operations are referred to as machine (M) cycles. Figure 4 shows how a typical instruc-
tion is a series of specific M and T cycles. In Figure 4, this instruction consists of the three
machine cycles M1, M2, and M3. The first machine cycle of any instruction is a fetch
cycle that is four, five, or six T cycles long (unless lengthened by the WAIT signal, which
is described in the next section). The fetch cycle (M1) is used to fetch the op code of the
next instruction to be executed. Subsequent machine cycles move data between the CPU
and memory or I/O devices, and they can feature anywhere from three to five T cycles
(again, they can be lengthened by wait states to synchronize external devices to the CPU).
The following paragraphs describe the timing which occurs within any of the basic
machine cycles.
During T2 and every subsequent automatic WAIT state (TW), the CPU samples the WAIT
line with the falling edge of the clock. If the WAIT line is active at this time, another
UM008011-0816 Timing
Z80 CPU
User Manual
WAIT state is entered during the following cycle. Using this technique, the read can be
lengthened to match the access time of any type of memory device. See the Input or Out-
put Cycles section on page 10 to learn more about the automatic WAIT state.
T Cycle
CLK
T1 T2 T3 T1 T2 T3 T1 T2 T3
Machine Cycle
M1 M2 M3
(Opcode Fetch) (Memory Read) (Memory Write)
Instruction Cycle
Figure 4. Basic CPU Timing Example
Instruction Fetch
Figure 5 depicts the timing during an M1 (op code fetch) cycle. The Program Counter is
placed on the address bus at the beginning of the M1 cycle. One half clock cycle later, the
MREQ signal goes active. At this time, the address to memory has had time to stabilize so
that the falling edge of MREQ can be used directly as a chip enable clock to dynamic
memories. The RD line also goes active to indicate that the memory read data should be
enabled onto the CPU data bus. The CPU samples the data from the memory space on the
data bus with the rising edge of the clock of state T3, and this same edge is used by the
CPU to turn off the RD and MREQ signals. As a result, the data is sampled by the CPU
before the RD signal becomes inactive. Clock states T3 and T4 of a fetch cycle are used to
refresh dynamic memories. The CPU uses this time to decode and execute the fetched
instruction so that no other concurrent operation can be performed.
During T3 and T4, the lower seven bits of the address bus contain a memory refresh
address and the RFSH signal becomes active, indicating that a refresh read of all dynamic
memories must be performed. To prevent data from different memory segments from
being gated onto the data bus, an RD signal is not generated during this refresh period. The
MREQ signal during this refresh period should be used to perform a refresh read of all
memory elements. The refresh signal cannot be used by itself, because the refresh address
is only guaranteed to be stable during the MREQ period.

Z80 CPU
User Manual
M1 Cycle
T1 T2 T3 T4 T1
CLK
A15 –A0 PC Refresh Address
MREQ
RD
WAIT
M1
D7–D0 IN
RFSH
Figure 5. Instruction Op Code Fetch
Memory Read Or Write

Figure 6 shows the timing of memory read or write cycles other than an op code fetch
cycle. These cycles are generally three clock periods long unless wait states are requested
by memory through the WAIT signal. The MREQ signal and the RD signal are used the
same way as in a fetch cycle. In a memory write cycle, the MREQ also becomes active
when the address bus is stable so that it can be used directly as a chip enable for dynamic
memories. The WR line is active when the data on the data bus is stable so that it can be
used directly as a R/W pulse to virtually any type of semiconductor memory. Furthermore,
the WR signal goes inactive one-half T state before the address and data bus contents are
changed so that the overlap requirements for almost any type of semiconductor memory
type is met.
UM008011-0816 Memory Read Or Write

Z80 CPU
User Manual
10
Memory Read Cycle Memory Write Cycle
T2 T3 T1 T2 T3
CLK
A15 –A0 Memory Address Memory Address
MREQ
RD
WR
D7–D0 In Data Out
WAIT
Figure 6. Memory Read or Write Cycle
Input or Output Cycles

Figure 7 shows an I/O read or I/O write operation. During I/O operations, a single wait
state is automatically inserted. The reason for this single wait state insertion is that during
I/O operations, the period from when the IORQ signal goes active until the CPU must
sample the WAIT line is short. Without this extra state, sufficient time does not exist for an
I/O port to decode its address and activate the WAIT line if a wait is required. Addition-
ally, without this wait state, it is difficult to design MOS I/O devices that can operate at
full CPU speed. During this wait state period, the WAIT request signal is sampled.
During a read I/O operation, the RD line is used to enable the addressed port onto the data
bus, just as in the case of a memory read. The WR line is used as a clock to the I/O port for
write operations.

Z80 CPU
User Manual
11
T1 T2 TW* T3 T1
CLK
A15 –A0 Port Address
IORQ
RD Read
Cycle
D7–D0 In
WAIT
WR Write
Cycle
D7–D0 Out
Figure 7. Input or Output Cycles
Note: *In Figure 7, TW is an automatically-inserted WAIT state.
Bus Request/Acknowledge Cycle

Figure 8 shows the timing for a Bus Request/Acknowledge cycle. The BUSREQ signal is
sampled by the CPU with the rising edge of the most recent clock period of any machine
cycle. If the BUSREQ signal is active, the CPU sets its address, data, and tristate control
signals to the high-impedance state with the rising edge of the next clock pulse. At that
time, any external device can control the buses to transfer data between memory and I/O
devices. (This operation is generally known as Direct Memory Access [DMA] using cycle
stealing.) The maximum time for the CPU to respond to a bus request is the length of a
machine cycle and the external controller can maintain control of the bus for as many
clock cycles as is required. If long DMA cycles are used, and dynamic memories are used,
the external controller also performs the refresh function. This situation only occurs if
UM008011-0816 Bus Request/Acknowledge Cycle

Z80 CPU
User Manual
12
large blocks of data are transferred under DMA control. During a bus request cycle, the
CPU cannot be interrupted by either an NMI or an INT signal.
Any M Cycle Bus Available Status
Last T State Tx Tx Tx T1
CLK
BUSREQ
Sample Sample
BUSACK
A15 –A0
D7–D0
MREQ, RD
WR. IORQ, Floating
RFSH
Figure 8. Bus Request/Acknowledge Cycle
Interrupt Request/Acknowledge Cycle

Figure 9 shows the timing associated with an interrupt cycle. The CPU samples the inter-
rupt signal (INT) with the rising edge of the final clock at the end of any instruction. The
signal is not accepted if the internal CPU software controlled interrupt enable flip-flop is
not set or if the BUSREQ signal is active. When the signal is accepted, a special M1 cycle
is generated. During this special M1 cycle, the IORQ signal becomes active (instead of the
normal MREQ) to indicate that the interrupting device can place an 8-bit vector on the
data bus. Two wait states are automatically added to this cycle. These states are added so
that a ripple priority interrupt scheme can be easily implemented. The two wait states
allow sufficient time for the ripple signals to stabilize and identify which I/O device must
insert the response vector. Refer to the Interrupt Response section on page 17 to learn
more about how the interrupt response vector is utilized by the CPU.

Z80 CPU
User Manual
13
Last M Cycle of Instruction M1
Last T State T1 T2 TW* TW* T3
CLK
INT
A15 –A0 PC Refresh
M1
MREQ
IORQ
D7–D0 In
WAIT
RD
Figure 9. Interrupt Request/Acknowledge Cycle
Nonmaskable Interrupt Response

Figure 10 shows the request/acknowledge cycle for the nonmaskable interrupt. This signal
is sampled at the same time as the interrupt line, but this line takes priority over the normal
interrupt and it cannot be disabled under software control. Its usual function is to provide
immediate response to important signals such as an impending power failure. The CPU
response to a nonmaskable interrupt is similar to a normal memory read operation. The
only difference is that the contents of the data bus are ignored while the processor auto-
matically stores the Program Counter in the external stack and jumps to address 0066h.
The service routine for the nonmaskable interrupt must begin at this location if this inter-
rupt is used.
UM008011-0816 Nonmaskable Interrupt Response

Z80 CPU
User Manual
14
Last M Cycle M1
Last T State T1 T2 T3 T4 T1
CLK
NMI
A15 –A0 PC Refresh
M1
MREQ
RD
RFSH
Figure 10. Nonmaskable Interrupt Request Operation
HALT Exit
When a software HALT instruction is executed, the CPU executes NOPs until an interrupt
is received (either a nonmaskable or a maskable interrupt while the interrupt flip-flop is
enabled). The two interrupt lines are sampled with the rising clock edge during each T4
state as depicted in Figure 11. If a nonmaskable interrupt is received or a maskable inter-
rupt is received and the interrupt enable flip-flop is set, then the HALT state is exited on
the next rising clock edge. The following cycle is an interrupt acknowledge cycle corre-
sponding to the type of interrupt that was received. If both are received at this time, then
the nonmaskable interrupt is acknowledged because it is the highest priority. The purpose
of executing NOP instructions while in the HALT state is to keep the memory refresh sig-
nals active. Each cycle in the HALT state is a normal M1 (fetch) cycle except that the data
received from the memory is ignored and an NOP instruction is forced internally to the
CPU. The HALT acknowledge signal is active during this time indicating that the proces-
sor is in the HALT state.

Z80 CPU
User Manual
15
M1 M1
T4 T1 T2 T3 T4 T1 T2
CLK
HALT
RD or
NMI
Figure 11. HALT Exit
Note: The HALT instruction is repeated during the memory cycle shown in Figure 11.
Power-Down Acknowledge Cycle

When the clock input to the Z80 CPU is stopped at either a High or Low level, the Z80
CPU stops its operation and maintains all registers and control signals. However, ICC2
(standby supply current) is guaranteed only when the system clock is stopped at a Low
level during T4 of the machine cycle following the execution of the HALT instruction.
The timing diagram for the power-down function (when implemented with the HALT
instruction) is shown in Figure 12.
T1 T2 T3 T4 T1 T2 T3 T4
CLK
M1
HALT
Figure 12. Power-Down Acknowledge
UM008011-0816 Power-Down Acknowledge Cycle

Z80 CPU
User Manual
16
Power-Down Release Cycle

The system clock must be supplied to the Z80 CPU to release the power-down state. When
the system clock is supplied to the CLK input, the Z80 CPU restarts operations from the
point at which the power-down state was implemented. The timing diagrams for the
release from power-down mode are featured in Figures 13 through 15. When the HALT
instruction is executed to enter the power-down state, the Z80 CPU also enters the HALT
state. An interrupt signal (either NMI or ANT) or a RESET signal must be applied to the
CPU after the system clock is supplied to release the power-down state.
T1 T2 T3 T4 T1
CLK
NMI
M1
HALT
Figure 13. Power-Down Release Cycle, #1 of 3
T1 T2 T3 T4
CLK
RESET
M1
HALT

Z80 CPU
User Manual
17
T1 T2 T3 T4 T1 T2 TWA TWA
CLK
INT
M1
HALT
Interrupt Response
An interrupt allows peripheral devices to suspend CPU operation and force the CPU to
start a peripheral service routine. This service routine usually involves the exchange of
data, status, or control information between the CPU and the peripheral. When the service
routine is completed, the CPU returns to the operation from which it was interrupted.
Interrupt Enable/Disable
The Z80 CPU contains two interrupt inputs: a software maskable interrupt (INT) and a
nonmaskable interrupt (NMI). The nonmaskable interrupt cannot be disabled by the pro-
grammer and is accepted when a peripheral device requests it. This interrupt is generally
reserved for important functions that can be enabled or disabled selectively by the pro-
grammer. This routine allows the programmer to disable the interrupt during periods when
the program contains timing constraints that wont allow interrupt. In the Z80 CPU, there is
an interrupt enable flip-flop (IFF) that is set or reset by the programmer using the Enable
Interrupt (EI) and Disable Interrupt (DI) instructions. When the IFF is reset, an interrupt
cannot be accepted by the CPU.
The two enable flip-flops are IFF1 and IFF2, as depicted in Figure 16.
IFF1 IFF2
Disables interrupts Temporary storage
from being accepted location for IFF1
Figure 16. Interrupt Enable Flip-Flops
UM008011-0816 Interrupt Response

Z80 CPU
User Manual
18
The state of IFF1 is used to inhibit interrupts while IFF2 is used as a temporary storage
location for IFF1.
A CPU reset forces both the IFF1 and IFF2 to the reset state, which disables interrupts.
Interrupts can be enabled at any time by an EI instruction from the programmer. When an
EI instruction is executed, any pending interrupt request is not accepted until after the
instruction following EI is executed. This single instruction delay is necessary when the
next instruction is a return instruction. Interrupts are not allowed until a return is com-
pleted. The EI instruction sets both IFF1 and IFF2 to the enable state. When the CPU
accepts a maskable interrupt, both IFF1 and IFF2 are automatically reset, inhibiting fur-
ther interrupts until the programmer issues a new El instruction.
Note: For all of the previous cases, IFF1 and IFF2 are always equal.
The purpose of IFF2 is to save the status of IFF1 when a nonmaskable interrupt occurs.
When a nonmaskable interrupt is accepted, IFF1 resets to prevent further interrupts until
reenabled by the programmer. Therefore, after a nonmaskable interrupt is accepted, mask-
able interrupts are disabled but the previous state of IFF1 is saved so that the complete
state of the CPU just prior to the nonmaskable interrupt can be restored at any time. When
a Load Register A with Register I (LD A, I) instruction or a Load Register A with Register
R (LD A, R) instruction is executed, the state of IFF2 is copied to the parity flag, where it
can be tested or stored.
A second method of restoring the status of IFF1 is through the execution of a Return From
Nonmaskable Interrupt (RETN) instruction. This instruction indicates that the nonmask-
able interrupt service routine is complete and the contents of IFF2 are now copied back
into IFF1 so that the status of IFF1 just prior to the acceptance of the nonmaskable inter-
rupt is restored automatically.
Table 1 is a summary of the effect of different instructions on the two enable flip-flops.
Table 1. Interrupt Enable/Disable, Flip-Flops
Action IFF1 IFF2 Comments

CPU Reset 0 0 Maskable interrupt, INT disabled.
DI Instruction Execution 0 0 Maskable INT disabled.
EI Instruction Execution 1 1 Maskable, INT enabled.
LD A,I Instruction * * IFF2 → Parity flag.
Execution
LD A,R instruction * * IFF2 → Parity flag.
Execution

Z80 CPU
User Manual
19
Table 1. Interrupt Enable/Disable, Flip-Flops (Continued)
Action IFF1 IFF2 Comments

Accept NMI 0 * Maskable → Interrupt.
RETN Instruction IFF2 * IFF2 → Indicates completion of
Execution nonmaskable interrupt service routine.
CPU Response
The CPU always accepts a nonmaskable interrupt. When this nonmaskable interrupt is
accepted, the CPU ignores the next instruction that it fetches and instead performs a restart
at address 0066h. The CPU functions as if it had recycled a restart instruction, but to a
location other than one of the eight software restart locations. A restart is merely a call to a
specific address in Page 0 of memory.
The CPU can be programmed to respond to the maskable interrupt in any one of three pos-
sible modes.
Mode 0
Mode 0 is similar to the 8080A interrupt response mode. With Mode 0, the interrupting
device can place any instruction on the data bus and the CPU executes it. Consequently,
the interrupting device provides the next instruction to be executed. Often this response is
a restart instruction because the interrupting device is required to supply only a single-byte
instruction. Alternatively, any other instruction such as a 3-byte call to any location in
memory could be executed.
The number of clock cycles necessary to execute this instruction is two more than the nor-
mal number for the instruction. The addition of two clock cycles occurs because the CPU
automatically adds two wait states to an Interrupt response cycle to allow sufficient time to
implement an external daisy-chain for priority control. Figures 9 and 10 on page 13 show
the timing for an interrupt response. After the application of RESET, the CPU automati-
cally enters interrupt Mode 0.
Mode 1
When Mode 1 is selected by the programmer, the CPU responds to an interrupt by execut-
ing a restart at address 0038h. As a result, the response is identical to that of a nonmask-
able interrupt except that the call location is 0038h instead of 0066h. The number of
cycles required to complete the restart instruction is two more than normal due to the two
added wait states.
Mode 2
Mode 2 is the most powerful interrupt response mode. With a single 8-bit byte from the
user, an indirect call can be made to any memory location.
UM008011-0816 CPU Response

Z80 CPU
User Manual
20
In Mode 2, the programmer maintains a table of 16-bit starting addresses for every inter-
rupt service routine. This table can be located anywhere in memory. When an interrupt is
accepted, a 16-bit pointer must be formed to obtain the required interrupt service routine
starting address from the table. The upper eight bits of this pointer is formed from the con-
tents of the I Register. The I register must be loaded with the applicable value by the pro-
grammer, such as LD I, A. A CPU reset clears the I Register so that it is initialized to 0.
The lower eight bits of the pointer must be supplied by the interrupting device. Only seven
bits are required from the interrupting device, because the least-significant bit must be a 0.
This process is required, because the pointer must receive two adjacent bytes to form a
complete 16-bit service routine starting address; addresses must always start in even loca-
tions.
Starting Address
Pointed to by:
Interrupt
Service
Low Order I Register Seven Bits From
Routine 0
Starting Contents Peripheral
High Order
Address
Table
Figure 17. Mode 2 Interrupt Response Mode
The first byte in the table is the least-significant (low-order portion of the address). The
programmer must complete the table with the correct addresses before any interrupts are
accepted.
The programmer can change the table by storing it in read/write memory, which also
allows individual peripherals to be serviced by different service routines.
When the interrupting device supplies the lower portion of the pointer, the CPU automati-
cally pushes the program counter onto the stack, obtains the starting address from the
table, and performs a jump to this address. This mode of response requires 19 clock peri-
ods to complete (seven to fetch the lower eight bits from the interrupting device, six to
save the program counter, and six to obtain the jump address).
The Z80 peripheral devices include a daisy-chain priority interrupt structure that automat-
ically supplies the programmed vector to the CPU during interrupt acknowledge. Refer to
the Z80 CPU Peripherals User Manual (UM0081) for more complete information.

Z80 CPU
User Manual
21
Hardware and Software Implementation

This chapter is an introduction to implementing systems that use the Z80 CPU. Figure 18
shows a simple Z80 system.
OSC +5V Power Supply

CLK
A9–A0 +5V GND

Address
IN
MREQ
CE1 8K Bit
RD CE2 ROM
+5V Z80 Data
CPU OUT
Data Bus
CLK
RESET IORQ
CE RD B/A A0
IORQ Z80-PIO
M1 A1
M1 Port A Port B C/D
Output Data Input Data
Figure 18. Minimum Z80 Computer System
Minimum System Hardware

Any Z80 system must include the following hardware elements:
• 5 V power supply
• Oscillator
• Memory devices
• I/O circuits
• CPU
UM008011-0816 Hardware and Software Implementation

Z80 CPU
User Manual
22
Because the Z80 CPU requires only a single 5 V power supply, most small systems can be
implemented using only this single supply.
The external memory can be any mixture of standard RAM, ROM, or PROM. In Fig-
ure 18, a single 8 Kb (1 KB) ROM comprises the entire memory system. The Z80 internal
register configuration contains sufficient read/write storage, requiring no external RAM
memory.
I/O circuits allow computer systems to interface with the external devices. In Figure 18,
the output is an 8-bit control vector and the input is an 8-bit status word. The input data
can be gated to the data bus using any standard three-state driver while the output data can
be latched with any type of standard TTL latch. A Z80 PIO serves as the I/O circuit. This
single circuit attaches to the data bus as indicated and provides the required 16 bits of
TTL-compatible I/O. Refer to the Z80 CPU Peripherals User Manual (UM0081) to learn
more about the operation of this circuit. This powerful computer is built with only three
LSI circuits, a simple oscillator, and a single 5V power supply.
Adding RAM
Most computer systems require some external read/write memory for data storage and
stack implementation. Figure 19 shows how 256 bytes of static memory are added to the
example shown in Figure 18.
Address Bus
A7–A0 A7–A0 A7–A0
MREQ • RD RD MRQ RD
CE1 OD CE1 OD CE1 MRQ
1K x 8 256 x 4 256 x 4
A10 ROM RAM A10 WR RAM
CE2 WR
R/W CE2 R/W CE2 A10
D7–D0 D3–D0 D7–D4
Data Bus
Figure 19. ROM and RAM Implementation
The memory space is assumed to be organized as shown in Figure 20.
Hardware and Software Implementation UM008011-0816

Z80 CPU
User Manual
23
Address:
0000h
1 Kbyte ROM
03FFh
0400h
256 Bytes RAM
04FFFh
Figure 20. RAM Memory Space Organization
In Figure 20, the address space is portrayed in hexadecimal notation. Address bit A10 sep-
arates the ROM space from the RAM space, allowing this address to be used for the chip
select function. For larger amounts of external ROM or RAM, a simple TTL decoder is
required to form the chip selects.
Memory Speed Control

Slow memories can reduce costs for many applications. The WAIT line on the CPU allows
the Z80 to operate with any speed memory. Memory access time requirements, which are
covered in the Memory Read Or Write section on page 9, are most severe during the M1
cycle instruction fetch. All other memory access cycles complete in an additional one half
clock cycle. Hence, it is sometimes appropriate to add one wait state to the M1 cycle so
slower memories can be used.
Figure 21 is an example of a simple circuit that accomplishes this objective. This circuit
can be changed to add a single wait state to any memory access, as indicated in Figure 22.
UM008011-0816 Memory Speed Control

Z80 CPU
User Manual
24
WAIT
M1
+5V
T1 T2 TW T3 T4
S S CLK
M1
D Q D Q
7474 7474 M1
CLK
C Q C Q
R R
WAIT
+5V +5V
Figure 21. Adding One Wait State to an M1 Cycle
WAIT
+5V 7400
T1 T2 TW
+5V
CLK
S S
MREQ Q
D Q D MREQ
7474 7474
CLK
C Q C Q WAIT
R R
+5V +5V
Figure 22. Adding One Wait State to Any Memory Cycle

Z80 CPU
User Manual
25
Interfacing Dynamic Memories

Each individual dynamic RAM space includes its own specifications that require minor
modifications to the examples provided here.
Figure 23 shows the logic necessary to interface 8 KB of dynamic RAM using 18-pin 4K
dynamic memories. This logic assumes that the RAMs are the only memory in the system
so that A12 is used to select between the two pages of memory. During refresh time, all
memories in the system must be read. The CPU provides the correct refresh address on
lines A0 through A6. When adding more memory to the system, it is necessary to replace
only the two gates that operate on A12 with a decoder that operates on all required address
bits. Address buffers and data bus buffers are generally required for larger systems.
RFSH
MREQ
A12
A11–A0 CE
4K x 8 RAM Array
R/W
Page 1
D7–D0 Data Bus (1000 to 1FFFF)
CE
4K x 8 RAM Array
WR
R/W
Page 0
(0000 to 0FFFF)
Figure 23. Interfacing Dynamic RAM Memory Spaces
UM008011-0816 Interfacing Dynamic Memories

Z80 CPU
User Manual
26
Software Implementation Examples

The Z80 instruction set provides the user with a large number of operations to control the
Z80 CPU. The main alternate and index registers can hold arithmetic and logical opera-
tions, form memory addresses, or act as fast-access storage for frequently used data.
Information can be moved directly from register to register, memory to memory, memory
to registers, or from registers to memory. In addition, register contents and register/mem-
ory contents can be exchanged without using temporary storage. In particular, the contents
of main and alternate registers can be completely exchanged by executing only two
instructions, EX and EXX. This register exchange procedure can be used to separate the
set of working registers from different logical procedures or to expand the set of available
registers in a single procedure.
Storage and retrieval of data between pairs of registers and memory can be controlled on a
last-in first-out basis through PUSH and POP instructions that utilize a special Stack
Pointer (SP) Register. This stack register is available both to manipulate data and to auto-
matically store and retrieve addresses for subroutine linkage. When a subroutine is called,
for example, the address following the CALL instruction is placed on the top of the push-
down stack pointed to by SP. When a subroutine returns to the calling routine, the address
on the top of the stack is used to set the program counter for the address of the next
instruction. The stack pointer is adjusted automatically to reflect the current top stack
position during PUSH, POP, CALL, and RET instructions. This stack mechanism allows
pushdown data stacks and subroutine calls to be nested to any practical depth because the
stack area can potentially be as large as memory space.
The sequence of instruction execution can be controlled by six different flags (carry, zero,
sign, parity/overflow, add/subtract, half-carry), which reflect the results of arithmetic, log-
ical, shift, and compare instructions. After the execution of an instruction that sets a flag,
that flag can be used to control a conditional jump or return instruction. These instructions
provide logical control following the manipulation of single bit, 8-bit byte, or 18-bit data
quantities.
A full set of logical operations, including AND, OR, XOR (exclusive-OR), CPL (NOR),
and NEG (two’s complement) are available for Boolean operations between the Accumu-
lator and all other 8-bit registers, memory locations, or immediate operands.
In addition, a full set of arithmetic and logical shifts in both directions are available which
operate on the contents of all 8-bit primary registers or directly on any memory location.
The carry flag can be included or set by these shift instructions to provide both the testing
of shift results and to link register/register or register/memory shift operations.

Z80 CPU
User Manual
27
Specific Z80 Instruction Examples

Example 1
When a 737-byte data string in memory location DATA must be moved to location BUF-
FER, the operation is programmed as follows:
LD HL, DATA ;START ADDRESS OF DATA STRING

LD DE, BUFFER ;START ADDRESS OF TARGET BUFFER
LD BC, 737 ;LENGTH OF DATA STRING
LDIR ;MOVE STRING–TRANSFER MEMORY POINTED
;TO BY HL INTO MEMORY LOCATION POINTED
;TO BY DE INCREMENT HL AND DE,
;DECREMENT BC PROCESS UNTIL BC = 0
Eleven bytes are required for this operation and each byte of data is moved in 21 clock
cycles.
Example 2
A string in memory (limited to a maximum length of 132 characters) starting at location
DATA is to be moved to another memory location starting at location BUFFER until an
ASCII $ (used as a string delimiter) is found. This operation is performed as follows:
LD HL, DATA ;STARTING ADDRESS OF DATA STRING

LD DE, BUFFER ;STARTING ADDRESS OF TARGET BUFFER
LD BC, 132 ;MAXIMUM STRING LENGTH
LD A, '$' ;STRING DELIMITER CODE
LOOP: CP (HL) ;COMPARE MEMORY CONTENTS WITH
;DELIMITER
JR Z, END-$ ;GO TO END IF CHARACTERS EQUAL
LDI ;MOVE CHARACTER (HL) to (DE)
;INCREMENT HL AND DE, DECREMENT BC
JP PE, LOOP ;GO TO LOOP IF MORE CHARACTERS
END: ;OTHERWISE, FALL THROUGH
;NOTE: P/V FLAG IS USED
;TO INDICATE THAT REGISTER BC WAS
;DECREMENTED TO ZERO
Nineteen bytes are required for this operation.
Example 3
A 16-digit decimal number is shifted as depicted in Figure 24. This shift is performed to
mechanize BCD multiplication or division. The 16-digit decimal number is represented in
packed BCD format (two BCD digits/byte) The operation is programmed as follows:
UM008011-0816 Specific Z80 Instruction Examples

Z80 CPU
User Manual
28
LD HL, DATA ;ADDRESS OF FIRST BYTE

LD B, COUNT ;SHIFT COUNT
XOR A ;CLEAR ACCUMULATOR
ROTAT: RLD ;ROTATE LEFT low-order DIGIT IN ACC
;WITH DIGITS IN (HL)
INC HL ;ADVANCE MEMORY POINTER.
DJNZ ROTAT-$ ;DECREMENT B AND GO TO ROTAT IF
;B IS NOT ZERO, OTHERWISE FALL
;THROUGH
Eleven bytes are required for this operation.
Figure 24. Shifting of BCD Digits/Bytes
Example 4
One number is to be subtracted from another number, both of which exist in packed BCD
format and are of equal but varying length. The result is stored in the location of the minu-
end. The operation is programmed as follows:
LD HL, ARG1 ;ADDRESS OF MINUEND

LD DE, ARG2 ;ADDRESS OF SUBTRAHEND
LD B, LENGTH ;LENGTH OF TWO ARGUMENTS
AND A ;CLEAR CARRY FLAG
SUBDEC:LD A, (DE) ;SUBTRAHEND TO ACC

Z80 CPU
User Manual
29
SBC A, (HL) ;SUBTRACT (HL) FROM ACC

DAA ;ADJUST RESULT TO DECIMAL CODED VALUE
LD (HL), A ;STORE RESULT
INC HL ;ADVANCE MEMORY POINTERS
INC DE
DJNZ SUBDEC–$ ;DECREMENT B AND GO TO SUBDEC
;IF B
;NOT ZERO, OTHERWISE FALL
;THROUGH
Seventeen bytes are required for this operation.
Programming Task Examples

As indicated in Table 2, this example program sorts an array of numbers to ascending
order, using a standard exchange sorting algorithm. These numbers range from 0 to 255.
Table 2. Bubble Listing
Object
Location Code Statement Source Statement
1 ; standard exchange (bubble) sort routine
2 ;
3 ; at entry: hl contains address of data
4 c contains number of elements to be sorted
(1 < c < 256)
5
6 ;
7 ; at exit data sorted in ascending order
8 ;
9 ; use of
registers
10 ;
11 ; register contents
12 ;
13 ; a temporary storage for calculations
14 ; b counter for data array
15 ; c length of data array
16 ; d first element in comparison
17 ; e second element in comparison
18 ; h flag to indicate exchange
UM008011-0816 Programming Task Examples

Z80 CPU
User Manual
30
Table 2. Bubble Listing (Continued)
Object
19 ; l unused
20 ; ix pointer into data array
21 ; iy unused
22 ;
0000 222600 23 sort: ld (data), hl ; save data address
0003 cb84 24 loop: res flag, h ; initialize exchange flag
0005 41 25 ld b, c ; initialize length counter
0006 05 26 dec b ; adjust for testing
0007 dd2a260 27 ld ix, (data) ; initialize array pointer
0
000b dd7e00 28 next: ld a, (ix) ; first element in comparison
000e 57 29 ld d, a ; temporary storage for element
goof dd5e01 30 ld e, (ix+1) ; second element in comparison
0012 93 31 sub e ; comparison first to second
0013 3008 32 jr pc, noex–$ ; if first > second, no jump
0015 dd7300 33 ld (ix), e ; exchange array elements
0018 dd7201 34 ld (ix+i), d
001b cbc4 35 set flag, h ; record exchange occurred
0010 dd23 36 noex: inc ix ; point to next data element
001f 10ea 37 djnz next–$ ; count number of comparisons
38 ; repeat if more data pairs
0021 cb44 39 bit flag, h ; determine if exchange occurred
0023 20de 40 jr nz, loop–$ ; continue if data unsorted
0025 c9 41 ret ; otherwise, exit
42 ;
0026 43 flag: equ 0 ; designation of flag bit
0026 44 data: defs 2 ; storage for data address
45 end

Z80 CPU
User Manual
31
The program outlined in Table 3 multiplies two unsigned 16-bit integers, leaving the result
in the HL register pair.
Table 3. Multiply Listing
Object
0000 1 mult:; unsigned sixteen bit integer multiply.
2 ; on entrance: multiplier in de.
3 ; multiplicand in hl.
4 ;
5 ; on exit result in hl.
6 ;
7 ; register uses:
8 ;
9 ;
10 ; h high-order partial result
11 ; l low-order partial result
12 ; d high-order multiplicand
13 ; e low-order multiplicand
14 ; b counter for number of shifts
15 ; c high-order bits of multiplier
16 ; a low-order bits of multiplier
17 ;
0000 0610 18 ld b, 16; number of bits-initialize
0002 4a 19 ld c, d; move multiplier
0003 7b 20 ld a, e;
0004 eb 21 ex de, hl; move multiplicand
0005 210000 22 ld hl, 0; clear partial result
0008 cb39 23 mloop: srl c; shift multiplier right
000a if 24 rra least-significant bit is
25 ; in carry.
000b 3001 26 jr nc, if no carry, skip the add.
noadd–$;
good 19 27 add hl, de; else add multiplicand to
28 ; partial result.
000e eb 29 noadd: ex de, h l; shift multiplicand left
goof 29 30 add hl, hl; by multiplying it by two.
0010 eb 31 ex de, hl;
0011 10f5 32 djnz mloop–$; repeat until no more bits.
0013 c9 33 ret;
34 end;
UM008011-0816 Programming Task Examples

Z80 CPU
User Manual
32
Z80 CPU Instructions

The Z80 CPU can execute 158 different instruction types including all 78 of the 8080A
CPU. The instructions fall into these major groups:
• Load and Exchange
• Block Transfer and Search
• Arithmetic and Logical
• Rotate and Shift
• Bit Manipulation (Set, Reset, Test)
• Jump, Call, and Return
• Input/Output
• Basic CPU Control
Instruction Types
The load instructions move data internally among CPU registers or between CPU registers
and external memory. All of these instructions specify a source location from which the
data is to be moved, and a destination location. The source location is not altered by a load
instruction. Examples of load group instructions include moves between any of the gen-
eral-purpose registers such as move the data to Register B from Register C. This group
also includes load-immediate to any CPU register or to any external memory location.
Other types of load instructions allow transfer between CPU registers and memory loca-
tions. The exchange instructions can trade the contents of two registers.
A unique set of block transfer instructions is provided in the Z80 CPU. With a single
instruction, a block of memory of any size can be moved to any other location in memory.
This set of block moves is extremely valuable when processing large strings of data. With
a single instruction, a block of external memory of any required length can be searched for
any 8-bit character. When the character is found or the end of the block is reached, the
instruction automatically terminates. Both the block transfer and the block search instruc-
tions can be interrupted during their execution so they are not occupying the CPU for long
periods of time.
The arithmetic and logical instructions operate on data stored in the Accumulator and
other general-purpose CPU registers or external memory locations. The results of the
operations are placed in the Accumulator and the appropriate flags are set according to the
result of the operation.
Z80 CPU Instructions UM008011-0816

Z80 CPU
User Manual
33
An example of an arithmetic operation is adding the Accumulator to the contents of an

external memory location. The results of the addition are placed in the Accumulator. This
group also includes 16-bit addition and subtraction between 16-bit CPU registers.
The rotate and shift group allows any register or any memory location to be rotated right
or left, with or without carry, and either arithmetic or logical. Additionally, a digit in the
Accumulator can be rotated right or left with two digits in any memory location.
The bit manipulation instructions allow any bit in the Accumulator, any general-purpose
register, or any external memory location to be set, reset, or tested with a single instruc-
tion. For example, the most-significant bit of Register H can be reset. This group is espe-
cially useful in control applications and for controlling software flags in general-purpose
programming.
The JUMP, CALL, and RETURN instructions are used to transfer between multiple loca-
tions in the user’s program. This group uses several different techniques for obtaining the
new program counter address from specific external memory locations. A unique type of
call is the RESTART instruction. This instruction actually contains the new address as a
part of the 8-bit op code. This instruction is possible because only eight separate addresses
located in Page 0 of external memory can be specified. Program jumps can also be
achieved by loading Register HL, IX, or IY directly into the Program Counter, which
allows the jump address to be a complex function of the routine being executed.
The input/output group of instructions in the Z80 CPU allow for a wide range of transfers
between external memory locations or the general-purpose CPU registers, and the external
I/O devices. In each case, the port number is provided on the lower eight bits of the
address bus during any I/O transaction. One instruction allows this port number to be
specified by the second byte of the instruction while other Z80 instructions allow it to be
specified as the contents of the C Register. One major advantage of using the C register as
a pointer to the I/O device is that it allows multiple I/O ports to share common software
driver routines. This advantage is not possible when the address is part of the op code if
the routines are stored in ROM. Another feature of these input instructions is the auto-
matic setting of the Flag Register, making additional operations unnecessary to determine
the state of the input data. The parity state is one example.
The Z80 CPU includes single instructions that can move blocks of data (up to 256 bytes)
automatically to or from any I/O port directly to any memory location. In conjunction with
the dual set of general-purpose registers, these instructions provide fast I/O block transfer
rates. The power of this I/O instruction set is demonstrated by the Z80 CPU providing all
required floppy disk formatting on double-density floppy disk drives on an interrupt-
driven basis. For example, the CPU provides the preamble, address, data, and enables the
CRC codes.
Finally, the basic CPU control instructions allow multiple options and modes. This group
includes instructions such as setting or resetting the interrupt enable flip-flop or setting the
mode of interrupt response.
UM008011-0816 Instruction Types

Z80 CPU
User Manual
34
Addressing Modes
Most of the Z80 instructions operate on data stored in internal CPU registers, external
memory, or in the I/O ports. Addressing refers to how the address of this data is generated
in each instruction. This section is a brief summary of the types of addressing used in the
Z80 CPU while subsequent sections detail the type of addressing available for each
instruction group.
Immediate Addressing
In the Immediate Addressing Mode, the byte following the op code in memory contains
the actual operand, as shown in Figure 25.
Op Code One or Two Bytes
Op Code
D7 D0
Figure 25. Immediate Addressing Mode
An example of this type of instruction is to load the Accumulator with a constant, in which
the constant is the byte immediately following the op code.
Immediate Extended Addressing

This mode is an extension of immediate addressing in that the two bytes following the op
codes are the operand, as shown in Figure 26.

Op Code low-order
Op Code high-order
Figure 26. Immediate Extended Addressing Mode
An example of this type of instruction is to load the HL register pair (16-bit register) with
16 bits (two bytes) of data.

Z80 CPU
User Manual
35
Modified Page Zero Addressing

The Z80 contains a special single-byte CALL instruction to any of eight locations in Page
0 of memory. This instruction, which is referred to as a restart, sets the Program Counter to
an effective address in Page 0. The value of this instruction is that it allows a single byte to
specify a complete 16-bit address at which commonly-called subroutines are located,
thereby saving memory space.
Op Code One Byte
B7 B0 Effective Address is
(B5 B4 B3 000)2
Figure 27. Modified Page Zero Addressing Mode
Relative Addressing
Relative addressing uses one byte of data following the op code to specify a displacement
from the existing program to which a program jump can occur. This displacement is a
signed two’s complement number that is added to the address of the op code of the follow-
ing instruction.
Op Code Jump Relative (One Byte Op Code)

8-bit Two’s Complement
Op Code Displacement Added to
Address (A+2)
Figure 28. Relative Addressing Mode
The value of relative addressing is that it allows jumps to nearby locations while only
requiring two bytes of memory space. For most programs, relative jumps are by far the
most prevalent type of jump due to the proximity of related program segments. Therefore,
these instructions can significantly reduce memory space requirements. The signed dis-
placement can range between +127 and –128 from A+2. This range allows for a total dis-
placement of +129 to –126 from the jump relative op code address. Another major
advantage is that it allows for relocatable code.
UM008011-0816 Modified Page Zero Addressing

Z80 CPU
User Manual
36
Extended Addressing
Extended Addressing provides for two bytes (16 bits) of address to be included in the
instruction. This data can be an address to which a program can jump or it can be an
address at which an operand is located.
One or
Op Code Two Bytes
low-order Address to low-order Operand
high-order Address to low-order Operand
Figure 29. Extended Addressing Mode
Extended addressing is required for a program to jump from any location in memory to
any other location, or load and store data in any memory location.
During extended addressing use, specify the source or destination address of an operand.
This notation (nn) is used to indicate the contents of memory at nn, in which nn is the 16-
bit address specified in the instruction. The two bytes of address nn are used as a pointer to
a memory location. The parentheses always indicates that the value enclosed within them
is used as a pointer to a memory location. For example, (1200) refers to the contents of
memory at location 1200.
Indexed Addressing
In the Indexed Addressing Mode, the byte of data following the op code contains a dis-
placement that is added to one of the two index registers (the op code specifies which
index register is used) to form a pointer to memory. The contents of the index register are
not altered by this operation.
Op Code
Two-Byte Op Code
Op Code
Displacement Operand added to index register

to form a pointer to memory
Figure 30. Indexed Addressing Mode
An example of an indexed instruction is to load the contents of the memory location

(Index Register + Displacement) into the Accumulator. The displacement is a signed two’s

Z80 CPU
User Manual
37
complement number. Indexed addressing greatly simplifies programs using tables of data
because the index register can point to the start of any table. Two index registers are pro-
vided because often operations require two or more tables. Indexed addressing also allows
for relocatable code.
The two index registers in the Z80 CPU are referred to as IX and IY. To indicate indexed
addressing, use the following notation:
(IX+d) or (IY+d)
In this notation, d is the displacement specified after the op code. The parentheses indicate
that this value is used as a pointer to external memory.
Register Addressing
Many of the Z80 op codes contain bits of information that specify which CPU register is to
be used for an operation. An example of register addressing is to load the data in Register
6 into Register C.
Implied Addressing
Implied addressing refers to operations in which the op code automatically implies one or
more CPU registers as containing the operands. An example is the set of arithmetic opera-
tions in which the Accumulator is always implied to be the destination of the results.
Register Indirect Addressing

This type of addressing specifies a 16-bit CPU register pair (such as HL) to be used as a
pointer to any location in memory. This type of instruction is powerful and it is used in a
wide range of applications.
Figure 31. Register Indirect Addressing Mode
An example of this type of instruction is to load the Accumulator with the data in the
memory location pointed to by the HL register contents. Indexed addressing is actually a
form of Register Indirect addressing except that a displacement is added with indexed
addressing. Register indirect addressing allows for powerful but simple to implement
memory accesses. The block move and search commands in the Z80 CPU are extensions
of this type of addressing in which automatic register incrementing, decrementing, and
comparing is added. The notation for indicating Register Indirect addressing is to put
UM008011-0816 Register Addressing

Z80 CPU
User Manual
38
parentheses around the name of the register that is to be used as the pointer. For example,
the symbol (HL) specifies that the contents of the HL register are to be used as a pointer to
a memory location. Often Register Indirect addressing is used to specify 16-bit operands.
In this case, the register contents point to the lower order portion of the operand while the
register contents are automatically incremented to obtain the upper portion of the operand.
Bit Addressing
The Z80 contains a large number of bit set, reset, and test instructions. These instructions
allow any memory location or CPU register to be specified for a bit operation through one
of three previous addressing modes (register, Register Indirect, and indexed) while three
bits in the op code specify which of the eight bits is to be manipulated.
Addressing Mode Combinations

Many instructions include more than one operand (such as arithmetic instructions or
loads). In these cases, two types of addressing can be employed. For example, load can use
immediate addressing to specify the source and Register Indirect or indexed addressing to
specify the destination.

Z80 CPU
User Manual
39
Instruction Notation Summary

Table 4 lists the operand notations and descriptions used in the Z80 Instruction Set.
Table 4. Instruction Notation Summary
Notation Description
r Identifies any of the registers A, B, C, D, E, H, or L
Identifies the contents of the memory location, whose address is specified by
(HL)
the contents of the register pair HL
(IX+d)
the contents of the Index register pair IX plus the signed displacement d
(IY+d)
the contents of the Index register pair IY plus the signed displacement d
n Identifies a one-byte unsigned integer expression in the range (0 to 255)
Identifies a two-byte unsigned integer expression in the range
nn
(0 to 65535)
Identifies a one-byte signed integer expression in the range
d
(-128 to +127)
Identifies a one-bit expression in the range (0 to 7). The most-significant bit
b
to the left is bit 7 and the least-significant bit to the right is bit 0
Identifies a one-byte signed integer expression in the range
e
(-126 to +129) for relative jump offset from current location
Identifies the status of the Flag Register as any of (NZ, Z, NC, C, PO, PE, P,
cc
or M) for the conditional jumps, calls, and return instructions
qq Identifies any of the register pairs BC, DE, HL or AF
ss Identifies any of the register pairs BC, DE, HL or SP
pp Identifies any of the register pairs BC, DE, IX or SP
rr Identifies any of the register pairs BC, DE, IY or SP
s Identifies any of r, n, (HL), (IX+d) or (IY+d)
m Identifies any of r, (HL), (IX+d) or (IY+d)
UM008011-0816 Instruction Notation Summary

Z80 CPU
User Manual
40
Instruction Op Codes
This section describes each of the Z80 instructions and provides tables listing the op codes
for every instruction. In each of these tables, the op codes in shaded areas are identical to
those offered in the 8080A CPU. Also depicted is the assembly language mnemonic that is
used for each instruction. All instruction op codes are listed in hexadecimal notation. Sin-
gle-byte op codes require two hex characters while double byte op codes require four hex
characters. For convenience, the conversion from hex to binary is repeated in Table 5.
Table 5. Hex, Binary, Decimal Conversion Table
Hex Binary Decimal

0 = 0000 = 0
1 = 0001 = 1
2 = 0010 = 2
3 = 0011 = 3
4 = 0100 = 4
5 = 0101 = 5
6 = 0110 = 6
7 = 0111 = 7
8 = 1000 = 8
9 = 1001 = 9
A = 1010 = 10
B = 1011 = 11
C = 1100 = 12
D = 1101 = 13
E = 1110 = 14
F = 1111 = 15
The Z80 instruction mnemonics consist of an op code and zero, one, or two operands.
Instructions in which the operand is implied contains no operand. Instructions that contain
only one logical operand, in which one operand is invariant (such as the Logical OR
instruction), are represented by a one-operand mnemonic. Instructions that contain two
varying operands are represented by two operand mnemonics.

Z80 CPU
User Manual
41
Load and Exchange

Table 6 defines the op codes for all of the 8-bit load instructions implemented in the Z80
CPU. Also described in this table is the type of addressing used for each instruction. The
source of the data is found on the top horizontal row and the destination is specified in the
left column. For example, load Register C from Register B uses the op code 48h. In all of
the figures, the op code is specified in hexadecimal notation and the 48h (0100 1000
binary) code is fetched by the CPU from external memory during M1 time, decoded, and
then the register transfer is automatically performed by the CPU.
The assembly language mnemonic for this entire group is LD, followed by the destination,
followed by the source (LD DEST, SOURCE).
Note: Several combinations of addressing modes are possible. For example, the source can use
register addressing and the destination can be registered indirect; such as load the memory
location pointed to by Register HL with the contents of the D Register. The op code for this
operation is 72. The mnemonic for this load instruction is LD (HL), D.
UM008011-0816 Load and Exchange

Z80 CPU
User Manual
42
Table 6. 8-Bit Load Group LD
Source
Implied Register Reg Indirect Indexed Ext. Imm.
Destination I R A B C D E F L (HL) (BC) (DE) (IX+d) (lY+d) (nn) n
Register DD FD
ED ED 3A 3E
A 7F 78 79 7A 7B 7C 7D 7E 0A 1A 7E 7E
57 5F nn n
d d
DD FD
06
B 47 40 41 42 43 44 45 46 46 46
n
d d
DD FD
0E
C 4F 48 49 4A 4B 4C 4D 4E 4E 4E
n
d d
DD FD
16
D 57 50 51 52 53 54 55 56 56 56
n
d d
DD FD
1E
E 5F 58 59 5A 5B 5C 5D 5E 5E 5E
n
d d
DD FD
26
H 67 60 61 62 63 64 65 66 66 66
n
d d
DD FD
2E
L 6F 68 69 6A 6B 6C 6D 6E 6E 6E
n
d d
Register 36
(HL) 77 70 71 72 73 74 75
Indirect n
(BC) 02
(DE) 12
Indexed DD
DD DD DD DD DD DD DD
36
(IX+d) 77 70 71 72 73 74 75
d
d d d d d d d
n
FD
FD FD FD FD FD FD FD
36
(IY+d) 77 70 71 72 73 74 75
d
d d d d d d d
n
Ext. Addr. 32
(nn) n .
n
Implied ED
I
47
ED
R
4F

Z80 CPU
User Manual
43
Note: Descriptions of the 8-Bit Load Group instructions begin on page 70.
The parentheses around the HL indicate that the contents of HL are used as a pointer to a
memory location. In all Z80 load instruction mnemonics, the destination is always listed
first, with the source following. The Z80 assembly language is defined for ease of pro-
gramming. Every instruction is self documenting and programs written in Z80 language
are easy to maintain.
In Table 6, some op codes that are available in the Z80 CPU use two bytes. This feature is
an efficient method of memory utilization because 8-, 18-, 24-, or 32-bit instructions are
implemented in the Z80 CPU. Often utilized instructions such as arithmetic or logical
operations are only eight bits, which results in better memory utilization than is achieved
with fixed instruction sizes such as 16 bits.
All load instructions using indexed addressing for either the source or destination location
actually use three bytes of memory, with the third byte being the displacement, d. For
example, a Load Register E instruction with the operand pointed to by IX with an offset of
+8 is written as:
LID E, (IX + 8)
The instruction sequence for this value in memory is shown in Figure 32.
Address A DD
Op Code
A+1 5E
A+2 08 Displacement
Operand
Figure 32. Example of a 3-Byte Load Indexed Instruction Sequence
The two extended addressing instructions are also three-byte instructions. For example,
the instruction to load the Accumulator with the operand in memory location 6F32h is
written as:
LID A, (6F 32h)

Z80 CPU
User Manual
44
Address A 3A Op Code
A+1 32 low-order Address
A+2 6F high-order Address
Figure 33. Example of a 3-Byte Load Extended Instruction Sequence
In this figure, note that the low-order portion of the address is always the first operand.
The load immediate instructions for the general-purpose 8-bit registers are two-byte
instructions. The instruction for loading Register H with the value 36h is written as:
LD H, 36h
Address A 26 Op Code
A+1 36 Operand
Figure 34. Example of a 2-Byte Load Immediate Instruction Sequence
Loading a memory location using indexed addressing for the destination and immediate
addressing for the source requires four bytes. For example:
LD (IX–15), 21h
Address A DD
Op Code
A+1 36
A+2 F1 One or Two Bytes

Displacement (–15 in Signed
A+3 21 Two’s Complement
Operand to Load
Figure 35. Example of a 4-Byte Load Indexed/Immediate Instruction Sequence

Z80 CPU
User Manual
45
In this figure, note that with any indexed addressing, the displacement always follows
directly after the op code.
Table 7 specifies the 16-bit load operations, for which the extended addressing feature
covers all register pairs. Register indirect operations specifying the stack pointer are the
PUSH and POP instructions. The mnemonic for these instructions is PUSH and POP.
Table 7. 16-Bit Load Group LD, PUSH, and POP
Source
Register Imm. Ext. Ext. Reg. Indir.
Register AF BC DE HL SP IX IY nn (nn) (SP)
AF P1
ED
01
4B
BC n C1
n
n
n
ED
11
5B
DE n D1
n
n
n
21 2A
HL n n E1
n n
ED
31
DD FD 7B
SP F9 n
F9 F9 n
n
n
DD DD
21 2A DD
IX
n n E1
n n
FD FD
21 2A FD
IY
n n E1
n n
Extended ED ED ED DD FD
22
43 53 73 22 22
(nn) n
n n n n n
n
n n n n n
PUSH Register DD FD
(SP) F6 C6 D6 E6
Instructions → Indirect E6 E6
. POP
Instructions
Note: The PUSH and POP instruction adjust the SP after every execution.

Z80 CPU
User Manual
46
Note: Descriptions of the 16-Bit Load Group instructions begin on page 98.
These 16-bit load operations differ from other 16-bit loads in that the stack pointer is auto-
matically decremented and incremented as each byte is pushed onto or popped from the
stack, respectively. For example, the PUSH AF instruction is a single-byte instruction with
the op code of F5h. During execution, this sequence is generated as:
Decrement SP
LD (SP), A
Decrement SP
LD (SP), F
The external stack now appears as shown in Figure 36.
(SP) F Top of stack
(SP+1) A
• •
• •
Figure 36. Example of a 16-Bit Load Operation
The POP instruction is the exact reverse of a PUSH. All PUSH and POP instructions uti-
lize a 16-bit operand and the high-order byte is always pushed first and popped last.
PUSH BC is PUSH B then C

PUSH DE is PUSH D then E
PUSH HL is PUSH H then L
POP HL is POP L then H
The instruction using extended immediate addressing for the source requires two bytes of
data following the op code, as shown in the following example:
LD DE, 0659h

Z80 CPU
User Manual
47
Address A E6 Op Code
A+1 07 Operand
Figure 37. Example of a 2-Byte Load Indexed/Immediate Instruction Sequence
In all extended immediate or extended addressing modes, the low-order byte always
appears first after the op code.
Table 8 lists the 16-bit exchange instructions implemented in the Z80 CPU. Op code 08h
allows the programmer to switch between the two pairs of Accumulator flag registers,
while D9h allows the programmer to switch between the duplicate set of six general-pur-
pose registers. These op codes are only one byte in length to minimize the time necessary
to perform the exchange so that the duplicate banks can be used to make fast interrupt
response times.
Table 8. Exchanges EX and EXX
Implied Addressing
BC', DE',
AF' and HL' HL IX IY
Implied AF 08
BC
DE D9
HL
DE EB
Register DD FD
(SP) E3
Indirect E3 E3
Block Transfer and Search

Table 9 lists the extremely powerful block transfer instructions. These instructions operate
with three registers.
• HL points to the source location
• DE points to the destination location
• BC is a byte counter
UM008011-0816 Block Transfer and Search

Z80 CPU
User Manual
48
Table 9. Block Transfer Group
Destination Source
Register (DE) Register
Indirect Indirect
(HL)
(ED) LDI – Load (DE) → (HL)

A0 Inc HL and DE, Dec BC
(ED) LDIR, – Load (DE) → (HL)
B0 Inc HL and DE, Dec BC; repeat until BC = 0.
(ED) LDD – Load (DE) → (HL)
A8 Inc HL and DE, Dec BC
(ED) LDDR – Load (DE) → (HL)
B8 Dec HL and DE, Dec BC; repeat until BC = 0.
Note: Register HL points to the source; the DE Register points to the destination; the BC Register is a byte counter.
After the programmer initializes these three registers, any of these four instructions can be
used. The Load and Increment (LDI) instruction moves one byte from the location pointed
to by HL to the location pointed to by DE. Register pairs HL and DE are then automati-
cally incremented and are ready to point to the following locations. The byte counter (i.e.,
register pair BC) is also decremented at this time. This instruction is valuable when the
blocks of data must be moved but other types of processing are required between each
move. The Load, Increment and Repeat (LDIR) instruction is an extension of the LDI
instruction. The same load and increment operation is repeated until the byte counter
reaches the count of zero. As a result, this single instruction can move any block of data
from one location to any other.
Because 16-bit registers are used, the size of the block can be up to 64 KB long
(1KB = 1024 bits) and can be moved from any location in memory to any other location.
Furthermore, the blocks can be overlapping because there are no constraints on the data
used in the three register pairs.
The LDD and LDDR instructions are similar to LDI and LDIR. The only difference is that
register pairs HL and DE are decremented after every move so that a block transfer starts
from the highest address of the designated block rather than the lowest.
Table 10 specifies the op codes for the four block search instructions. The first, CPI (Com-
pare and Increment) compares the data in the Accumulator with the contents of the mem-
ory location pointed to by Register HL. The result of the compare is stored in one of the
flag bits and the HL register pair is then incremented and the byte counter (register pair
BC) is decremented.

Z80 CPU
User Manual
49
Table 10. Block Search Group
Search Location
Register Indirect
(HL)
(ED) CPI
A1 Inc HL, Dec BC
(ED) CPRI. Inc HL, Dec BC
B1 Repeat until) BC = 0 or find match
(ED)
WD Dec HL and BC
A9
(ED) CPDR Dec HL and BC
B9 Repeat until BC = 0 or find match
Note: HL points to a location in memory to be compared with
Accumulator contents; BC is a byte counter.
Note: Descriptions of the Exchange, Block Transfer, and Search Group instructions begin on
page 123.
The CPIR instruction is merely an extension of the CPl instruction in which the compare is
repeated until either a match is found or the byte counter (register pair BC) becomes zero.
As a result, this single instruction can search the entire memory for any 8-bit character.
The Compare and Decrement (CPD) and Compare, Decrement, and Repeat (CPDR)
instructions are similar; however, their only difference is that they decrement HL after
every compare so that they search the memory in the opposite direction; i.e., the search is
started at the highest location in the memory block.
These block transfer and compare instructions are extremely powerful in string manipula-
tion applications.
Arithmetic and Logical

Table 11 lists all of the 8-bit arithmetic operations that can be performed with the Accu-
mulator. Also listed are the increment (INC) and decrement (DEC) instructions. In all of
these instructions, with the exception of INC and DEC, the specified 8-bit operation is per-
formed between the data in the Accumulator and the source data.
UM008011-0816 Arithmetic and Logical

Z80 CPU
User Manual
50
Table 11. 8-Bit Arithmetic and Logic
Source
Register
Register Addressing Indirect Indexed Immediate
Destination A B C D E F L (HL) (IX+d) (lY+d) n
DD FD
C6
ADD 87 80 81 82 83 84 85 88 86 86
n
d d
DD FD
Add with Carry CE
8F 88 89 8A 8B 8C 8D 8E 8E 8E
ADC n
d d
DD FD
Subtract D6
97 90 91 92 93 94 95 96 96 96
SUB n
d d
DD FD
Subtract with Carry DE
9F 98 99 9A 9B 9C 9D 9E 9E 9E
SBC n
d d
DD FD
E6
AND A7 A0 A1 A2 A3 A4 A5 A6 A6 A6
n
d d
DD FD
EE
XOR AF A8 A9 AA AB AC AD AE AE AE
n
d d
DD FD
F6
OR B7 B0 B1 B2 B3 B4 B5 B6 B6 B6
n
d d
DD FD
Compare FE
BF B8 B9 BA BB BC BD BE BE BE
CP n
d d
DD FD
Increment
3C 04 0C 14 1C 24 2C 34 34 34
INC
d d
DD FD
Decrement
3D 05 0D 15 1D 25 2D 35 35 35
DEC
d d
Note: Descriptions of the 8-Bit Arithmetic Group instructions begin on page 144.
The result of the operation is placed in the Accumulator with the exception of the compare
(CP) instruction, which leaves the Accumulator unchanged. All of these operations effect
the Flag Register as a result of a specified operation.

Z80 CPU
User Manual
51
The INC and DEC instructions specify a register or a memory location as both the source
and the destination of the result. When the source operand is addressed using the index
registers, the displacement must directly follow. With immediate addressing, the actual
operand directly follows. As an example, the AND 07h instruction is shown in Figure 38.
Address A E6 Op Code
A+1 07 Operand
Figure 38. Example of an AND Instruction Sequence
Assuming that the Accumulator contains the value F3h, the result of 03h is placed in the
Accumulator:
Accumulator before operation 1111 0011 = F3h
Operand 0000 0111 = 07h
Result to Accumulator 0000 0011 = 03h
The Add (ADD) instruction performs a binary add between the data in the source location
and the data in the Accumulator. The Subtract (SUB) instruction performs a binary sub-
traction. When an Add with Carry (ADC) or Subtract with Carry (SBC) instruction is
specified, the Carry flag is also added or subtracted, respectively. The flags and the Deci-
mal Adjust (DAA) instruction in the Z80 CPU allow arithmetic operations for processing
the following items:
• Multiprecision packed BCD numbers
• Multiprecision signed or unsigned binary numbers
• Multiprecision two’s complement signed numbers
Other instructions in this group are the Logical And (AND), Logical Or (OR), Exclusive
Or (XOR), and Compare (CP) instructions.
Five general-purpose arithmetic instructions operate on the Accumulator or Carry flag.
These five instructions are listed in Table 12.
Table 12. General-Purpose AF Operation
Decimal Adjust Accumulator (DAA) 27

Complement Accumulator (CPL) 2F
Negate Accumulator (NEG) ED
(two’s complement 44
Complement Carry Flag (CCF) 3F
Set Carry Flag (SCF) 37
UM008011-0816 Arithmetic and Logical

Z80 CPU
User Manual
52
Note: Descriptions of the General-Purpose Arithmetic and CPU Control Groups instructions
begin on page 172.
The decimal adjust instruction can adjust for subtraction and addition, making BCD arith-
metic operations simple.
Notes: 1. To allow for this operation, the N flag is used. This flag is set if the most recent arithmetic
operation was a Subtract. The Negate Accumulator (NEG) instruction forms the two’s
complement of the number in the Accumulator.
2. A Reset Carry instruction is not included in the Z80 CPU, because this operation can
be easily achieved through other instructions such as a logical AND of the Accumu-
lator with itself.
Table 12 lists all of the 16-bit arithmetic operations between 16-bit registers. There are
five groups of instructions, including the Add with Carry and Subtract with Carry instruc-
tions; ADC and SBC affect all of the flags. These two groups simplify address calculation
or other 16-bit arithmetic operations.
Table 13. 16-Bit Arithmetic
Source
BC DE HL SP IX IY
Destination HL 09 19 29 39
DD DD DD DD
IX
09 19 39 29
Add (ADD)
FD FD FD FD
IY
09 19 39 29
ED ED ED ED
Add with Carry and set ADC flags HL
4A 5A 6A 7A
ED ED ED ED
Subtract with Carry and set SBC flags HL
42 52 62 72
DD FD
Increment (INC) 03 13 23 33
23 23
DD FD
Decrement (DEC) DB 1B 2B 3B
2B 2B
Note: Descriptions of the 16-Bit Arithmetic Group instructions begin on page 187.

Z80 CPU
User Manual
53
Rotate and Shift

A major feature of the Z80 CPU is to rotate or shift data in the Accumulator, any general-
purpose register, or any memory location. All of the Rotate and Shift op codes are
depicted in Figure 39. Also included in the Z80 CPU are arithmetic and logical shift oper-
ations. These operations are useful in a wide range of applications including integer multi-
plication and division. Two BCD digit rotate instructions (RRD and RLD) allow a digit in
the Accumulator to be rotated with the two digits in a memory location pointed to by reg-
ister pair HL. These instructions allow for efficient BCD arithmetic.
UM008011-0816 Rotate and Shift

Z80 CPU
User Manual
54
Source
Type
of
Rotate
Shift A B C D E F L (HL) (IX+d) (lY+d) A
Rotate
DD FD CY b7 b0 Left Circular
CB CB CB CB CB CB CB CB CB CB
RCL RLCA 07
07 00 01 02 03 04 06 0E d d Rotate
06 06 Right Circular
DD FD
CB CB CB CB CB CB CB CB CB CB Rotate
RRC RRCA 0F Left
0F 08 09 0A 06 0C 0D 0E d d
0E 0E
DD FD Rotate
Right
RL RLA 17
17 10 11 12 13 14 15 16 d d
16 16 Shift
CY
Left Arithmetic
DD FD
RR RRA 1F Shift
1F 18 19 1A 1B 1C 1D 1E d d Right Arithmetic
1E 1E
DD FD
Shift
CB CB CB CB CB CB CB CB CB CB Right Logical
SLA
27 20 21 22 23 24 25 26 d d
26 26 0
Rotate
DD FD b3–b0 b7–b4 b3–b0 (HL) Digit
Left
CB CB CB CB CB CB CB CB CB CB ACC
SRA
2F 28 29 2A 2B 2C 2D 2E d d
2E 2E
(HL) Rotate
DD FD Digit
CB CB CB CB CB CB CB CB CB CB ACC Right
3F 38 39 3A 3B 3C 3D 3E d d
3E 3E
SRL
ED
6F
ED
67
Figure 39. Rotates and Shifts
Note: Descriptions of the Rotate and Shift Group instructions begin on page 204.

Z80 CPU
User Manual
55
Bit Manipulation
The ability to set, reset, and test individual bits in a register or memory location is required
in almost every program. These bits can be flags in a general-purpose software routine,
indications of external control conditions, or data packed into memory locations, making
memory utilization more efficient.
With a single instruction, the Z80 CPU can set, reset, or test any bit in the Accumulator, in
any general-purpose register, or in any memory location. Table 14 lists the 240 instruc-
tions that are available for this purpose.
Table 14. Bit Manipulation Group

Register
Register Addressing Indirect Indexed
A 8 C D E H L (HL) (IX+d) (IY+d)
Bit DD FD
Test Bit C8 C8 C8 C8 C8 C8 C8 C8 C8 C8
0
47 40 41 42 43 44 45 46 d d
46 46
DD FD
1 C8 C8 C8 C8 C8 C8 C8 C8 C8 C8
4F 48 49 4A 48 4C 4D 4E d d
4E 4E
DD FD
C8 C8 C8 C8 C8 C8 C8 C8 C8 C8
2
57 50 51 52 53 54 55 56 d d
56 56
DD FD
C8 C8 C8 C8 C8 C8 C8 C8 C8 C8
3
5F 58 59 5A 5B 5C 5D 5E d d
46 46
DD FD
C8 C8 C8 C8 C8 C8 C8 C8 C8 C8
4
67 60 61 62 63 64 65 66 d d
66 66
DD FD
C8 C8 C8 C8 C8 C8 C8 C8 C8 C8
5
6F 68 69 6A 68 6C 6D 6E d d
6E 6E
UM008011-0816 Bit Manipulation

Z80 CPU
User Manual
56
Table 14. Bit Manipulation Group (Continued)

Register
Test Bit DD FD
(cont’d.)
C8 C8 C8 C8 C8 C8 C8 C8 C8 C8
6
77 70 71 72 73 74 75 76 d d
76 76
DD DD
C8 C8 C8 C8 C8 C8 CS C8 C8 C8
7
7F 78 79 7A 78 7C 7D 7E d d
46 46
Rest Bit DD FD
RES
C8 C8 C8 C8 C8 C8 C8 C8 C8 C8
0
87 80 81 82 83 84 85 86 d d
86 86
DD FD
C8 C8 C8 C8 C8 C8 C8 C8 C8 C8
1
8F 88 89 8A 88 8C 8D 8E d d
8E 8E
DD FD
C8 C8 CS C8 C8 C8 C8 C8 C8 C8
2
97 90 91 92 93 94 95 96 d d
96 96
DD FD
C8 C8 C8 C8 CS C8 C8 C8 C8 C8
3
9F 98 99 9A 98 90 90 9E d d
9E 9E
DD FD
C8 C8 C8 C8 C6 C8 C8 C8 C8 C8
4
A7 AO AI A2 A3 A4 A5 A6 d d
A6 A6
DD FD
C8 C8 C8 C8 08 C8 C8 C8 C8 C8
5
AF A8 A9 AA AB AC AD AE d d
AE AE
DD FD
C8 C8 C8 C8 C8 C8 C8 C8 C8 C8
6
B7 B0 B1 82 B3 B4 B5 B6 d d
B6 B6

Z80 CPU
User Manual
57
Table 14. Bit Manipulation Group (Continued)

Register
Rest Bit DD DD
RES
C8 C8 C8 C8 C8 C8 C8 C8 C8 C8
(cont’d.) 7
BF B8 89 8A B8 8C BD 9E d d
BE BE
Set Bit DD FD
SET
C8 C8 C8 C8 C8 C8 C8 C8 C8 C8
0
C7 C0 C1 C2 C3 C4 C5 C6 d d
C6 C6
DD FD
C8 C8 C8 C8 C8 C8 C8 C8 C8 C8
1
CF C8 C9 CA C8 CC CD CE d d
CE CE
DD FD
C8 C8 C8 C8 C8 C8 C8 C8 C8 C8
2
D7 DO D1 D2 D3 D4 DS D6 d d
D6 D6
DD FD
C8 C8 C8 C8 C8 C8 C8 C8 C8 C8
3
DF D8 09 DA DS DC DD DE d d
DE DE
DD FD
C8 C8 C8 C8 C8 C8 C8 C8 C8 C8
4
E7 E0 E1 E2 E3 E4 E5 E6 d d
E6 E6
DD FD
C8 C8 C8 C8 C8 C8 C8 C8 C8 C8
5
EF E8 E9 EA EB EC ED EE d d
EE EE
DD FD
C8 C8 C8 C8 C8 C8 C8 C8 C8 C8
6
F7 FO F1 F2 F3 F4 FS F6 d d
F6 F6
DD FD
C8 C8 C8 C8 C8 C8 C8 C8 C8 C8
7
FF F8 F9 FA FB FC FD FE d d
FE FE
UM008011-0816 Bit Manipulation

Z80 CPU
User Manual
58
Register addressing can specify the Accumulator or any general-purpose register on which
an operation is to be performed. Register Indirect and Indexed addressing are available for
operations at external memory locations. Bit test operations set the Zero flag (Z) if the
tested bit is a 0.
Note: Descriptions of the Bit Set, Reset, and Test Group instructions begin on page 242.
Jump, Call, and Return

Table 15 lists all of the jump, call, and return instructions implemented in the Z80 CPU. A
jump is a branch in a program in which the program counter is loaded with a 16-bit value
as specified by one of the three available addressing modes (Immediate Extended, Rela-
tive, or Register Indirect). In Table 15, the jump group includes several conditions that can
be specified before the jump is made. If these conditions are not met, the program merely
continues with the next sequential instruction. The conditions are all dependent on the data
in the Flag Register. The immediate extended addressing is used to jump to any location in
the memory. This instruction requires three bytes (i.e., two bytes designated to specifying
the 16-bit address), with the low-order address byte first, followed by the high-order
address byte.
An example of an unconditional jump to memory location 3E32h is shown in Figure 40.
Address A C3 Op Code
A+1 32 low-order Address
A+2 3E high-order Address
Figure 40. Example of an Unconditional Jump Sequence
The Relative Jump instruction uses only two bytes, the second byte is a signed two’s com-
plement displacement from the existing Program Counter. This displacement can be in the
range of +129 to –126 and is measured from the address of the instruction op code.

Z80 CPU
User Manual
59
Table 15. Jump, Call, and Return Group
Condition
Un- Non- Non- Parity Parity Sign Sign Reg
Cond. Carry Carry Zero Zero Even Odd Neg Pos B¹0
C3 D8 D2 CA C2 EA E2 FA F2
JUMP IMMED.
nn n n n n n n n n n
JP EXT.
n n n n n n n n n
JUMP 18 38 30 28 20
RELATIVE PC+e
JR e–2 e–2 e–2 e–2 e–2
(HL) EB
JUMP Register DD
(IX)
JP INDIR. E9
FD
(IY)
E9
CD DC D4 CC C4 EC E4 FC F4
IMMED.
CALL nn n n n n n n n n n
EXT.
n n n n n n n n n
Decrement B,
10
Jump If Non-Zero RELATIVE PC+e
e–2
DJNZ
Return
C9 D8 D0 C8 C0 E8 E0 F8 F0
RE
Return From
ED
Interrupt
REGISTER (SP) 4D
RETI
INDIR. (SP+1)
Return From Non-
Maskable ED
Interrupt 45
RETN
Note: Descriptions of the Jump Group instructions begin on page 261.
Three types of Register Indirect jumps are also included. These instructions are imple-
mented by loading the register pair HL or one of the index registers IX or IY directly into
the Program Counter. This feature allows for program jumps to be a function of previous
calculations.
A Call is a special form of a jump in which the address of the byte following the call
instruction is pushed onto the stack before the jump is made. A return instruction is the
reverse of a call because the data on the top of the stack is popped directly into the Pro-
UM008011-0816 Jump, Call, and Return

Z80 CPU
User Manual
60
gram Counter to form a jump address. The call and return instructions allow for simple
subroutine and interrupt handling. Two special return instruction are included in the Z80
family of microprocessors. The return from interrupt instruction (RETI) and the return
from nonmaskable interrupt (RETN) are treated in the CPU as an unconditional return
identical to the op code C9h. The difference is that (RETI) can be used at the end of an
interrupt routine and all Z80 peripheral chips recognize the execution of this instruction
for proper control of nested priority interrupt handling. This instruction, coupled with the
Z80 CPU’s peripheral devices implementation, simplifies the normal return from nested
interrupt. Without this feature, the following software sequence is necessary to inform the
interrupting device that the interrupt routine is completed:
Disable Interrupt ; Prevent interrupt before routine is exited.

LD A, n ; Notify peripheral that service routine
; is complete.
OUT n, A
Enable Interrupt
Return
This seven-byte sequence can be replaced with the one-byte EI instruction and the two-
byte RETI instruction in the Z80 CPU. This instruction is important because interrupt ser-
vice time often must be minimized.
The DJNZ instruction is used to facilitate program loop control. This two-byte relative
jump instruction decrements Register B, and the jump occurs if Register B is not decre-
mented to 0. The relative displacement is expressed as a signed two’s complement num-
ber. A simple example of its use is shown in Table 16.
Table 16. Example Usage of the DJNZ Instruction
Address Instruction Comments

N, N+1 LD B, 7 ; Set B Register to count of 7
N+2 to N+9 (Perform a sequence of instructions) ; Loop to be performed 7 times
N+10,N+11 DJNZ – 8 ; To jump from N+12 to N+2
N + 12 (Next instruction)
Table 17 lists the eight op codes for the Restart instruction, which is a single-byte call to
any of the eight addresses listed. A simple mnemonic for each of these eight calls is also
listed. The Restart instruction is useful for frequently-used routines due to its minimal
memory consumption.

Z80 CPU
User Manual
61
Table 17. Restart Group
Op Code
0000h C7 RST 0
0008h CF RST 8
0010h D7 RST 16
0018h DF RST 24
CALL Address
0020h E7 RST 32
0028h EF RST 40
0030h F7 RST 48
0038h FF RST 56
Note: Descriptions of the Call and Return Group instructions begin on page 280.
Input/Output
The Z80 CPU contains an extensive set of input and output instructions, as shown in
Tables 18 and 19. The addressing of the input or output device can be either absolute or
Register Indirect, using the C register. In the Register Indirect addressing mode, data can
be transferred between the I/O devices and any of the internal registers. In addition, eight
block transfer instructions are implemented. These instructions are similar to the memory
block transfers except that they use register pair HL for a pointer to the memory source
(output commands) or destination (input commands) while Register B is used as a byte
counter. Register C holds the address of the port for which the input or output command is
required. Because Register B is eight bits in length, the I/O block transfer command han-
dles up to 256 bytes.
In the IN A and OUT n, A instructions, the I/O device’s n address appears in the lower half
of the address bus (A7–A0), while the Accumulator content is transferred in the upper half
of the address bus. In all Register Indirect input output instructions, including block I/O
transfers, the contents of the C Register are transferred to the lower half of the address bus
(device address) while the contents of Register B are transferred to the upper half of the
address bus.
UM008011-0816 Input/Output
Z80 CPU
User Manual
62
Table 18. Input Group
Register
Immediate Indirect)
(n) (c)
DB ED
A
n 7B
ED
B
40
ED
C
48
Input Register ED
D
IN Address 50
ED
E
58
Input ED
H
Destination 60
ED
L
68
INI: input & ED
inc HL, Dec B A2
INIR: INP, Inc HL, ED
Dec B, repeat if B≠0 B2 Block
Register
(HL) Input
IND: input & Inc Indir ED Commands
Dec HL, Dec B AA
INDR: input, Dec HL, ED
Dec B, repeat if B≠0 BA

Z80 CPU
User Manual
63
Table 19. 8-Bit Arithmetic and Logic
Source
Register Register Indirect
A B C D E H L (HL)
D3
Immediate (n)
n
11OUT
ED ED ED ED ED ED ED
79 41 49 51 59 61 69
11OUT: output ED Block
inc HL, dec B A3 Output
11OUT: output ED Command
Register
dec B, repeat if B≠0 (c) B3
Indirect
11OUT: output ED
dec HL and B AB
11OUTDR: output, dec
ED
HL and B, repeat if
BB
B≠0
Port
Destination
Address
Note: Descriptions of the Input and Output Group instructions begin on page 294.
CPU Control Group

Table 20 shows the six general-purpose CPU control instructions. The HALT instruction
suspends CPU operation until a subsequent interrupt is received, while the DI and EI are
used to lock out and enable interrupts. The three interrupt mode commands set the CPU to
any of the three available interrupt response modes; each of these is described in the next
paragraph. The NOP instruction has no function.
UM008011-0816 CPU Control Group

Z80 CPU
User Manual
64
Table 20. Miscellaneous CPU Control
NOP 00
HALT 76
Disable INT (EI) F3
Enable INT (EI) FB
Set INT Mode 0 ED

8080A mode
IM0 46
Set INT Mode 1 ED
Call to address 0038h
IM1 56
Set INT Mode 2 ED Indirect call using Register I and B bits from
IM2 5E INTER device as a pointer
If Mode 0 is set, the interrupting device can insert any instruction on the data bus and
allow the CPU to execute it. Mode 1 is a simplified mode in which the CPU automatically
executes a restart (RST) at address 0038h so that no external hardware is required (the old
Program Counter content is pushed onto the stack). Mode 2 is the most powerful because
it allows for an indirect call to any location in memory. With this mode, the CPU forms a
16-bit memory address in which the upper eight bits are the contents of Register I, and the
lower eight bits are supplied by the interrupting device. This address points to the first of
two sequential bytes in a table in which the address of the service routine is located, as
shown in Figure 41. The CPU automatically obtains the starting address and performs a
CALL instruction to this address.
Pointer to Interrupt Table,

Address of Interrupt Register I is Upper Address,
Service Routine Peripheral Supplies
Lower Address
Figure 41. Mode 2 Interrupt Command

Z80 CPU
User Manual
65
Z80 Instruction Set

This chapter provides a description of the assembly language instructions available with
the Z80 CPU.
Z80 Assembly Language

Assembly language allows the user to write a program without concern for memory
addresses or machine instruction formats. It uses symbolic addresses to identify memory
locations and mnemonic codes (op codes and operands) to represent the instructions.
Labels (symbols) are assigned to a particular instruction step in a source program to iden-
tify that step as an entry point for use in subsequent instructions. Operands following each
instruction represent storage locations, registers, or constant values. The assembly lan-
guage also includes assembler directives that supplement the machine instruction. A
pseudo-op, for example, is a statement that is not translated to a machine instruction, but
rather is interpreted as a directive that controls the assembly process.
A program written in assembly language is called a source program, which consists of
symbolic commands called statements. Each statement is written on a single line and can
consist of one to four entries: A label field, an operation field, an operand field, and a com-
ment field. The source program is processed by the assembler to obtain a machine lan-
guage program (object program) that can be executed directly by the Z80 CPU.
Zilog provides several assemblers that differ in the features offered. Both absolute and
relocatable assemblers are available with the Development and Micro-computer Systems.
The absolute assembler is contained in base level software operating in a 16K memory
space, while the relocating assembler is part of the RIO environment operating in a 32K
memory space.
Z80 Status Indicator Flags

The Flag registers, F and F', supply information to the user about the status of the Z80
CPU at any particular time. The bit positions for each flag are listed in Table 21 and
defined in
Table 21. Flag Register Bit Positions
Bit 7 6 5 4 3 2 1 0
Position S Z X H X P/V N C
UM008011-0816 Z80 Instruction Set

Z80 CPU
User Manual
66
Table 22. Flag Definitions
Symbol Field Name

C Carry Flag
N Add/Subtract
P/V Parity/Overflow Flag
H Half Carry Flag
Z Zero Flag
S Sign Flag
X Not Used
Each of these two Flag registers contains 6 bits of status information that are set or cleared
by CPU operations; bits 3 and 5 are not used. Four of these bits (C, P/V, Z, and S) can be
tested for use with conditional JUMP, CALL, or RETURN instructions. The H and N flags
cannot be tested; these two flags are used for BCD arithmetic.
Carry Flag
The Carry Flag (C) is set or cleared depending on the operation being performed. For
ADD instructions that generate a Carry, and for SUB instructions that generate a Borrow,
the Carry Flag is set. The Carry Flag is reset by an ADD instruction that does not generate
a Carry, and by a SUB instruction that does not generate a Borrow. This saved Carry facil-
itates software routines for extended precision arithmetic. Additionally, the DAA instruc-
tion sets the Carry Flag if the conditions for making the decimal adjustment are met.
For the RLA, RRA, RLS, and RRS instructions, the Carry bit is used as a link between the
least-significant byte (LSB) and the most-significant byte (MSB) for any register or mem-
ory location. During the RLCA, RLC, and SLA instructions, the Carry flag contains the
final value shifted out of bit 7 of any register or memory location. During the RRCA,
RRC, SRA, and SRL instructions, the Carry flag contains the final value shifted out of bit
0 of any register or memory location.
For the logical instructions AND, OR, and XOR, the Carry flag is reset.
The Carry flag can also be set by the Set Carry Flag (SCF) instruction and complemented
by the Compliment Carry Flag (CCF) instruction.
Add/Subtract Flag
The Add/Subtract Flag (N) is used by the Decimal Adjust Accumulator instruction (DAA)
to distinguish between the ADD and SUB instructions. For ADD instructions, N is cleared
to 0. For SUB instructions, N is set to 1.
Z80 Instruction Set UM008011-0816

Z80 CPU
User Manual
67
Decimal Adjust Accumulator Flag

The Decimal Adjust Accumulator (DAA) instruction uses this flag to distinguish between
ADD and SUBTRACT instructions. For all ADD instructions, N sets to 0. For all SUB-
TRACT instructions, N sets to 1.
Parity/Overflow Flag
The Parity/Overflow (P/V) Flag is set to a specific state depending on the operation being
performed. For arithmetic operations, this flag indicates an overflow condition when the
result in the Accumulator is greater than the maximum possible number (+127) or is less
than the minimum possible number (–128). This overflow condition is determined by
examining the sign bits of the operands.
For addition, operands with different signs never cause overflow. When adding operands
with similar signs and the result contains a different sign, the Overflow Flag is set, as
shown in the following example.
+120 = 0111 1000 ADDEND
+105 = 0110 1001 AUGEND
+225 = 1110 0001 (–95) SUM
The two numbers added together result in a number that exceeds +127 and the two posi-
tive operands result in a negative number (–95), which is incorrect. The Overflow Flag is
therefore set.
For subtraction, overflow can occur for operands of unalike signs. Operands of alike signs
never cause overflow, as shown in the following example.
+127 0111 1111 MINUEND
(–) –64 1100 0000 SUBTRAHEND
+191 1011 1111 DIFFERENCE
The minuend sign has changed from a positive to a negative, resulting in an incorrect dif-
ference; the Overflow Flag is set.
Another method for identifying an overflow is to observe the Carry to and out of the sign
bit. If there is a Carry in and no Carry out, or if there is no Carry in and a Carry out, then
an Overflow has occurred.
This flag is also used with logical operations and rotate instructions to indicate the result-
ing parity is even. The number of 1 bits in a byte are counted. If the total is Odd, ODD par-
ity is flagged (i.e., P = 0). If the total is even, even parity is flagged (i.e., P = 1).
UM008011-0816 Decimal Adjust Accumulator Flag

Z80 CPU
User Manual
68
During the CPI, CPIR, CPD, and CPDR search instructions and the LDI, LDIR, LDD, and
LDDR block transfer instructions, the P/V Flag monitors the state of the Byte Count (BC)
Register. When decrementing, if the byte counter decrements to 0, the flag is cleared to 0;
otherwise the flag is set to1.
During the LD A, I and LD A, R instructions, the P/V Flag is set with the value of the inter-
rupt enable flip-flop (IFF2) for storage or testing.
When inputting a byte from an I/O device with an IN r, (C) instruction, the P/V Flag is
adjusted to indicate data parity.
Half Carry Flag

The Half Carry Flag (H) is set (1) or cleared (0) depending on the Carry and Borrow status
between bits 3 and 4 of an 8-bit arithmetic operation. This flag is used by the Decimal
Adjust Accumulator (DAA) instruction to correct the result of a packed BCD add or sub-
tract operation. The H Flag is set (1) or cleared (0) as shown in Table 23.
Table 23. Half Carry Flag Add/Subtract Operations
H Flag Add Subtract

1 A Carry occurs from bit 3 to bit 4 A Borrow from bit 4 occurs
0 No Carry occurs from bit 3 to bit 4 No Borrow from bit 4 occurs
Zero Flag
The Zero Flag (Z) is set (1) or cleared (0) if the result generated by the execution of certain
instructions is 0.
For 8-bit arithmetic and logical operations, the Z flag is set to a 1 if the resulting byte in
the Accumulator is 0. If the byte is not 0, the Z flag is reset to 0.
For Compare (search) instructions, the Z flag is set to 1 if the value in the Accumulator is
equal to the value in the memory location indicated by the value of the register pair HL.
When testing a bit in a register or memory location, the Z flag contains the complemented
state of the indicated bit (see Bit b, r in the Bit Set, Reset, and Test Group section on page
242).
When inputting or outputting a byte between a memory location and an INI, IND, OUTI,
or OUTD I/O device, if the result of decrementing Register B is 0, then the Z flag is 1; oth-
erwise, the Z flag is 0. Additionally, for byte inputs from I/O devices using IN r, (C), the Z
flag is set to indicate a 0-byte input.

Z80 CPU
User Manual
69
Sign Flag
The Sign Flag (S) stores the state of the most-significant bit of the Accumulator (bit 7).
When the Z80 CPU performs arithmetic operations on signed numbers, the binary twos-
complement notation is used to represent and process numeric information. A positive
number is identified by a 0 in Bit 7. A negative number is identified by a 1. The binary
equivalent of the magnitude of a positive number is stored in bits 0 to 6 for a total range of
from 0 to 127. A negative number is represented by the twos complement of the equiva-
lent positive number. The total range for negative numbers is from –1 to –128.
When inputting a byte from an I/O device to a register using an IN r, (C) instruction, the S
Flag indicates either positive (S = 0) or negative (S = 1) data.
Z80 Instruction Description

Execution time (E.T.) for each instruction is provided in microseconds for an assumed
4 MHz clock. Total machine cycles (M) are indicated with total clock periods, or T states.
Also indicated are the number of T states for each M cycle, as shown in the following
example.
M Cycles T States E.T.

2 7(4,3) 4 MHz 1.75
This example indicates that the instruction consists of two machine cycles. The first cycle
contains 4 clock periods/T states). The second cycle contains 3 clock periods, for a total of
7 clock periods/T states. The instruction executes in 1.75 microseconds.
In the register format of each of the instructions that follow, the most-significant bit to the
left and the least-significant bit to the right.
UM008011-0816 Sign Flag

Z80 CPU
User Manual
70
8-Bit Load Group

The following 8-bit load instructions are each described in this section. Simply click to
jump to an instruction’s description to learn more.
LD r, r' – see page 71
LD r,n – see page 72
LD r, (HL) – see page 74
LD r, (IX+d) – see page 75
LD r, (IY+d) – see page 77
LD (HL), r – see page 79
LD (IX+d), r – see page 81
LD (IY+d), r – see page 83
LD (HL), n – see page 85
LD (IX+d), n – see page 86
LD (IY+d), n – see page 87
LD A, (BC) – see page 88
LD A, (DE) – see page 89
LD A, (nn) – see page 90
LD (BC), A – see page 91
LD (DE), A – see page 92
LD (nn), A – see page 93
LD A, I – see page 94
LD A, R – see page 95
LD I,A – see page 96
LD R, A – see page 97

Z80 CPU
User Manual
71
LD r, r'
Operation
r, ← r′
Op Code
LD
Operands
r, r′
0 1 r r'
Description
The contents of any register r' are loaded to any other register r. r, r' identifies any of the
registers A, B, C, D, E, H, or L, assembled as follows in the object code:
Register r, C
A 111
B 000
C 001
D 010
E 011
H 100
L 101
M Cycles T States MHz E.T.

1 4 1.0
Condition Bits Affected

None.
Example
If the H Register contains the number 8Ah, and the E register contains 10h, the instruction
LD H, E results in both registers containing 10h.
UM008011-0816 Z80 Instruction Description

Z80 CPU
User Manual
72
LD r,n
Operation
r←n
Op Code
LD
Operands
r, n
0 0 r 1 1 0
Description
The 8-bit integer n is loaded to any register r, in which r identifies registers A, B, C, D, E,
H, or L, assembled as follows in the object code:
Register r
A 111
B 000
C 001
D 010
E 011
H 100
L 101
M Cycles T States 4 MHz E.T.

2 7 (4, 3) 1.75

None.

Z80 CPU
User Manual
73
Example
Upon the execution of an LD E, A5h instruction, Register E contains A5h.

Z80 CPU
User Manual
74
LD r, (HL)
Operation
r ← (HL)
Op Code
LD
Operands
r, (HL)
0 1 r 1 1 0
Description
The 8-bit contents of memory location (HL) are loaded to register r, in which r identifies
registers A, B, C, D, E, H, or L, assembled as follows in the object code:
Register r
A 111
B 000
C 001
D 010
E 011
H 100
L 101

2 7 (4, 3) 1.75

None.
Example
If register pair HL contains the number 75A1h, and memory address 75A1h contains byte
58h, the execution of LD C, (HL) results in 58h in Register C.

Z80 CPU
User Manual
75
LD r, (IX+d)
Operation
r ← (IX+d)
Op Code
LD
Operands
r, (IX+d)
1 1 0 1 1 1 0 1 DD
0 1 r 1 1 0
Description
The (IX+d) operand (i.e., the contents of Index Register IX summed with two’s-comple-
ment displacement integer d) is loaded to register r, in which r identifies registers A, B, C,
D, E, H, or L, assembled as follows in the object code:
Register r
A 111
B 000
C 001
D 010
E 011
H 100
L 101

5 19 (4, 4, 3, 5, 2.50
3)

None.

Z80 CPU
User Manual
76
Example
If Index Register IX contains the number 25AFh, the instruction LD B, (IX+19h) allows
the calculation of the sum 25AFh + 19h, which points to memory location 25C8h. If this
address contains byte 39h, the instruction results in Register B also containing 39h.

Z80 CPU
User Manual
77
LD r, (IY+d)
Operation
r ← (IY+D)
Op Code
LD
Operands
r, (lY+d)
1 1 1 1 1 1 0 1 FD
0 1 r 1 1 0
Description
The operand (lY+d) loads the contents of Index Register IY summed with two’s-comple-
ment displacement integer, d, to register r, in which r identifies registers A, B, C, D, E, H,
or L, assembled as follows in the object code:
Register r
A 111
B 000
C 001
D 010
E 011
H 100
L 101

5 19 (4, 4, 3, 5, 3) 4.75

None.

Z80 CPU
User Manual
78
Example
If Index Register IY contains the number 25AFh, the instruction LD B, (IY+19h) allows
the calculation of the sum 25AFh + 19h, which points to memory location 25C8h. If this
address contains byte 39h, the instruction results in Register B also containing 39h.

Z80 CPU
User Manual
79
LD (HL), r
Operation
(HL) ← r
Op Code
LD
Operands
(HL), r
0 1 1 1 0 r
Description
The contents of register r are loaded to the memory location specified by the contents of
the HL register pair. The r symbol identifies registers A, B, C, D, E, H, or L, assembled as
follows in the object code:
Register r
A 111
B 000
C 001
D 010
E 011
H 100
L 101

2 7 (4, 3) 1.75

None.

Z80 CPU
User Manual
80
Example
If the contents of register pair HL specify memory location 2146h and Register B contains
byte 29h, then upon the execution of an LD (HL), B instruction, memory address 2146h
also contains 29h.

Z80 CPU
User Manual
81
LD (IX+d), r
Operation
(IX+d) ← r
Op Code
LD
Operands
(IX+d), r
1 1 0 1 1 1 0 1 DD
0 1 1 1 0 r
Description
The contents of register r are loaded to the memory address specified by the contents of
Index Register IX summed with d, a two’s-complement displacement integer. The r sym-
bol identifies registers A, B, C, D, E, H, or L, assembled as follows in the object code:
Register r
A 111
B 000
C 001
D 010
E 011
H 100
L 101

5 19 (4, 4, 3, 5, 3) 4.75

None.

Z80 CPU
User Manual
82
Example
If the C register contains byte 1Ch, and Index Register IX contains 3100h, then the
instruction LID (IX + 6h), C performs the sum 3100h + 6h and loads 1Ch to memory
location 3106h.

Z80 CPU
User Manual
83
LD (IY+d), r
Operation
(lY+d) ← r
Op Code
LD
Operands
(lY+d), r
1 1 1 1 1 1 0 1 FD
0 1 1 1 0 r
Description
The contents of resister r are loaded to the memory address specified by the sum of the
contents of Index Register IY and d, a two’s-complement displacement integer. The r sym-
bol is specified according to the following table.
Register r
A 111
B 000
C 001
D 010
E 011
H 100
L 101

5 19 (4, 4, 3, 5, 3) 4.75

None.

Z80 CPU
User Manual
84
Example
If the C register contains byte 48h, and Index Register IY contains 2A11h, then the
instruction LD (IY + 4h), C performs the sum 2A11h + 4h, and loads 48h to memory
location 2A15.

Z80 CPU
User Manual
85
LD (HL), n
Operation
(HL) ← n
Op Code
LD
Operands
(HL), n
0 0 1 1 0 1 1 0 36
Description
The n integer is loaded to the memory address specified by the contents of the HL register
pair.

3 10 (4, 3, 3) 2.50

None.
Example
If the HL register pair contains 4444h, the instruction LD (HL), 28h results in the mem-
ory location 4444h containing byte 28h.

Z80 CPU
User Manual
86
LD (IX+d), n
Operation
(IX+d) ← n
Op Code
LD
Operands
(IX+d), n
1 1 0 1 1 1 0 1 DD
0 0 1 1 0 1 1 0 36
Description
The n operand is loaded to the memory address specified by the sum of Index Register IX
and the two’s complement displacement operand d.

5 19 (4, 4, 3,5,3) 4.75

None.
Example
If Index Register IX contains the number 219Ah, then upon execution of an LD (IX+5h),
5Ah instruction, byte 5Ah is contained in memory address 219Fh.

Z80 CPU
User Manual
87
LD (IY+d), n
Operation
(lY+d) ← n
Op Code
LD
Operands
(lY+d), n
1 1 1 1 1 1 0 1 FD
0 0 1 1 0 1 1 0 36
Description
The n integer is loaded to the memory location specified by the contents of Index Register
summed with the two’s-complement displacement integer, d.

5 19 (4, 4, 3, 5, 3) 2.50

None.
Example
If Index Register IY contains the number A940h, the instruction LD (IY+10h), 97h
results in byte 97h in memory location A950h.

Z80 CPU
User Manual
88
LD A, (BC)
Operation
A ← (BC)
Op Code
LD
Operands
A, (BC)
0 0 0 0 1 0 1 0 0A
Description
The contents of the memory location specified by the contents of the BC register pair are
loaded to the Accumulator.

2 7 (4, 3) 1.75

None.
Example
If the BC register pair contains the number 4747h, and memory address 4747h contains
byte 12h, then the instruction LD A, (BC) results in byte 12h in Register A.

Z80 CPU
User Manual
89
LD A, (DE)
Operation
A ← (DE)
Op Code
LD
Operands
A, (DE)
0 0 0 1 1 0 1 0 1A
Description
The contents of the memory location specified by the register pair DE are loaded to the
Accumulator.

2 7 (4, 3) 1.75

None.
Example
If the DE register pair contains the number 30A2h and memory address 30A2h contains
byte 22h, then the instruction LD A, (DE) results in byte 22h in Register A.

Z80 CPU
User Manual
90
LD A, (nn)
Operation
A ← (nn)
Op Code
LD
Operands
A, (nn)
0 0 1 1 1 0 1 0 3A
Description
The contents of the memory location specified by the operands nn are loaded to the Accu-
mulator. The first n operand after the op code is the low-order byte of a 2-byte memory
address.

4 13 (4, 3, 3, 3) 3.25

None.
Example
If nn contains 8832h and memory address 8832h contains byte 04h, then upon the execu-
tion of an LD A, (nn) instruction, the 04h byte is in the Accumulator.

Z80 CPU
User Manual
91
LD (BC), A
Operation
(BC) ← A
Op Code
LD
Operands
(BC), A
0 0 0 0 0 0 1 0 02
Description
The contents of the Accumulator are loaded to the memory location specified by the con-
tents of the register pair BC.

2 7 (4, 3) 1.75

None.
Example
If the Accumulator contains 7Ah and the BC register pair contains 1212h the instruction
LD (BC), A results in 7Ah in memory location 1212h.

Z80 CPU
User Manual
92
LD (DE), A
Operation
(DE) ← A
Op Code
LD
Operands
(DE), A
0 0 0 1 0 0 1 0 12
Description
The contents of the Accumulator are loaded to the memory location specified by the con-
tents of the DE register pair.

2 7 (4, 3) 1.75

None.
Example
If register pair DE contains 1128h and the Accumulator contains byte A0h, then the exe-
cution of a LD (DE), A instruction results in A0h being stored in memory location 1128h.

Z80 CPU
User Manual
93
LD (nn), A
Operation
(nn) ← A
Op Code
LD
Operands
(nn), A
0 0 1 1 0 0 1 0 32
Description
The contents of the Accumulator are loaded to the memory address specified by the oper-
and nn. The first n operand after the op code is the low-order byte of nn.

4 13 (4, 3, 3, 3) 3.25

None.
Example
If the Accumulator contains byte D7h, then executing an LD (3141h), AD7h instruction
results in memory location 3141h.

Z80 CPU
User Manual
94
LD A, I
Operation
A←1
Op Code
LD
Operands
A, I
1 1 1 0 1 1 0 1 ED
0 1 0 1 0 1 1 1 57
Description
The contents of the Interrupt Vector Register I are loaded to the Accumulator.

2 9 (4, 5) 2.25

S is set if the I Register is negative; otherwise, it is reset.
Z is set if the I Register is 0; otherwise, it is reset.
H is reset.
P/V contains contents of IFF2.
N is reset.
C is not affected.
If an interrupt occurs during execution of this instruction, the Parity flag contains a 0.

Z80 CPU
User Manual
95
LD A, R
Operation
A←R
Op Code
LD
Operands
A, R
1 1 1 0 1 1 0 1 ED
0 1 0 1 1 1 1 1 5F
Description
The contents of Memory Refresh Register R are loaded to the Accumulator.

2 9 (4, 5) 2.25

S is set if, R-Register is negative; otherwise, it is reset.
Z is set if the R Register is 0; otherwise, it is reset.
H is reset.
P/V contains contents of IFF2.
N is reset.
C is not affected.
If an interrupt occurs during execution of this instruction, the parity flag contains a 0.

Z80 CPU
User Manual
96
LD I,A
Operation
I←A
Op Code
LD
Operands
I, A
1 1 1 0 1 1 0 1 ED
0 1 0 0 0 1 1 1 47
Description
The contents of the Accumulator are loaded to the Interrupt Control Vector Register, I.

2 9 (4, 5) 2.25

None.

Z80 CPU
User Manual
97
LD R, A
Operation
R←A
Op Code
LD
Operands
R, A
1 1 1 0 1 1 0 1 ED
0 1 0 0 1 1 1 1 4F
Description
The contents of the Accumulator are loaded to the Memory Refresh register R.

2 9 (4, 5) 2.25

None.

Z80 CPU
User Manual
98
16-Bit Load Group

The following 16-bit load instructions are each described in this section. Simply click to
LD dd, nn – see page 99
LD IX, nn – see page 100
LD IY, nn – see page 101
LD HL, (nn) – see page 102
LD dd, (nn) – see page 103
LD IX, (nn) – see page 105
LD IY, (nn) – see page 106
LD (nn), HL – see page 107
LD (nn), dd – see page 108
LD (nn), IX – see page 110
LD (nn), IY – see page 111
LD SP, HL – see page 112
LD SP, IX – see page 113
LD SP, IY – see page 114
PUSH qq – see page 115
PUSH IX – see page 117
PUSH IY – see page 118
POP qq – see page 119
POP IX – see page 121
POP IY – see page 122

Z80 CPU
User Manual
99
LD dd, nn
Operation
dd ← nn
Op Code
LD
Operands
dd, nn
0 0 d d 0 0 0 1
Description
The 2-byte integer nn is loaded to the dd register pair, in which dd defines the BC, DE,
HL, or SP register pairs, assembled as follows in the object code:
Pair dd
BC 00
DE 01
HL 10
SP 11
The first n operand after the op code is the low-order byte.

2 10 (4, 3, 3) 2.50

None.
Example
Upon the execution of an LD HL, 5000h instruction, the HL register pair contains 5000h.

Z80 CPU
User Manual
100
LD IX, nn
Operation
IX ← nn
Op Code
LD
Operands
IX, nn
1 1 0 1 1 1 0 1 DD
0 0 1 0 0 0 0 1 21
Description
The n integer is loaded to Index Register IX. The first n operand after the op code is the
low-order byte.

4 14 (4, 4, 3, 3) 3.50

None.
Example
Upon the execution of an LD IX, 45A2h instruction, the index register contains integer
45A2h.

Z80 CPU
User Manual
101
LD IY, nn
Operation
IY ← nn
Op Code
LD
Operands
IY, nn
1 1 1 1 1 1 0 1 FD
0 0 1 0 0 0 0 1 21
Description
The nn integer is loaded to Index Register IY. The first n operand after the op code is the
low-order byte.

4 14 (4, 4, 3, 3) 3.50

None.
Example
Upon the execution of a LD IY, 7733h instruction, Index Register IY contains the integer
7733h.

Z80 CPU
User Manual
102
LD HL, (nn)
Operation
H ← (nn + 1), L ← (nn)
Op Code
LD
Operands
HL, (nn)
0 0 1 0 1 0 1 0 2A
Description
The contents of memory address (nn) are loaded to the low-order portion of register pair
HL (Register L), and the contents of the next highest memory address (nn + 1) are loaded
to the high-order portion of HL (Register H). The first n operand after the op code is the
low-order byte of nn.

5 16 (4, 3, 3, 3, 3) 4.00

None.
Example
If address 4545h contains 37h and address 4546h contains A1h, then upon the execution
of an LD HL, (4545h) instruction, the HL register pair contains A137h.

Z80 CPU
User Manual
103
LD dd, (nn)
Operation
ddh ← (nn + 1) ddl ← (nn)
Op Code
LD
Operands
dd, (nn)
1 1 1 0 1 1 0 1 ED
0 1 d d 1 0 1 1
Description
The contents of address (nn) are loaded to the low-order portion of register pair dd, and the
contents of the next highest memory address (nn + 1) are loaded to the high-order portion
of dd. Register pair dd defines BC, DE, HL, or SP register pairs, assembled as follows in
the object code:
Pair dd
BC 00
DE 01
HL 10
SP 11
The first n operand after the op code is the low-order byte of (nn).

6 20 (4, 4, 3, 3, 3, 3) 5.00

None.

Z80 CPU
User Manual
104
Example
If Address 2130h contains 65h and address 2131h contains 78h, then upon the execution
of an LD BC, (2130h) instruction, the BC register pair contains 7865h.

Z80 CPU
User Manual
105
LD IX, (nn)
Operation
IXh ← (nn + 1), IXI ← (nn)
Op Code
LD
Operands
IX, (nn)
1 1 0 1 1 1 0 1 DD
0 0 1 0 1 0 1 0 2A
Description
The contents of the address (nn) are loaded to the low-order portion of Index Register IX,
and the contents of the next highest memory address (nn + 1) are loaded to the high-order
portion of IX. The first n operand after the op code is the low-order byte of nn.

6 20 (4, 4, 3, 3, 3, 3) 5.00

None.
Example
If address 6666h contains 92h, and address 6667h contains DAh, then upon the execution
of an LD IX, (6666h) instruction, Index Register IX contains DA92h.

Z80 CPU
User Manual
106
LD IY, (nn)
Operation
IYh ← (nn + 1), IYI ← nn)
Op Code
LD
Operands
IY, (nn)
1 1 1 1 1 1 0 1 FD
0 0 1 0 1 0 1 0 2A
Description
The contents of address (nn) are loaded to the low-order portion of Index Register IY, and
the contents of the next highest memory address (nn + 1) are loaded to the high-order por-
tion of IY. The first n operand after the op code is the low-order byte of nn.

6 20 (4, 4, 3, 3, 3, 3) 5.00

None.
Example
If address 6666h contains 92h, and address 6667h contains DAh, then upon the execution
of an LD IY, (6666h) instruction, Index Register IY contains DA92h.

Z80 CPU
User Manual
107
LD (nn), HL
Operation
(nn + 1) ← H, (nn) ← L
Op Code
LD
Operands
(nn), HL
0 0 1 0 0 0 1 0 22
Description
The contents of the low-order portion of register pair HL (Register L) are loaded to mem-
ory address (nn), and the contents of the high-order portion of HL (Register H) are loaded
to the next highest memory address (nn + 1). The first n operand after the op code is the
low-order byte of nn.

5 16 (4, 3, 3, 3, 3) 4.00

None.
Example
If register pair HL contains 483Ah, then upon the execution of an LD (B2291 – 1), HL
instruction, address B229h contains 3Ah and address B22Ah contains 48h.

Z80 CPU
User Manual
108
LD (nn), dd
Operation
(nn + 1) ← ddh, (nn) ← ddl
Op Code
LD
Operands
(nn), dd
1 1 1 0 1 1 0 1 ED
0 1 d d 0 0 1 1
Description
The low-order byte of register pair dd is loaded to memory address (nn); the upper byte is
loaded to memory address (nn + 1). Register pair dd defines either BC, DE, HL, or SP,
assembled as follows in the object code:
Pair dd
BC 00
DE 01
HL 10
SP 11
The first n operand after the op code is the low-order byte of a two byte memory address.

6 20 (4, 4, 3, 3, 3, 3) 5.00

None.

Z80 CPU
User Manual
109
Example
If register pair BC contains the number 4644h, the instruction LD (1000h), BC results in
44h in memory location 1000h, and 46h in memory location 1001h.

Z80 CPU
User Manual
110
LD (nn), IX
Operation
(nn + 1) ← IXh, (nn) ← IXI
Op Code
LD
Operands
(nn), IX
1 1 0 1 1 1 0 1 DD
0 0 1 0 0 0 1 0 22
Description
The low-order byte in Index Register IX is loaded to memory address (nn); the upper order
byte is loaded to the next highest address (nn + 1). The first n operand after the op code is
the low-order byte of nn.

6 20 (4, 4, 3, 3, 3, 3) 5.00

None.
Example
If Index Register IX contains 5A30h, then upon the execution of an LD (4392h), IX
instruction, memory location 4392h contains number 30h and location 4393h contains
5Ah.

Z80 CPU
User Manual
111
LD (nn), IY
Operation
(nn + 1) ← IYh, (nn) ← IYI
Op Code
LD
Operands
(nn), IY
1 1 1 1 1 1 0 1 FD
0 0 1 0 0 0 1 0 22
Description
The low-order byte in Index Register IY is loaded to memory address (nn); the upper order
byte is loaded to memory location (nn + 1). The first n operand after the op code is the low-
order byte of nn.

6 20 (4, 4, 3, 3, 3, 3) 5.00

None.
Example
If Index Register IY contains 4174h, then upon the execution of an LD (8838h), IY
instruction, memory location 8838h contains 74h and memory location 8839h contains
41h.

Z80 CPU
User Manual
112
LD SP, HL
Operation
SP ← HL
Op Code
LD
Operands
SP, HL
1 1 1 1 1 0 0 1 F9
Description
The contents of the register pair HL are loaded to the Stack Pointer (SP).

1 6 1.5

None.
Example
If the register pair HL contains 442Eh, then upon the execution of an LD SP, HL instruc-
tion, the Stack Pointer also contains 442Eh.

Z80 CPU
User Manual
113
LD SP, IX
Operation
SP ← IX
Op Code
LD
Operands
SP, IX
1 1 0 1 1 1 0 1 DD
1 1 1 1 1 0 0 1 F9
Description
The 2-byte contents of Index Register IX are loaded to the Stack Pointer (SP).

2 10 (4, 6) 2.50

None.
Example
If Index Register IX contains 98DAh, then upon the execution of an LD SP, IX instruction,
the Stack Pointer also contains 98DAh.

Z80 CPU
User Manual
114
LD SP, IY
Operation
SP ← IY
Op Code
LD
Operands
SP, IY
1 1 1 1 1 1 0 1 FD
1 1 1 1 1 0 0 1 F9
Description
The 2-byte contents of Index Register IY are loaded to the Stack Pointer SP.

2 10 (4, 6) 2.50

None.
Example
If Index Register IY contains the integer A227h, then upon the execution of an LD SP, IY
instruction, the Stack Pointer also contains A227h.

Z80 CPU
User Manual
115
PUSH qq
Operation
(SP – 2) ← qqL, (SP – 1) ← qqH
Op Code
PUSH
Operand
qq
1 1 q q 0 1 0 1
Description
The contents of the register pair qq are pushed to the external memory last-in, first-out
(LIFO) stack. The Stack Pointer (SP) Register pair holds the 16-bit address of the current
top of the Stack. This instruction first decrements SP and loads the high-order byte of reg-
ister pair qq to the memory address specified by the SP. The SP is decremented again and
loads the low-order byte of qq to the memory location corresponding to this new address
in the SP. The operand qq identifies register pair BC, DE, HL, or AF, assembled as follows
in the object code:
Pair qq
BC 00
DE 01
HL 10
AF 11

3 11 (5, 3, 3) 2.75

None.

Z80 CPU
User Manual
116
Example
If the AF Register pair contains 2233h and the Stack Pointer contains 1007h, then upon
the execution of a PUSH AF instruction, memory address 1006h contains 22h, memory
address 1005h contains 33h, and the Stack Pointer contains 1005h.

Z80 CPU
User Manual
117
PUSH IX
Operation
(SP – 2) ← IXL, (SP – 1) ← IXH
Op Code
PUSH
Operand
IX
1 1 0 1 1 1 0 1 DD
1 1 1 0 0 1 0 1 E5
Description
The contents of Index Register IX are pushed to the external memory last-in, first-out
top of the Stack. This instruction first decrements SP and loads the high-order byte of IX
to the memory address specified by SP; then decrements SP again and loads the low-order
byte to the memory location corresponding to this new address in SP.

4 15 (4, 5, 3, 3) 3.75

None.
Example
If Index Register IX contains 2233h and the Stack Pointer contains 1007h, then upon the
execution of a PUSH IX instruction, memory address 1006h contains 22h, memory

Z80 CPU
User Manual
118
PUSH IY
Operation
(SP – 2) ← IYL, (SP – 1) ← IYH
Op Code
PUSH
Operand
IY
1 1 1 1 1 1 0 1 FD
1 1 1 0 0 1 0 1 E5
Description
The contents of Index Register IY are pushed to the external memory last-in, first-out
top of the Stack. This instruction first decrements the SP and loads the high-order byte of
IY to the memory address specified by SP; then decrements SP again and loads the low-
order byte to the memory location corresponding to this new address in SP.

4 15 (4, 5, 3, 3) 3.75

None.
Example
If Index Register IY contains 2233h and the Stack Pointer contains 1007h, then upon the
execution of a PUSH IY instruction, memory address 1006h contains 22h, memory

Z80 CPU
User Manual
119
POP qq
Operation
qqH ← (SP+1), qqL ← (SP)
Op Code
POP
Operand
qq
1 1 q q 0 0 0 1
Description
The top two bytes of the external memory last-in, first-out (LIFO) stack are popped to reg-
ister pair qq. The Stack Pointer (SP) Register pair holds the 16-bit address of the current
top of the Stack. This instruction first loads to the low-order portion of qq, the byte at the
memory location corresponding to the contents of SP; then SP is incremented and the con-
tents of the corresponding adjacent memory location are loaded to the high-order portion
of qq and the SP is now incremented again. The operand qq identifies register pair BC,
DE, HL, or AF, assembled as follows in the object code:
Pair r
BC 00
DE 01
HL 10
AF 11

3 10 (4, 3, 3) 2.50

None.

Z80 CPU
User Manual
120
Example
If the Stack Pointer contains 1000h, memory location 1000h contains 55h, and location
1001h contains 33h, the instruction POP HL results in register pair HL containing 3355h,
and the Stack Pointer containing 1002h.

Z80 CPU
User Manual
121
POP IX
Operation
IXH ← (SP+1), IXL ← (SP)
Op Code
POP
Operand
IX
1 1 0 1 1 1 0 1 DD
1 1 1 0 0 0 0 1 E1
Description
The top two bytes of the external memory last-in, first-out (LIFO) stack are popped to
Index Register IX. The Stack Pointer (SP) Register pair holds the 16-bit address of the
current top of the Stack. This instruction first loads to the low-order portion of IX the byte
at the memory location corresponding to the contents of SP; then SP is incremented and
the contents of the corresponding adjacent memory location are loaded to the high-order
portion of IX. The SP is incremented again.

4 14 (4, 4, 3, 3) 3.50

None.
Example
If the Stack Pointer contains 1000h, memory location 1000h contains 55h, and location
1001h contains 33h, the instruction POP IX results in Index Register IX containing
3355h, and the Stack Pointer containing 1002h.

Z80 CPU
User Manual
122
POP IY
Operation
IYH ← (SP – X1), IYL ← (SP)
Op Code
POP
Operand
IY
1 1 1 1 1 1 0 1 FD
1 1 1 0 0 0 0 1 E1
Description
The top two bytes of the external memory last-in, first-out (LIFO) stack are popped to
Index Register IY. The Stack Pointer (SP) Register pair holds the 16-bit address of the cur-
rent top of the Stack. This instruction first loads to the low-order portion of IY the byte at
the memory location corresponding to the contents of SP; then SP is incremented and the
contents of the corresponding adjacent memory location are loaded to the high-order por-
tion of IY. The SP is incremented again.

4 14 (4, 4, 3, 3) 3.50

None.
Example
If the Stack Pointer Contains 1000h, memory location 1000h contains 55h, and location
1001h contains 33h, the instruction POP IY results in Index Register IY containing
3355h, and the Stack Pointer containing 1002h.

Z80 CPU
User Manual
123
Exchange, Block Transfer, and Search Group

The following exchange, block transfer, and search group instructions are each described
in this section. Simply click to jump to an instruction’s description to learn more.
EX DE, HL – see page 124
EX AF, AF′ – see page 125
EXX – see page 126
EX (SP), HL – see page 127
EX (SP), IX – see page 128
EX (SP), IY – see page 129
LDI – see page 130
LDIR – see page 132
LDD – see page 134
LDDR – see page 136
CPI – see page 138
CPIR – see page 139
CPD – see page 141
CPDR – see page 142

Z80 CPU
User Manual
124
EX DE, HL
Operation
DE ↔ HL
Op Code
EX
Operands
DE, HL
1 1 1 0 1 0 1 1 EB
Description
The 2-byte contents of register pairs DE and HL are exchanged.

1 4 1.00

None.
Example
If register pair DE contains 2822h and register pair HL contains 499Ah, then upon the
execution of an EX DE, HL instruction, register pair DE contains 499Ah and register pair
HL contains 2822h.

Z80 CPU
User Manual
125
EX AF, AF′
Operation
AF ↔ AF'
Op Code
EX
Operands
AF, AF′
0 0 0 0 1 0 0 0 08
Description
The 2-byte contents of the register pairs AF and AF' are exchanged. Register pair AF con-
sists of registers A′ and F′.

1 4 1.00

None.
Example
If register pair AF contains 9900h and register pair AF′ contains 5944h, the contents of
AF are 5944h and the contents of AF′ are 9900h upon execution of the EX AF, AF′
instruction.

Z80 CPU
User Manual
126
EXX
Operation
(BC) ↔ (BC′), (DE) ↔ (DE'), (HL) ↔ (HL′)
Op Code
EXX
Operands
None.
1 1 0 1 1 0 0 1 D9
Description
Each 2-byte value in register pairs BC, DE, and HL is exchanged with the 2-byte value in
BC', DE', and HL', respectively.

1 4 1.00

None.
Example
If register pairs BC, DE, and HL contain 445Ah, 3DA2h, and 8859h, respectively, and
register pairs BC’, DE’, and HL’ contain 0988h, 9300h, and 00E7h, respectively, then
upon the execution of an EXX instruction, BC contains 0988h; DE contains 9300h; HL
contains 00E7h; BC’ contains 445Ah; DE’ contains 3DA2h; and HL’ contains 8859h.

Z80 CPU
User Manual
127
EX (SP), HL
Operation
H ↔ (SP+1), L ↔ (SP)
Op Code
EX
Operands
(SP), HL
1 1 1 0 0 0 1 1 E3
Description
The low-order byte contained in register pair HL is exchanged with the contents of the
memory address specified by the contents of register pair SP (Stack Pointer), and the high-
order byte of HL is exchanged with the next highest memory address (SP+1).

5 19 (4, 3, 4, 3, 5) 4.75

None.
Example
If the HL register pair contains 7012h, the SP register pair contains 8856h, the memory
location 8856h contains byte 11h, and memory location 8857h contains byte 22h, then
the instruction EX (SP), HL results in the HL register pair containing number 2211h,
memory location 8856h containing byte 12h, memory location 8857h containing byte
70h and Stack Pointer containing 8856h.

Z80 CPU
User Manual
128
EX (SP), IX
Operation
IXH ↔ (SP+1), IXL ↔ (SP)
Op Code
EX
Operands
(SP), IX
1 1 0 1 1 1 0 1 DD
1 1 1 0 0 0 1 1 E3
Description
The low-order byte in Index Register IX is exchanged with the contents of the memory
address specified by the contents of register pair SP (Stack Pointer), and the high-order
byte of IX is exchanged with the next highest memory address (SP+1).

6 23 (4, 4, 3, 4, 3, 5) 5.75

None.
Example
If Index Register IX contains 3988h, the SP register pair Contains 0100h, memory loca-
tion 0100h contains byte 90h, and memory location 0101h contains byte 48h, then the
instruction EX (SP), IX results in the IX register pair containing number 4890h, memory
location 0100h containing 88h, memory location 0101h containing 39h, and the Stack
Pointer containing 0100h.

Z80 CPU
User Manual
129
EX (SP), IY
Operation
IYH ↔ (SP+1), IYL ↔ (SP)
Op Code
EX
Operands
(SP), IY
1 1 1 1 1 1 0 1 FD
1 1 1 0 0 0 1 1 E3
Description
The low-order byte in Index Register IY is exchanged with the contents of the memory
address specified by the contents of register pair SP (Stack Pointer), and the high-order
byte of IY is exchanged with the next highest memory address (SP+1).

6 23 (4, 4, 3, 4, 3, 5) 5.75

None.
Example
If Index Register IY contains 3988h, the SP register pair contains 0100h, memory loca-
tion 0100h contains byte 90h, and memory location 0101h contains byte 48h, then the
instruction EX (SP), IY results in the IY register pair containing number 4890h, memory
location 0100h containing 88h, memory location 0101h containing 39h, and the Stack
Pointer containing 0100h.

Z80 CPU
User Manual
130
LDI
Operation
(DE) ← (HL), DE ← DE + 1, HL ← HL + 1, BC ← BC – 1
Op Code
LDI
Operands
None
1 1 1 0 1 1 0 1 ED
1 0 1 0 0 0 0 0 A0
Description
A byte of data is transferred from the memory location addressed, by the contents of the
HL register pair to the memory location addressed by the contents of the DE register pair.
Then both these register pairs are incremented and the Byte Counter (BC) Register pair is
decremented.

4 16 (4, 4, 3, 5) 4.00

S is not affected.
Z is not affected.
H is reset.
P/V is set if BC – 1 ≠ 0; otherwise, it is reset.
N is reset.
C is not affected.
Example
If the HL register pair contains 1111h, memory location 1111h contains byte 88h, the DE
register pair contains 2222h, the memory location 2222h contains byte 66h, and the BC

Z80 CPU
User Manual
131
register pair contains 7h, then the instruction LDI results in the following contents in reg-
ister pairs and memory addresses:
HL contains 1112h
(1111h) contains 88h
DE contains 2223h
BC contains 6H

Z80 CPU
User Manual
132
LDIR
Operation
repeat {(DE) ← (HL), DE ← DE + 1, HL ← HL + 1, BC ← BC – 1} while (BC ≠ 0)
Op Code
LDIR
Operand
None
1 1 1 0 1 1 0 1 ED
1 0 1 1 0 0 0 0 B0
Description
This 2-byte instruction transfers a byte of data from the memory location addressed by the
contents of the HL register pair to the memory location addressed by the DE register pair.
Both these register pairs are incremented and the Byte Counter (BC) Register pair is dec-
remented. If decrementing allows the BC to go to 0, the instruction is terminated. If BC is
not 0, the program counter is decremented by two and the instruction is repeated. Inter-
rupts are recognized and two refresh cycles are executed after each data transfer. When the
BC is set to 0 prior to instruction execution, the instruction loops through 64 KB.
For BC ≠ 0:

5 21 (4, 4, 3, 5, 5) 5.25
For BC = 0:

4 16 (4, 4, 3, 5) 4.00

S is not affected.
Z is not affected.
H is reset.

Z80 CPU
User Manual
133

N is reset.
C is not affected.
Example
The HL register pair contains 11111h, the DE register pair contains 2222h, the BC regis-
ter pair contains 0003h, and memory locations contain the following data.
(1111h) contains 88h (2222h) contains 66h
(1113h) contains A5h (2224h) contains C5h
Upon the execution of an LDIR instruction, the contents of register pairs and memory
locations now contain:
HL contains 1114h
DE contains 2225h
BC contains 0000h
(1113h) contains A5h (2224h) contains A5h

Z80 CPU
User Manual
134
LDD
Operation
(DE) ← (HL), DE ← DE – 1, HL ← HL– 1, BC ← BC– 1
Op Code
LDD
Operands
None.
1 1 1 0 1 1 0 1 ED
1 0 1 0 1 0 0 0 A8
Description
contents of the HL register pair to the memory location addressed by the contents of the
DE register pair. Then both of these register pairs including the Byte Counter (BC) Regis-
ter pair are decremented.

4 16 (4, 4, 3, 5) 4.00

S is not affected.
Z is not affected.
H is reset.
N is reset.
C is not affected.
Example
If the HL register pair contains 1111h, memory location 1111h contains byte 88h, the DE
register pair contains 2222h, memory location 2222h contains byte 66h, and the BC reg-

Z80 CPU
User Manual
135
ister pair contains 7h, then instruction LDD results in the following contents in register
pairs and memory addresses:
HL contains 1110h
DE contains 2221h
BC contains 6h

Z80 CPU
User Manual
136
LDDR
Operation
(DE) ← (HL), DE ← DE – 1, HL ← HL – 1, BC ← BC – 1
Op Code
LDDR
Operands
None.
1 1 1 0 1 1 0 1 ED
1 0 1 1 1 0 0 0 B8
Description
contents of the HL register pair to the memory location addressed by the contents of the
DE register pair. Then both of these registers, and the BC (Byte Counter), are decre-
mented. If decrementing causes BC to go to 0, the instruction is terminated. If BC is not 0,
the program counter is decremented by two and the instruction is repeated. Interrupts are
recognized and two refresh cycles execute after each data transfer.
When the BC is set to 0, prior to instruction execution, the instruction loops through
64 KB.
For BC ≠ 0:

5 21 (4, 4, 3, 5, 5) 5.25
For BC = 0:

4 16 (4, 4, 3, 5) 4.00

Z80 CPU
User Manual
137

S is not affected.
Z is not affected.
H is reset.
P/V is reset.
N is reset.
Example
The HL register pair contains 1114h, the DE register pair contains 2225h, the BC register
pair contains 0003h, and memory locations contain the following data.
(1114h) contains A5h (2225h) contains C5h
Upon the execution of an LDDR instruction, the contents of the register pairs and memory
locations now contain:
HL contains 1111h
DE contains 2222h
DC contains 0000h
(1114h) contains A5h (2225h) contains A5h

Z80 CPU
User Manual
138
CPI
Operation
A – (HL), HL ← HL +1, BC ← BC – 1
Op Code
CPI
Operands
None.
1 1 1 0 1 1 0 1 ED
1 0 1 0 0 0 0 1 A1
Description
The contents of the memory location addressed by the HL register is compared with the
contents of the Accumulator. With a true compare, a condition bit is set. Then HL is incre-
mented and the Byte Counter (register pair BC) is decremented.

4 16 (4, 4, 3, 5) 4.00

S is set if result is negative; otherwise, it is reset.
Z is set if A is (HL); otherwise, it is reset.
H is set if borrow from bit 4; otherwise, it is reset.
P/V is set if BC – 1 is not 0; otherwise, it is reset.
N is set.
C is not affected.
Example
If the HL register pair contains 1111h, memory location 1111h contains 3Bh, the Accu-
mulator contains 3Bh, and the Byte Counter contains 0001h. Upon the execution of a CPI
instruction, the Byte Counter contains 0000h, the HL register pair contains 1112h, the Z
flag in the F register is set, and the P/V flag in the F Register is reset. There is no effect on
the contents of the Accumulator or to address 1111h.

Z80 CPU
User Manual
139
CPIR
Operation
A – (HL), HL ← HL+1, BC ← BC – 1
Op Code
CPIR
Operands
None.
1 1 1 0 1 1 0 1 ED
1 0 1 1 0 0 0 1 B1
Description
The contents of the memory location addressed by the HL register pair is compared with
the contents of the Accumulator. During a compare operation, a condition bit is set. HL is
incremented and the Byte Counter (register pair BC) is decremented. If decrementing
causes BC to go to 0 or if A = (HL), the instruction is terminated. If BC is not 0 and A ≠
(HL), the program counter is decremented by two and the instruction is repeated. Inter-
rupts are recognized and two refresh cycles are executed after each data transfer.
If BC is set to 0 before instruction execution, the instruction loops through 64 KB if no
match is found.
For BC ≠ 0 and A ≠ (HL):

5 21 (4, 4, 3, 5, 5) 5.25
For BC = 0 and A = (HL):

4 16 (4, 4, 3, 5) 4.00

Z80 CPU
User Manual
140

Z is set if A equals (HL); otherwise, it is reset.
P/V is set if BC – 1 does not equal 0; otherwise, it is reset.
N is set.
C is not affected.
Example
If the HL register pair contains 1111h, the Accumulator contains F3h, the Byte Counter
contains 0007h, and memory locations contain the following data.
(1113h) contains F3h
Upon the execution of a CPIR instruction, register pair HL contains 1114h, the Byte
Counter contains 0004h, the P/V flag in the F Register is set, and the Z flag in the F Reg-
ister is set.

Z80 CPU
User Manual
141
CPD
Operation
A – (HL), HL ← HL – 1, BC ← BC – 1
Op Code
CPD
Operands
None.
1 1 1 0 1 1 0 1 ED
1 0 1 0 1 0 0 1 A9
Description
the contents of the Accumulator. During a compare operation, a condition bit is set. The
HL and Byte Counter (register pair BC) are decremented.

4 16 (4, 4, 3, 5) 4.00

Z is set if A equals (HL); otherwise, it is reset.
P/V is set if BC – 1≠ 0; otherwise, it is reset.
N is set.
C is not affected.
Example
If the HL register pair contains 1111h, memory location 1111h contains 3Bh, the Accu-
mulator contains 3Bh, and the Byte Counter contains 0001h. Upon the execution of a
CPD instruction, the Byte Counter contains 0000h, the HL register pair contains 1110h,
the flag in the F Register is set, and the P/V flag in the F Register is reset. There is no
effect on the contents of the Accumulator or address 1111h.

Z80 CPU
User Manual
142
CPDR
Operation
A – (HL), HL ← HL – 1, BC ← BC – 1
Op Code
CPDR
Operands
None.
1 1 1 0 1 1 0 1 ED
1 0 1 1 1 0 0 1 B9
Description
the contents of the Accumulator. During a compare operation, a condition bit is set. The
HL and Byte Counter (BC) Register pairs are decremented. If decrementing allows the BC
to go to 0 or if A = (HL), the instruction is terminated. If BC is not 0 and A = (HL), the
program counter is decremented by two and the instruction is repeated. Interrupts are rec-
ognized and two refresh cycles execute after each data transfer. When the BC is set to 0,
prior to instruction execution, the instruction loops through 64 KB if no match is found.
For BC ≠ 0 and A ≠ (HL):

5 21 (4, 4, 3, 5, 5) 5.25
For BC = 0 and A = (HL):

4 16 (4, 4, 3, 5) 4.00

Z is set if A = (HL); otherwise, it is reset.
H is set if borrow form bit 4; otherwise, it is reset.

Z80 CPU
User Manual
143

N is set.
C is not affected.
Example
The HL register pair contains 1118h, the Accumulator contains F3h, the Byte Counter
contains 0007h, and memory locations contain the following data.
(1116h) contains F3h
Upon the execution of a CPDR instruction, register pair HL contains 1115h, the Byte
Counter contains 0004h, the P/V flag in the F Register is set, and the Z flag in the F Reg-
ister is set.

Z80 CPU
User Manual
144
8-Bit Arithmetic Group

The following 8-bit arithmetic group instructions are each described in this section. Sim-
ply click to jump to an instruction’s description to learn more.
ADD A, r – see page 145
ADD A, n – see page 147
ADD A, (HL) – see page 148
ADD A, (IX + d) – see page 149
ADD A, (IY + d) – see page 150
ADC A, s – see page 151
SUB s – see page 153
SBC A, s – see page 155
AND s – see page 157
OR s – see page 159
XOR s – see page 161
CP s – see page 163
INC r – see page 165
INC (HL) – see page 167
INC (IX+d) – see page 168
INC (IY+d) – see page 169
DEC m – see page 170

Z80 CPU
User Manual
145
ADD A, r
Operation
A←A+r
Op Code
ADD
Operands
A, r
1 0 0 0 0 r
Description
The contents of register r are added to the contents of the Accumulator, and the result is
stored in the Accumulator. The r symbol identifies the registers A, B, C, D, E, H, or L,
assembled as follows in the object code:
Register r
A 111
B 000
C 001
D 010
E 011
H 100
L 101

1 4 1.00

Z is set if result is 0; otherwise, it is reset.
H is set if carry from bit 3; otherwise, it is reset.

Z80 CPU
User Manual
146
P/V is set if overflow; otherwise, it is reset.

N is reset.
C is set if carry from bit 7; otherwise, it is reset.
Example
If the Accumulator contains 44h and Register C contains 11h, then upon the execution of
an ADD A, C instruction, the Accumulator contains 55h.

Z80 CPU
User Manual
147
ADD A, n
Operation
A←A+n
Op Code
ADD
Operands
A, n
1 1 0 0 0 1 1 0 C6
Description
The n integer is added to the contents of the Accumulator, and the results are stored in the
Accumulator.

2 7 (4, 3) 1.75

N is reset.
Example
If the Accumulator contains 23h, then upon the execution of an ADD A, 33h instruction,
the Accumulator contains 56h.

Z80 CPU
User Manual
148
ADD A, (HL)
Operation
A ← A + (HL)
Op Code
ADD
Operands
A, (HL)
1 0 0 0 0 1 1 0 86
Description
The byte at the memory address specified by the contents of the HL register pair is added
to the contents of the Accumulator, and the result is stored in the Accumulator.

2 7 (4, 3) 1.75

N is reset.
Example
If the Accumulator contains A0h, register pair HL contains 2323h, and memory location
2323h contains byte 08h, then upon the execution of an ADD A, (HL) instruction, the
Accumulator contains A8h.

Z80 CPU
User Manual
149
ADD A, (IX + d)
Operation
A ← A + (IX+d)
Op Code
ADD
Operands
A, (IX + d)
1 1 0 1 1 1 0 1 DD
1 0 0 0 0 1 1 0 86
Description
The contents of the Index (register pair IX) Register is added to a two’s complement dis-
placement d to point to an address in memory. The contents of this address is then added to
the contents of the Accumulator and the result is stored in the Accumulator.

5 19 (4, 4, 3, 5, 3) 4.75

N is reset.
Example
If the Accumulator contains 11h, Index Register IX contains 1000h, and memory location
1005h contains 22h, then upon the execution of an ADD A, (IX + 5h) instruction, the
Accumulator contains 33h.

Z80 CPU
User Manual
150
ADD A, (IY + d)
Operation
A ← A + (IY+d)
Op Code
ADD
Operands
A, (IY + d)
1 1 1 1 1 1 0 1 FD
1 0 0 0 0 1 1 0 86
Description
The contents of the Index (register pair IY) Register is added to a two’s complement dis-
placement d to point to an address in memory. The contents of this address is then added to
the contents of the Accumulator, and the result is stored in the Accumulator.

5 19(4, 4, 3, 5, 3) 4.75

H is set if carry from bit 3: otherwise, it is reset.
N is reset.
Example
If the Accumulator contains 11h, Index Register IY contains 1000h, and memory location
1005h contains 22h, then upon the execution of an ADD A, (IY + 5h) instruction, the
Accumulator contains 33h.

Z80 CPU
User Manual
151
ADC A, s
Operation
A ← A + s + CY
Op Code
ADC
Operands
A, s
This s operand is any of r, n, (HL), (IX+d), or (lY+d) as defined for the analogous ADD
instruction. These possible op code/operand combinations are assembled as follows in the
object code:
ADC A,r 1 0 0 0 1 r*
ADC A,n 1 1 0 0 1 1 1 0 CE
ADC A, (HL) 1 0 0 0 1 1 1 0 8E
ADC A, (IX+d) 1 1 0 1 1 1 1 0 DD
1 0 0 0 1 1 1 0 8E
ADC A, (IY+d) 1 1 1 1 1 1 0 1 FD
1 0 0 0 1 1 1 0 8E

Z80 CPU
User Manual
152
r identifies registers B, C, D, E, H, L, or A, assembled as follows in the object code field:
Register r
B 000
C 001
D 010
E 011
H 100
L 101
A 111
Description
The s operand, along with the Carry Flag (C in the F Register) is added to the contents of
the Accumulator, and the result is stored in the Accumulator.
Instruction M Cycle T States 4 MHz E.T.

ADC A, r 1 4 1.00
ADC A, n 2 7 (4, 3) 1.75
ADC A, (HL) 2 7 (4, 3) 1.75
ADC A, (IX+d) 5 19 (4, 4, 3, 5, 3) 4.75
ADC A, (lY+d) 5 19 (4, 4, 3, 5, 3) 4.75

N is reset.
C is set if carry from bit 7: otherwise, it is reset.
Example
If the Accumulator contents are 16h, the Carry Flag is set, the HL register pair contains
6666h, and address 6666h contains 10h, then upon the execution of an ADC A, (HL)
instruction, the Accumulator contains 27h.

Z80 CPU
User Manual
153
SUB s
Operation
A←A–s
Op Code
SUB
Operand
s
This s operand is any of r, n, (HL), (IX+d), or (lY+d) as defined for the analogous ADD
instruction. These possible op code/operand combinations are assembled as follows in the
object code:
SUB r 1 0 0 1 0 r*
SUB n 1 1 0 1 0 1 1 0 D6
SUB (HL) 1 0 0 1 0 1 1 0 96
SUB (IX+d) 1 1 0 1 1 1 0 1 DD
1 0 0 1 0 1 1 0 96
SUB (IY+d) 1 1 1 1 1 1 0 1 FD
1 0 0 1 0 1 1 0 96

Z80 CPU
User Manual
154
r identifies registers B, C, D, E, H, L, or A assembled as follows in the object code field:
Register r
B 000
C 001
D 010
E 011
H 100
L 101
A 111
Description
The s operand is subtracted from the contents of the Accumulator, and the result is stored
in the Accumulator.
Instruction M Cycle T States 4 MHz E.T.

SUB r 1 4 1.00
SUB n 2 7 (4, 3) 1.75
SUB (HL) 2 7 (4, 3) 1.75
SUB (IX+d) 5 19 (4, 4, 3, 5, 3) 4.75
SUB (lY+d) 5 19 (4, 4, 3, 5, 3) 4.75

N is set.
C is set if borrow; otherwise, it is reset.
Example
If the Accumulator contents are 29h, and the D Register contains 11h, then upon the exe-
cution of a SUB D instruction, the Accumulator contains 18h.

Z80 CPU
User Manual
155
SBC A, s
Operation
A ← A – s – CY
Op Code
SBC
Operands
A, s
The s operand is any of r, n, (HL), (IX+d), or (lY+d) as defined for the analogous ADD
instructions. These possible op code/operand combinations are assembled as follows in
the object code.
SBC A, r 1 0 0 1 1 r*
SBC A, n 1 1 0 1 1 1 1 0 DE
SBC A, (HL) 1 0 0 1 1 1 1 0 9E
SBC A, (IX+d) 1 1 0 1 1 1 0 1 DD
1 0 0 1 1 1 1 0 9E
SBC A, (IY+d) 1 1 1 1 1 1 0 1 FD
1 0 0 1 1 1 1 0 9E

Z80 CPU
User Manual
156
Register r
B 000
C 001
D 010
E 011
H 100
L 101
A 111
Description
The s operand, along with the Carry flag (C in the F Register) is subtracted from the con-
tents of the Accumulator, and the result is stored in the Accumulator.
Instruction M Cycles T States 4 MHz E.T.

SBC A, r 1 4 1.00
SBC A, n 2 7(4, 3) 1.75
SBC A, (HL) 2 7 (4, 3) 1.75
SBC A, (IX+d) 5 19 (4, 4, 3, 5, 3) 4.75
SBC A, (lY+d) 5 19 (4, 4, 3, 5, 3) 4.75

P/V is reset if overflow; otherwise, it is reset.
N is set.
Example
If the Accumulator contains 16h, the carry flag is set, the HL register pair contains 3433h,
and address 3433h contains 05h, then upon the execution of an SBC A, (HL) instruction,
the Accumulator contains 10h.

Z80 CPU
User Manual
157
AND s
Operation
A←A˄s
Op Code
AND
Operand
s
The s operand is any of r, n, (HL), (IX+d), or (lY+d), as defined for the analogous ADD
the object code:
AND r* 1 0 1 0 0 r*
AND n 1 1 1 0 0 1 1 0 E6
AND (HL) 1 0 1 0 0 1 1 0 A6
AND (IX+d) 1 1 0 1 1 1 0 1 DD
1 0 1 0 0 1 1 0 A6
AND (IY+d) 1 1 1 1 1 1 0 1 FD
1 0 1 0 0 1 1 0 A6

Z80 CPU
User Manual
158
r identifies registers B, C, D, E, H, L, or A specified in the assembled object code field, as

follows:
Register r
B 000
C 001
D 010
E 011
H 100
L 101
A 111
Description
A logical AND operation is performed between the byte specified by the s operand and the
byte contained in the Accumulator; the result is stored in the Accumulator.

AND r 1 4 1.00
AND n 2 7 (4, 3) 1.75
AND (HL) 2 7 (4, 3) 1.75
AND (IX+d) 5 19 (4, 4, 3, 5, 3) 4.75
AND (IX+d) 5 19 (4, 4, 3. 5, 3) 4.75

H is set.
P/V is reset if overflow; otherwise, it is reset.
N is reset.
C is reset.
Example
If Register B contains 7Bh (0111 1011) and the Accumulator contains C3h (1100 0011),
then upon the execution of an AND B instruction, the Accumulator contains 43h (0100
0011).

Z80 CPU
User Manual
159
OR s
Operation
A←A˅s
Op Code
OR
Operand
s
the object code:
OR r* 1 0 1 1 0 r*
OR n 1 1 1 1 0 1 1 0 F6
OR (HL) 1 0 1 1 0 1 1 0 B6
OR (IX+d) 1 1 0 1 1 1 0 1 DD
1 0 1 1 0 1 1 0 B6
OR (IY+d) 1 1 1 1 1 1 0 1 FD
1 0 1 1 0 1 1 0 B6

Z80 CPU
User Manual
160
r identifies registers B, C–, D, E, H, L, or A specified in the assembled object code field,

as follows:
Register r
B 000
C 001
D 010
E 011
H 100
L 101
A 111
Description
A logical OR operation is performed between the byte specified by the s operand and the
byte contained in the Accumulator; the result is stored in the Accumulator.

OR r 1 4 1.00
OR n 2 7 (4, 3) 1.75
OR (HL) 2 7 (4, 3) 1.75
OR (IX+d) 5 19 (4, 4, 3, 5, 3) 4.75
OR (lY+d) 5 19 (4, 4, 3, 5, 3) 4.75

H is reset.
N is reset.
C is reset.
Example
If the H Register contains 48h (0100 0100), and the Accumulator contains 12h (0001
0010), then upon the execution of an OR H instruction, the Accumulator contains 5Ah
(0101 1010).

Z80 CPU
User Manual
161
XOR s
Operation
A←A ⊕s
Op Code
XOR
Operand
s
instructions. These possible Op Code/operand combinations are assembled as follows in
the object code:
XOR r* 1 0 1 0 1 r*
XOR n 1 1 1 0 1 1 1 0 EE
XOR (HL) 1 0 1 0 1 1 1 0 AE
XOR (IX+d) 1 1 0 1 1 1 0 1 DD
1 0 1 0 1 1 1 0 AE
XOR (IY+d) 1 1 1 1 1 1 0 1 FD
1 0 1 0 1 1 1 0 AE

Z80 CPU
User Manual
162

follows:
Register r
B 000
C 001
D 010
E 011
H 100
L 101
A 1l1
Description
The logical exclusive-OR operation is performed between the byte specified by the s oper-
and and the byte contained in the Accumulator; the result is stored in the Accumulator.

XOR r 1 4 1.00
XOR n 2 7 (4, 3) 1.75
XOR (HL) 2 7 (4, 3) 1.75
XOR (IX+d) 5 19 (4, 4, 3, 5, 3) 4.75
XOR (lY+d) 5 19 (4, 4, 3, 5, 3) 4.75

H is reset.
P/V is set if parity even; otherwise, it is reset.
N is reset.
C is reset.
Example
If the Accumulator contains 96h (1001 0110), then upon the execution of an XOR 5Dh
(5Dh = 0101 1101) instruction, the Accumulator contains CBh (1100 1011).

Z80 CPU
User Manual
163
CP s
Operation
A–s
Op Code
CP
Operand
s
the object code:
CP r* 1 0 1 1 1 r*
CP n 1 1 1 1 1 1 1 0 FE
CP (HL) 1 0 1 1 1 1 1 0 BE
CP (IX+d) 1 1 0 1 1 1 0 1 DD
1 0 1 1 1 1 1 0 BE
CP (IY+d) 1 1 1 1 1 1 0 1 FD
1 0 1 1 1 1 1 0 BE

Z80 CPU
User Manual
164

follows:
Register r
B 000
C 001
D 010
E 011
H 100
L 101
A 111
Description
The contents of the s operand are compared with the contents of the Accumulator. If there
is a true compare, the Z flag is set. The execution of this instruction does not affect the
contents of the Accumulator.

CP r 1 4 1.00
CP n 2 7(4, 3) 1.75
CP (HL) 2 7 (4, 3) 1.75
CP (IX+d) 5 19 (4, 4, 3, 5, 3) 4.75
CP (lY+d) 5 19 (4, 4, 3, 5, 3) 4.75

N is set.
Example
If the Accumulator contains 63h, the HL register pair contains 6000h, and memory loca-
tion 6000h contains 60h, the instruction CP (HL) results in the PN flag in the F Register
resetting.

Z80 CPU
User Manual
165
INC r
Operation
r←r+1
Op Code
INC
Operand
r
0 0 r 1 0 0
Description
Register r is incremented and register r identifies any of the registers A, B, C, D, E, H, or
L, assembled as follows in the object code.
Register r
A 111
B 000
C 001
D 010
E 011
H 100
L 101

1 4 1.00

P/V is set if r was 7Fh before operation; otherwise, it is reset.

Z80 CPU
User Manual
166
N is reset.
C is not affected.
Example
If the D Register contains 28h, then upon the execution of an INC D instruction, the D
Register contains 29h.

Z80 CPU
User Manual
167
INC (HL)
Operation
(HL) ← (HL) + 1
Op Code
INC
Operand
(HL)
0 0 1 1 0 1 0 0 34
Description
The byte contained in the address specified by the contents of the HL register pair is incre-
mented.

3 11 (4, 4, 3) 2.75

P/V is set if (HL) was 7Fh before operation; otherwise, it is reset.
N is reset.
C is not affected.
Example
If the HL register pair contains 3434h and address 3434h contains 82h, then upon the
execution of an INC (HL) instruction, memory location 3434h contains 83h.

Z80 CPU
User Manual
168
INC (IX+d)
Operation
(IX+d) ← (IX+d) + 1
Op Code
INC
Operands
(IX+d)
1 1 0 1 1 1 0 1 DD
0 0 1 1 0 1 0 0 34
Description
The contents of Index Register IX (register pair IX) are added to the two’s-complement
displacement integer, d, to point to an address in memory. The contents of this address are
then incremented.

6 23 (4, 4, 3, 5, 4, 3) 5.75

P/V is set if (IX+d) was 7Fh before operation; otherwise, it is reset.
N is reset.
C is not affected.
Example
If Index Register pair IX contains 2020h and memory location 2030h contains byte 34h,
then upon the execution of an INC (IX+10h) instruction, memory location 2030h con-
tains 35h.

Z80 CPU
User Manual
169
INC (IY+d)
Operation
(lY+d) ← (lY+d) + 1
Op Code
INC
Operands
(lY+d)
1 1 1 1 1 1 0 1 FD
0 0 1 1 0 1 0 0 34
Description
The contents of Index Register IY (register pair IY) are added to the two’s-complement
displacement integer, d, to point to an address in memory. The contents of this address are
then incremented.

6 23 (4, 4, 3, 5, 4, 3) 5.75

P/V is set if (lY+d) was 7Fh before operation; otherwise, it is reset.
N is reset.
C is not affected.
Example
If Index Register IY are 2020h and memory location 2030h contains byte 34h, then upon
the execution of an INC (IY+10h) instruction, memory location 2030h contains 35h.

Z80 CPU
User Manual
170
DEC m
Operation
m←m–1
Op Code
DEC
Operand
m
The m operand is any of r, (HL), (IX+d), or (lY+d), as defined for the analogous INC
the object code:
DEC r* 0 0 r 1 0 1
DEC (HL) 0 0 1 1 0 1 0 1 35
DEC (IX+d) 1 1 0 1 1 1 0 1 DD
0 0 1 1 0 1 0 1 35
DEC (IY+d) 1 1 1 1 1 1 0 1 FD
0 0 1 1 0 1 0 1 35
Register r
B 000
C 001
D 010
E 011
H 100
L 101
A 111

Z80 CPU
User Manual
171
Description
The byte specified by the m operand is decremented.

DEC r 1 4 1.00
DEC (HL) 3 11 (4, 4, 3) 2.75
DEC (IX+d) 6 23 (4, 4, 3, 5, 4, 3) 5.75
DEC (lY+d) 6 23 (4, 4, 3, 5, 4, 3) 5.75

H is set if borrow from bit 4, otherwise, it is reset.
P/V is set if m was 80h before operation; otherwise, it is reset.
N is set.
C is not affected.
Example
If the D Register contains byte 2Ah, then upon the execution of a DEC D instruction, the D
Register contains 29h.

Z80 CPU
User Manual
172
General-Purpose Arithmetic and CPU

Control Groups
The following general-purpose arithmetic and CPU control group instructions are each
described in this section. Simply click to jump to an instruction’s description to learn
more.
DAA – see page 173
CPL – see page 175
NEG – see page 176
CCF – see page 178
SCF – see page 179
NOP – see page 180
HALT – see page 181
DI – see page 182
EI – see page 183
IM 0 – see page 184

Z80 CPU
User Manual
173
DAA
Operation
@
Op Code
DAA
0 0 1 0 0 1 1 1 27
Operands
None.
Description
This instruction conditionally adjusts the Accumulator for BCD addition and subtraction
operations. For addition (ADD, ADC, INC) or subtraction (SUB, SBC, DEC, NEG), the
following table indicates the operation being performed:
Hex Value Hex Value

In Upper In Lower Number
C Before Digit H Before Digit Added To C After
Operation DAA (Bits 7–4) DAA (Bits 3–0) Byte DAA
0 9–0 0 0–9 00 0
0 0–8 0 A–F 06 0
0 0–9 1 0–3 06 0
ADD 0 A–F 0 0–9 60 1
ADC 0 9–F 0 A–F 66 1
INC 0 A–F 1 0–3 66 1
1 0–2 0 0–9 60 1
1 0–2 0 A–F 66 1
1 0–3 1 0–3 66 1
SUB 0 0–9 0 0–9 00 0
SBC 0 0–8 1 6–F FA 0
DEC 1 7–F 0 0–9 A0 1
NEG 1 6–7 1 6–F 9A 1

Z80 CPU
User Manual
174

1 4 1.00

S is set if most-significant bit of the Accumulator is 1 after an operation; otherwise, it is
reset.
Z is set if the Accumulator is 0 after an operation; otherwise, it is reset.
H: see the DAA instruction table on the previous page.
P/V is set if the Accumulator is at even parity after an operation; otherwise, it is reset.
N is not affected.
C: see the DAA instruction table on the previous page.
Example
An addition operation is performed between 15 (BCD) and 27 (BCD); simple decimal
arithmetic provides the following result:
15
+ 27
42
The binary representations are added in the Accumulator according to standard binary
arithmetic, as follows:
0001 0101
+ 0010 0111
0011 1100 = 3C
The sum is ambiguous. The DAA instruction adjusts this result so that the correct BCD
representation is obtained, as follows:
0011 1100
+ 0000 0110
0100 0010 = 42

Z80 CPU
User Manual
175
CPL
Operation
A←A
Op Code
CPL
0 0 1 0 1 1 1 1 2F
Operands
None.
Description
The contents of the Accumulator (Register A) are inverted (one’s complement).

1 4 1.00

S is not affected.
Z is not affected.
H is set.
P/V is not affected.
N is set.
C is not affected.
Example
If the Accumulator contains 1011 0100, then upon the execution of a CPL instruction, the
Accumulator contains 0100 1011.

Z80 CPU
User Manual
176
NEG
Operation
A←0–A
Op Code
NEG
1 1 1 0 1 1 0 1 ED
0 1 0 0 0 1 0 0 44
Operands
None.
Description
The contents of the Accumulator are negated (two’s complement). This method is the
same as subtracting the contents of the Accumulator from zero.
Note: The 80h address remains unchanged.

2 8 (4, 4) 2.00

P/V is set if Accumulator was 80h before operation; otherwise, it is reset.
N is set.
C is set if Accumulator was not 00h before operation; otherwise, it is reset.

Z80 CPU
User Manual
177
Example
The Accumulator contains the following data:
1 0 0 1 1 0 0 0
Upon the execution of a NEG instruction, the Accumulator contains:
0 1 1 0 1 0 0 0

Z80 CPU
User Manual
178
CCF
Operation
CY ← CY
Op Code
CCF
0 0 1 1 1 1 1 1 3F
Operands
None.
Description
The Carry flag in the F Register is inverted.

1 4 1.00

S is not affected.
Z is not affected.
H, previous carry is copied.
N is reset.
C is set if CY was 0 before operation; otherwise, it is reset.

Z80 CPU
User Manual
179
SCF
Operation
CY ← 1
Op Code
SCF
0 0 1 1 0 1 1 1 37
Operands
None.
Description
The Carry flag in the F Register is set.

1 4 1.00

S is not affected.
Z is not affected.
H is reset.
N is reset.
C is set.

Z80 CPU
User Manual
180
NOP
Operation
—
Op Code
NOP
0 0 0 0 0 0 0 0 00
Operands
None.
Description
The CPU performs no operation during this machine cycle.

1 4 1.00

None.

Z80 CPU
User Manual
181
HALT
Operation
—
Op Code
HALT
0 1 1 1 0 1 1 0 76
Operands
None.
Description
The HALT instruction suspends CPU operation until a subsequent interrupt or reset is
received. While in the HALT state, the processor executes NOPs to maintain memory
refresh logic.

1 4 1.00

None.

Z80 CPU
User Manual
182
DI
Operation
IFF ← 0
Op Code
DI
1 1 1 1 0 0 1 1 F3
Operands
None.
Description
DI disables the maskable interrupt by resetting the interrupt enable flip-flops (IFF1 and
IFF2).
Note: This instruction disables the maskable interrupt during its execution.

1 4 1.00

None.
Example
When the CPU executes the instruction DI the maskable interrupt is disabled until it is
subsequently re-enabled by an EI instruction. The CPU does not respond to an Interrupt
Request (INT) signal.

Z80 CPU
User Manual
183
EI
Operation
IFF ← 1
Op Code
EI
1 1 1 1 1 0 1 1 FB
Operands
None.
Description
The enable interrupt instruction sets both interrupt enable flip flops (IFFI and IFF2) to a
logic 1, allowing recognition of any maskable interrupt.
Note: During the execution of this instruction and the following instruction, maskable interrupts
are disabled.

1 4 1.00

None.
Example
When the CPU executes an EI RETI instruction, the maskable interrupt is enabled then
upon the execution of an the RETI instruction.

Z80 CPU
User Manual
184
IM 0
Operation
Set Interrupt Mode 0
Op Code
IM
Operand
0
1 1 1 0 1 1 0 1 ED
0 1 0 0 0 1 1 0 46
Description
The IM 0 instruction sets Interrupt Mode 0. In this mode, the interrupting device can insert
any instruction on the data bus for execution by the CPU. The first byte of a multi-byte
instruction is read during the interrupt acknowledge cycle. Subsequent bytes are read in by
a normal memory read sequence.

2 8 (4, 4) 2.00

None.

Z80 CPU
User Manual
185
IM 1
Operation
Op Code
IM
Operand
1
1 1 1 0 1 1 0 1 ED
0 1 0 1 0 1 1 0 56
Description
The IM 1 instruction sets Interrupt Mode 1. In this mode, the processor responds to an
interrupt by executing a restart at address 0038h.

2 8 (4, 4) 2.00

None.

Z80 CPU
User Manual
186
IM 2
Operation
Op Code
IM
Operand
2
1 1 1 0 1 1 0 1 ED
0 1 0 1 1 1 1 0 5E
Description
The IM 2 instruction sets the vectored Interrupt Mode 2. This mode allows an indirect call
to any memory location by an 8-bit vector supplied from the peripheral device. This vector
then becomes the least-significant eight bits of the indirect pointer, while the I Register in
the CPU provides the most-significant eight bits. This address points to an address in a
vector table that is the starting address for the interrupt service routine.

2 8 (4, 4) 2.00

None.

Z80 CPU
User Manual
187
16-Bit Arithmetic Group

The following 16-bit arithmetic group instructions are each described in this section. Sim-
ADD HL, ss – see page 188
ADC HL, ss – see page 190
SBC HL, ss – see page 192
ADD IX, pp – see page 194
ADD IY, rr – see page 196
INC ss – see page 198
INC IX – see page 199
INC IY – see page 200
DEC ss – see page 201
DEC IX – see page 202
DEC IY – see page 203

Z80 CPU
User Manual
188
ADD HL, ss
Operation
HL ← HL + ss
Op Code
ADD
Operands
HL, ss
0 0 s s 1 0 0 1
Description
The contents of register pair ss (any of register pairs BC, DE, HL, or SP) are added to the
contents of register pair HL and the result is stored in HL. In the assembled object code,
operand ss is specified as follows:
Register
Pair ss
BC 00
DE 01
HL 10
SP 11

3 11 (4, 4, 3) 2.75

S is not affected.
Z is not affected.
N is reset.

Z80 CPU
User Manual
189
Example
If register pair HL contains the integer 4242h and register pair DE contains 1111h, then
upon the execution of an ADD HL, DE instruction, the HL register pair contains 5353h.

Z80 CPU
User Manual
190
ADC HL, ss
Operation
HL ← HL + ss + CY
Op Code
ADC
Operands
HL, ss
1 1 1 0 1 1 0 1 ED
0 1 s s 1 0 1 0
Description
The contents of register pair ss (any of register pairs BC, DE, HL, or SP) are added with
the Carry flag (C flag in the F Register) to the contents of register pair HL, and the result is
stored in HL. In the assembled object code, operand ss is specified as follows:
Register
Pair ss
BC 00
DE 01
HL 10
SP 11

4 15 (4, 4, 4, 3) 3.75


Z80 CPU
User Manual
191
N is reset.
Example
If register pair BC contains 2222h, register pair HL contains 5437h, and the Carry Flag is
set, then upon the execution of an ADC HL, BC instruction, HL contains 765Ah.

Z80 CPU
User Manual
192
SBC HL, ss
Operation
HL ← HL – ss – CY
Op Code
SBC
Operands
HL, ss
1 1 1 0 1 1 0 1 ED
0 1 s s 0 0 1 0
Description
The contents of the register pair ss (any of register pairs BC, DE, HL, or SP) and the Carry
Flag (C flag in the F Register) are subtracted from the contents of register pair HL, and the
result is stored in HL. In the assembled object code, operand ss is specified as follows:
Register
Pair ss
BC 00
DE 01
HL 10
SP 11

4 15 (4, 4, 4, 3) 3.75


Z80 CPU
User Manual
193
N is set.
Example
If the HL register pair contains 9999h, register pair DE contains 1111h, and the Carry
flag is set, then upon the execution of an SBC HL, DE instruction, HL contains 8887h.

Z80 CPU
User Manual
194
ADD IX, pp
Operation
IX ← IX + pp
Op Code
ADD
Operands
IX, pp
1 1 0 1 1 1 0 1 DD
0 0 p p 1 0 0 1
Description
The contents of register pair pp (any of register pairs BC, DE, IX, or SP) are added to the
contents of Index Register IX, and the results are stored in IX. In the assembled object
code, operand pp is specified as follows:
Register
Pair ss
BC 00
DE 01
IX 10
SP 11

4 15 (4, 4, 4, 3) 3.75

S is not affected.
Z is not affected.

Z80 CPU
User Manual
195
N is reset.
Example
If Index Register IX contains 333h and register pair BC contains 5555h, then upon the
execution of an ADD IX, BC instruction, IX contains 8888h.

Z80 CPU
User Manual
196
ADD IY, rr
Operation
IY ← IY + rr
Op Code
ADD
Operands
IY, rr
1 1 1 1 1 1 0 1 FD
0 0 r r 1 0 0 1
Description
The contents of register pair rr (any of register pairs BC, DE, IY, or SP) are added to the
contents of Index Register IY, and the result is stored in IY. In the assembled object code,
the rr operand is specified as follows:
Register
Pair ss
BC 00
DE 01
IY 10
SP 11

4 15 (4, 4, 4, 3) 3.75

S is not affected.
Z is not affected.

Z80 CPU
User Manual
197
N is reset.
Example
If Index Register IY contains 333h and register pair BC contains 555h, then upon the exe-
cution of an ADD IY, BC instruction, IY contains 8888h.

Z80 CPU
User Manual
198
INC ss
Operation
ss ← ss + 1
Op Code
INC
Operand
ss
0 0 s s 0 0 1 1
Description
The contents of register pair ss (any of register pairs BC, DE, HL, or SP) are incremented.
In the assembled object code, operand ss is specified as follows:
Register
Pair ss
BC 00
DE 01
HL 10
SP 11

1 6 1.50

None.
Example
If the register pair contains 1000h, then upon the execution of an INC HL instruction, HL
contains 1001h.

Z80 CPU
User Manual
199
INC IX
Operation
IX ← IX + 1
Op Code
INC
Operand
IX
1 1 0 1 1 1 0 1 DD
0 0 1 0 0 0 1 1 23
Description
The contents of Index Register IX are incremented.

2 10 (4, 6) 2.50

None.
Example
If Index Register IX contains the integer 3300h, then upon the execution of an INC IX
instruction, Index Register IX contains 3301h.

Z80 CPU
User Manual
200
INC IY
Operation
IY ← IY + 1
Op Code
INC
Operand
IY
1 1 1 1 1 1 0 1 FD
0 0 1 0 0 0 1 1 23
Description
The contents of Index Register IY are incremented.

2 10 (4, 6) 2.50

None.
Example
If the index register contains 2977h, then upon the execution of an INC IY instruction,
Index Register IY contains 2978h.

Z80 CPU
User Manual
201
DEC ss
Operation
ss ← ss – 1
Op Code
DEC
Operand
ss
0 0 s s 1 0 1 1
Description
The contents of register pair ss (any of the register pairs BC, DE, HL, or SP) are decre-
mented. In the assembled object code, operand ss is specified as follows:
Register
Pair ss
BC 00
DE 01
HL 10
SP 11

1 6 1.50

None.
Example
If register pair HL contains 1001h, then upon the execution of an DEC HL instruction, HL
contains 1000h.

Z80 CPU
User Manual
202
DEC IX
Operation
IX ← IX – 1
Op Code
DEC
Operand
IX
1 1 0 1 1 1 0 1 DD
0 0 1 0 1 0 1 1 2B
Description
The contents of Index Register IX are decremented.

2 10 (4, 6) 2.50

None.
Example
If Index Register IX contains 2006h, then upon the execution of a DEC IX instruction,
Index Register IX contains 2005h.

Z80 CPU
User Manual
203
DEC IY
Operation
IY ← IY– 1
Op Code
DEC
Operand
IY
1 1 1 1 1 1 0 1 FD
0 0 1 0 1 0 1 1 2B
Description
The contents of Index Register IY are decremented.

2 10 (4, 6) 2.50

None.
Example
If Index Register IY contains 7649h, then upon the execution of a DEC IY instruction,
Index Register IY contains 7648h.

Z80 CPU
User Manual
204
Rotate and Shift Group

The following rotate and shift group instructions are each described in this section. Simply
click to jump to an instruction’s description to learn more.
RLCA – see page 205
RLA – see page 207
RRCA – see page 209
RRA – see page 211
RLC r – see page 213
RLC (HL) – see page 215
RLC (IX+d) – see page 217
RLC (IY+d) – see page 219
RL m – see page 221
RRC m – see page 224
RR m – see page 227
SLA m – see page 230
SRA m – see page 233
SRL m – see page 236
RLD – see page 238
RRD – see page 240

Z80 CPU
User Manual
205
RLCA
Operation
CY 7 0
A
Op Code
RLCA
Operands
None.
0 0 0 0 0 1 1 1 07
Description
The contents of the Accumulator (Register A) are rotated left 1 bit position. The sign bit
(bit 7) is copied to the Carry flag and also to bit 0. Bit 0 is the least-significant bit.

1 4 1.00

S is not affected.
Z is not affected.
H is reset.
N is reset.
C is data from bit 7 of Accumulator.

Z80 CPU
User Manual
206
Example
The Accumulator contains the following data:
7 6 5 4 3 2 1 0
1 0 0 0 1 0 0 0
Upon the execution of an RLCA instruction, the Accumulator and Carry flag contains:
C 7 6 5 4 3 2 1 0
1 0 0 0 1 0 0 0 1

Z80 CPU
User Manual
207
RLA
Operation
Op Code
RLA
Operands
None.
0 0 0 1 0 1 1 1 17
Description
The contents of the Accumulator (Register A) are rotated left 1 bit position through the
Carry flag. The previous contents of the Carry flag are copied to bit 0. Bit 0 is the least-
significant bit.

1 4 1.00

Condition Bits Affected.
S is not affected.
Z is not affected.
H is reset.
N is reset.

Z80 CPU
User Manual
208
Example
The Accumulator and the Carry flag contains the following data:
C 7 6 5 4 3 2 1 0
1 0 1 1 1 0 1 1 0
Upon the execution of an RLA instruction, the Accumulator and the Carry flag contains:
C 7 6 5 4 3 2 1 0
0 1 1 1 0 1 1 0 1

Z80 CPU
User Manual
209
RRCA
Operation
7 0 CY
A
Op Code
RRCA
Operands
None.
0 0 0 0 1 1 1 1 0F
Description
The contents of the Accumulator (Register A) are rotated right 1 bit position. Bit 0 is cop-
ied to the Carry flag and also to bit 7. Bit 0 is the least-significant bit.

1 4 1.00

S is not affected.
Z is not affected.
H is reset.
N is reset.
Example
The Accumulator contains the following data.

Z80 CPU
User Manual
210
7 6 5 4 3 2 1 0
0 0 0 1 0 0 0 1
Upon the execution of an RRCA instruction, the Accumulator and the Carry flag now con-
tain:
7 6 5 4 3 2 1 0 C
1 0 0 1 1 0 0 0 1

Z80 CPU
User Manual
211
RRA
Operation
7 0 CY
A
Op Code
RRA
Operands
None.
0 0 0 1 1 1 1 1 1F
Description
The contents of the Accumulator (Register A) are rotated right 1 bit position through the
Carry flag. The previous contents of the Carry flag are copied to bit 7. Bit 0 is the least-
significant bit.

1 4 1.00

S is not affected.
Z is not affected.
H is reset.
N is reset.

Z80 CPU
User Manual
212
Example
The Accumulator and the Carry Flag contain the following data:
7 6 5 4 3 2 1 0 C
1 1 1 0 0 0 0 1 0
Upon the execution of an RRA instruction, the Accumulator and the Carry flag now con-
tain:
7 6 5 4 3 2 1 0 C
0 1 1 1 0 0 0 0 1

Z80 CPU
User Manual
213
RLC r
Operation
CY 7 0
r
Op Code
RLC
Operand
r
1 1 0 0 1 0 1 1 CB
0 0 0 0 0 r
Description
The contents of register r are rotated left 1 bit position. The contents of bit 7 are copied to
the Carry flag and also to bit 0. In the assembled object code, operand r is specified as fol-
lows:
Register r
B 000
C 001
D 010
E 011
H 100
L 101
A 111

2 8 (4, 4) 2.00

Z80 CPU
User Manual
214

H is reset.
N is reset.
C is data from bit 7 of source register.
Example
Register r contains the following data.
7 6 5 4 3 2 1 0
1 0 0 0 1 0 0 0
Upon the execution of an RLC r instruction, register r and the Carry flag now contain:
C 7 6 5 4 3 2 1 0
1 0 0 0 1 0 0 0 1

Z80 CPU
User Manual
215
RLC (HL)
Operation
CY 7 0
(HL)
Op Code
RLC
Operand
(HL)
1 1 0 0 1 0 1 1 CB
0 0 0 0 0 1 1 0 06
Description
The contents of the memory address specified by the contents of register pair HL are
rotated left 1 bit position. The contents of bit 7 are copied to the Carry flag and also to bit
0. Bit 0 is the least-significant bit.

4 15 (4, 4, 4, 3) 3.75

H is reset.
N is reset.

Z80 CPU
User Manual
216
Example
The HL register pair contains 2828h and the contents of memory location 2828h are:
7 6 5 4 3 2 1 0
1 0 0 0 1 0 0 0
Upon the execution of an RLC(HL) instruction, memory location 2828h and the Carry
flag now contain:
C 7 6 5 4 3 2 1 0
1 0 0 0 1 0 0 0 1

Z80 CPU
User Manual
217
RLC (IX+d)
Operation
CY 7 0
(IX+d)
Op Code
RLC
Operand
(IX+d)
1 1 0 1 1 1 0 1 DD
1 1 0 0 1 0 1 1 CB
0 0 0 0 0 1 1 0 06
Description
The contents of the memory address specified by the sum of the contents of Index Register
IX and the two’s-complement displacement integer, d, are rotated left 1 bit position. The
contents of bit 7 are copied to the Carry flag and also to bit 0. Bit 0 is the least-significant
bit.

6 23 (4, 4, 3, 5, 4, 3) 5.75

H is reset.
N is reset.

Z80 CPU
User Manual
218
Example
Index Register IX contains 1000h and memory location 1022h contains the following
data.
7 6 5 4 3 2 1 0
1 0 0 0 1 0 0 0
Upon the execution of an RLC (IX+2h) instruction, memory location 1002h and the
Carry flag now contain:
C 7 6 5 4 3 2 1 0
1 0 0 0 1 0 0 0 1

Z80 CPU
User Manual
219
RLC (IY+d)
Operation
CY 7 0
(IY+d)
Op Code
RLC
Operand
(lY+d)
1 1 1 1 1 1 0 1 FD
1 1 0 0 1 0 1 1 CB
0 0 0 0 0 1 1 0 06
Description
The contents of the memory address specified by the sum of the contents of Index Register
IY and the two’s-complement displacement integer, d, are rotated left 1 bit position. The
contents of bit 7 are copied to the Carry flag and also to bit 0. Bit 0 is the least-significant
bit.

6 23 (4, 4, 3, 5, 4, 3) 5.75

H is reset.
N is reset.

Z80 CPU
User Manual
220
Example
Index Register IY contains 1000h and memory location 1002h contain the following
data:
7 6 5 4 3 2 1 0
1 0 0 0 1 0 0 0
Upon the execution of an RLC (IY+2h) instruction, memory location 1002h and the
C 7 6 5 4 3 2 1 0
1 0 0 0 1 0 0 0 1

Z80 CPU
User Manual
221
RL m
Operation
CY 7 0
m
Op Code
RL
Operand
m
The m operand is any of r, (HL), (IX+d), or (lY+d), as defined for the analogous RLC
instructions. In the assembled object code, the possible op code/operand combinations are
specified as follows:
RL r* 1 1 0 0 1 0 1 1 CB
0 0 0 1 0 r*
RL (HL) 1 1 0 0 1 0 1 1 CB
0 0 0 1 0 1 1 0 16
RL (IX+d) 1 1 0 1 1 1 0 1 DD
1 1 0 0 1 0 1 1 CB
0 0 0 1 0 1 1 0 16
RL (IY+d) 1 1 1 1 1 1 0 1 FD
1 1 0 0 1 0 1 1 CB
0 0 0 1 0 1 1 0 16

Z80 CPU
User Manual
222
Register r
B 000
C 001
D 010
E 011
H 100
L 101
A 111
Description
The contents of the m operand are rotated left 1 bit position. The contents of bit 7 are cop-
ied to the Carry flag, and the previous contents of the Carry flag are copied to bit 0.

RL r 2 8 (4, 4) 2.00
RL (HL) 4 15(4, 4, 4, 3) 3.75
RL (IX+d) 6 23 (4, 4, 3, 5, 4, 3) 5.75
RL (IY+d) 6 23 (4, 4, 3, 5, 4, 3) 5.75

H is reset.
N is reset.
Example
The D Register and the Carry flag contain the following data.
C 7 6 5 4 3 2 1 0
0 1 0 0 0 1 1 1 1

Z80 CPU
User Manual
223
Upon the execution of an RL D instruction, the D Register and the Carry flag now contain:
C 7 6 5 4 3 2 1 0
1 0 0 0 1 1 1 1 0

Z80 CPU
User Manual
224
RRC m
Operation
Op Code
RRC
Operand
m

Z80 CPU
User Manual
225
RRC r* 1 1 0 0 1 0 1 1 CB
0 0 0 0 1 r*
RRC (HL) 1 1 0 0 1 0 1 1 CB
0 0 0 0 1 1 1 0 OE
RRC (IX+d) 1 1 0 1 1 1 0 1 DD
1 1 0 0 1 0 1 1 CB
0 0 0 0 1 1 1 0 OE
RRC (IY+d) 1 1 1 1 1 1 0 1 FD
1 1 0 0 1 0 1 1 CB
0 0 0 0 1 1 1 0 OE
Register r
B 000
C 001
D 010
E 011
H 100
L 101
A 111
Description
The contents of the m operand are rotated right 1 bit position. The contents of bit 0 are
copied to the Carry flag and also to bit 7. Bit 0 is the least-significant bit.

Z80 CPU
User Manual
226

RRC r 2 8 (4, 4) 2.00
RRC (HL) 4 15 (4, 4, 4, 3) 3.75
RRC (IX+d) 6 23 (4, 4, 3, 5, 4, 3) 5.75
RRC (lY+d) 6 23 (4, 4, 3, 5, 4, 3) 5.75

H is reset.
N is reset.
Example
Register A contains the following data.
7 6 5 4 3 2 1 0
0 0 1 1 0 0 0 1
Upon the execution of an RRC A instruction, Register A and the Carry flag now contain:
7 6 5 4 3 2 1 0 C
1 0 0 1 1 0 0 0 1

Z80 CPU
User Manual
227
RR m
Operation
Op Code
RR
Operand
m

Z80 CPU
User Manual
228
RR r* 1 1 0 0 1 0 1 1 CB
0 0 0 0 1 r*
RR (HL) 1 1 0 0 1 0 1 1 CB
0 0 0 1 1 1 1 0 1E
RR (IX+d) 1 1 0 1 1 1 0 1 DD
1 1 0 0 1 0 1 1 CB
0 0 0 1 1 1 1 0 1E
RR (IY+d) 1 1 1 1 1 1 0 1 FD
1 1 0 0 1 0 1 1 CB
0 0 0 1 1 1 1 0 1E
Register r
B 000
C 001
D 010
E 011
H 100
L 101
A 111
Description
The contents of operand m are rotated right 1 bit position through the Carry flag. The con-
tents of bit 0 are copied to the Carry flag and the previous contents of the Carry flag are
copied to bit 7. Bit 0 is the least-significant bit.

Z80 CPU
User Manual
229

RR r 2 8 (4, 4) 2.00
RR (HL) 4 15 (4, 4, 4, 3) 3.75
RR (IX+d) 6 23 (4, 4, 3, 5, 4, 3) 5.75
RR (lY+d) 6 23 (4, 4, 3, 5, 4, 3) 5.75

H is reset.
N is reset.
Example
The HL register pair contains 4343h and memory location 4343h and the Carry flag con-
tain the following data.
7 6 5 4 3 2 1 0 C
1 1 0 1 1 1 0 1 0
Upon the execution of an RR (HL) instruction, location 4343h and the Carry flag now
contain:
7 6 5 4 3 2 1 0 C
0 1 1 0 1 1 1 0 1

Z80 CPU
User Manual
230
SLA m
Operation
CY 7 0 0
m
Op Code
SLA
Operand
m
SLA r* 1 1 0 0 1 0 1 1 CB
0 0 1 0 0 r*
SLA (HL) 1 1 0 0 1 0 1 1 CB
0 0 1 0 0 1 1 0 26
SLA (IX+d) 1 1 0 1 1 1 0 1 DD
1 1 0 0 1 0 1 1 CB
0 0 1 0 0 1 1 0 26
SLA (IY+d) 1 1 1 1 1 1 0 1 FD
1 1 0 0 1 0 1 1 CB
0 0 1 0 0 1 1 0 26

Z80 CPU
User Manual
231
Register r
B 000
C 001
D 010
E 011
H 100
L 101
A 111
Description
An arithmetic shift left 1 bit position is performed on the contents of operand m. The con-
tents of bit 7 are copied to the Carry flag. Bit 0 is the least-significant bit.

SLA r 2 8 (4, 4) 2.00
SLA (HL) 4 15 (4, 4, 4, 3) 3.75
SLA (IX+d) 6 23 (4, 4, 3, 5, 4, 3) 5.75
SLA (IY+d) 6 23 (4, 4, 3, 5, 4, 3) 5.75

H is reset.
P/V is set if parity is even; otherwise, it is reset.
N is reset.
C is data from bit 7.
Example
Register L contains the following data.
7 6 5 4 3 2 1 0
1 0 1 1 0 0 0 1

Z80 CPU
User Manual
232
Upon the execution of an SLA L instruction, Register L and the Carry flag now contain:
C 7 6 5 4 3 2 1 0
1 0 1 1 0 0 0 1 0

Z80 CPU
User Manual
233
SRA m
Operation
7 0 CY
m
Op Code
SRA
Operand
m
SRA r* 1 1 0 0 1 0 1 1 CB
0 0 1 0 1 r*
SRA (HL) 1 1 0 0 1 0 1 1 CB
0 0 1 0 1 1 1 0 2E
SRA (IX+d) 1 1 0 1 1 1 0 1 DD
1 1 0 0 1 0 1 1 CB
0 0 1 0 1 1 1 0 2E
SRA (IY+d) 1 1 1 1 1 1 0 1 FD
1 1 0 0 1 0 1 1 CB
0 0 1 0 1 1 1 0 2E

Z80 CPU
User Manual
234
Register r
B 000
C 001
D 010
E 011
H 100
L 101
A 111
Description
An arithmetic shift right 1 bit position is performed on the contents of operand m. The
contents of bit 0 are copied to the Carry flag and the previous contents of bit 7 remain
unchanged. Bit 0 is the least-significant bit.

SRA r 2 8 (4, 4) 2.00
SRA (HL) 4 15 (4, 4, 4, 3) 3.75
SRA (IX+d) 6 23 (4, 4, 3, 5, 4, 3) 5.75
SRA (lY+d) 6 23 (4, 4, 3, 5, 4, 3) 5.75

H is reset.
N is reset.
Example
Index Register IX contains 1000h and memory location 1003h contains the following
data.
7 6 5 4 3 2 1 0
1 0 1 1 1 0 0 0

Z80 CPU
User Manual
235
Upon the execution of an SRA (IX+3h) instruction, memory location 1003h and the
7 6 5 4 3 2 1 0 C
1 1 0 1 1 1 0 0 0

Z80 CPU
User Manual
236
SRL m
Operation
0 7 0 CY
m
Op Code
SRL
Operand
m
The operand m is any of r, (HL), (IX+d), or (lY+d), as defined for the analogous RLC
SRL r* 1 1 0 0 1 0 1 1 CB
0 0 1 1 1 r*
SRL (HL) 1 1 0 0 1 0 1 1 CB
0 0 1 1 1 1 1 0 3E
SRL (IX+d) 1 1 0 1 1 1 0 1 DD
1 1 0 0 1 0 1 1 CB
0 0 1 1 1 1 1 0 3E
SRL (IY+d) 1 1 1 1 1 1 0 1 FD
1 1 0 0 1 0 1 1 CB
0 0 1 1 1 1 1 0 3E

Z80 CPU
User Manual
237
r identifies registers B, C, D, E, H, L, or A.
Description
The contents of operand m are shifted right 1 bit position. The contents of bit 0 are copied
to the Carry flag, and bit 7 is reset. Bit 0 is the least-significant bit.

SRL r 2 8 (4, 4) 2.00
SRL (HL) 4 15 (4, 4, 4, 3) 3.75
SRL (IX+d) 6 23 (4, 4, 3, 5, 4, 3) 5.75
SRL (lY+d) 6 23 (4, 4, 3, 5, 4, 3) 5.75

S is reset.
H is reset.
N is reset.
Example
Register B contains the following data.
7 6 5 4 3 2 1 0
1 0 0 0 1 1 1 1
Upon the execution of an SRL B instruction, Register B and the Carry flag now contain:
7 6 5 4 3 2 1 0 C
0 1 0 0 0 1 1 1 1

Z80 CPU
User Manual
238
RLD
Operation
A 7 4 3 0 7 4 3 0
Op Code
RLD
Operands
1 1 1 0 1 1 0 1 ED
0 1 1 0 1 1 1 1 6F
Description
The contents of the low-order four bits (bits 3, 2, 1, and 0) of the memory location (HL)
are copied to the high-order four bits (7, 6, 5, and 4) of that same memory location; the
previous contents of those high-order four bits are copied to the low-order four bits of the
Accumulator (Register A); and the previous contents of the low-order four bits of the
Accumulator are copied to the low-order four bits of memory location (HL). The contents
of the high-order bits of the Accumulator are unaffected.
Note: (HL) refers to the memory location specified by the contents of the HL register pair.

5 18 (4, 4, 3, 4, 3) 4.50

S is set if the Accumulator is negative after an operation; otherwise, it is reset.
H is reset.

Z80 CPU
User Manual
239
P/V is set if the parity of the Accumulator is even after an operation; otherwise, it is reset.
N is reset.
C is not affected.
Example
The HL register pair contains 5000h and the Accumulator and memory location 5000h
contain the following data.
7 6 5 4 3 2 1 0
0 1 1 1 1 0 1 0 Accumulator
7 6 5 4 3 2 1 0
0 0 1 1 0 0 0 1 (5000h)
Upon the execution of an RLD instruction, the Accumulator and memory location 5000h
now contain:
7 6 5 4 3 2 1 0
7 6 5 4 3 2 1 0
0 0 0 1 1 0 1 0 (5000h)

Z80 CPU
User Manual
240
RRD
Operation
A 7 4 3 0 7 4 3 0 (HL)
Op Code
RRD
Operands
1 1 1 0 1 1 0 1 ED
0 1 1 0 0 1 1 1 67
Description
The contents of the low-order four bits (bits 3, 2, 1, and 0) of memory location (HL) are
copied to the low-order four bits of the Accumulator (Register A). The previous contents
of the low-order four bits of the Accumulator are copied to the high-order four bits (7, 6, 5,
and 4) of location (HL); and the previous contents of the high-order four bits of (HL) are
copied to the low-order four bits of (HL). The contents of the high-order bits of the Accu-
mulator are unaffected.
Note: (HL) refers to the memory location specified by the contents of the HL register pair.

5 18 (4, 4, 3, 4, 3) 4.50

S is set if the Accumulator is negative after an operation; otherwise, it is reset.
H is reset.

Z80 CPU
User Manual
241
P/V is set if the parity of the Accumulator is even after an operation; otherwise, it is reset.
N is reset.
C is not affected.
Example
The HL register pair contains 5000h and the Accumulator and memory location 5000h
contain the following data.
7 6 5 4 3 2 1 0
7 6 5 4 3 2 1 0
0 0 1 0 0 0 0 0 (5000h)
Upon the execution of an RRD instruction, the Accumulator and memory location 5000h
now contain:
7 6 5 4 3 2 1 0
7 6 5 4 3 2 1 0
0 1 0 0 0 0 1 0 (5000h)

Z80 CPU
User Manual
242
Bit Set, Reset, and Test Group

The following bit set, reset, and test group instructions are each described in this section.
Simply click to jump to an instruction’s description to learn more.
BIT b, r – see page 243
BIT b, (HL) – see page 245
BIT b, (IX+d) – see page 247
BIT b, (IY+d) – see page 249
SET b, r – see page 251
SET b, (HL) – see page 253
SET b, (IX+d) – see page 255
SET b, (IY+d) – see page 257
RES b, m – see page 259

Z80 CPU
User Manual
243
BIT b, r
Operation
Z ← rb
Op Code
BIT
Operands
b, r
1 1 0 0 1 0 1 1 CB
0 1 b r
Description
This instruction tests bit b in register r and sets the Z flag accordingly. In the assembled
object code, operands b and r are specified as follows:
Bit Tested b Register r

0 000 B 000
1 001 C 001
2 010 D 010
3 011 E 011
4 100 H 100
5 101 L 101
6 110 A 111
7 111

2 8 (4, 4) 4.50

S is unknown.
Z is set if specified bit is 0; otherwise, it is reset.

Z80 CPU
User Manual
244
H is set.
P/V is unknown.
N is reset.
C is not affected.
Example
If bit 2 in Register B contains 0, then upon the execution of a BIT 2, B instruction, the Z
flag in the F Register contains 1, and bit 2 in Register B remains at 0. Bit 0 in Register B is
the least-significant bit.

Z80 CPU
User Manual
245
BIT b, (HL)
Operation
Z ← (HL)b
Op Code
BIT
Operands
b, (HL)
1 1 0 0 1 0 1 1 CB
0 1 b 1 1 0
Description
This instruction tests bit b in the memory location specified by the contents of the HL reg-
ister pair and sets the Z flag accordingly. In the assembled object code, operand b is speci-
fied as follows:
Bit Tested b
0 000
1 001
2 010
3 011
4 100
5 101
6 110
1 111

3 12 (4, 4, 4) 4 3.00

S is unknown.

Z80 CPU
User Manual
246

H is set.
P/V is unknown.
H is reset.
C is not affected.
Example
If the HL register pair contains 4444h, and bit 4 in the memory location 444h contains 1,
then upon the execution of a BIT 4, (HL) instruction, the Z flag in the F Register contains
0, and bit 4 in memory location 4444h remains at 1. Bit 0 in memory location 4444h is
the least-significant bit.

Z80 CPU
User Manual
247
BIT b, (IX+d)
Operation
Z ← (IX+d)b
Op Code
BIT
Operands
b, (IX+d)
1 1 0 1 1 1 0 1 DD
1 1 0 0 1 0 1 1 CB
0 1 b 1 1 0
Description
This instruction tests bit b in the memory location specified by the contents of register pair
IX combined with the two’s complement displacement d and sets the Z flag accordingly.
In the assembled object code, operand b is specified as follows:
Bit Tested b
0 000
1 001
2 010
3 011
4 100
5 101
6 110
7 111

5 20 (4, 4, 3, 5, 4) 5.00

Z80 CPU
User Manual
248

S is unknown.
H is set.
P/V is unknown.
N is reset.
C is not affected.
Example
If Index Register IX contains 2000h and bit 6 in memory location 2004h contains 1, then
upon the execution of a BIT 6, (IX+4h) instruction, the Z flag in the F Register contains a
0 and bit 6 in memory location 2004h still contains a 1. Bit 0 in memory location 2004h
is the least-significant bit.

Z80 CPU
User Manual
249
BIT b, (IY+d)
Operation
Z ← (IY+d)b
Op Code
BIT
Operands
b, (lY+d)
1 1 1 1 1 1 0 1 FD
1 1 0 0 1 0 1 1 CB
0 1 b 1 1 0
Description
This instruction tests bit b in the memory location specified by the contents of register pair
IY combined with the two’s complement displacement d and sets the Z flag accordingly.
In the assembled object code, operand b is specified as follows.
Bit Tested b
0 000
1 001
2 010
3 011
4 100
5 101
6 110
7 111

5 20 (4, 4, 3, 5, 4) 5.00

Z80 CPU
User Manual
250

S is unknown.
H is set.
P/V is unknown.
H is reset.
C is not affected.
Example
If Index Register contains 2000h and bit 6 in memory location 2004h contains a 1, then
upon the execution of a BIT 6, (IY+4h) instruction, the Z flag and the F Register still con-
tains a 0, and bit 6 in memory location 2004h still contains a 1. Bit 0 in memory location
2004h is the least-significant bit.

Z80 CPU
User Manual
251
SET b, r
Operation
rb ← 1
Op Code
SET
Operands
b, r
1 1 0 0 1 0 1 1 CB
1 1 b r
Description
Bit b in register r (any of registers B, C, D, E, H, L, or A) is set. In the assembled object
code, operands b and r are specified as follows:
Bit b Register r
0 000 B 000
1 001 C 001
2 010 D 010
3 011 E 011
4 100 H 100
5 101 L 101
6 110 A 111
7 111

2 8 (4, 4) 2.00

None.

Z80 CPU
User Manual
252
Example
Upon the execution of a SET 4, A instruction, bit 4 in Register A is set. Bit 0 is the least-
significant bit.

Z80 CPU
User Manual
253
SET b, (HL)
Operation
(HL)b ← 1
Op Code
SET
Operands
b, (HL)
Description
Bit b in the memory location addressed by the contents of register pair HL is set. In the
assembled object code, operand b is specified as follows:
Bit Tested b
0 000
1 001
2 010
3 011
4 100
5 101
6 110
7 111

4 15 (4, 4, 4, 3) 3.75

None.

Z80 CPU
User Manual
254
Example
If the HL register pair contains 3000h, then upon the execution of a SET 4, (HL) instruc-
tion, bit 4 in memory location 3000h is 1. Bit 0 in memory location 3000h is the least-sig-
nificant bit.

Z80 CPU
User Manual
255
SET b, (IX+d)
Operation
(IX+d)b ← 1
Op Code
SET
Operands
b, (IX+d)
Description
Bit b in the memory location addressed by the sum of the contents of the IX register pair
and the two’s complement integer d is set. In the assembled object code, operand b is spec-
ified as follows:
Bit Tested b
0 000
1 001
2 010
3 011
4 100
5 101
6 110
7 111

6 23 (4, 4, 3, 5, 4, 3) 5.75

Z80 CPU
User Manual
256

None.
Example
If the index register contains 2000h, then upon the execution of a SET 0, (IX + 3h)
instruction, bit 0 in memory location 2003h is 1. Bit 0 in memory location 2003h is the
least-significant bit.

Z80 CPU
User Manual
257
SET b, (IY+d)
Operation
(IY + d) b ← 1
Op Code
SET
Operands
b, (IY + d)
1 1 1 1 1 1 0 1 FD
1 1 0 0 1 0 1 1 CB
1 1 b 1 1 0
Description
Bit b in the memory location addressed by the sum of the contents of the IY register pair
and the two’s complement displacement d is set. In the assembled object code, operand b
is specified as follows:
Bit Tested b
0 000
1 001
2 010
3 011
4 100
5 101
6 110
7 111

6 23 (4, 4, 3, 5, 4, 3) 5.75

Z80 CPU
User Manual
258

None.
Example
If Index Register IY contains 2000h, then upon the execution of a Set 0, (IY+3h) instruc-
tion, bit 0 in memory location 2003h is 1. Bit 0 in memory location 2003h is the least-sig-
nificant bit.

Z80 CPU
User Manual
259
RES b, m
Operation
sb ← 0
Op Code
RES
Operands
b, m
The b operand represents any bit (7 through 0) of the contents of the m operand, (any of r,
(HL), (IX+d), or (lY+d)) as defined for the analogous SET instructions. These possible op
code/operand combinations are assembled as follows in the object code:
RES b, rn 1 1 0 0 1 0 1 1 CB
1 0 b r
RES b, (HL) 1 1 0 0 1 0 1 1 CB
1 0 b 1 1 0
RES b, (IX+d) 1 1 0 1 1 1 0 1 DD
1 1 0 0 1 0 1 1 CB
1 0 b 1 1 0
RES b, (IY+d) 1 1 1 1 1 1 0 1 FD
1 1 0 0 1 0 1 1 CB
1 0 b 1 1 0

Z80 CPU
User Manual
260
Bit b Register r
0 000 B 000
1 001 C 001
2 010 D 010
3 011 E 011
4 100 H 100
5 101 L 101
6 110 A 111
7 111
Description
Bit b in operand m is reset.

RES r 4 8 (4, 4) 2.00
RES (HL) 4 15 (4, 4, 4, 3) 3.75
RES (IX+d) 6 23 (4, 4, 3, 5, 4, 3) 5.75
RES (lY+d) 6 23 (4, 4, 3, 5, 4, 3) 5.75

None.
Example
Upon the execution of a RES 6, D instruction, bit 6 in register 0 is reset. Bit 0 in the D
Register is the least-significant bit.

Z80 CPU
User Manual
261
Jump Group
The following jump group instructions are each described in this section. Simply click to
JP nn – see page 262
JP cc, nn – see page 263
JR e – see page 265
JR C, e – see page 267
JR NC, e – see page 269
JR Z, e – see page 271
JR NZ, e – see page 273
JP (HL) – see page 275
JP (IX) – see page 276
JP (IY) – see page 277
DJNZ, e – see page 278

Z80 CPU
User Manual
262
JP nn
Operation
PC ← nn
Op Code
JP
Operand
nn
1 1 0 0 0 0 1 1 C3
Note: The first operand in this assembled object code is the low-order byte of a two-byte address.
Description
Operand nn is loaded to register pair Program Counter (PC). The next instruction is
fetched from the location designated by the new contents of the PC.

3 10 (4, 3, 3) 2.50

None.

Z80 CPU
User Manual
263
JP cc, nn
Operation
IF cc true, PC ← nn
Op Code
JP
Operands
cc, nn
The first n operand in this assembled object code is the low-order byte of a 2-byte memory
address.
Description
If condition cc is true, the instruction loads operand nn to register pair Program Counter
(PC), and the program continues with the instruction beginning at address nn. If condition
cc is false, the Program Counter is incremented as usual, and the program continues with
the next sequential instruction. Condition cc is programmed as one of eight statuses that
correspond to condition bits in the Flag Register (Register F). These eight statuses are
defined in the following table, which specifies the corresponding cc bit fields in the
assembled object code.
Relevant
cc Condition Flag
000 Non-Zero (NZ) Z
001 Zero (Z) Z
010 No Carry (NC) C
011 Carry (C) C
100 Parity Odd (PO) P/V
101 Parity Even (PE) P/V
110 Sign Positive (P) S
111 Sign Negative (M) S

Z80 CPU
User Manual
264

3 10 (4, 3, 3) 2.50

None.
Example
If the Carry flag (i.e., the C flag in F Register) is set and address 1520h contains 03h, then
upon the execution of a JP C, 1520h instruction, the Program Counter contains 1520h
and, on the next machine cycle, the CPD fetches byte 03h from address 1520h.

Z80 CPU
User Manual
265
JR e
Operation
PC ← PC + e
Op Code
JR
Operand
e
0 0 0 1 1 0 0 0 18
e–2
Description
This instruction provides for unconditional branching to other segments of a program. The
value of displacement e is added to the Program Counter (PC) and the next instruction is
fetched from the location designated by the new contents of the PC. This jump is mea-
sured from the address of the instruction op code and contains a range of –126 to +129
bytes. The assembler automatically adjusts for the twice incremented PC.

3 12 (4, 3, 5) 3.00

None.
Example
To jump forward five locations from address 480, the following assembly language state-
ment is used:
JR $+5
The resulting object code and final Program Counter value is shown in the following table:

Z80 CPU
User Manual
266
Location Instruction
480 18
481 03
482 –
483 –
484 –
485 ← PC after jump

Z80 CPU
User Manual
267
JR C, e
Operation
If C = 0, continue
If C = 1, PC ← PC+ e
Op Code
JR
Operands
C, e
0 0 1 1 1 0 0 0 38
e–2
Description
This instruction provides for conditional branching to other segments of a program
depending on the results of a test on the Carry Flag. If the flag = 1, the value of displace-
ment e is added to the Program Counter (PC) and the next instruction is fetched from the
location designated by the new contents of the PC. The jump is measured from the address
of the instruction op code and contains a range of –126 to +129 bytes. The assembler auto-
matically adjusts for the twice incremented PC.
If the flag = 0, the next instruction executed is taken from the location following this
instruction. If condition is met

3 12 (4, 3, 5) 3.00
If condition is not met:

2 7 (4, 3) 1.75

None.

Z80 CPU
User Manual
268
Example
The Carry flag is set and it is required to jump back four locations from 480. The assembly
language statement is JR C, $–4
The resulting object code and final Program Counter value is shown in the following table:
47C ← PC after jump
47D –
47E –
47F –
480 38
481 FA (two’s
complement – 6)

Z80 CPU
User Manual
269
JR NC, e
Operation
If C = 1, continue
If C = 0, PC ← PC + e
Op Code
JR
Operands
NC, e
0 0 1 1 0 0 0 0 30
e–2
Description
depending on the results of a test on the Carry Flag. If the flag is equal to 0, the value of
displacement e is added to the Program Counter (PC) and the next instruction is fetched
from the location designated by the new contents of the PC. The jump is measured from
the address of the instruction op code and contains a range of –126 to +129 bytes. The
assembler automatically adjusts for the twice incremented PC.
If the flag = 1, the next instruction executed is taken from the location following this
instruction.
If the condition is met:

3 12 (4, 3, 5) 3.00
If the condition is not met:

7 7 (4, 3) 1.75

None.

Z80 CPU
User Manual
270
Example
The Carry Flag is reset and it is required to repeat the jump instruction. The assembly lan-
guage statement is JR NC, $
The resulting object code and Program Counter after the jump are:
480 30 ← PC after jump
481 00

Z80 CPU
User Manual
271
JR Z, e
Operation
If Z = 0, continue
If Z = 1, PC ← PC + e
Op Code
JR
Operands
Z, e
0 0 1 0 1 0 0 0 28
e–2
Description
depending on the results of a test on the Zero Flag. If the flag = 1, the value of displace-
matically adjusts for the twice-incremented PC.
If the Zero Flag = 0, the next instruction executed is taken from the location following this
instruction.
If this condition is met, the following data results:

3 12 (4, 3, 5) 3.00
If this condition is not met, the following data results:

2 7 (4, 3) 1.75

None.

Z80 CPU
User Manual
272
Example
The Zero Flag is set and it is required to jump forward five locations from address 300.
The following assembly language statement is used:
JR Z ,$ + 5
The resulting object code and final Program Counter value are:
300 28
301 03
302 –
303 –
304 –
305 ← PC after jump

Z80 CPU
User Manual
273
JR NZ, e
Operation
If Z = 1, continue
If Z = 0, PC ← pc + e
Op Code
JR
Operands
NZ, e
0 0 1 0 0 0 0 0 20
e–2
Description
depending on the results of a test on the Zero Flag. If the flag = 0, the value of displace-
matically adjusts for the twice incremented PC.
If the Zero Flag = 1, the next instruction executed is taken from the location following this
instruction.
If the condition is met:

3 12 (4, 3, 5) 3.00
If the condition is not met:

2 7 (4, 3) 1.75

None.

Z80 CPU
User Manual
274
Example
The Zero Flag is reset and it is required to jump back four locations from 480. The assem-
bly language statement is JR NZ, $–4
The resulting object code and final Program Counter value is:
47C ← PC after jump
47D –
47E –
47F –
480 20
481 FA (two’s
complement – 6)

Z80 CPU
User Manual
275
JP (HL)
Operation
PC ← HL
Op Code
JP
Operand
(HL)
1 1 1 0 1 0 0 1 E9
Description
The Program Counter (PC) is loaded with the contents of the HL register pair. The next
instruction is fetched from the location designated by the new contents of the PC.

1 4 1.00

None.
Example
If the Program Counter contains 1000h and the HL register pair contains 4800h, then
upon the execution of a JP (HL) instruction, the Program Counter contains 4800h.

Z80 CPU
User Manual
276
JP (IX)
Operation
pc ← IX
Op Code
JP
Operand
(IX)
1 1 0 1 1 1 0 1 DD
1 1 1 0 1 0 0 1 E9
Description
The Program Counter (PC) is loaded with the contents of the IX register pair. The next

2 8 (4, 4) 2.00

None.
Example
If the Program Counter contains 1000h and the IX register pair contains 4800h, then
upon the execution of a JP (IX) instruction, the Program Counter contains 4800h.

Z80 CPU
User Manual
277
JP (IY)
Operation
PC ← IY
Op Code
JP
Operand
(IY)
1 1 1 1 1 1 0 1 FD
1 1 1 0 1 0 0 1 E9
Description
The Program Counter (PC) is loaded with the contents of the IY register pair. The next

2 8 (4, 4) 2.00

None.
Example
If the Program Counter contains 1000h and the IY register pair contains 4800h, then
upon the execution of a JP (IY) instruction, the Program Counter contains 4800h.

Z80 CPU
User Manual
278
DJNZ, e
Operation
B← B –1
If B = 0, continue
If B ≠ 0, PC ← PC + e
Op Code
DJNZ
Operand
e
0 0 0 1 0 0 0 0 10
e–2
Description
This instruction is similar to the conditional jump instructions except that a register value
is used to determine branching. Register B is decremented, and if a nonzero value remains,
the value of displacement e is added to the Program Counter (PC). The next instruction is
fetched from the location designated by the new contents of the PC. The jump is measured
from the address of the instruction op code and contains a range of –126 to +129 bytes.
The assembler automatically adjusts for the twice incremented PC.
If the result of decrementing leaves B with a zero value, the next instruction executed is
taken from the location following this instruction.
if B ≠ 0:

3 13 (5,3, 5) 3.25
If B = 0:

2 8 (5, 3) 2.00

Z80 CPU
User Manual
279

None.
Example
A typical software routine is used to demonstrate the use of the DJNZ instruction. This
routine moves a line from an input buffer (INBUF) to an output buffer (OUTBUF). It
moves the bytes until it finds a CR, or until it has moved 80 bytes, whichever occurs first.
LD 8, 80 ;Set up counter
LD HL, Inbuf ;Set up pointers
LD DE, Outbuf
LOOP: LID A, (HL) ;Get next byte from

;input buffer
LD (DE), A ;Store in output buffer
CP ODH ;Is it a CR?
JR Z, DONE ;Yes finished
INC HL ;Increment pointers
INC DE
DJNZ LOOP ;Loop back if 80
;bytes have not
;been moved
DONE:

Z80 CPU
User Manual
280
Call and Return Group

The following call and return group instructions are each described in this section. Simply
click to jump to an instruction’s description to learn more.
CALL nn – see page 281
CALL cc, nn – see page 283
RET – see page 285
RET cc – see page 286
RETI – see page 288
RETN – see page 290
RST p – see page 292

Z80 CPU
User Manual
281
CALL nn
Operation
(SP – 1) ← PCH, (SP – 2) ← PCL, PC ← nn
Op Code
CALL
Operand
nn
1 1 0 0 1 1 0 1 CD
The first of the two n operands in the assembled object code above is the least-significant
byte of a 2-byte memory address.
Description
The current contents of the Program Counter (PC) are pushed onto the top of the external
memory stack. The operands nn are then loaded to the PC to point to the address in mem-
ory at which the first op code of a subroutine is to be fetched. At the end of the subroutine,
a RETurn instruction can be used to return to the original program flow by popping the top
of the stack back to the PC. The push is accomplished by first decrementing the current
contents of the Stack Pointer (register pair SP), loading the high-order byte of the PC con-
tents to the memory address now pointed to by the SP; then decrementing SP again, and
loading the low-order byte of the PC contents to the top of stack.
Because this process is a 3-byte instruction, the Program Counter was incremented by
three before the push is executed.

5 17 (4, 3, 4, 3, 3) 4.25

None.

Z80 CPU
User Manual
282
Example
The Program Counter contains 1A47h, the Stack Pointer contains 3002h, and memory
locations contain the following data.
Location Contents
1A47h CDh
IA48h 35h
1A49h 21h
If an instruction fetch sequence begins, the 3-byte instruction CD 3521h is fetched to the
CPU for execution. The mnemonic equivalent of this instruction is CALL 2135h. Upon
the execution of this instruction, memory address 3001h contains 1Ah, address 3000h
contains 4Ah, the Stack Pointer contains 3000h, and the Program Counter contains
2135h, thereby pointing to the address of the first op code of the next subroutine to be
executed.

Z80 CPU
User Manual
283
CALL cc, nn
Operation
IF cc true: (sp – 1) ← PCH
(sp – 2) ← PCL, pc ← nn
Op Code
CALL
Operands
cc, nn
1 1 cc 1 0 0
The first of the two n operands in the assembled object code above is the least-significant
byte of the 2-byte memory address.
Description
If condition cc is true, this instruction pushes the current contents of the Program Counter
(PC) onto the top of the external memory stack, then loads the operands nn to PC to point
to the address in memory at which the first op code of a subroutine is to be fetched. At the
end of the subroutine, a RETurn instruction can be used to return to the original program
flow by popping the top of the stack back to PC. If condition cc is false, the Program
Counter is incremented as usual, and the program continues with the next sequential
instruction. The stack push is accomplished by first decrementing the current contents of
the Stack Pointer (SP), loading the high-order byte of the PC contents to the memory
address now pointed to by SP; then decrementing SP again, and loading the low-order
byte of the PC contents to the top of the stack.
Because this process is a 3-byte instruction, the Program Counter was incremented by
three before the push is executed.
Condition cc is programmed as one of eight statuses that corresponds to condition bits in
the Flag Register (Register F). These eight statuses are defined in the following table,
which also specifies the corresponding cc bit fields in the assembled object code.

Z80 CPU
User Manual
284
Relevant
cc Condition Flag
000 Non-Zero (NZ) Z
001 Zero (Z) Z
010 Non Carry (NC) C
011 Carry (C) Z
If cc is true:
5 17 (4, 3, 4, 3, 3) 4.25
If cc is false:
3 10 (4, 3, 3) 2.50

None.
Example
The C Flag in the F Register is reset, the Program Counter contains 1A47h, the Stack
Pointer contains 3002h, and memory locations contain the following data.
Location Contents
1A47h D4h
1448h 35h
1A49h 21h
If an instruction fetch sequence begins, the 3-byte instruction D43521h is fetched to the
CPU for execution. The mnemonic equivalent of this instruction is CALL NC, 2135h.
Upon the execution of this instruction, memory address 3001h contains 1Ah, address
3000h contains 4Ah, the Stack Pointer contains 3000h, and the Program Counter contains
2135h, thereby pointing to the address of the first op code of the next subroutine to be
executed.

Z80 CPU
User Manual
285
RET
Operation
pCL ← (sp), pCH ← (sp+1)
Op Code
RET
1 1 0 0 1 0 0 1 C9
Operands
None.
Description
The byte at the memory location specified by the contents of the Stack Pointer (SP) Regis-
ter pair is moved to the low-order eight bits of the Program Counter (PC). The SP is now
incremented and the byte at the memory location specified by the new contents of this
instruction is fetched from the memory location specified by the PC. This instruction is
normally used to return to the main line program at the completion of a routine entered by
a CALL instruction.

3 10 (4, 3, 3) 2.50

None.
Example
The Program Counter contains 3535h, the Stack Pointer contains 2000h, memory loca-
tion 2000h contains B5h, and memory location 2001h contains 18h. Upon the execution
of a RET instruction, the Stack Pointer contains 2002h and the Program Counter contains
18B5h, thereby pointing to the address of the next program op code to be fetched.

Z80 CPU
User Manual
286
RET cc
Operation
If cc true: PCL ← (sp), pCH ← (sp+1)
Op Code
RET
Operand
cc
1 1 cc 0 0 0
Description
If condition cc is true, the byte at the memory location specified by the contents of the
Stack Pointer (SP) Register pair is moved to the low-order eight bits of the Program Coun-
ter (PC). The SP is incremented and the byte at the memory location specified by the new
contents of the SP are moved to the high-order eight bits of the PC. The SP is incremented
again. The next op code following this instruction is fetched from the memory location
specified by the PC. This instruction is normally used to return to the main line program at
the completion of a routine entered by a CALL instruction. If condition cc is false, the PC
is simply incremented as usual, and the program continues with the next sequential
instruction. Condition cc is programmed as one of eight status that correspond to condition
bits in the Flag Register (Register F). These eight status are defined in the following table,
which also specifies the corresponding cc bit fields in the assembled object code.
Relevant
cc Condition Flag
000 Non-Zero (NZ) Z
001 Zero (Z) Z
010 Non Carry (NC) C
011 Carry (C) C

Z80 CPU
User Manual
287
If cc is true, then the following data is returned:

3 11 (5, 3, 3) 2.75
If cc is false, then the following data is returned:

1 5 1.25

None.
Example
The S flag in the F Register is set, the Program Counter contains 3535h, the Stack Pointer
contains 2000h, memory location 2000h contains B5h, and memory location 2001h con-
tains 18h. Upon the execution of a RET M instruction, the Stack Pointer contains 2002h
and the Program Counter contains 18B5h, thereby pointing to the address of the next pro-
gram op code to be fetched.

Z80 CPU
User Manual
288
RETI
Operation
Return from Interrupt
Op Code
RETI
1 1 1 0 1 1 0 1 ED
0 1 0 0 1 1 0 1 4D
Operands
None.
Description
This instruction is used at the end of a maskable interrupt service routine to:
• Restore the contents of the Program Counter (analogous to the RET instruction)
• Signal an I/O device that the interrupt routine is completed. The RETI instruction also
facilitates the nesting of interrupts, allowing higher priority devices to temporarily
suspend service of lower priority service routines. However, this instruction does not
enable interrupts that were disabled when the interrupt routine was entered. Before
doing the RETI instruction, the enable interrupt instruction (EI) should be executed to
allow recognition of interrupts after completion of the current service routine.

4 14 (4, 4, 3, 3) 3.50

None.
Example
Assume that there are two interrupting devices, A and B, connected in a daisy-chain con-
figuration, with A having a higher priority than B.

Z80 CPU
User Manual
289
A B
+
IEI IEO IEI IEO
INT
B generates an interrupt and is acknowledged. The interrupt enable out, IEO, of B goes
Low, blocking any lower priority devices from interrupting while B is being serviced.
Then A generates an interrupt, suspending service of B. The IEO of A goes Low, indicat-
ing that a higher priority device is being serviced. The A routine is completed and a RETI
is issued resetting the IEO of A, allowing the B routine to continue. A second RETI is
issued on completion of the B routine and the IE0 of B is reset (High), allowing lower-pri-
ority devices interrupt access.

Z80 CPU
User Manual
290
RETN
Operation
Return from nonmaskable interrupt
Op Code
RETN
1 1 1 0 1 1 0 1 ED
0 1 0 0 0 1 0 1 45
Operands
None.
Description
This instruction is used at the end of a nonmaskable interrupts service routine to restore
the contents of the Program Counter (analogous to the RET instruction). The state of IFF2
is copied back to IFF1 so that maskable interrupts are enabled immediately following the
RETN if they were enabled before the nonmaskable interrupt.

4 14 (4, 4, 3, 3) 3.50

None.
Example
If the Stack Pointer contains 1000h and the Program Counter contains 1A45h when a
Nonmaskable Interrupt (NMI) signal is received, the CPU ignores the next instruction and
instead restarts, returning to memory address 0066h. The current Program Counter con-
tains 1A45h, which is pushed onto the external stack address of 0FFFh and 0FFEh, high-
order byte first, and 0066h is loaded onto the Program Counter. That address begins an
interrupt service routine that ends with a RETN instruction.
Upon the execution of a RETN instruction, the contents of the former Program Counter
are popped off the external memory stack, low-order first, resulting in the Stack Pointer
again containing 1000h. The program flow continues where it left off with an op code
fetch to address 1A45h, order-byte first, and 0066h is loaded onto the Program Counter.

Z80 CPU
User Manual
291
That address begins an interrupt service routine that ends with a RETN instruction. Upon
the execution of a RETN instruction, the contents of the former Program Counter are
popped off the external memory stack, low-order first, resulting in stack pointer contents
of 1000h. The program flow continues where it left off with an op code fetch to address
1A45h.

Z80 CPU
User Manual
292
RST p
Operation
(SP – 1) ← PCH, (SP – 2) ← PCL, PCH ← 0, PCL ← P
Op Code
RST
Operand
p
1 1 t 1 1 1
Description
The current Program Counter (PC) contents are pushed onto the external memory stack,
and the Page 0 memory location assigned by operand p is loaded to the PC. Program exe-
cution then begins with the op code in the address now pointed to by PC. The push is per-
formed by first decrementing the contents of the Stack Pointer (SP), loading the high-order
byte of PC to the memory address now pointed to by SP, decrementing SP again, and load-
ing the low-order byte of PC to the address now pointed to by SP. The Restart instruction
allows for a jump to one of eight addresses indicated in the following table. The operand p
is assembled to the object code using the corresponding T state.
Because all addresses are stored in Page 0 of memory, the high-order byte of PC is loaded
with 00h. The number selected from the p column of the table is loaded to the low-order
byte of PC.
p t
00h 000
08h 001
10h 010
18h 011
20h 100
28h 101
30h 110
38h 111

Z80 CPU
User Manual
293

3 11 (5, 3, 3) 2.75
Example
If the Program Counter contains 15B3h, then upon the execution of an RST 18h (object
code 1101111) instruction, the PC contains 0018h as the address of the next fetched op
code.

Z80 CPU
User Manual
294
Input and Output Group

The following input and output group instructions are each described in this section. Sim-
IN A, (n) – see page 295
IN r (C) – see page 296
INI – see page 298
INIR – see page 300
IND – see page 302
INDR – see page 304
OUT (n), A – see page 306
OUT (C), r – see page 307
OUTI – see page 309
OTIR – see page 311
OUTD – see page 313
OTDR – see page 315

Z80 CPU
User Manual
295
IN A, (n)
Operation
A ← (n)
Op Code
IN
Operands
A, (n)
1 1 0 1 1 0 1 1 DB
Description
The operand n is placed on the bottom half (A0 through A7) of the address bus to select
the I/O device at one of 256 possible ports. The contents of the Accumulator also appear
on the top half (A8 through A15) of the address bus at this time. Then one byte from the
selected port is placed on the data bus and written to the Accumulator (Register A) in the
CPU.
M Cycles T States 4 MHz LT.

3 11 (4, 3, 4) 2.75

None.
Example
The Accumulator contains 23h, and byte 7Bh is available at the peripheral device mapped
to I/O port address 01h. Upon the execution of an IN A, (01h) instruction, the Accumula-
tor contains 7Bh.

Z80 CPU
User Manual
296
IN r (C)
Operation
r ← (C)
Op Code
IN
Operands
r, (C)
1 1 1 0 1 1 0 1 ED
0 1 r 0 0 0
Description
The contents of Register C are placed on the bottom half (A0 through A7) of the address
bus to select the I/O device at one of 256 possible ports. The contents of Register B are
placed on the top half (A8 through A15) of the address bus at this time. Then one byte
from the selected port is placed on the data bus and written to register r in the CPU. Regis-
ter r identifies any of the CPU registers shown in the following table, which also indicates
the corresponding 3-bit r field for each. The flags are affected, checking the input data.
Register r
Flag 110 Undefined op code; set the flag
B 000
C 001
D 010
E 011
H 100
L 101
A 111

3 12 (4, 4, 4) 3.00

Z80 CPU
User Manual
297

S is set if input data is negative; otherwise, it is reset.
Z is set if input data is 0; otherwise, it is reset.
H is reset.
N is reset.
C is not affected.
Example
Register C contains 07h, Register B contains 10h, and byte 7Bh is available at the periph-
eral device mapped to I/O port address 07h. Upon the execution of an IN D, (C) com-
mand, the D Register contains 7Bh.

Z80 CPU
User Manual
298
INI
Operation
(HL) ← (C), B ← B – 1, HL ← HL + 1
Op Code
INI
1 1 1 0 1 1 0 1 ED
1 0 1 0 0 0 1 0 A2
Operands
None.
Description
bus to select the I/O device at one of 256 possible ports. Register B can be used as a byte
counter, and its contents are placed on the top half (A8 through A15) of the address bus at
this time. Then one byte from the selected port is placed on the data bus and written to the
CPU. The contents of the HL register pair are then placed on the address bus and the input
byte is written to the corresponding location of memory. Finally, the byte counter is decre-
mented and register pair HL is incremented.

4 16 (4, 5, 3, 4) 4.00

S is unknown.
Z is set if B – 1 = 0; otherwise it is reset.
H is unknown.
P/V is unknown.
N is set.
C is not affected.

Z80 CPU
User Manual
299
Example
Register C contains 07h, Register B contains 10h, the HL register pair contains 1000h,
and byte 7Bh is available at the peripheral device mapped to I/O port address 07h. Upon
the execution of an INI instruction, memory location 1000h contains 7Bh, the HL register
pair contains 1001h, and Register B contains 0Fh.

Z80 CPU
User Manual
300
INIR
Operation
(HL) ← (C), B ← B – 1, HL ← HL +1
Op Code
INIR
1 1 1 0 1 1 0 1 ED
1 0 1 1 0 0 1 0 B2
Operands
None.
Description
bus to select the I/O device at one of 256 possible ports. Register B is used as a byte coun-
ter, and its contents are placed on the top half (A8 through A15) of the address bus at this
time. Then one byte from the selected port is placed on the data bus and written to the
CPU. The contents of the HL register pair are placed on the address bus and the input byte
is written to the corresponding location of memory. Then register pair HL is incremented,
the byte counter is decremented. If decrementing causes B to go to 0, the instruction is ter-
minated. If B is not 0, the Program Counter is decremented by two and the instruction
repeated. Interrupts are recognized and two refresh cycles execute after each data transfer.
Note: If B is set to 0 prior to instruction execution, 256 bytes of data are input.
If B ≠ 0:

5 21 (4, 5, 3, 4, 5) 5.25
If B = 0:

4 16 (4, 5, 3, 4) 4.00

Z80 CPU
User Manual
301

S is unknown.
Z is set.
H is unknown.
P/V is unknown.
N is set.
C is not affected.
Example
and the following sequence of bytes is available at the peripheral device mapped to I/O
port of address 07h.
51h
A9h
03h
Upon the execution of an INIR instruction, the HL register pair contains 1003h, Register
B contains a 0, and the memory locations contain the following data:
1000h 51h
1001h A9h
1002h 03h

Z80 CPU
User Manual
302
IND
Operation
(HL) ← (C), B ← B – 1, HL ← HL – 1
Op Code
IND
1 1 1 0 1 1 0 1 ED
1 0 1 0 1 0 1 0 AA
Operands
None.
Description
bus to select the I/O device at one of 256 possible ports. Register B can be used as a byte
counter, and its contents are placed on the top half (A8 through A15) of the address bus at
this time. Then one byte from the selected port is placed on the data bus and written to the
is written to the corresponding location of memory. Finally, the byte counter and register
pair HL are decremented.

4 16 (4, 5, 3, 4) 4.00

S is unknown.
Z is set if B – 1 = 0; otherwise, it is reset.
H is unknown.
P/V is unknown.
N is set.
C is not affected.

Z80 CPU
User Manual
303
Example
and byte 7Bh is available at the peripheral device mapped to I/O port address 07h. Upon
the execution of an IND instruction, memory location 1000h contains 7Bh, the HL regis-
ter pair contains 0FFFh, and Register B contains 0Fh.

Z80 CPU
User Manual
304
INDR
Operation
(HL) ← (C), B ← 131, HL ← HL1
Op Code
INDR
1 1 1 0 1 1 0 1 ED
1 0 1 1 1 0 1 0 BA
Operands
None.
Description
bus to select the I/O device at one of 256 possible ports. Register B is used as a byte coun-
ter, and its contents are placed on the top half (A8 through A15) of the address bus at this
time. Then one byte from the selected port is placed on the data bus and written to the
is written to the corresponding location of memory. Then HL and the byte counter are dec-
remented. If decrementing causes B to go to 0, the instruction is terminated. If B is not 0,
the Program Counter is decremented by two and the instruction repeated. Interrupts are
recognized and two refresh cycles are executed after each data transfer.
When B is set to 0 prior to instruction execution, 256 bytes of data are input.
If B ≠ 0:

5 21 (4, 5, 3, 4, 5) 5.25
If B = 0:

4 16 (4, 5, 3, 4) 4.00

Z80 CPU
User Manual
305

S is unknown.
Z is set.
H is unknown.
P/V is unknown.
N is set.
C is not affected.
Example
Register C contains 07h, Register B contains 03h, the HL register pair contains 1000h
and the following sequence of bytes is available at the peripheral device mapped to I/O
port address 07h:
51h
A9h
03h
Upon the execution of an INDR instruction, the HL register pair contains 0FFDh, Register
B contains a 0, and the memory locations contain the following data:
0FFEh 03h
0FFFh A9h
1000h 51h

Z80 CPU
User Manual
306
OUT (n), A
Operation
(n) ← A
Op Code
OUT
Operands
(n), A
1 1 0 1 0 0 1 1 D3
Description
The operand n is placed on the bottom half (A0 through A7) of the address bus to select
the I/O device at one of 256 possible ports. The contents of the Accumulator (Register A)
also appear on the top half (A8 through A15) of the address bus at this time. Then the byte
contained in the Accumulator is placed on the data bus and written to the selected periph-
eral device.

3 11 (4, 3, 4) 2.75

None.
Example
If the Accumulator contains 23h, then upon the execution of an OUT (01h) instruction,
byte 23h is written to the peripheral device mapped to I/O port address 01h.

Z80 CPU
User Manual
307
OUT (C), r
Operation
(C) ← r
Op Code
OUT
Operands
(C), r
1 1 1 0 1 1 0 1 ED
0 1 r 0 0 1
Description
bus to select the I/O device at one of 256 possible ports. The contents of Register B are
placed on the top half (A8 through A15) of the address bus at this time. Then the byte con-
tained in register r is placed on the data bus and written to the selected peripheral device.
Register r identifies any of the CPU registers shown in the following table, which also
shows the corresponding three-bit r field for each that appears in the assembled object
code.
Register r
B 000
C 001
D 010
E 011
H 100
L 101
A 111

3 12 (4, 4, 4) 3.00

Z80 CPU
User Manual
308

None.
Example
If Register C contains 01h and the D Register contains 5Ah, then upon the execution of an
OUT (C), D instruction, byte 5Ah is written to the peripheral device mapped to I/O port
address 01h.

Z80 CPU
User Manual
309
OUTI
Operation
(C) ← (HL), B ← B – 1, HL ← HL + 1
Op Code
OUTI
1 1 1 0 1 1 0 1 ED
1 0 1 0 0 0 1 1 A3
Operands
None.
Description
The contents of the HL register pair are placed on the address bus to select a location in
memory. The byte contained in this memory location is temporarily stored in the CPU.
Then, after the byte counter (B) is decremented, the contents of Register C are placed on
the bottom half (A0 through A7) of the address bus to select the I/O device at one of 256
possible ports. Register B can be used as a byte counter, and its decremented value is
placed on the top half (A8 through A15) of the address bus. The byte to be output is placed
on the data bus and written to a selected peripheral device. Finally, the register pair HL is
incremented.

4 16 (4, 5, 3, 4) 4.00

S is unknown.
H is unknown.
P/V is unknown.
N is set.
C is not affected.

Z80 CPU
User Manual
310
Example
If Register C contains 07h, Register B contains 10h, the HL register pair contains 100014
and memory address 1000h contains 5914, then upon the execution of an OUTI instruc-
tion, Register B contains 0Fh, the HL register pair contains 1001h, and byte 59h is writ-
ten to the peripheral device mapped to I/O port address 07h.

Z80 CPU
User Manual
311
OTIR
Operation
(C) ← (HL), B ← B – 1, HL ← HL + 1
Op Code
OTIR
1 1 1 0 1 1 0 1 ED
1 0 1 1 0 0 1 1 B3
Operands
None.
Description
placed on the top half (A8 through A15) of the address bus at this time. Next, the byte to
be output is placed on the data bus and written to the selected peripheral device. Then reg-
ister pair HL is incremented. If the decremented B Register is not 0, the Program Counter
(PC) is decremented by two and the instruction is repeated. If B has gone to 0, the instruc-
tion is terminated. Interrupts are recognized and two refresh cycles are executed after each
data transfer.
Note: When B is set to 0 prior to instruction execution, the instruction outputs 256 bytes of data.
If B ≠ 0:

5 21 (4, 5, 3, 4, 5) 5.25

Z80 CPU
User Manual
312
If B = 0:

4 16 (4, 5, 3, 4) 4.00

S is unknown.
Z is set.
H is unknown.
P/V is unknown.
N is set.
C is not affected.
Example
and memory locations contain the following data.
1000h contains 51h
1001h contains A9h
1002h contains 03h
Upon the execution of an OTIR instruction, the HL register pair contains 1003h, Register
B contains a 0, and a group of bytes is written to the peripheral device mapped to I/O port
address 07h in the following sequence:
51h
A9h
03h

Z80 CPU
User Manual
313
OUTD
Operation
(C) ← (HL), B ← B – 1, HL ← HL – 1
Op Code
OUTD
1 1 1 0 1 1 0 1 ED
1 0 1 0 1 0 1 1 AB
Operands
None.
Description
be output is placed on the data bus and written to the selected peripheral device. Finally,
the register pair HL is decremented.

4 16 (4, 5, 3. 4) 4.00

S is unknown.
H is unknown.
P/V is unknown.
N is set.
C is not affected.

Z80 CPU
User Manual
314
Example
If Register C contains 07h, Register B contains 10h, the HL register pair contains 1000h,
and memory location 1000h contains 59h, then upon the execution of an OUTD instruc-
tion, Register B contains 0Fh, the HL register pair contains 0FFFh, and byte 59h is writ-
ten to the peripheral device mapped to I/O port address 07h.

Z80 CPU
User Manual
315
OTDR
Operation
(C) ← (HL), B ← B – 1, HL ← HL – 1
Op Code
OTDR
1 1 1 0 1 1 0 1 ED
1 0 1 1 1 0 1 1 BB
Operands
None.
Description
be output is placed on the data bus and written to the selected peripheral device. Then, reg-
ister pair HL is decremented and if the decremented B Register is not 0, the Program
Counter (PC) is decremented by two and the instruction is repeated. If B has gone to 0, the
instruction is terminated. Interrupts are recognized and two refresh cycles are executed
after each data transfer.
Note: When B is set to 0 prior to instruction execution, the instruction outputs 256 bytes of data.
If B ≠ 0:

5 21 (4, 5, 3, 4, 5) 5.25

Z80 CPU
User Manual
316
If B = 0:

4 16 (4, 5, 3, 4) 4.00

S is unknown.
Z is set.
H is unknown.
P/V is unknown.
N is set.
C is not affected.
Example
and memory locations contain the following data.
0FFEh 51h
0FFFh A9h
1000h 03h
Upon the execution of an OTDR instruction, the HL register pair contain 0FFDh, Register
B contains a 0, and a group of bytes is written to the peripheral device mapped to I/O port
address 07h in the following sequence:
03h
A9h
51h

Z80 CPU
User Manual
317
Customer Support
To share comments, get your technical questions answered, or report issues you may be
experiencing with our products, please visit Zilog’s Technical Support page at
http://support.zilog.com.
To learn more about this product, find additional documentation, or to discover other fac-
ets about Zilog product offerings, please visit the Zilog Knowledge Base at http://
zilog.com/kb or consider participating in the Zilog Forum at http://zilog.com/forum.
This publication is subject to replacement by a later edition. To determine whether a later
edition exists, please visit the Zilog website at http://www.zilog.com.
UM008011-0816 Customer Support

Z80 CPU
User Manual
318
Customer Support UM008011-0816

Zilog PDF

Uploaded by

Copyright:

Available Formats

You might also like

Zilog PDF

Uploaded by

Document Information

Original Title

Copyright

Available Formats

Share this document

Share or Embed Document

Sharing Options

Did you find this document useful?

Is this content inappropriate?

Copyright:

Available Formats

Zilog PDF

Uploaded by

Copyright:

Available Formats

Z8018x

Windows is a registered trademark of Microsoft Corporation.

Baud Rate Generator

Software Architecture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 173

Timing Diagrams . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 197

Instruction Set . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 207

Instruction Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .237

Operating Modes Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .281

Status Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .287

I/O Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .293

Figure 21. SLEEP Timing Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . 35

Figure 49. TEND0 Output Timing Diagram . . . . . . . . . . . . . . . . . . .108

Software Architecture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 173

Timing Diagrams . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 197

Table 23. Timer Output Control . . . . . . . . . . . . . . . . . . . . . . . . . . . .163

Software Architecture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .173

Instruction Set . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .207

Table 43. Block Transfer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 225

Op Code Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 247

Bus Control Signal Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . 251

Operating Modes Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 281

Status Signals 287

I/O Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 293

Z80180, Z8S180, Z8L180 MPU Operation

on-chip memory management unit (MMU) with the capability of

Reduced system costs are obtained by incorporating several key system

• 64-Pin Dual In-line Package (DIP), Figure 1

• 68-Pin Plastic Leaded Chip Carrier (PLCC), Figure 2

• 80-Pin Quad Flat Pack (QFP), Figure 3

Pin out package descriptions for other Z8X180-based products are

Figure 4 depicts the block diagram that is shared throughout all

Figure 1. 64-Pin DIP

Figure 2. 68-Pin PLCC

Figure 3. 80-Pin QFP

Figure 4. Z80180/Z8S180/Z8L180 Block Diagram

D0–D7. Data Bus (Bidirectional, Active High, 3-state). D0-D7 constitute

RTS0. Request to Send 0 (Output, Active Low). This output is a

Table 1. Status Summary

0 1 0 CPU operation (1st Op Code fetch)

TEND0, TEND1. Transfer End 0 and 1 (Outputs, Active Low). This

Table 2. Multiplexed Pin Descriptions

During RESET, this pin is initialized as A18 pin. If either

• Programmable Reload Timers (PRT, 2 channels)

• Clock Serial I/O (CSIO) channel.

Other Z8X180 family members (such as Z80183, Z80S183, Z80185/195)

Bus State Controller

Memory Management Unit

Central Processing Unit

Asynchronous Serial Communications Interface (ASCI)

Programmable Reload Timer (PRT)

Clocked Serial I/O (CSIO)

Operation Mode Control Register

Figure 5. Operation Mode Control Register

Write into OMCR Op Code Fetch

Figure 6. M1 Temporary Enable Timing

The user must program the Operation Mode Control Register

Instruction (Op Code) Fetch Timing

Figure 9. Op Code Fetch (without Wait State) Timing Diagram