Computer Architecture

Homework #5 Solution

1. Exercise 5.1

Combinational logic only: a, b, c, h, i

Sequential logic only: f, g, j
Mixed sequential and combinational: d, e, k

2. Exercise 5.3

a. RegWrite = 1: sw and beq should not write results to the register file. sw ( or beq ) will
overwrite a random register with either the store address (or branch target) or random data
from the memory data read port. Hence sw and beq will not work correctly.

b. ALUop0 = 1: lw and sw will not work correctly because they will perform subtraction
instead of the addition necessary for address calculation.

c. ALUop1 = 1: lw and sw will not work correctly. lw and sw will perform a random
operation depending on the least significant bits of the address field instead of addition
operation necessary for address calculation.

d. Branch = 1: Instructions other than branches (beq) will not work correctly if the ALU Zero
signal is raised. An R-format instruction that produces zero output will branch to a random
address determined by its least significant 16 bits.

e. MemRead = 1: All instructions will work correctly. (Data memory is always read, but memory
data is never written to the register file except in the case of lw.)

f. MemWrite = 1: Only sw will work correctly. The rest of instructions will store their results in
the data memory, while they should not.

3. Similar to Exercise 5.8 except that instead of jr, we wish to add the instruction addi
(add immediate) to the single-cycle datapath.

No additions to the datapath are required. A new row should be added to the truth table in Figure
5.18. The new control is similar to load word because we want to use the ALU to add the
immediate to a register (and thus RegDst = 0, ALUSrc = 1, ALUOp = 00). The new control is
also similar to an R-format instruction, because we want to write the result of the ALU into a
register (and thus MemtoReg = 0, RegWrite = 1) and of course we aren’t branching or using
memory (Branch = 0, MemRead = 0, MemWrite = 0).

The setting of control lines:

Instruction Reg ALU Memto Reg Mem Mem Branch ALU ALU
 Dst Src Reg Write Read Write Op1 Op0
R-format 1 0 0 1 0 0 0 1 0
lw 0 1 1 1 1 0 0 0 0
sw x 1 x 0 0 1 0 0 0
beq x 0 x 0 0 0 1 0 1
addi 0 1 0 1 0 0 0 0 0

4. Similar to Exercise 5.8 except that instead of jr, we wish to add the instruction jal
(jump and link) to the single-cycle datapath of Figure 5.24 of pg. 314.

Instruction Reg ALU Memto Reg Mem Mem Branch ALU ALU Jump
Dst Src Reg Write Read Write Op1 Op0
R-format 01 0 00 1 0 0 0 1 0 0
lw 00 1 01 1 1 0 0 0 0 0
sw xx 1 xx 0 0 1 0 0 0 0
beq xx 0 xx 0 0 0 1 0 1 0
jal 10 x 10 1 0 0 0 x x 1

We already have a way to change the PC based on the specified address (using the
datapath for
the jump instruction), but we’ll need a way to put PC+4 into a register $ra (31), and
this will require changing the datapath. We can expend the multiplexor controlled by
RegDst to includeas a new input. We can expand the multiplexor controlled by
MemtoReg to have PC+4 as an input. Because we expand these multiplexors, the entire
columns for RegDst and MemtoReg mchanged appropriately in the truth table. The jal
instruction doesn’t use the ALU, so ALUSrc and ALUOp can be don’t cares. We’ll have
Jump = 1, RegWrite = 1, and we aren’t branching ousing memory (Branch = 0,
MemRead = 0, MemWrite = 0).

5. Exercise 5.12

Here, the l_inc instruction uses a single cycle for two actions:

lw $rt, L($rs)
addi $rs, $rs, 4

This instruction requires two writes to the register file. The only way to implement it is to
modify the register file to have two write ports instead of one.

6. Exercise 5.26

Load instructions are on the critical path that includes the following functional units:
instruction memory,
register file read,
ALU,
data memory, and
register file write,
with a total of (200 + 50 + 100 + 200 + 50) ps = 600 ps. Increasing the delay of any of
these units will increase the clock period of this datapath. The units that outside this
critical path are the two adders used for PC calculation (PC + 4 and PC + Immediate
field) (100 + 100 = 200 ps), which produce the branch outcome.

Based on the numbers given on page 315, the sum of the two adder’s delay can tolerate
delays up to 400 more ps.

Any reduction in the critical path components will lead to a reduction in the clock period.