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Table of Content Version/Revision History


Page 1 TITLE PAGE Ver Rev Date Description Reason for Amendment Review Person

Page 2 POS_FPS_AP Rev X1 Draft


V001 X1 10/03/2017 1. Initial release for POS

V001 REV0 10/17/2017 Release to Prototype Phase


Rev X2 Draft
D
V001 X2 10/03/2017 1. Mech placement modified for the board compatible D
for MFS enclosure

V001 X3 11/22/2017 Rev X3 Draft


1. QFN package changed for CYPRESS controller.

V001 REV0 01/03/2018 Release to Prototype Phase

V001 Rev0 - 1 09/20/2018 Rev1 - Draft 1 - Updated Review comments


1. PCB footprint changed for image sensor IC
2. Few Test points added
3. More decoupling Capacitors added near the image
sensor.
4. Transorbs added to the USB section
5. R16 changed to 170E and C17 changed to 2.2uF/10V

C C

B B

A A

POS FPS
SIZE
Prepared Checked Approved Title:
POS FPS (using Aptina) C

Rev
Design Ref: Sub-Title: TITLE PAGE
POS_FPS_AP_V001_R01 01

DWG No: OMAG1700234 PCB Ref: OAS PR 200252_Mod1 Date: Sheet 1 of 2


Friday, September 21, 2018

5 4 3 2 1
5 4 3 2 1

USB controller Interface

1 3.3V
1 TEST POINT 3.3V
MCL R9 3.3V
3.3V
1 MCLK

22K_0402
1 R4
R16
TEST POINT 0E_0402
Sensor
3.3V

1.5K_0402
3.3V
3.3V R5 Interface
100nF_0402
1

170E_0402 R6 R7 U3

10uF/25V_1206
2.2uF/10V_1206

D D
C18

C17

2.2K_0402
1
45

14
54
52
51
50
49
48
47
46
45
44

10K_0402

2.2K_0402
2

U7 C6 R8 DOUT0 44

100K_0402
1 GND D1 MCLK 47 DOUT1 43 DOUT2

CLKOUT/**PE1
PD7/FD15
PD6/FD14
PD5/FD13
PD4/FD12
PD3/FD11
PD2/FD10
PD1/FD9
PD0/FD8
RESERVED

*WAKEUP

2
1 TEST POINT M7_DO214AC R14 SDATA 24 SVSCLK DOUT2 42 DOUT3
SCLK 25 SDATA DOUT3 41 DOUT4
C8 32 SCLK DOUT4 15 DOUT5
LV RESET DOUT5
Y1 1 42 DIG TEST 29 16 DOUT6
12pF_0402 1 4 1 LV 2 RDY0/*SLRD RESET# OE 28 DIG DOUT6 17 DOUT7

100nF_0402
1 RDY1/*SLWR FV OE DOUT7

1
3 40 R20 0E_0402 led STDBY 33 18 DOUT8
2 3 TEST POINT 7 AVCC PA7/*FLAGD/SLCS# 39 FV 1 C15 ADR0 30 STAND DOUT8 19 DOUT9
5 AVCC1 PA6/*PKTEND 38 2 JP2 1 1 1uF/25V_1206 ADR1 31 ADR0 DOUT9 21 FV

1.5K_0402
2
XTALIN PA5/FIFOADR1 ADR1 FRAME

C7
C12 24MHz 4 37 2 1 TEST POINT R12 DATAIN_N 10 20 LV
XTALOUT PA4/FIFOADR0 36 JP1 3.3V 11 SER_N LINE 46 PCLK
12pF_0402 8 PA3/*WU2 35 R11 9 SER_P PIXCLK 23
D+ 1 9 DPLUS PA2/*SLOE 34 8 CLK_P EXPOSE 27
1 DMINUS PA1/INT1# CLK_N LEDOUT
RMC CONNECTOR 5PIN

VBUS TEST POINT 10 33 37 22


J1 12 AGND1 PA0/INT0# 32 1K_0402 36 VREF STLN OUT 5
1 VBUS 26 GND VCC3 11 R13 VTEST DATAOUT_P 4
1 1 TEST POINT 28 GND1 VCC 27 7 DATAOUT_N 3

CTL2/*FLAGC

CTL1/*FLAGB
CTL0/*FLAGA
GND2 VCC2 PLGND CLK_OUT_P

*IFCLK/**PE0
2 D- 56 17 3.3V 12 2 3.3V
3 D+ 53 GND5 VCC1 43 1K_0402 38 LVDS CLK_OUT_N 1
GND4 VCC4 AGND1 VDD0

PB0/FD0
PB1/FD1
PB2/FD2
PB3/FD3
PB4/FD4
PB5/FD5
PB6/FD6
PB7/FD7
4 6 55 34 14
5 1 41 AGND VCC5 48 AGND0 VDD1 6

10uF/25V_1206
SDA
SCL
1 D- GND3 13 DGND0 PLVDD 40

100nF_0402
1
TEST POINT 26 DGND1 VAAP 39

10uF/25V_1206
SYFRM VAA1 35

C10
CY7C68013A C9

100nF_0402

100nF_0402

100nF_0402

100nF_0402

100nF_0402
15
16
31
18
19
20
21
22
23
24
25
30
29
13
VAA0

C13
2
1

C14

C21

C20

C23

C22
C11 SCL
PCL
EZJZ0V500AA_0402

EZJZ0V500AA_0402

EZJZ0V500AA_0402

TEST POINT1 SCLK MT9V034_CLCC48

2
DOUT2
DOUT3
DOUT4
DOUT5
DOUT6
DOUT7
DOUT8
DOUT9
STDBY
SDA 1 SDATA R10 PCLK 1
100nF_0402 TEST POINT1 0E_0402 1

R15 D2 D3 D4 TEST POINT


DO2 1 1 DO9
TEST POINT1 1 TEST POINT
1M_0402 DO3 1 1 DO8
C TEST POINT1 1 TEST POINT
C
DO4 1 1 DO7
TEST POINT1 1 TEST POINT
DO5 1 1 DO6
TEST POINT1 1 TEST POINT

C16
LDO
Interface EPROM
VBUS 3.3V
Interface 100nF_0402 LENS
U1
3.3V 3.3V
JP3
PLACEMENT LED ILLUMINATION 3.3V
1 3
NCP705_WDFN
Jumper_0603 3.3V

MTG1

MTG2
6 1 R17 R18 U5 CAMERA TO LED
10K_0402

10K_0402

1
IN OUT 1 LENS 2 WIRE
100nF_0402/25V

100nF_0402/25V

2 MOUNT JP4
VCC
10uF/25V_1206

10uF/25V_1206

NC
1

2
4 1 R19 Jumper_0603 2 1
EN A0 BC857
C3

C5

C2 3 C4 SCLK 6 2 led 1 2
GND1 SDATA 5 SCL A1 3 PART(Will update) Q1
GND
2

5 SDA A2 4 10K_0402

3
NC1 GND 7 J2
WP led_out
GND

AT24C512/1024

B B

A A

POS FPS
SIZE
Prepared Checked Approved Title:
POS FPS (using Aptina) C

Rev
Design Ref: Sub-Title: POS_FPS
POS_FPS_AP_V001_R01 01

DWG No: OMAG1700234 PCB Ref: OAS PR 200252_Mod1 Date: Sheet 2 of 2


Friday, September 21, 2018

5 4 3 2 1

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