Microchip Debugging Methodology PDF

DEBUGGING
METHODOLOGY
© 2013 Microchip Technology Incorporated. All Rights Reserved. 17002 DEV Slide 37
Debugging Methodology
 PIC® MCUs utilize particular features and

characteristics during debugging
 Understanding the debug methodology is

essential to debugging PIC MCU
applications
In-Circuit Serial Programming Interface
Integrated
Development
Environment Programmer Target
+ Debugger Hardware
Language Tool
MPLAB®
REAL ICE
TM
ACTIVE
STATUS
FUNCTION RESET
MPLAB® X IDE
MPLAB REAL ICE™ Your Hardware
In-Circuit Emulator
C language Design
MPLAB ICD 3 or
Compiler(s)
PICkit™ 3 A Microchip
Programmer/Debugger development board
Connecting the Hardware to the
Programmer/Debugger
Vdd
Vpp/MCLR
PIC® PGC
MCU PGD
Vss
For more info reference Microchip’s In-Circuit serial Programming™

(ICSP™) Guide reference document number DS30277
Communicating with a
Programmer/Debugger
Vdd
Vpp/MCLR • ICSP™ clock and data pins

PGC
are called different names on
some PIC® MCUs. These alternate
PGD names include ICDDAT & ICDCLK
and PGED & PGEC.
Vss
• Check your data sheet for the

specific name of these pins.
For more info reference Microchip’s In-Circuit Serial Programming™ (ICSP™)

Guide reference document number DS30277
ICSP™ Connectors
Vdd
Vpp/MCLR
PGC
PGD
Vss
For more info reference Microchip’s In-Circuit Serial Programming™ (ICSP)

ICSP™ Connectors
Vdd
Vpp/MCLR
PGC
PGD
Vss

ICSP™ Connectors
Vdd
Vpp/MCLR
PGC
PGD
Vss
Part Number
AC164110

Elements of a PIC® MCU
Program
Memory
VDD
vpp/MCLR
PIC®
CPU
Microcontroller
PGC
configuration bits
PGD HW Stack File Registers

(8 bit processors)
VSS
Configuration Bits
• Set at program
time the
Configuration Program
Memory
Bits enable VDD
circuitry on the
PIC® MCU vpp/MCLR
CPU
•For example:
A PIC ® MCU PGC
determines It’s configuration bits
CPU clock source PGD HW Stack File Registers

from the (8 bit processors)
Configuration bit
VSS
settings
• For debug one
particular
configuration bit
is of importance:
Configuration Bits
•Set at program
time the
Program
Configuration Internal Memory
Bits enable VDD
Debug
circuitry on the Hardware
PIC® MCU vpp/MCLR
•For example: CPU
A PIC MCU
determines its PGC
debug configuration bit
CPU clock source
from the PGD HW Stack File Registers
Configuration Bit (8 bit processors)
settings VSS
•For debug one

particular
configuration bit
is of importance:
Internal Debug Hardware
Program
Internal Memory
VDD
Debug
Hardware
vpp/MCLR
CPU
PGC
debug configuration bit
PGD HW Stack File Registers

(8 bit processors)
VSS
Internal Debug Hardware
 Communicates with MPLAB® X
IDE and Debugger through the
PGD and PGC pins
Internal  Controls the operation of the

Debug
PIC® MCU when in Debug
mode
Hardware
 Sets breakpoint conditions and

informs MPLAB X IDE of
conditions within the PIC MCU
 May need additional firmware

to loaded into program
memory in order to operate
Debug Executive
The Debug Executive is the firmware
needed to communicate between the debug
hardware the and Programmer/Debugger
 Added by MPLAB® X IDE to User Program

at build time
 Size depends upon which MCU is being

used and programmer/debugger selected
 In addition to Program Memory the Debug

Executive will use some RAM
Debugging Considerations
 A PIC® MCU will run at FULL SPEED

when in debug mode!!
 The debug configuration bit is set by

MPLAB® X IDE based upon user input
 When in Debug mode, the developer

must take into consideration the
resources used by the PIC MCU’s debug
process
Resources Used while
Debugging
 Exclusive use of two I/O pins
 Shared control of MCLR pin
 Some File Registers (RAM)
 Some Program Memory locations
(Flash)
 One or two hardware stack locations
For details, select from the menu:

Help ► Help Contents
and find the Reserved Resources topic
in your debug tool’s help section.
Debug Headers
 Allows debugging
when:
 Not enough pins are
available
 Device doesn’t have
debug capability
Many new small pin count

and low cost devices will
require a debug header!
Debug Mode Operation
Program
Internal Memory
Debug
VDD
Hardware
vpp/MCLR
CPU
 When the code is Debug config. bit
PGC
ready to test the File Registers
user selects PGD
“Debug Main
Project” icon from VSS
the MPLAB® X IDE
toolbar
 MPLAB® X IDE will
build a image to be
programmed into
the PIC® MCU’s Internal
Program
Memory
Program Memory VDD
Debug
Hardware
 This image vpp/MCLR

includes the user’s CPU
Debug config. bit
applications code
PGC
plus the File Registers
appropriate PGD
debug executive
VSS
 This downloadable
image will also
have the debug
configuration bit
enabled

connect to the selected Internal
Program
Memory
programmer/debugger Debug
VDD
Hardware
vpp/MCLR
MPLAB® CPU
REAL ICE Debug config. bit
TM
ACTIVE
STATUS
PGC
FUNCTION RESET
File Registers
PGD
 The program/debugger VSS
signals the PIC® MCU

to accept a new
programming by
applying Vpp to the
Vpp/MCLR pin
 The program image
is programmed into
Program
the PIC® MCU using Internal Memory
the PGC and PGD VDD
Debug
Hardware
pins User Code
vpp/MCLR
Debug Executive
MPLAB® CPU
TM
ACTIVE
STATUS
PGC
FUNCTION RESET
File Registers
PGD
VSS
 After programming,
when MCLR is
Program
released all resource Internal Memory
needed for VDD
Debug
Hardware
debugging are User Code
allocated
vpp/MCLR
Debug Executive
MPLAB® CPU
TM
ACTIVE
STATUS
PGC
FUNCTION RESET
File Registers
2 HW stack Debug variables
PGD
 In debugging mode locations ( 8 bit)
the PIC® MCU is

VSS
controlled with
MPLAB® X IDE Icons
via PGD and PGC
Production Mode Programming
Program
Internal Memory
Debug
VDD
Hardware
vpp/MCLR
CPU
Debug config. bit
PGC
When the code is ready File Registers
to run Stand alone” on the PGD
PIC® MCU the user selects

“Make and Program VSS
Device Main Project”

icon from the toolbar
•MPLAB ®X
IDE will build a Internal
Program
Memory
image to be download VDD
Debug
Hardware
which includes only the
user’s applications code
vpp/MCLR
and no debug executive.
CPU
•This downloadable image

Debug config. bit
PGC
File Registers
will have the debug PGD
configuration bit
DISABLED VSS

connect to the selected Internal
Program
Memory
programmer/debugger Debug
VDD
Hardware
vpp/MCLR
MPLAB® CPU
TM
ACTIVE
STATUS
PGC
FUNCTION RESET
File Registers
PGD
 The program/debugger VSS
signals the PIC® MCU to

accept a new
programming by
applying Vpp to the
Vpp/MCLR pin
 The program image is

programmed into the Internal
Program
Memory
PIC® MCU using the Debug
VDD
PGD and PGC pins Hardware
User Code
vpp/MCLR
MPLAB® CPU
TM
ACTIVE
STATUS
PGC
FUNCTION RESET
File Registers
PGD
VSS
• MCLR is released by
programmer/debugger Program
Internal
PIC® MCU exits RESET Debug
Memory
VDD
Hardware
User Code
vpp/MCLR
MPLAB® CPU
TM
ACTIVE
STATUS
PGC
FUNCTION RESET
File Registers
PGD
VSS
Program
Memory
VDD
User Code
vpp/MCLR
MPLAB® CPU
TM
ACTIVE
STATUS
PGC
FUNCTION RESET
File Registers
PGD
• In Production mode VSS

PGD and PCG can
be used by the PIC®
MCU as I/O pins
Knowledge Check
Question:
TRUE or FALSE it is generally a good idea to
enter a compiler directive to set the debug
configuration bit?
Answer:
False! This particular configuration bit is set by

MPLAB® X IDE when a debug session builds the project
Knowledge Check
Question:
When the Software Simulator is used instead of a
programmer/debugger the developer can expect a
different user interface?
Answer:
No! The simulator and programmer/debuggers have

identical user interfaces in MPLAB® X IDE
Knowledge Check
Question:
When running in debug mode a PIC® MCU runs at
slightly slower speed than in release more?
Answer:
No! PIC MCUs run at full speed in debug mode

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DEBUGGING

 PIC® MCUs utilize particular features and

 Understanding the debug methodology is

For more info reference Microchip’s In-Circuit serial Programming™

Vpp/MCLR • ICSP™ clock and data pins

• Check your data sheet for the

For more info reference Microchip’s In-Circuit Serial Programming™ (ICSP™)

For more info reference Microchip’s In-Circuit Serial Programming™ (ICSP)

For more info reference Microchip’s In-Circuit Serial Programming™ (ICSP)

For more info reference Microchip’s In-Circuit Serial Programming™ (ICSP)

PGD HW Stack File Registers

CPU clock source PGD HW Stack File Registers

•For debug one

PGD HW Stack File Registers

Internal  Controls the operation of the

 Sets breakpoint conditions and

 May need additional firmware

 Added by MPLAB® X IDE to User Program

 Size depends upon which MCU is being

 In addition to Program Memory the Debug

 A PIC® MCU will run at FULL SPEED

 The debug configuration bit is set by

 When in Debug mode, the developer

For details, select from the menu:

Many new small pin count

 This image vpp/MCLR

 MPLAB® X IDE will

 The program/debugger VSS

signals the PIC® MCU

the PIC® MCU is

to run Stand alone” on the PGD

PIC® MCU the user selects

Device Main Project”

•This downloadable image

 MPLAB® X IDE will

 The program/debugger VSS

signals the PIC® MCU to

 The program image is

• In Production mode VSS

False! This particular configuration bit is set by

No! The simulator and programmer/debuggers have

No! PIC MCUs run at full speed in debug mode

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