CMR Institute of Technology, Bangalore

Department(s): Electronics and Communication Engineering

Semester: 03 Section(s): A,B,C&D
VLSI Lab 17ECL77 Lab/week: 03Hr
Course Instructor(s):Dr. Amit Jain, Dr. Nasir Abdul Quadir, Prof. Chetan H, Prof. Vinay V K, Prof.
Mahesh Gour, Prof. Sridevi S, prof. Suchismita
Course duration: 01Aug 2018 – Nov 2018

Course Objectives
 Explore the CAD tool and understand the flow of the Full Custom IC design cycle.
 Learn DRC, LVS and Parasitic Extraction of the various designs.
 Design and simulate the various basic CMOS analog circuits and use them in higher circuits like data
converters using design abstraction concepts.
 Design and simulate the various basic CMOS digital circuits and use them in higher circuits like adders
and shift registers using design abstraction concepts.

Teaching
Lab # Topics
Aids
1 Introduction Lab Cadence Tool
Design an Inverter with given specifications**, completing the
design flow mentioned below: a. Draw the schematic and verify
the following i) DC Analysis ii) Transient Analysis b. Draw the
2 Cadence Virtuoso
Layout and verify the DRC, ERC c. Check for LVS d. Extract RC and
back annotate the same and verify the Design e. Verify &
Optimize for Time, Power and Area to the given constraint
Design the (i) Common source and Common Drain amplifier and
(ii) A Single Stage differential amplifier, with given
specifications**, completing the design flow mentioned below:
3 a. Draw the schematic and verify the following i) DC Analysis ii) Cadence Virtuoso
AC Analysis iii) Transient Analysis b. Draw the Layout and verify
the DRC, ERC c. Check for LVS d. Extract RC and back annotate
the same and verify the Design.
Design an op-amp with given specification** using given
differential amplifier Common source and Common Drain
amplifier in library*** and completing the design flow
4 mentioned below: a. Draw the schematic and verify the Cadence Virtuoso
following i) DC Analysis ii). AC Analysis iii) Transient Analysis b.
Draw the Layout and verify the DRC, ERC c. Check for LVS d.
Extract RC and back annotate the same and verify the Design.
Design a 4 bit R-2R based DAC for the given specification and
completing the design flow mentioned using given op-amp in
5 the library***. a. Draw the schematic and verify the following i) Cadence Virtuoso
DC Analysis ii) AC Analysis iii) Transient Analysis b. Draw the
Layout and verify the DRC, ERC
For the SAR based ADC mentioned in the figure below draw the
6 mixed signal schematic and verify the functionality by Cadence Virtuoso
completing ASIC Design FLOW. [Specifications to GDS-II]
Write Verilog Code for the following circuits and their Test
Bench for verification, observe the waveform and synthesize the
7-1 Cadence Encounter
code with technological library with given constraints*. Do the
initial timing verification with gate level simulation.
 i. An inverter
ii. A Buffer
iii. Transmission Gate
iv. Basic/universal gates
7-2 Cadence Encounter
v. Flip flop -RS, D

i. Flip flop - JK, MS, T Cadence Encounter

7-3
ii. Serial & Parallel adder
i. 4-bit counter [Synchronous and Asynchronous counter] Cadence Encounter
7-4
ii. Successive approximation register [SAR]
Extra experiment : Design an integrator and differentiator using
the op-amp.
 #132, AECS Layout, IT Park Road, Kundalahalli, Bangalore – 560 037
T:+9180 28524466 / 77

CMR

INSTITUTE OF

TECHNOLOGY

CO-PO and CO-PSO MAPPING

DEPARTMENT OF ELECTRONICS AND COMMUNICATION ENGINEERING

NAME OF THE COURSE : 17ECL77 VLSI Lab

NAME OF THE FACULTY : Dr. Amit Jain, Dr. Nasir Abdul Quadir, Prof. Chetan H, Prof. Vinay V
K, Prof. Mahesh S Gour, Prof. Sridevi S, prof. Suchismita

PSO1

PSO2

PSO3
PO10

PO11

PO12
PO1

PO2

PO3

PO4

PO5

PO6

PO7

PO8

PO9
Course Outcomes

Write test 3 - 3 - - - 1 2 - 2 2 1 -
bench to
CO1 simulate
various digital
circuits.
Interpret 3 - 3 - - - 1 2 - 2 2 1 -
concepts of
DC Analysis,
AC Analysis
CO2
and Transient
Analysis in
analog
circuits
Design and 3 3 3 - 3 - - - 1 2 - 2 2 1 -
simulate basic
CMOS
circuits like
inverter,
CO3
common
source
amplifier and
differential
amplifiers
Use basic 3 3 3 2 3 - - - 1 2 - 2 2 1 -
amplifiers and
further design
higher level
CO4 circuits like
operational
amplifier and
analog/digital
converters to
 meet desired
parameters.
Use 3 3 3 2 3 - - - 1 2 - 2 2 1 -
transistors to
design gates
and further
using gates
CO5
realize shift
registers and
adders to
meet desired
parameters

Cognitive
REVISED BLOOMS TAXONOMY KEYWORDS
level

List, define, tell, describe, identify, show, label, collect, examine, tabulate, quote, name, who,
L1
when, where, etc.

summarize, describe, interpret, contrast, predict, associate, distinguish, estimate, differentiate,

L2
discuss, extend

Apply, demonstrate, calculate, complete, illustrate, show, solve, examine, modify, relate,
L3
change, classify, experiment, discover.

Analyze, separate, order, explain, connect, classify, arrange, divide, compare, select, explain,
L4
infer.

Assess, decide, rank, grade, test, measure, recommend, convince, select, judge, explain,
L5
discriminate, support, conclude, compare, summarize.

CORRELATION
PROGRAM OUTCOMES(PO), PROGRAM SPECIFIC OUTCOMES(PSO)
LEVELS

PO1 Engineering knowledge PO7 Environment and sustainability 0 No Correlation

PO2 Problem analysis PO8 Ethics 1 Slight/Low

Design/development of Moderate/
PO3 PO9 Individual and team work 2
solutions Medium

Conduct investigations of Substantial/

PO4 PO10 Communication 3
complex problems High

PO5 Modern tool usage PO11 Project management and finance

PO6 The Engineer and society PO12 Life-long learning

PSO1 Apply principles of electrical and electronic circuit theory to

 i) design and simulate basic electronic circuits and

ii) make use of the measuring instruments including ‘digital storage oscilloscope’ in elaborate
circuit analysis and in the design of analog and digital circuits

Apply principles of mathematics, signal processing and communication theory to analyse different
types of signals, operations on signals, design and realization of simple systems like digital filters,
PSO2 modulators, demodulators, microwave antennas and resonators and support activities of design of
communication engineering and VLSI systems

Take part in collaborative and consultancy projects as an electronic design engineer and support
PSO3 diverse tasks of circuit design projects, schedule, quality and efficiency management, and
documentation and publication of reports.

Justification of levels of correlation for COs & POs

CO1: Write test bench to simulate various digital circuits.

CO2: Interpret concepts of DC Analysis, AC Analysis and Transient Analysis in analog circuits

CO3: Design and simulate basic CMOS circuits like inverter, common source amplifier and differential
amplifiers

CO4: Use basic amplifiers and further design higher level circuits like operational amplifier and
analog/digital converters to meet desired parameters.

CO5: Use transistors to design gates and further using gates realize shift registers and adders to meet desired
parameters

PO1: Engineering Knowledge: It is a core engineering subject so correlation level is substantial for
Engineering Knowledge for all COs: 3

PO2: Problem Analysis: the course outcome 3, 4 and 5 deals with design and analysis of core analog and
digital circuits so for these 3 Cos the correlation is: 3

PO3: Design/Development of solution: the course outcome 3, 4 and 5 deals with designs for different
application oriented specifications which ultimately provide solution for design problem. So, for these 3 Cos
the correlation is: 3
PO4: Conduct investigations of complex problems: the course outcome 4 and 5 deals with standard analog
and digital design. So, for these 2 Cos the correlation is: 2

PO5: Modern tool usage: Cadence tool is used in the lab, which is the best tool for circuit design and also
being used extensively in industry. So, the correlation treated as high for all COs – 2

PO9: Individual and team work: Student conduct experiments as an individual so the team effort is very
less. So the Correlation is 1.

PO12: Life Long Learning: This course provides a basic insight in to circuit design. Correlation for all COs
-2

PSO1: Apply principles of electrical and electronic circuit theory to

i) design and simulate basic electronic circuits and

ii) make use of the measuring instruments including ‘digital storage oscilloscope’ in elaborate circuit
analysis and in the design of analog and digital circuits. This subject deals design simulation of basic
analog and digital circuits. But we don’t have any measurement setup for this lab. So, the correlation
level is moderate for all COs– 2

PSO2: Apply principles of mathematics, signal processing and communication theory to analyse
different types of signals, operations on signals, design and realization of simple systems like digital
filters, modulators, demodulators, microwave antennas and resonators and support activities of
design of communication engineering and VLSI systems . This course equips the students with basic
knowledge of circuit design and analysis. Low correlation level for all COs -1

2. Analysis on previous attainments.(Can be taken for 2013-17,2014-18,2015-19,2016-2020

and 2017-21) and setting targets on CO attainments for current semester subjects.

Note:If new subject was introduced this time and previous analysis was not there then set only the target
value for current semester randomly.

We have redefined CO-PO, CO-PSO mappings this semester. The VTU curriculum has changed based on
scheme of evaluation. The lab instruction class content delivery is redefined. An improvement in internal
attainment is expected.
Couse Attainment Target for Attainment Gap Gap Analysis
Outcome Level for last current exam Level of current
year year

CO1 2.67 2.75

CO2 2.67 2.75

CO3 2.67 2.75

CO4 2.67 2.75

CO-PO attainment computation formula along with Rubrics

Rubrics for internal assessment test

60% Stud >= 70% of max marks allocated to CO:

ATT 3

50% Stud >= 70% of max marks allocated to CO:

ATT 2
CRL – Correlation level
40% Stud >= 70% of max marks allocated to CO:
CO-PO* - CO-PO correlation for a particular ATT 1 else
PO ATT 0

ALIACOX – Attainment level through IA for Rubrics for external assessment test
CX
60% Stud > 55% MARKS: ATT 3
3. Final CO attainment w.r.t PO and PSO
ALUEX – Attainment level through UE for
50% Stud > 55% MARKS: ATT 2
CX
40% Stud > 55% MARKS: ATT 1
CO-PO and CO-PSO attainment
Final CO else ATT 0
attainment
CO- CO- CO- CO- CO- CO- CO- CO- CO- CO- CO- CO- CO- CO- CO-
value
PO1 PO2 PO3 PO4 PO5 PO6 PO7 PO8 PO9 PO10 PO11 PO12 PSO1 PSO2 PSO3

3 3 2 - 2 - - - 2 2 - 1 3 1

Course Instructor Signature/s