VLSI SRAM READ, WRITE OPERATION

AND SENSE AMPLIFIER STUDY

Under The Supervision of

Prof. Krishanu Datta
Department of Electronics and
Communication
Heritage Institute of Technology
Presented By:

• ABRARUL HAQUE (125243)

• DEBASMITA SIKDER (125222)

• JAYEESHA CHAKRABORTY (125241)

• SOUMYAJIT LANGAL (125239

 LITERATURE SURVEY

• In the initial phase of our project we had gone through several articles from
the web resources.

• For better understanding we have gone through “CMOS VLSI Design

A Circuits and Systems Perspective” by Weste Harris Banerjee.

• And after all we are highly grateful to our mentor

Prof. Krishanu Datta for the detailed and complete understanding of our
project.
 PROJECT OVERVIEW
• Focus to design : 32 KB SRAM memory array

• Memory Size : 512*512 (512 rows & 512 columns)

• Tool used : Cadence Virtuoso

• Technology used : Cadence gpdk45nm

• Supply Voltage applied : 1.1V

• Comparative Study : a) Differential Sense Amplifier

VS.
b) Latch Based Sense Amplifier

• Key Parameters to analyze performance :

a) Access time
b) Speed
c) Power consumption
6 TRANSISTOR SRAM CELL
SRAM MEMORY ARCHITECTURE
ROW DECODER AND COLUMN DECODER
 CRITICAL PATH MODELLING

Schematics to be designed on the critical path :

 Precharge circuit
 RC model for bitline and bitline_bar
 Column multiplexer for write operation For write operation
 Write enable circuit
 Column multiplexer for read operation
For read operation
 Sense Amplifier
PRECHARGE CIRCUIT
 RC MODELLING OF BIT LINES
PROBLEM
How to model 512 bit line
segments on a single
column ??

SOLUTION 1 SOLUTION 2
Modeling for each of 512 bit line Grouping 512 bit line segments
segments to an equivalent one

Equivalent bit line

OPTIMUM SOLUTION represented using Pi
Grouping 64 such bit line model and source to
segment to form a segment and drain capacitance of
8 such segments NMOS
 SPECIFICATIONS GIVEN

Parameter Value
Channel length(L) of Memory 45nm
cell MOS
Channel width(W) of Memory 120nm
cell MOS
Area Formula L=√A/12

Resistance for mid-level wire 1.01 Ω/ µm for 50nm

Capacitance for mid-level wire 0.294 fF/ µm for 50nm

 CALCULATION FOR MODELING
Sl. Name of the parameter Specification
No.
1. Cell Area (A) A=X2=144*L2 =144* 45nm2

2. Length of each side of the cell (X=√A) X=0.54 µm

3. Using 20% guard band(X´=1.2*X) X´=0.648 µm

4. Bitline length per segment (grouped by 64 cells) 64*0.648 µm = 41.472 µm

5. Resistance of Bitline per segment (grouped by 64 cells) 41.472*1.01 Ω=42.3 Ω

6. Capacitance of Bitline per segment: 41.472*0.294 fF=12.1927 fF

7. Source to drain capacitance of pass transistor w=120n*64=7.68u, l=45n

RC MODELLING

8 such
segments
COLUMN MULTIPLEXER FOR WRITE

Input/Output
Buffer
WRITE ENABLE CIRCUIT
wrt =1 to
enable AND
gate
 WRITE STABILITY
For successful write operation PMOS PM5 must be weaker than the access transistor NM8.

So size of PM5 ≤ size of NM8

COLUMN MULTIPLEXER FOR READ
 READ STABILITY
To read successfully from the cell the driver NM5 must be stronger than the access transistor NM7.

So size of NM4 ≥ size of NM7

 SENSE AMPLIFIER

SRAM without Sense

Amp

SRAM with Sense Amp

 TYPES OF SENSE AMPLIFIER

SENSE
AMPLIFIER

DIFFERENTIAL LATCHED
DIFFERENTIAL SENSE AMPLIFIER

rout
rout_b

bit bit_b

senb
Current source
LATCH BASED SENSE AMPLIFIER
CRITICAL PATH SCHEMATIC
 SIMULATION & RESULTS

• The constraints are as follows

a) Timing of control signals
b) Sizing of NMOS & PMOS in critical path

• Results include 2 measurements in case of both the sense amplifiers during read operation.
a) Delay (the time lag between the wordline activation and
the Output from sense amplifier)
b)Power (during read operation the amount of power that is
consumed by the sense amplifier)
 TIMING DIAGRAM
Parameter Logic State

Initialize Write Read

Precharge (pre) Active Low

Wordline (wl) Active High

Multiplexer enable for For Latched Sense Amplifier
write (colselw) Active High
Write circuit enable
(wrenb) Active High
Multiplexer enable for
read (colselr) Active Low
Initialize Write Read
Sense Amplifier enable
(senb) Active High

For Differential Sense Amplifier

 SIZING

Col. Mux. Diff. Sense

Pi circuit
Write Amp
 READ SIMULATION
For Latch Based Sense Amplifier

Precharge+Mem
cell+pi model

bit_b

bit

rout

Sense Amplifier
FOR DIFFERENTIAL SENSE AMPLIFIER

Precharge+Mem
cell+pi model

bit_b

bit

r_out

Sense Amplifier
 POWER AND DELAY MEASUREMENT
FOR READ
TYPE OF Average POWER DELAY WIDTH
AMPLIFIER Current (µWatt) (pSec) (µm)
(µA)

0.8564 0.94 120.2 0.84

Latched Sense
Amplifier

12.82 14.1 211.0 7.2

Differential
Sense Amplifier
 CONCLUSION
Latched base consume 14X less power.

Latched based has less READ delay.

Latched based has less size.

LATCHED VS. DIFFERENTIAL

LATCHED BASE IS
THE BEST