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ASML Enabling Semiconductor Innovation
ASML Enabling Semiconductor Innovation
ASML Enabling Semiconductor Innovation
These statements are not historical facts, but rather are based on current expectations, estimates, assumptions and projections about the business and our future financial
results and readers should not place undue reliance on them. Forward-looking statements do not guarantee future performance and involve risks and uncertainties. These
risks and uncertainties include, without limitation, economic conditions, product demand and semiconductor equipment industry capacity, worldwide demand and
manufacturing capacity utilization for semiconductors, including the impact of general economic conditions on consumer confidence and demand for our customers'
products, competitive products and pricing, the impact of any manufacturing efficiencies and capacity constraints, performance of our systems, the continuing success of
technology advances and the related pace of new product development and customer acceptance of new products including EUV, the number and timing of EUV systems
expected to be shipped and recognized in revenue, delays in EUV systems production and development and volume production by customers, including meeting
development requirements for volume production, demand for EUV systems being sufficient to result in utilization of EUV facilities in which ASML has made significant
investments, our ability to enforce patents and protect intellectual property rights, the outcome of intellectual property litigation, availability of raw materials, critical
manufacturing equipment and qualified employees, trade environment, changes in exchange rates, changes in tax rates, available cash and liquidity, our ability to refinance
our indebtedness, distributable reserves for dividend payments and share repurchases, results of the new share repurchase plan and other risks indicated in the risk factors
included in ASML's Annual Report on Form 20-F and other filings with the US Securities and Exchange Commission. These forward-looking statements are made only as of
the date of this document. We do not undertake to update or revise the forward-looking statements, whether as a result of new information, future events or otherwise.
Public
Semiconductor Scaling has changed how we…
Slide 3
Public
Insatiable need to transfer, store and analyse data
drives a continuous and growing demand for semiconductors Slide 4
Consumer
Electronics Smartphones
PC, laptop,
tablets
Factory
Automation
Autonomous driving
Public
Scaling/Shrinking Supports Moore’s Law
Moore’s Law is underpinning a business model Slide 5
IC performance
1 improvement at
similar cost
Takeaways
Part of the profits are
reinvested in R&D,
equipment >$250+ billion of annual
operating profit is riding on
4 2
the industry’s ability to
Improved electronic keep this cycle going
devices and new
applications
>$250+ billion of
operating profit
per year
Consumers and businesses 3
upgrade or adopt new products
Public
ASML operates in a highly profitable value chain
with strong incentives to compete and drive innovation Slide 6
ASML
ASML Applied Materials LAM Research KLA-Tencor TEL
Peers
2 2 1 1 1 Semi Equipment
Semi
Semi Manufacturing
Non-Semi
NVIDIA
13 12 25 6 5 2 3 11 Semi Design
TE Connect
Canon
Murata
Total EBIT, B$
60 2 Hardware
13 5 8 2 2 4 ~290
~275 ~280
~250
Cognizant
NetEase
Yahoo
Baidu
eBay
ADP
®
2013 14 15 2016
/ Alphabet
Revenue growth is coming from those segments where roadmap Lately we’ve seen the following trends in
innovation continues: advanced logic, DRAM and NAND (non-
volatile memory) semiconductor markets:
WW Semiconductor revenue [B$] • Strong transition to 3D-NAND to
450 continue enabling large capacities at
lower cost
WW semiconductor Revenue [B$]
400 CAGR
3D NAND
5%
• Slowing DRAM roadmap leading to
350
2D NAND DRAM CAGR
lower bit growth resulting in price
300 14% increases, triggering capacity
250
investments
Logic ≤20 nm
Relative Semiconductor
content in automotive [%COG]
100
90
80
70
60
50
40
30
20
10
0
1991 2015 2020 2030
Source: Berthold Hellenhtal, Audi, “Cross industry collaboration networks accelerate innovations”, ISS Europe, Munich, March 2017 Public
Disruptive trends also drive litho demand
Growth drivers: 2017 to 2020+ Slide 9
Storage Class Memory Growth and China Greenfield Emerging connected devices
CHINA
NAND
IoT
Data volume
& complexity
Sensors &
Devices
Text
IoT devices shipments, B units
Enterprise
Chinese government +65% p.a.
2010 2020 supports massive 0.4
0.3
Source: John Kelly III, IBM, December 2015 investment into domestic 0.2
0.2
semi industry 0
0.1
2015 16 17 18 19 2020
Public
Scaling will continue towards 1 billion transistors per mm2
We are ready to support the Semi industry’s ambition through the extension Slide 10
of Moore’s Law
High-NA
Transistor density
EUV
Millions per mm2
EUV
(+ pattern fidelity control)
Multi-patterning
(+ source-mask optimization, control loops)
Immersion
(+ optical proximity correction)
Public
EUV – A New Technology in Lithography Slide 11
~4 m
~3 m ~8 m
Public
What is EUV? A litho technology that delivers 3x -> 5x
Resolution Enhancement Slide 12
It does not
It works
work
We have it
☺
We do not
have it ??
Public
How customers approach new technology insertions
Slide 14
• Visionary/champion
• R&D enthusiasm EUV Case
• First results Done
Public
Technology transitions: decisions based on early results
“You have to move to where the puck will be, not where it is” (Wayne Gretzky) Slide 15
Decision point
Desired performance
at the time of volume
ramp
Performance
Increasing complexity
introduces additional
risk - lengthening
leadtimes
Time
Public
General rule of New Technology adoption
Slide 16
Early adoption is
risky
Late adoption is
expensive
Public
EUV “rewards” at 7nm are clear: simpler process,
shorter cycle time enabling faster yield ramp and time to Public
Slide 17
Jan 2018
market
Typical # Litho Passes Modelled 7nm Cycle Time, weeks
90 0 1 2 3 4 5 6 7 8 9 10 11 12 13
85
-13% ArFi
80 -21% only
-19%
75
EUV
70 Low
65 -33%
60 EUV
High Dr. Gary Patton, Global Foundries
0 SEMI ISS 2017
14/16nm 10nm 7nm
Public
EUV introduction delivers compelling benefits in layout
Public
Esin Terzioglu, Qualcomm, International Symposium on EUV, October, 2014 Jeffrey Shearer et al, IBM, AVS, November 2014
Lithography
50 Track
Deposition
40 Clean
34 Hard mask
30 27
LE3 = 3x Litho-Etch, “Triple patterning”
20
LE4 = 4x Litho-Etch, “Quad patterning”
10
10 SAQP = Spacer Assisted Quad Patterning
Cut = Separate Litho-Etch step
0
LE3 LE4 SAQP Single
+ 3 cuts exposure Public
EUV enables continued Litho cost reduction
PAS 5500/60 Slide 20
PAS 2500/10
1
Res. 450nm XT:1400
Res. 900nm, 200mm 48wph
150mm 66wph
Relative Cost per Pixel
AT:850
Res. 13nm
300mm 125wph
0.01 NXT:1950i
Res. 110nm
300mm 102wph
Res 38nm,
300mm 190wph
0.001
1984 1987 1990 1993 1996 1999 2002 2005 2008 2011 2014 2017 TBD
Public
Slide 21
Public
EUV industrialisation: from technology demonstration to
HVM System 2006 2017
Slide 22
Resolution : 40 nm 3x 13 nm
Overlay : 15 nm 10x 1.5 nm
Throughput : 0.05 WPH 2,500x 125 WPH
Public
Significant progress in EUV industrialisation Slide 23
EUV Source & Throughput EUV Availability Cumulative EUV wafer exposures
Proven Power1 & Wafers/Hour2 Uptime % NXE:3xxx, Wafers
100% >2M
Source Power
Throughput, W/Hr ✓ 300W
250W3
1.1M
✓ 155W/Hr
125 W/Hr 0.6M
Uptime 0.3M
Planned upgrades
0%
2014 2015 2016 2017 2020 2016 2017 2018 2011 2012 2013 2014 2015 2016 2017
Target
1 Demonstrated on test rig, 2 Demonstrated at ASML or Customer, 3 Enables 145W/Hr on NXE:3400B Public
Evolution of EUV Infrastructure readiness
Slide 24
Pellicle
EUV Blank
Quality
Blank multi-layer
deposition tool
EUV Resist QC
Actinic Patterned
Mask Inspection
Source: Britt Turkot, Intel, International Workshop on EUV Lithography, California, June 2017.
Public
Industry shrink roadmap and EUV insertion plans
Slide 25
EUV in Production
HVM 2014 2015 2016 2017 2018 2019 2020 2021 2022
Logic
DRAM
Research1
Roadmap2
3D NAND
x24 x32 x48 x64 >x96 >x128 >x192 >x200 x number of layers
Installed Base
Planned
Shipments 30+
22 22
Public
Slide 28
What’s next?
Public
Customer roadmaps extend 10 years
Slide 29
1000
1 nm
2 nm
Transitor Density MTr / mm2
3 nm
100 5 nm
7 nm
10 nm
45/40 nm
1
2007 2008 2009 2010 2011 2012 2013 2014 2015 2016 2017 2018 2019 2020 2021 2022 2023 2024 2025 2026 2027
HVM Wafer Start Date
Public
High NA extends EUV with a larger resolution step than
immersion did for ArF Slide 31
1,000
Wavelength, nm
436, g-line
365, i-line
NXE:3400
248, KrF
193, ArF
45%
100 XT:1400
= k1 x Wavelength / NA
Resolution, nm
1.000
Res. 450nm XT:1400
Res. 900nm, 200mm 48wph
150mm 66wph
Relative Cost per Pixel
Res. 13nm
0.010 300mm 125wph
NXT:1950i
Res. 110nm Res. <8nm
300mm 102wph 300mm 185wph
1984 1987 1990 1993 1996 1999 2002 2005 2008 2011 2014 2017 2020 TBD
2023
Public
EUV shrink + Holistic Litho (addressing k1) keeps Moore’s
Law affordable Slide 32
Exposure with
high order
optimisation
Optical
Computational
& e-beam
Lithography
Ensure measurement captures a Metrology
maximum of relevant information
Public
Our innovation pipeline will enable advanced imaging
and imaging process control the next 10 years and Slide 33
beyond
Public
EUV Summary
Slide 34
Public
Summary - Our customers and their environment
Slide 36
Public
Public