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Lab 1
Lab 1
二、 Verilog Code
主程式
`timescale 1ns / 1ps
module FA_FS(d,led,a,b);
input [3:0]a,b;
output [3:0]d;
output led;
wire [3:0]s;
wire c0,c1,c2,c3;
FA fa1(s[0],c0,a[0],~b[0],c3);
FA fa2(s[1],c1,a[1],~b[1],c0);
FA fa3(s[2],c2,a[2],~b[2],c1);
FA fa4(s[3],c3,a[3],~b[3],c2);
assign d[0]=s[0]^(~c3);
assign d[1]=s[1]^(~c3);
assign d[2]=s[2]^(~c3);
assign d[3]=s[3]^(~c3);
assign led=~c3;
endmodule
module FA(s,co,a,b,cin);
input a,b,cin;
output s,co;
assign s=a^b^cin;
assign co=(a&b)|(cin&(a^b));
endmodule
測試程式
`timescale 1ns / 1ps
module FA_FS_test;
// Inputs
reg [3:0] a;
reg [3:0] b;
// Outputs
wire [3:0] d;
wire led;
initial begin
#10 a=0;b=15;
#10 a=1;b=14;
#10 a=2;b=6;
#10 a=3;b=5;
#10 a=4;b=4;
#10 a=5;b=3;
#10 a=6;b=2;
#10 a=14;b=1;
#10 a=15;b=0;
#10 $finish;
end
endmodule
三、 RTL View
四、 TestBench Setting & Waveform Result
Stimulus_tb.v
moudule
…..
……
endmodule
五、 板子照片(包含敘述)