MACD HOMEWORK 3

vdd

M5 M3

M2

VIN VB

M1
VOUT

M6 M4

Figure1. The schematic of the circuit that is analyzed

During the analysis below, simulations will be done using LEVEL 1 MOSFET PSpice
parameters. Also, for NMOS KP=135u, VTO=0.7, LAMBDA=0.05 and for PMOS KP=40u,
VTO=-0.8V, LAMBDA=0.1. Transistor sizes found in the hand calculations are also used.

Applying the values determined in the solution of the circuit, first step is to analyze the
DC bias points. Using a sine wave input with a frequency of 10khz (which is sensed to be a
proper value for medium frequency for the circuit) following values determined:

VD1=1.502V, ID1=21.38uA, ID2=20.47uA. Also PDC=185.5uW. Schematics related to

these results can be seen in Figure2, 3 and 4.

VD D V IN
VD D 3 .0 0 0 V 8 5 2 .0 m V
3 .0 0 0 V M5 V1
VD D M 3 V O F F = 0 .8 5 2
3Vdc VAM PL = 1m
2 .0 0 9 V F R EQ = 10k
0V
M b re a k p M b re a k P
0V
0
0 1 .5 0 2 V
M 2
VB I1
5 6 7 .0 m V 20uAdc M 1 VB
VB V IN 5 6 7 .0 m V
0 .5 6 7 V d c 8 5 2 .0 m V
M b re a k n M b re a k P
0V
0V M 6 0 1 .3 8 4 V
0 M4

8 9 4 .5 m V
M b re a k N
0V M b re a k N 0V
0
0

Figure2. Bias voltages of the circuit

 VD D V IN
VD D
M5 0 AV 1
VD D 1 . 02 00 1. p0 A0 u A 4 1 .1 8M. 5 3u0 A8 p A V O F F = 0 .8 5 2
3Vdc VAM PL = 1m
0A 0A F R EQ = 10k

6 1 .8 5 u A - 2 0 . 0 M0 ub Ar e a k p - 4 1M. 8b 5r eu aA k P
0
0
M 2
VB 2 0I 1. 0 0 u A 1 2 82 0. 4. f4 A7 u A
20uAdc M 1 2 1 .3 8 u A VB
0 AV B V IN 0A
0 .5 6 7 V d c 0A
M b re a k n - 2 0 . 4 M7 ub Ar e a k P
- 2 1- .1 3. 85 u1 A2 p A
M 6 0
0 2 0 .0 0 u A M4 2 0 .4 7 u A

0A 0A
M b re a k N
- 9 0- 42 .0 5. f0 AM0 ub Ar e a k N - 2 0- .1 4. 73 u9 A4 p A
0
0

Figure3. Bias currents of the circuit

VD D V IN
VD D
M 5 V1
VD D 1 9 .8 2 u W M3 V O F F = 0 .8 5 2 0 W
3Vdc -1 8 5 .5 u W 6 2 .6 8 u W VAMPL = 1m
F R EQ = 10k

M b re a k p M b re a k P
0
0
M2
VB I1 2 .4 2 5 u W
2 0 u A d c 2 2 .3 0 u W M 1 VB
VB V IN 3 2 .1 1 u W
0 .5 6 7 V d c 0W
M b re a k n M b re a k P

M6 0
0 1 7 .8 9 u W M 4
2 8 .3 2 u W

M b re a k N
M b re a k N
0
0

Figure4. Power consumptions of the circuit

Overdrive voltages (which is defined as VGS-VT) of M5 and M6 can easily be

determined from Figure2. VodM5=(3-2.009)-|0.8|=0.191V and VodM6=894.5mV-
0.7V=0.1945V.

When it comes to the calculation of small signal voltage gain, it is determined using a
1mV amplitude sinusoidal input. Frequency is chosen 1khz. Thus, it is long enough to run the
simulation 5 periods which is equal to 5ms. The output is depicted in the Figure5.
 1.5V
(743.478u,1.4799)

1.4V

1.3V

1.2V

(1.2478m,1.1067)

1.1V
0s 0.5ms 1.0ms 1.5ms 2.0ms 2.5ms 3.0ms 3.5ms 4.0ms 4.5ms 5.0ms
V(VOUT)
Time

Figure5. Output voltage for 10khz, 2mVpp input

In order for us to calculate the small signal voltage gain, we must use the max and min
values signed in the graph. The peak to peak value of output is 1.4799-1.1087=0.3712V.
Since the input is 2mVpp, the gain is determined as Av=185.6.

The next step is the determination of the maximum output voltage swings. As in
Figure6 and 7, proper sinus waves are expected at maximum 1.3968V and at minimum
0.245V.
1.40V
(745.614u,1.3956)

1.39V

1.38V

1.37V (1.2500m,1.3674)

1.36V
0s 0.5ms 1.0ms 1.5ms 2.0ms 2.5ms 3.0ms 3.5ms 4.0ms 4.5ms 5.0ms
V(VOUT)
Time

Figure6. The output just before the top limit above

2.0V

1.5V

1.0V

0.5V
(247.826u,248.561m)

0V
0s 0.5ms 1.0ms 1.5ms 2.0ms 2.5ms 3.0ms 3.5ms 4.0ms 4.5ms 5.0ms
V(VOUT)
Time

Figure7. The output just before the bottom limit

 DISCUSSION

Examining the values we get from the simulation and comparing them with hand
calculations, we can see that the small signal gain is not 250 at all. Pspice gives a 185.6 gain
which is a quite different value. The first thing that comes to our mind is to check the input
DC level which is calculated as 0.852V. One can say that this biasing level fails to supply
such a gain. In further analyses, we’ve changed this value by 2mV only (0.854V) and see an
approximate gain of 270. This result shows that the input DC level is not adequate for such
gain. If we check all transistors to make sure that they are in saturation (Figure1), we see that
they are actually in the saturation and the lack of this gain is not about any of them entering
into the triode region. Another subject is the power consumption. The circuit consumes 5mW
more power according to PSpice, this means more current is driven. According to the
simulation results ID1 is not actually equal to ID2. This raises the question of the ideality of the
current mirror. The mismatch in the currents also makes VD1 vary from 1.5V exactly by 2mV.
The output voltage swing boundaries seem to be close enough to be considered equal in both
cases. Overdrive voltages are also in this manner. To sum up, the simulation and the hand
calculations match except for small signal gain. This is caused by the minor lack of DC input
level which is dictated in the solution beforehand. Finally, I’d like to explain why I did not
simulate the circuit in AC Sweep Analysis in order to obtain the frequency response of the
structure. Since there is no capacitance information given in the model (parasitic capacitances
like CGD) and no other series capacitances at the input and the output of the circuit we don’t
expect any poles. This means there are no such points on which gain falls 3db. This will cause
the frequency-gain graph look as if an infinite bandwidth amplifier with maximum and equal
gain at every frequency value. This wouldn’t make any sense at all.