International Conference on Innovative Mechanisms for Industry Applications

(ICIMIA 2017)

A Low Power Dynamic Logic with nMOS Based

Resistive Keeper Circuit
Riazul Islam1 , Kazi Fatima Sharif1 , Mahbubul Haque 1 , Satyendra N. Biswas 1* , Sunil R. Das2 , Mansour Assaf3 , Emil
M. Petriu2
1
Electrical and Electronic Engineering Dept., Ahsanullah Universit y of Science and Technology. Dhaka, Bangladesh
2
School of Electronic Engineering and Computer Science, University of Ottawa. Ottawa, Canada
3
Dept. of Engineering and Physics, University of South Pacific, Suva, Fiji
*
Corresponding author: sbiswas.eee@aust.edu / sbiswas@linuxmail.org

Abstract—Designing VLS I circuit using dynamic logic is one decreases the noise margin of Domino logic outputs [7]. To
of the most area efficient techniques. However, the performance solve these problems, we need to design a keeper architecture
of the dynamic logic is not so promising due to longe r time delay that gives better performance from conventional proposals.
and higher leakage power. This research proposes a new model
of dynamic logic by incorporating nMOS based resistive gate
circuit. The proposed circuit reduces the contention time delay
and the leakage power. Extensive simulation results using
LTS pice tools demonstrate the validity and superiority of the
proposed circuit.

Keywords—Domino logic; resistive gate; keeper circuit;

contention time;

I. INT RODUCT ION

High speed and low power logic circuits design [1-3]
remain to become more consideration of VLSI design. Power
saving has more importance than any kind. More power
efficient and comparatively faster dynamic (Domino) logic
circuits needs to have almost half the transistor count with
respect to traditional logic circuits. Basically, a Domino circuit
consist of a precharge (PMOS Device), a pull-down network
(PDN), PMOS keeper, and an NMOS footer device. For
control and operation of Domino logic circuit a clock signal is
used [4]. Dynamic logic circuits output has stored in the
parasitic capacitance which is situated just before the static
inverter [5]. Parasitic capacitance just stores the output voltage
and its forwarded to next stage which is output stage and
remaining in load capacitor [4] of Domino circuit. Dynamic Fig. 1. T raditional Domino logic
logic circuits require two phases, precharge phase and
II. PREVIOUS W ORKS
evaluation phase. When logic circuit clock is high is called
evaluation phase [5] and when low is called precharge phase. A Domino logic circuits is shown in Fig. 1. Precharge
However, the major disadvantages of dynamic node is low phase indicates the clock is low. In the phase, precharge
noise margin because of dynamic node is not always transistor is ON and the dynamic node is charged at VDD ,
connected to the VDD . The pMOS keeper has been used to driving output to the ground and turns ON the keeper device.
compensates the leakage current of the pull-down network. If In this time foot switch NMOS turns off and domino node is
any input is high, stored charge on the dynamic node should disconnected from being discharged. In the case of domino
be partially removed due to the capacitor in pull down logic, all inputs should be zero in order to eliminate the
network. However, the keeper circuit stays ON until the discharging path during the precharge mode. During
voltage of the output reaches to a minimum voltage. This time evaluation phase, foot switch turns on and provides a path for
interval between the pull-down network and keeper transistor discharging the dynamic node X to the ground and it depends
increases the time delay, power consumption [6]. It also on the input combination. However, when the keeper circuit is

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ON, domino node starts to discharged through PDN. The connected parallelly but the difference is that both are not ON
output voltage starts to decrease and reaches to a certain state at the same time. When one nMOS operates, other one
amount to turn the keeper transistor off. This contention remains in off state. Both are of same length and width. It
provides the time delay, more power consumption and low works like a resistor before the keeper gate. Traditional
noise margin [8]. This trade-off is becoming more demanding domino logic takes more time delay and low noise margin but
in sub-100 nm technologies; because of increasing extreme applying this resistive gate shows better time delay and high
leakage current, which indicates the dynamic gates need larger noise margin. The resistive gate input is coming from domino
keepers [9]. Several models have been proposed to identify node and it will change the value during precharge and
this problem of dynamic gates. A group of researchers evaluation phase. The complete structure of the nMOS based
attempts to decrease the amount of leakage current by resistive gate domino logic is shown in Fig. 3. where two
reengineering the pull down network [10]. Another group is pMOS M p and M k are used as precharge and keeper device.
involved to modify the keeper circuit [11-14]. Usually Two nMOS devices are connected in parallel.
redesign of keeper circuit has less overhead than redesigning
of pull down network. Hamed F.Dadgour et al. [8] presents a
new approach of keeper design by introducing a voltage
source and current source combined circuit that reduce the
contention between keeper and pull down network.
Krishnamurthy et al. [9] also proposed a new pull down
network to reduce the leakage current significantly across the
top transistors of PDN by applying a negative voltage when all
inputs are “0”. Li, Mazumder et al. [10] have proposed a
approach, a semiconductor device is used instead of PMOS
transistor that contains negative resistance characteristics and
this is not easily integral in traditional bulk CMOS process.
Alvandpour et al. [11] has divided the keeper circuits into two
phases during the evaluation phase, one part is always ON and
second part is ON after a certain time delay. Delay provides
the decrease of contention between the PMOS keeper and pull Fig. 2. Proposed nMOS based resistive gate
down network throughout switching operation. The keeper is
significantly weak during the precharge or evaluation phase
and it is the main disadvantage of this approach. Anis et al.
[12] have shown a keeper circuit where he used only one
PMOS transistor, which remains ON in the stage of evaluation
phase and turns ON where dynamic node remains high for the
rest of the time depending on input combination.
A new programmable keeper circuit is presented by Kim et
al. [13] its capability can be adjusted by a 3-bit enable digital
input. After using a sensor for parameter variation, 3-bit input
signal is applied according to appropriate strength for the
keeper. In this circuit, gate and junction capacitance of control
and keeper transistors are heavily loaded through dynamic
node, so overall performance decreases. Kursun, Friedman et
al. [14] proposed a circuit reduces contention between the
PDN and keeper network during the switching transition and
applying a body bias to keeper transistor.
In this paper, nMOS based resistive gate, a differential
waveform of the keeper dynamically controls the keeper gate-
source voltage of the PMOS keeper transistor. At the start of
the evaluation phase, lower gate source voltage reduces the
drive capability of keeper, while the gate source gradually
converts VDD to get better noise margin, low delay and power
consumption.
Fig. 3. Proposed nMOS based Domino logic
III. PROPOSE CIRCUIT
In the precharge phase, when clock is zero, dynamic node
In this work, nMOS based resistive gate is used, which
is in high state (1) and the output is 0. M1 is on and M2 is off
connects the keeper gate as shown in Fig. 2. Basically, this
as biased by 0. In the evaluation phase, clock is 1, dynamic
gate is made out of two nMOS transistors. These are
gate is discharged from PDN, output switches from 0 to 1

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state. In this time M2 operates as biased by high voltage from as well as with traditional domino logic circuits. Table. 1.
output. represents the comparative results of time delay and power
At the beginning of the evaluation phase, nMOS based consumption with recently proposed models . To evaluate the
resistive gate and 0 to 1 transition of the clock creates performance of proposed domino logic 32nm standard CMOS
differential waveforms at the keeper transistor gate as shown technology is used. In this table the proposed model
in fig. 4. So the keeper is weaker than the pull-down network. demonstrates the power saving and high performance.
Since the minimum voltage VGMIN is needed on keeper device. T able. 1. Comparison between mean delay, power consumption for proposed
keeper and existing works.
However, reducing or increasing the threshold voltage of
keeper device solves the driving degradation of keeper device.
Parame te rs Powe r (μW) Delay (ps)
This circuit will create a path for keeper gate to reach zero
voltage. N1 is added in the design where it operates as sub- Proposed model 7.0938 0.13801
threshold condition, and assist resistive gate to discharge the
T raditional 104.3 0.2
keeper gate completely (if input combination is “0”) and
develops the drive capability of precharge and keeper Ref [15] 11.06 98
transistor. That’s why noise margin and time delay will
Ref [16] 0.338 2
increase in domino logic. Fig. 5 depicts the wave shapes of
resistive gate feedback during precharge and evaluation phase. Ref [17] 7.10 99

Ref [8] 86.8 0.2

Ref [9] 174.2 3.1

Ref [11] 94.9 0.6

Ref [12] 90.1 0.9

Ref [13] 100.5 12.3

Ref [14] 98.2 1.1

Fig. 4. Waveshape of clock versus domino node X

Fig. 6. Comparison of calculated time delay at different threshold voltage for

various model.

Fig. 5. Waveshape of clock versus feedback resistive gate
IV. A NALYSIS AND SIMULAT ION RESULT S
Simulation experiments are carried out using LTSpice
simulation tool by employing PTM transistor model.
Experimental results are compared with several existing model
Fig. 6. Depicts the comparison of different types previous
model in terms of time delay better time delay performance of
proposed circuits. These data are taken at different threshold
(Vth 0-2 - Vth 0+2 ) voltage of transistor.

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Fig. 7. Comparison of power consumption versus threshold voltage for eight

input OR gates
As the power consumption depends on threshold voltage
of the transistors so power consumption at different threshold
voltage for eight (8) input OR gates is calculated and
compared as shown in fig. 7. It is clearly noticed that when
Fig. 9. Noise margin versus for four input and eight input OR gat es at
different threshold voltage.
T able. 2. Comparison of W/L ratio between proposed and previous works.
Different

Traditional
Proposed
Works
threshold voltage of transistor increases then the power

Ref [6]

Ref [8]

Ref [9]
consumption also increases. However, the maximum power
consumption is significantly less for the proposed model as
compared to others. W/L ratio 0.5 2.5 0.25 1.5 3

V. CONCLUSION:
A new model of dynamic logic circuit is proposed in the
present research. In order to make the contention time
minimum, a resistive circuit consist of two nMOS transistors
are used. Current through that resistive circuit is less as
compared to the tradition model and consequently the keeper
transistor becomes weaker at the beginning. Vigorous
simulation results by varying different parameters such as
threshold voltage, number of inputs and size of the keeper
circuit clearly demonstrates the competency and adaptability
of the proposed model.

Fig. 8. Comparison of normalized delay versus threshold voltage for eight
input and four input OR gate.
The proposed circuit is simulated at different combination
of inputs for OR gate. Fig. 8 shows the normalized delay with
8-input and 4-input OR gate. The proposed model generates
better normalized delay than the traditional domino logic. We
calculated the noise margin by varying the threshold voltage
for eight and four input OR gate and the results are shown in
fig.9. It is seen that the noise margin increases with the
increase of threshold voltage and also the number of inputs is
a contributing factor for that. Table. 2 shows that lower value
of W/L ratio is selected in the proposed model for the keeper
device. So, the keeper device remains weaker in order to
improve the driven capability.
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