Professional Documents
Culture Documents
A Comparative Study of Methodologies To Optimize P
A Comparative Study of Methodologies To Optimize P
A Comparative Study of Methodologies To Optimize P
net/publication/283040318
CITATIONS READS
0 96
2 authors, including:
Kavita Khare
Maulana Azad National Institute of Technology, Bhopal
92 PUBLICATIONS 204 CITATIONS
SEE PROFILE
Some of the authors of this publication are also working on these related projects:
All content following this page was uploaded by Kavita Khare on 01 August 2017.
1. INTRODUCTION
Nanometer technology scaling to the leading edge nodes
(28nm/14nm or below) demands higher accuracy and
performance with good productivity. Deep sub threshold
nanometer processes introduces multi-layer, closely-spaced,
thin and tall metal interconnects which results in large number
of interconnect resistances and capacitances (millions of new
parasitic effect in design), hence circuit performance
dominated by parasitic delays. In today’s era designers
strongly needs advanced technique which reduce the gap
between the parasitic values estimated during implementation
and results of post-layout extraction. Parasitic needs to
extracted and simulated with sufficient accuracy to enable
design team to, at least, find and fix violations like setup, hold
and glitches confidently. The sensitivity of the parasitic to the Fig 1: Planer CMOS Schematic Showing Various Parasitic
process variation also need to understood well enough to Resistances and Capacitances [8]
avoid the yield loss. As the number of transistors increases, the number of nets
IC designer need an advanced parasitic extraction solution to also increases proportionally. This means that extraction tool
boost simulation performance and designer productivity. has to extract, manage and pass much amount of data to the
simulator. In the earlier nodes only capacitors were extracted
The rest of this paper is organized as follows. The challenges but now a day’s resistance plays an important role. Since
facing by the designer during parasitic extraction and post- resistance is a function of temperature, extraction process
layout simulation is explained in section 2. The basic post- needs to be run multiple times for multiple temperatures. With
layout design flow is discussed in section 3. Section 4 covers advanced technology number of process corners is also
the advanced extraction techniques and section 5 covers the increased. Designers are facing problems due to large
advanced simulation techniques. Finally paper concluded in extraction run time and unmanageable volume of data
section 6 followed by acknowledgment and references. (billions of transistors and millions of parasitic).
27
International Journal of Computer Applications (0975 – 8887)
Volume 124 – No.8, August 2015
2.2 Post-Layout Simulation Related and complex use of traditional simulators are very tedious job.
Fast-spice simulators use matrix portioning, model
Challenges simplification, RC reduction techniques to accelerate
Simulation challenges creates larger bottleneck in post-layout simulation and expand capacity beyond that of traditional
verification as compared to parasitic extraction. Simulation spice simulators. The need for fast-spice simulator is arises
run time and capacity are directly related to the parasitic because the design sizes exceeding the capacity limit of
netlist size and the number of parasitic elements or nodes in traditional spice simulators and need to simulate nanometer
the generated netlist. Parasitic extraction of full-chip with all effects using large post-layout parasitic RCs. In this paper we
the nets results in huge netlist size and can lead to present the useful techniques provided by fast-spice
unnecessary simulation inefficiency with same accuracy (not simulators to address the outlined challenges [2].
improved accuracy). As designers moved from “C” to “RC”
post-layout verification, the extracted netlist to be managed To analyze the impact of parasitic on the simulator run time,
and simulated has blown up and it directly cost to simulation we have run the simulation using fast spice simulator on a
run time. Another major challenge is a need of varying memory design and seen that if the pre-layout simulation
simulation process corners (voltage, temperature e.t.c.), due to takes X time then post – layout simulation takes 2.5X for
the designer’s specific application need. Designers need to capacitive netlist and 4.5X for “RC” netlist.
rerun simulation process multiple time for multiple process
corners which is heavy loss in simulation run time and disk 4. ADVANCED EXTRACTION AND
usage. But the comprehensive post-layout simulation are SIMULATIO N TECHNIQUES
required to capture the nanometer effect in order to reduce the To address all the outlined challenges many techniques have
risk that a design passes verification before tape out, but fails been developed. In this paper we will discuss all the advanced
after fabrication. techniques for parasitic extraction and post-layout simulation.
3. BASIC PRE AND POST LAYOUT 4.1 Hierarchical Extraction and
DESIGN FLOW Simulation
Figure 2 sowing the typical pre-layout and post-layout design This methodology offers IC designers a great option to
flow. Once the schematic and layout of design is completed improve design’s post-layout verification and this techniques
designers apply various checks like layout vs schematic check supported by many extraction tools (for example starRC from
and design rule check. Then parasitic extraction should be Synopsys, Calibre from Mentor graphics). Since flat
perform to analyze actual circuit performance. The reason extraction allows all coupling effects to be taken into
behind the parasitic extraction is to create an accurate analog consideration, the runtime can be too long and file size of
model of the circuit, so that detailed simulation can give extracted netlist should be very large. Flat parasitic extraction
actual circuit responses and the pre – layout simulation result all though a most accurate method but it is very time
does not contain the effect of parasitic. consuming for big design circuits. Hierarchical extraction can
be use to tackle these challenges. In hierarchical extraction,
each level of hierarchy is extracted separately and then each
level of parasitic is stitched together. The upper levels of
hierarchy can see coupling capacitance effects into lower
levels of hierarchy, but then the coupling is grounded. This is
known as a “grey box flow”[2].
28
International Journal of Computer Applications (0975 – 8887)
Volume 124 – No.8, August 2015
29
International Journal of Computer Applications (0975 – 8887)
Volume 124 – No.8, August 2015
[3] Karen Chow, “The Challenges and Impact of Parasitic [8] Scott E. Thompson and Srivatsan Parthasarathy,
Extraction at 65 nm”, Proceedings of the 7th “Moore’s law: the future of Si microelectronics”,
International Symposium on Quality Electronic Design Materials today volume 9, 2006.
(ISQED’06).
[9] William H. Kao, Chi- Yuan Lo, Mark Basel and
[4] Weibing Gong, Wenjian Yu, Yongqiang Lu, Qiming Raminderpal Singh, “Parasitic Extraction: Current State
Tang, Qiang Zhou, Yici Cai, “A Parasitic Extraction of the Art and Future Trends”, PROCEEDINGS OF THE
Method of VLSI Interconnects for Pre-Route Timing IEEE, VOL. 89, NO. 5, MAY 2001.
Analysis”, IEEE2010.
[10] Paul-Franzon and Mark S. Basel, “ Panel: Parasitic
[5] Michał Rewienski, “A Perspective on Fast-SPICE extraction accuracy; How much is enough?”,
simulation Technology” Springer Science+Business
Media B.V. 2011. [11] Saisanthosh Balakrishnan and Charlie C.P. Chen,
“SeaPEEC: A Comprehensive Hierarchical Parasitic
[6] Application Note on “Parasitic Back Annotation for Post Extraction Tool Based on Partial Element Equivalent
Layout Simulation” Circuits”.
[7] Omar Shah and Shekhar Kapoor, “Extraction Techniques [12] “Parasitic Extraction of FinFET-based Memory Cells “,
for High-performance, High-capacity Simulation”, http://www.silvaco.com/content/appNotes/iccad/2-
Synopsys white paper 2009 005_Guardian.pdf
[13] Datasheet of “StarRC; Parasitic Extraction”, Synopsys
IJCATM : www.ijcaonline.org 30