UNIT III:

Behavioral Modeling

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 Unit Outline
● Verilog behavioral constructs
● Combinational circuits in Verilog

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 Behavioral Modeling
● Structural modeling using
gate-level primitives is very
tedious especially in large
designs.

● Behavioral modeling allows

the use of programming
language-like constructs to
ease the task of describing
circuits.

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 Assign Construct
● The assign construct is a straightforward way of assigning
a COMBINATIONAL logic function to a wire
● The use of operators is allowed in an assign statement.

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 Commonly used Verilog
Operators
Bitwise AND & Logical AND &&
Bitwise OR | Logical OR ||
Bitwise NOT ~ Logical NOT !
Bitwise XOR ^
Logical Equality == Logical Inequality !=
Less Than < Greater Than >
Less than or Greater than or
<= >=
equal equal
Addition + Subtraction -

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Example: Full Adder

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 Exercise:
● Modify the following modules and use the assign construct
instead of the gate primitives.
– HalfAdder module
– 4-bit Majority function module

● Write a Verilog description of a 3-bit parity generator

with enable input.

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 Number Representation
● Constants are represented as follows:
[width]' [base] [constant]

● Width is the number of bits in which the number is going to

be represented (in bits)
● Examples:
– Binary: 2'b01, 4'b1010, 16'b1100001010001101
– Decimal: 2'd1, 4'd10,  16'd49805
– Hexadecimal: 2'h1, 4'hA, 16'hC28D

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 Conditional Assignment
● Assigned value is dependent on evaluation of a conditional
statement.
● Can be used in conjunction with the assign statement, but
is not limited to it
assign output_sig=(cond_statement)?val_true:val_false;

A 0
assign X = (S==0) ? A : B;
X assign X = (S==1) ? B : A;
B 1 assign X = (S) ? B : A;

S
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 Conditional Assignment
● Conditional assignments can also be “nested”
● Less lines of code but can be harder to read

A
0
B 0 X
1
C 1
S
R

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 Concatenation
● Multiple signals can be concatenated to form a larger signal
using the concatenation operator.
● Useful for transforming individual signals into buses.
assign big_sig = {sig1, sig2, …};

q x n
r b[2:0] sub2 w
s

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 Replication
● Used to replicate a signal a finite number of times
● Useful for padding bits or for sign-extension
assign big_sig = { num_rep {sig_to_rep}};
is equivalent to
assign big_sig = {sig, sig, sig, …, sig};
where sig is concatenated to itself num_rep times
● Example: 2's complement sign-extension from 8-bit to
32-bit

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 Exercise
● Create a simple 1-bit ALU S[1] S[0] MODE
that has the following
0 0 Addition
operations:
0 1 Subtraction
1 0 Bitwise AND
1 1 Bitwise OR

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 Always Block
● The always construct can be used to describe both
COMBINATIONAL and SEQUENTIAL circuits.

● Can also be used as a construct for simulations.

● Consists of a sensitivity list which is a list of signals that is

monitored by the simulator for changes.

● Whenever a signal in the sensitivity list changes its value,

the statements inside the always block are evaluated.

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 Always Block
● All signals assigned inside the always block must be
declared as reg.
always @ (sensitivity_list)
        begin
          …
        end

● Note: Use of begin-end are required when contents are

more than one statement

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 Sensitivity List
● In describing combinational circuits, make sure that the
sensitivity list contains all signals which are “read”

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 Sensitivity List
● Alternatively, * can be used in the sensitivity list to ensure
that circuit described will be combinational (sensitive to all
inputs)

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 Blocking vs. Non-Blocking
Assignment
● Blocking assignment (=)
– Evaluated and assigned in a single step
– Execution flow within the procedure is blocked until the
assignment is completed
– Evaluations of concurrent statemetns in the same time step
are blocked until the assignment is completed

Execution:
1. x is evaluated
2. y is evaluated using value
from (1)

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 Blocking vs. Non-Blocking
Assignment
● Non-blocking assignment (<=)
– Executes all statements in the always block concurrently
– Evaluated and assigned in two steps:
● The right-hand side is evaluated immediately.
● The assignment to the left-hand side is postponed until
other evaluations in the current time step are completed

Execution:
1. (a & b) is evaluated
2. (x | c) is evaluated
3. (1) is assigned to x, (2) is
assigned to y (concurrent)

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 Blocking vs. Non-Blocking
Assignment
● Blocking assignments (=) should be used in
combinational circuits.
– The previous examples should have been in blocking
assingments since they are combinational circuits.

● Non-blocking assignments (<=) should be used in

sequential circuits.

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 If-else and Case
● Allows conditional assignments
● Can only be used inside an always or initial block
if (cond_statement) case (var)
begin val_1 : body_1
body_true val_2 : 
end begin
else body_2
begin End
body_false val_3 : body_3
end endcase

● Note: Use of begin-end are required when contents are

more than one statement

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 Example: Multiplexer

A 0

X
1
B

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 Incorporating Logic

a 0
1 f
2
b 3

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 Nesting If-else
● Nesting if-else statements implies PRIORITY

VS.

A
B 0
0 C 1
B X
0 X A 2
A 3
1
C 1
S {S,R}
R
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 Exercise
● Use if/else statements to ● Use case statements to
create a 3x8 Decoder. create a 4-to-2 line priority
encoder.

● Modify the simple 1-bit ALU to utilize an always block.

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 References
● Introduction to HDL, USC-PIIC Workshop Manual
● M. Morris Mano and Michael D. Ciletti, “Digital Design with
an Introduction to the Verilog HDL”, 5th edition.
● Understanding Verilog Blocking and Non-blocking
Assignments, Stuart Sutherland.
● www.asic-world.com

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