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VHDL Class 2 Architecture
VHDL Class 2 Architecture
Example of an architecture:
Syntax of ARCHITECTURE
ENTITY my_or IS
PORT(
x, y: IN std_logic;
z: OUT std_logic );
END my_or;
library ieee;
use ieee.std_logic_1164.all;
ENTITY my_block IS
PORT( a, b,c,d : IN std_logic;
out1,out2 : OUT std_logic );
END my_block;
Let us assume that a and b are bit inputs and c and d are Boolean inputs.
library ieee;
use ieee.std_logic_1164.all;
ENTITY my_block IS
PORT( a, b : IN bit ;
c, d : IN Boolean ;
out1 : OUT bit ;
out2 : OUT boolean );
END my_block;