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Ijarece Vol 5 Issue 1 110 115 PDF
Ijarece Vol 5 Issue 1 110 115 PDF
110
All Rights Reserved © 2016 IJARECE
ISSN: 2278 – 909X
International Journal of Advanced Research in Electronics and Communication Engineering (IJARECE)
Volume 5, Issue 1, January 2016
Voltage across the CapacitorVC (t) = 1/C.I(t).t ECRL has two cross coupled PMOS and two NMOS
The average current from 0 to t, I(t) = C. VC(t)/t tree structure. An AC power supplyis used to recover
the charge & reuse the supplied energy.[4] Both Out
Total energy dissipation in resistor R from 0 to t= T and 𝑂𝑢𝑡is generated so that power clock generator
is given by always drive a load capacitance which is independent
of the input signal. The logic function which is to be
𝑇 2 2𝑅𝐶 1 implemented is realized using NMOS transistors, in
E= Ediss = R 0
𝐼 dt = ( CV2) both true and complementary forms.
𝑇 2
where,
E ― Energy dissipated during charging,
C ―Load capacitance,
R ― Resistance of the MOS switch turned on,
V ― Final value of the voltage at the load,
T ― Charging time.
111
All Rights Reserved © 2016 IJARECE
ISSN: 2278 – 909X
International Journal of Advanced Research in Electronics and Communication Engineering (IJARECE)
Volume 5, Issue 1, January 2016
3.3 DIODE FREE ADIABATIC LOGIC In this paper, three adiabatic techniques (ECRL,
PFAL & DFAL) & conventional CMOS logic were
(DFAL) used to design 2:1 Multiplexer. The schematic &
simulations of 2:1 Mux designed using the logic
In this logic, no diode is used in the charging or styles are shown in the figures.
discharging path. DFAL uses a two phase clocked
split-level sinusoidal power clock supply 𝑉PC and 4.1.Conventional CMOS 2:1 MUX
𝑉𝑃𝐶 to minimize the voltage difference between the
current-carrying electrodes and consequently reduce A multiplexer is a combinational circuit that selects
the power consumption. Split level clock one of the data inputs and transmits it to the output
charges/discharges the load capacitance slightly depending on the control signals. It implements the
slowly than the other adiabatic power clocks.[9] function F = A𝑆 + BS. When select(S) is Low, it
Since the efficiency of adiabatic logic circuits outputs the signal A & when select(S) is High, it
depends upon how slowly the load capacitance is outputs the signal B.
charged or discharged so power dissipation has been
minimized further.
112
All Rights Reserved © 2016 IJARECE
ISSN: 2278 – 909X
International Journal of Advanced Research in Electronics and Communication Engineering (IJARECE)
Volume 5, Issue 1, January 2016
113
All Rights Reserved © 2016 IJARECE
ISSN: 2278 – 909X
International Journal of Advanced Research in Electronics and Communication Engineering (IJARECE)
Volume 5, Issue 1, January 2016
5. SIMULATION RESULTS
6. CONCLUSION
A 2:1 Multiplexer has been implemented using
various adiabatic techniques and was compared with
the conventional CMOS logic. Table.1 shows the
average power dissipation of ECRL, PFAL, DFAL&
CMOS based 2:1 Mux at different frequencies. It
was observed that the power dissipation in DFAL,
ECRL & PFAL is very less as compared to CMOS
based design. These adiabatic techniques can be used
for low power applications over the wide range of
parameter variations. Tanner EDA v14 is used for
the simulation of the circuits in 90nm CMOS
Figure.10: Simulation waveform of 2:1 MUX using
technology at 1V supply voltage. A 2:1 Mux
ECRL
designed using adiabatic techniques can further be
114
All Rights Reserved © 2016 IJARECE
ISSN: 2278 – 909X
International Journal of Advanced Research in Electronics and Communication Engineering (IJARECE)
Volume 5, Issue 1, January 2016
used in applications such as Barrel Shifters, Memory principles”. IEEE Transactions on VLSI SystemVol.
designing & other low power applications. 2,Dec.1994,pp.398-407.
7. REFERENCES
[1] A.G.Dickinson and J.S.Denker, Adiabatic
Dynamic Logic, IEEE Journal of Solid-state Circuits,
Vol. 30 No.3.
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