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Pic16f1717 Datasheet PDF
Pic16f1717 Datasheet PDF
Description:
PIC16(L)F1717/8/9 microcontrollers combine Intelligent Analog integration with low cost and extreme low power (XLP)
to suit a variety of general purpose applications. These 28-pin and 40-pin devices deliver on-chip op amps, Core
Independent Peripherals (CLC, NCO and COG), Peripheral Pin Select and Zero-Cross Detect, providing for increased
design flexibility.
Core Features: Digital Peripherals:
• C Compiler Optimized RISC Architecture • Configurable Logic Cell (CLC):
• Only 49 Instructions - Integrated combinational and sequential logic
• Operating Speed: • Complementary Output Generator (COG):
- 0-32 MHz clock input - Rising/falling edge dead-band control/
- 125 ns minimum instruction cycle blanking
• Interrupt Capability • Numerically Controlled Oscillator (NCO):
• 16-Level Deep Hardware Stack - Generates true linear frequency control and
• Up to Four 8-Bit Timers increased frequency resolution
• One 16-Bit Timer - Input Clock: 0 Hz < FNCO < 32 MHz
• Power-on Reset (POR) - Resolution: FNCO/220
• Power-up Timer (PWRT) • Capture/Compare/PWM (CCP) module
• Low-Power Brown-out Reset (LPBOR) • PWM: Two 10-Bit Pulse-Width Modulators
• Programmable Watchdog Timer (WDT) up to • Serial Communications:
256s - SPI, I2C, RS-232, RS-485, LIN compatible
• Programmable Code Protection - Auto-Baud Detect, auto-wake-up on start
• Up to 35 I/O Pins and One Input Pin:
Memory:
- Individually programmable pull-ups
• Up to 16 Kwords Flash Program Memory
- Slew rate control
• Up to 2048 Bytes Data SRAM Memory
- Interrupt-on-Change with edge-select
• Direct, Indirect and Relative Addressing modes
• Peripheral Pin Select (PPS):
• High-Endurance Flash (HEF):
- Enables pin mapping of digital I/O
- 128B of nonvolatile data storage
- 100K Erase/Write cycles Intelligent Analog Peripherals:
• Operational Amplifiers:
Operating Characteristics:
- Two configurable rail-to-rail op amps
• Operating Voltage Range:
- Selectable internal and external channels
- 1.8V to 3.6V (PIC16LF1717/8/9)
- 2 MHz gain bandwidth product
- 2.3V to 5.5V (PIC16F1717/8/9)
• High-Speed Comparators:
• Temperature Range:
- Up to two comparators
- Industrial: -40°C to 85°C
- 50 ns response time
- Extended: -40°C to 125°C
- Rail-to-rail inputs
eXtreme Low-Power (XLP) Features: • 10-Bit Analog-to-Digital Converter (ADC):
• Sleep mode: 50 nA @ 1.8V, typical - Up to 28 external channels
• Watchdog Timer: 500 nA @ 1.8V, typical - Conversion available during Sleep
• Secondary Oscillator: 500 nA @ 32 kHz - Temperature indicator
• Operating Current: • Zero-Cross Detector (ZCD):
- 8 uA @ 32 kHz, 1.8V, typical - Detect when AC signal on pin crosses
- 32 uA/MHz @ 1.8V, typical ground
• 8-Bit Digital-to-Analog Converter (DAC):
- Output available externally
- Internal connections to comparators, op
amps, Fixed Voltage Reference (FVR) and
ADC
• Internal Voltage Reference module
MSSP (I2C/SPI)
Flash (words)
Comparators
High-Speed/
Data SRAM
5/8-bit DAC
Zero Cross
Debug(1)
EUSART
(8/16-bit)
Op Amp
(bytes)
(bytes)
Timers
I/Os(2)
PWM
COG
NCO
CCP
CLC
PPS
XLP
Device
Note: For other small form-factor package availability and marking information, please visit
http://www.microchip.com/packaging or contact your local sales office.
VPP/MCLR/RE3 1 28 RB7
RA0 2 27 RB6
RA1 3 26 RB5
RA2 4 25 RB4
RA3 5 24 RB3
RA4 6 23 RB2
PIC16(L)F1718
RA5 7 22 RB1
VSS 8 21 RB0
RA7 9 20 VDD
RA6 10 19 VSS
RC0 11 18 RC7
RC1 12 17 RC6
RC2 13 16 RC5
RC3 14 15 RC4
RB7
RB6
RB5
RB4
28
27
26
24
23
22
25
RA2 1 21 RB3
RA3 2 20 RB2
RA4 3 19 RB1
PIC16(L)F1718
RA5 4 18 RB0
VSS 5 17 VDD
RA7 6 16 VSS
RA6 7 15 RC7
10
12
13
14
11
8
9
RC0
RC1
RC2
RC3
RC4
RC5
RC6
PIC16(L)F1717/8/9
6PDIP,SOIC,
Comparator
QFN, UQFN
Zero Cross
Reference
EUSART
Interrupt
Op Amp
Timers
Pull-up
MSSP
SSOP
Basic
PWM
COG
NCO
CCP
ADC
DAC
(2)
CLC
I/O
C1IN0- (1)
RA0 2 27 AN0 CLCIN0 IOC Y
C2IN0-
C1IN1- (1)
RA1 3 28 AN1 OPA1OUT CLCIN1 IOC Y
C2IN1-
C1IN0+
RA2 4 1 AN2 V5()- DAC1OUT1 IOC Y
C2IN0+
RA3 5 2 AN3 V5()+ C1IN1+ IOC Y
(1)
RA4 6 3 OPA1IN+ T0CKI IOC Y
(1)
RA5 7 4 AN4 OPA1IN- DAC2OUT1 nSS IOC Y
OSC2
RA6 10 7 IOC Y
CLKOUT
OSC1
RA7 9 6 IOC Y
CLKIN
(1)
C2IN1+ (1) INT
RB0 21 18 AN12 ZCD COG1IN Y
IOC
C1IN3-
RB1 22 19 AN10 OPA2OUT IOC Y
C2IN3-
RB2 23 20 AN8 OPA2IN- IOC Y
C1IN2-
RB3 24 21 AN9 OPA2IN+ IOC Y
C2IN2-
RB4 25 22 AN11 IOC Y
(1)
RB5 26 23 AN13 T1G IOC Y
(1)
RB6 27 24 CLCIN2 IOC Y ICSPCLK
DAC1OUT2 (1)
RB7 28 25 CLCIN3 IOC Y ICSPDAT
DAC2OUT2
2014-2015 Microchip Technology Inc.
(1)
T1CKI
RC0 11 8 IOC Y
SOSCO
(1)
RC1 12 9 SOSCI CCP2 IOC Y
(1)
RC2 13 10 AN14 CCP1 IOC Y
(1)
RC3 14 11 AN15 6&/SCK IOC Y
Note 1: Default peripheral input. Alternate pins can be selected as the peripheral input with the PPS input selection registers.
2: All pin digital outputs default to PORT latch data. Alternate outputs can be selected as the peripheral digital output with the PPS output selection registers.
3: These peripheral functions are bidirectional. The output pin selections must be the same as the input pin selections.
4: Alternate outputs are excluded from solid shaded areas.
5: Alternate inputs are excluded from dot shaded areas.
TABLE 1: 28-PIN ALLOCATION TABLE (PIC16(L)F1718) (CONTINUED)
2014-2015 Microchip Technology Inc.
6PDIP,SOIC,
Comparator
QFN, UQFN
Zero Cross
Reference
EUSART
Interrupt
Op Amp
Timers
Pull-up
MSSP
SSOP
Basic
PWM
COG
NCO
CCP
ADC
DAC
(2)
CLC
I/O
(1)
SDI
RC4 15 12 AN16 (1)
IOC Y
SDA
RC5 16 13 AN17 IOC Y
(3)
RC6 17 14 AN18 CK IOC Y
(3)
RC7 18 15 AN19 RX IOC Y
MCLR
RE3 1 26 IOC Y
V33
V'' 20 17 V''
8 5 V66
V66
19 16
NCOOUT
(3)
PWM3OUT
PWM4OUT
CLC4OUT
CLC3OUT
CLC2OUT
CLC1OUT
COG1C
COG1D
COG1A
COG1B
SCK/SCL
C1OUT
C2OUT
TX/CK
SDA(3)
CCP1
CCP2
SDO
DT(3)
OUT(4)
(3)
COG1IN
CLCIN0
CLCIN1
CLCIN2
CLCIN3
SCK/SCL
T1CKI
T0CKI
CCP1
CCP2
T1G
RX(3)
SDI
INT
CK
SS
(5)
IN
Note 1: Default peripheral input. Alternate pins can be selected as the peripheral input with the PPS input selection registers.
2: All pin digital outputs default to PORT latch data. Alternate outputs can be selected as the peripheral digital output with the PPS output selection registers.
3: These peripheral functions are bidirectional. The output pin selections must be the same as the input pin selections.
PIC16(L)F1717/8/9
4: Alternate outputs are excluded from solid shaded areas.
5: Alternate inputs are excluded from dot shaded areas.
DS40001740B-page 5
PIC16(L)F1717/8/9
FIGURE 3: 40-PIN PDIP
VPP/MCLR/RE3 1 40 RB7/ICSPDAT
RA0 2 39 RB6/ICSPCLK
RA1 3 38 RB5
RA2 4 37 RB4
RA3 5 36 RB3
RA4 6 35 RB2
RA5 7 34 RB1
RE0 8 33 RB0
VDD
PIC16L(F)1717/9
RE1 9 32
RE2 10 31 VSS
VDD 11 30 RD7
VSS 12 29 RD6
RA7 13 28 RD5
RA6 14 27 RD4
RC0 15 26 RC7
RC1 16 25 RC6
RC2 17 24 RC5
RC3 18 23 RC4
RD0 19 22 RD3
RD1 20 21 RD2
RC4
RD3
RD2
RD1
RD0
RC3
RC2
RC1 31
34
40
39
37
36
35
33
32
38
RC7 1
RD4 2 30 RC0
RD5 3 29 RA6
RD6 4 28 RA7
RD7 5 27 VSS
VSS PIC16L(F)1717/9
6 26 VDD
VDD 7 25 RE2
RB0 8 24 RE1
RB1 9 23 RE0
RB2 10
22 RA5
21 RA4
12
13
14
15
16
17
18
19
20
11 RB3
RB4
RB5
RA0
RA1
RA2
RA3
ICSPDAT/RB7
ICSPCLK/RB6
VPP/MCLR/RE3
RC5
RC6
RC4
RD3
RD2
RD1
RD0
RC3
RC2
RC1
NC
41
40
39
37
36
35
34
42
44
43
38
RC7 1 33 NC
RD4 2 32 RC0
RD5 3 31 RA6
RD6 4 30 RA7
RD7 5 29 VSS
VSS 6 PIC16(L)F1717/9 28 VDD
VDD 7 27 RE2
RB0 8 26 RE1
RB1 9 25 RE0
RB2 10 24 RA5
RB3 11 12 23 RA4
13
14
15
16
17
18
19
20
21
22
NC
NC
RB4
RB5
RA0
RA1
RA2
RA3
ICSPDAT/RB7
ICSPCLK/RB6
VPP/MCLR/RE3
PIC16(L)F1717/8/9
TABLE 2: 40/44-PIN ALLOCATION TABLE (PIC16(L)F1717/9)
Comparator
Zero Cross
Reference
EUSART
Interrupt
Op Amp
Timers
Pullup
MSSP
UQFN
TQFP
Basic
PWM
COG
PDIP
CCP
NCO
ADC
DAC
CLC
I/O(2)
C1IN0-
RA0 2 19 17 AN0
C2IN0- CLCIN0(1) IOC Y
C1IN1-
RA1 3 20 18 AN1
C2IN1-
OPA1OUT CLCIN1(1) IOC Y
C1IN0+
RA2 4 21 19 AN2 V5()- DAC1OUT1 IOC Y
C2IN0+
RA3 5 22 20 AN3 V5()+ C1IN1+ IOC Y
RA4 6 23 21 OPA1IN+ T0CKI(1) IOC Y
RA5 7 24 22 AN4 OPA1IN- DAC2OUT1 nSS(1) IOC Y
OSC2
RA6 14 31 29 IOC Y
CLKOUT
OSC1
RA7 13 30 28 IOC Y
CLKIN
INT(1)
RB0 33 8 8 AN12 C2IN1+ ZCD COG1IN(1) Y
IOC
C1IN3-
RB1 34 9 9 AN10 OPA2OUT IOC Y
C2IN3-
RB2 35 10 10 AN8 OPA2IN- IOC Y
C1IN2-
RB3 36 11 11 AN9 OPA2IN+ IOC Y
C2IN2-
RB4 37 14 12 AN11 IOC Y
RB5 38 15 13 AN13 T1G(1) IOC Y
RB6 39 16 14 CLCIN2(1) IOC Y ICSPCLK
DAC1OUT2
RB7 40 17 15 CLCIN3(1) IOC Y ICSPDAT
DAC2OUT2
2014-2015 Microchip Technology Inc.
(1)
RC0 15 32 30 T1CKI IOC Y
SOSCO
(1)
RC1 16 35 31 SOSCI
CCP2 IOC Y
RC2 17 36 32 AN14 CCP1(1) IOC Y
RC3 18 37 33 AN15 6&/SCK(1) IOC Y
Note 1: Default peripheral input. Alternate pins can be selected as the peripheral input with the PPS input selection registers.
2: All pin digital outputs default to PORT latch data. Alternate outputs can be selected as the peripheral digital output with the PPS output selection registers.
3: These peripheral functions are bidirectional. The output pin selections must be the same as the input pin selections.
4: Alternate outputs are excluded from solid shaded areas.
5: Alternate inputs are excluded from dot shaded areas.
TABLE 2: 40/44-PIN ALLOCATION TABLE (PIC16(L)F1717/9) (CONTINUED)
2014-2015 Microchip Technology Inc.
Comparator
Zero Cross
Reference
EUSART
Interrupt
Op Amp
Timers
Pullup
MSSP
UQFN
TQFP
Basic
PWM
COG
PDIP
CCP
NCO
ADC
DAC
CLC
I/O(2)
SDI(1)
RC4 23 42 38 AN16 IOC Y
SDA(1)
RC5 24 43 39 AN17 IOC Y
RC6 25 44 40 AN18 CK(3) IOC Y
RC7 26 1 1 AN19 RX(3) IOC Y
RD0 19 38 34 AN20 Y
RD1 20 39 35 AN21 Y
RD2 21 40 36 AN22 Y
RD3 22 41 37 AN23 Y
RD4 27 2 2 AN24 Y
RD5 28 3 3 AN25 Y
RD6 29 4 4 AN26 Y
RD7 30 5 5 AN27 Y
RE0 8 25 23 AN5 Y
RE1 9 26 24 AN6 Y
RE2 10 27 25 AN7 Y
MCLR
RE3 1 18 16 IOC Y
V33
11 7 7 V''
V''
32 28 26
12 6 6 V66
PIC16(L)F1717/8/9
V66
31 29 27
PWM3OUT
PWM4OUT
SCK/SCL(3)
NCOOUT
CLC4OUT
CLC3OUT
CLC2OUT
CLC1OUT
COG1C
COG1D
COG1A
COG1B
C1OUT
C2OUT
TX/CK
SDA(3)
CCP1
CCP2
SDO
DT (3)
OUT(4)
(3)
COG1IN
CLCIN0
CLCIN1
CLCIN2
CLCIN3
SCK/SCL
T1CKI
T0CKI
CCP1
CCP2
RX (3)
T1G
SDI
INT
CK
SS
IN(5)
Note 1: Default peripheral input. Alternate pins can be selected as the peripheral input with the PPS input selection registers.
DS40001740B-page 9
2: All pin digital outputs default to PORT latch data. Alternate outputs can be selected as the peripheral digital output with the PPS output selection registers.
3: These peripheral functions are bidirectional. The output pin selections must be the same as the input pin selections.
4: Alternate outputs are excluded from solid shaded areas.
5: Alternate inputs are excluded from dot shaded areas.
PIC16(L)F1717/8/9
Table of Contents
1.0 Device Overview ........................................................................................................................................................................ 12
2.0 Enhanced Mid-Range CPU ........................................................................................................................................................ 22
3.0 Memory Organization ................................................................................................................................................................. 24
4.0 Device Configuration .................................................................................................................................................................. 55
5.0 Resets ........................................................................................................................................................................................ 60
6.0 Oscillator Module (with Fail-Safe Clock Monitor) ....................................................................................................................... 68
7.0 Interrupts .................................................................................................................................................................................... 86
8.0 Power-Down Mode (Sleep) ........................................................................................................................................................ 98
9.0 Watchdog Timer (WDT) ........................................................................................................................................................... 102
10.0 Flash Program Memory Control ............................................................................................................................................... 106
11.0 I/O Ports ................................................................................................................................................................................... 122
12.0 Peripheral Pin Select (PPS) Module ........................................................................................................................................ 150
13.0 Interrupt-On-Change ................................................................................................................................................................ 156
14.0 Fixed Voltage Reference (FVR) .............................................................................................................................................. 163
15.0 Temperature Indicator Module ................................................................................................................................................. 166
16.0 Comparator Module.................................................................................................................................................................. 168
17.0 Pulse Width Modulation (PWM) ............................................................................................................................................... 177
18.0 Complementary Output Generator (COG) Module................................................................................................................... 184
19.0 Configurable Logic Cell (CLC).................................................................................................................................................. 218
20.0 Numerically Controlled Oscillator (NCO) Module ..................................................................................................................... 233
21.0 Analog-to-Digital Converter (ADC) Module .............................................................................................................................. 242
22.0 Operational Amplifier (OPA) Modules ...................................................................................................................................... 255
23.0 8-Bit Digital-to-Analog Converter (DAC1) Module .................................................................................................................... 258
24.0 5-Bit Digital-to-Analog Converter (DAC2) Module .................................................................................................................... 261
25.0 Zero-Cross Detection (ZCD) Module........................................................................................................................................ 264
26.0 Timer0 Module ......................................................................................................................................................................... 268
27.0 Timer1 Module with Gate Control............................................................................................................................................. 271
28.0 Timer2/4/6 Module ................................................................................................................................................................... 282
29.0 Capture/Compare/PWM Modules ............................................................................................................................................ 287
30.0 Master Synchronous Serial Port (MSSP) Module .................................................................................................................... 295
31.0 Enhanced Universal Synchronous Asynchronous Receiver Transmitter (EUSART) ............................................................... 351
32.0 In-Circuit Serial Programming (ICSP™) ................................................................................................................................... 381
33.0 Instruction Set Summary .......................................................................................................................................................... 383
34.0 Electrical Specifications............................................................................................................................................................ 397
35.0 DC and AC Characteristics Graphs and Charts ....................................................................................................................... 432
36.0 Development Support............................................................................................................................................................... 454
37.0 Packaging Information.............................................................................................................................................................. 458
Appendix A: Data Sheet Revision History ......................................................................................................................................... 479
Errata
An errata sheet, describing minor operational differences from the data sheet and recommended workarounds, may exist for current
devices. As device/documentation issues become known to us, we will publish an errata sheet. The errata will specify the revision
of silicon and revision of document to which it applies.
To determine if an errata sheet exists for a particular device, please check with one of the following:
• Microchip’s Worldwide Website; http://www.microchip.com
• Your local Microchip sales office (see last page)
When contacting a sales office, please specify which device, revision of silicon and data sheet (include literature number) you are
using.
PIC16(L)F1717
PIC16(L)F1718
PIC16(L)F1719
• 28-pin SPDIP, SSOP, SOIC, QFN and UQFN
• 40-pin PDIP and UQFN Peripheral
• 44-pin TQFP
Figure 1-1 and Figure 1-2 show block diagrams of the
PIC16(L)F1717/8/9 devices. Table 1-2 shows the Analog-to-Digital Converter (ADC) ● ● ●
pinout descriptions.
Fixed Voltage Reference (FVR) ● ● ●
Reference Table 1-1 for peripherals available per device. Zero-Cross Detection (ZCD) ● ● ●
Temperature Indicator ● ● ●
Complementary Output Generator (COG)
COG ● ● ●
Numerically Controlled Oscillator (NCO)
NCO ● ● ●
Digital-to-Analog Converter (DAC)
DAC1 ● ● ●
DAC2 ● ● ●
Capture/Compare/PWM (CCP/ECCP) Modules
CCP1 ● ● ●
CCP2 ● ● ●
Comparators
C1 ● ● ●
C2 ● ● ●
Configurable Logic Cell (CLC)
CLC1 ● ● ●
CLC2 ● ● ●
CLC3 ● ● ●
CLC4 ● ● ●
Enhanced Universal Synchronous/Asynchronous
Receiver/Transmitter (EUSART)
EUSART ● ● ●
Master Synchronous Serial Ports
MSSP ● ● ●
Op Amp
Op Amp 1 ● ● ●
Op Amp 2 ● ● ●
Pulse-Width Modulator (PWM)
PWM3 ● ● ●
PWM4 ● ● ●
Timers
Timer0 ● ● ●
Timer1 ● ● ●
Timer2 ● ● ●
Program
Flash Memory
RAM PORTA
PORTB
CLKOUT Timing
Generation
HFINTOSC/
CLKIN CPU PORTC
LFINTOSC
Oscillator
MCLR
NCO
ZCD
Temp. ADC
FVR DACs CCPs EUSART CLCs
Indicator 10-Bit
Program
Flash Memory
RAM PORTA
PORTB
CLKOUT Timing
Generation
PORTC
HFINTOSC/
CLKIN CPU
LFINTOSC
Oscillator
PORTD
Figure 2-1: Core Block Diagram
MCLR
PORTE
NCO
ZCD
Temp. ADC
FVR DACs CCPs EUSART CLCs
Indicator 10-Bit
15
Configuration 15 8
Data Bus
Program Counter
Flash
MUX
Program
Memory 16-Level
8 Level Stack
Stack
RAM
(13-bit)
(15-bit)
Program
14 Program Memory 12 RAM Addr
Bus
Read (PMR)
Addr MUX
Instruction
Instruction Reg
reg
Indirect
Direct Addr 7 Addr
5 12 12
15 BSR
FSR Reg
reg
FSR0reg
FSR Reg
FSR1 Reg
FSR reg
15 STATUS Reg
STATUS reg
8
3 MUX
Power-up
Timer
Instruction Oscillator
Decodeand
Decode & Start-up Timer
ALU
Control
OSC1/CLKIN Power-on
Reset 8
Timing Watchdog
OSC2/CLKOUT Generation Timer W reg
Brown-out
Reset
Internal
Oscillator
Block
VDD VSS
PC<14:0> PC<14:0>
CALL, CALLW 15 CALL, CALLW 15
RETURN, RETLW RETURN, RETLW
Interrupt, RETFIE Interrupt, RETFIE
Stack Level 0 Stack Level 0
Stack Level 1 Stack Level 1
Rollover to Page 1
7FFFh
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets
‘1’ = Bit is set ‘0’ = Bit is cleared q = Value depends on condition
Note 1: For Borrow, the polarity is reversed. A subtraction is executed by adding the two’s complement of the
second operand.
00h
Core Registers
(12 bytes)
0Bh
0Ch
Special Function Registers
(20 bytes maximum)
1Fh
20h
6Fh
70h
Common RAM
(16 bytes)
7Fh
PIC16(L)F1717/8/9
BANK 0 BANK 1 BANK 2 BANK 3 BANK 4 BANK 5 BANK 6 BANK 7
000h 080h 100h 180h 200h 280h 300h 380h
Core Registers Core Registers Core Registers Core Registers Core Registers Core Registers Core Registers Core Registers
(Table 3-2) (Table 3-2) (Table 3-2) (Table 3-2) (Table 3-2) (Table 3-2) (Table 3-2) (Table 3-2)
00Bh 08Bh 10Bh 18Bh 20Bh 28Bh 30Bh 38Bh
00Ch PORTA 08Ch TRISA 10Ch LATA 18Ch ANSELA 20Ch WPUA 28Ch ODCONA 30Ch SLRCONA 38Ch INLVLA
00Dh PORTB 08Dh TRISB 10Dh LATB 18Dh ANSELB 20Dh WPUB 28Dh ODCONB 30Dh SLRCONB 38Dh INLVLB
00Eh PORTC 08Eh TRISC 10Eh LATC 18Eh ANSELC 20Eh WPUC 28Eh ODCONC 30Eh SLRCONC 38Eh INLVLC
00Fh — 08Fh — 10Fh — 18Fh — 20Fh — 28Fh — 30Fh — 38Fh —
010h PORTE 090h TRISE 110h — 190h — 210h WPUE 290h — 310h — 390h INLVLE
011h PIR1 091h PIE1 111h CM1CON0 191h PMADRL 211h SSP1BUF 291h CCPR1L 311h — 391h IOCAP
012h PIR2 092h PIE2 112h CM1CON1 192h PMADRH 212h SSP1ADD 292h CCPR1H 312h — 392h IOCAN
013h PIR3 093h PIE3 113h CM2CON0 193h PMDATL 213h SSP1MSK 293h CCP1CON 313h — 393h IOCAF
014h — 094h — 114h CM2CON1 194h PMDATH 214h SSP1STAT 294h — 314h — 394h IOCBP
015h TMR0 095h OPTION_REG 115h CMOUT 195h PMCON1 215h SSP1CON1 295h — 315h — 395h IOCBN
016h TMR1L 096h PCON 116h BORCON 196h PMCON2 216h SSP1CON2 296h — 316h — 396h IOCBF
017h TMR1H 097h WDTCON 117h FVRCON 197h VREGCON(1) 217h SSP1CON3 297h — 317h — 397h IOCCP
018h T1CON 098h OSCTUNE 118h DAC1CON0 198h — 218h — 298h CCPR2L 318h — 398h IOCCN
019h T1GCON 099h OSCCON 119h DAC1CON1 199h RC1REG 219h — 299h CCPR2H 319h — 399h IOCCF
01Ah TMR2 09Ah OSCSTAT 11Ah DAC2CON0 19Ah TX1REG 21Ah — 29Ah CCP2CON 31Ah — 39Ah —
01Bh PR2 09Bh ADRESL 11Bh DAC2CON1 19Bh SP1BRGL 21Bh — 29Bh — 31Bh — 39Bh —
01Ch T2CON 09Ch ADRESH 11Ch ZCD1CON 19Ch SP1BRGH 21Ch — 29Ch — 31Ch — 39Ch —
01Dh — 09Dh ADCON0 11Dh — 19Dh RC1STA 21Dh — 29Dh — 31Dh — 39Dh IOCEP
01Eh — 09Eh ADCON1 11Eh — 19Eh TX1STA 21Eh — 29Eh CCPTMRS 31Eh — 39Eh IOCEN
01Fh — 09Fh ADCON2 11Fh — 19Fh BAUD1CON 21Fh — 29Fh — 31Fh — 39Fh IOCEF
020h 0A0h 120h 1A0h 220h 2A0h 320h 3A0h
General General General General General General General General
Purpose Purpose Purpose Purpose Purpose Purpose Purpose Purpose
Register Register Register Register Register Register Register Register
80 Bytes 80 Bytes 80 Bytes 80 Bytes 80 Bytes 80 Bytes 80 Bytes 80 Bytes
PIC16(L)F1717/8/9
Purpose Purpose Purpose Purpose Purpose Purpose Purpose Purpose
Register Register Register Register Register Register Register Register
80 Bytes 80 Bytes 80 Bytes 80 Bytes 80 Bytes 80 Bytes 80 Bytes 80 Bytes
PIC16(L)F1717/8/9
BANK 8 BANK 9 BANK 10 BANK 11 BANK 12 BANK 13 BANK 14 BANK 15
400h 480h 500h 580h 600h 680h 700h 780h
Core Registers Core Registers Core Registers Core Registers Core Registers Core Registers Core Registers Core Registers
(Table 3-2) (Table 3-2) (Table 3-2) (Table 3-2) (Table 3-2) (Table 3-2) (Table 3-2) (Table 3-2)
40Bh 48Bh 50Bh 58Bh 60Bh 68Bh 70Bh 78Bh
40Ch — 48Ch — 50Ch — 58Ch — 60Ch — 68Ch — 70Ch — 78Ch —
40Dh — 48Dh — 50Dh — 58Dh — 60Dh — 68Dh — 70Dh — 78Dh —
40Eh — 48Eh — 50Eh — 58Eh — 60Eh — 68Eh — 70Eh — 78Eh —
40Fh — 48Fh — 50Fh — 58Fh — 60Fh — 68Fh — 70Fh — 78Fh —
410h — 490h — 510h — 590h — 610h — 690h — 710h — 790h —
411h — 491h — 511h OPA1CON 591h — 611h — 691h COG1PHR 711h — 791h —
412h — 492h — 512h — 592h — 612h — 692h COG1PHF 712h — 792h —
413h — 493h — 513h — 593h — 613h — 693h COG1BLKR 713h — 793h —
414h — 494h — 514h — 594h — 614h — 694h COG1BLKF 714h — 794h —
415h TMR4 495h — 515h OPA2CON 595h — 615h — 695h COG1DBR 715h — 795h —
416h PR4 496h — 516h — 596h — 616h — 696h COG1DBF 716h — 796h —
417h T4CON 497h — 517h — 597h — 617h PWM3DCL 697h COG1CON0 717h — 797h —
418h — 498h NCO1ACCL 518h — 598h — 618h PWM3DCH 698h COG1CON1 718h — 798h —
419h — 499h NCO1ACCH 519h — 599h — 619h PWM3CON 699h COG1RIS 719h — 799h —
41Ah — 49Ah NCO1ACCU 51Ah — 59Ah — 61Ah PWM4DCL 69Ah COG1RSIM 71Ah — 79Ah —
41Bh — 49Bh NCO1INCL 51Bh — 59Bh — 61Bh PWM4DCH 69Bh COG1FIS 71Bh — 79Bh —
41Ch TMR6 49Ch NCO1INCH 51Ch — 59Ch — 61Ch PWM4CON 69Ch COG1FSIM 71Ch — 79Ch —
41Dh PR6 49Dh NCO1INCU 51Dh — 59Dh — 61Dh — 69Dh COG1ASD0 71Dh — 79Dh —
41Eh T6CON 49Eh NCO1CON 51Eh — 59Eh — 61Eh — 69Eh COG1ASD1 71Eh — 79Eh —
41Fh — 49Fh NCO1CLK 51Fh — 59Fh — 61Fh — 69Fh COG1STR 71Fh — 79Fh —
420h 4A0h 520h 5A0h 620h 6A0h 720h 7A0h
General Purpose
General General General General Register 48 Bytes
Purpose Purpose Purpose Purpose 64Fh Unimplemented Unimplemented Unimplemented
Register Register Register Register 650h Read as ‘0’ Read as ‘0’ Read as ‘0’
80 Bytes 80 Bytes 80 Bytes 80 Bytes Unimplemented
Read as ‘0’
46Fh 4EFh 56Fh 5EFh 66Fh 6EFh 76Fh 7EFh
470h 4F0h 570h 5F0h 670h 6F0h 770h 7F0h
Accesses Accesses Accesses Accesses Accesses Accesses Accesses Accesses
70h – 7Fh 70h – 7Fh 70h – 7Fh 70h – 7Fh 70h – 7Fh 70h – 7Fh 70h – 7Fh 70h – 7Fh
47Fh 4FFh 57Fh 5FFh 67Fh 6FFh 77Fh 7FFh
2014-2015 Microchip Technology Inc.
PIC16(L)F1717/8/9
470h 4F0h 570h 5F0h 670h 6F0h 770h 7F0h
Accesses Accesses Accesses Accesses Accesses Accesses Accesses Accesses
70h – 7Fh 70h – 7Fh 70h – 7Fh 70h – 7Fh 70h – 7Fh 70h – 7Fh 70h – 7Fh 70h – 7Fh
47Fh 4FFh 57Fh 5FFh 67Fh 6FFh 77Fh 7FFh
PIC16(L)F1717/8/9
BANK 24 BANK 25 BANK 26 BANK 27 BANK 28 BANK 29 BANK 30 BANK 31
C00h C80h D00h D80h E00h E80h F00h F80h
Core Registers Core Registers Core Registers Core Registers Core Registers Core Registers Core Registers Core Registers
(Table 3-2) (Table 3-2) (Table 3-2) (Table 3-2) (Table 3-2) (Table 3-2) (Table 3-2) (Table 3-2)
C0Bh C8Bh D0Bh D8Bh E0Bh E8Bh F0Bh F8Bh
C0Ch — C8Ch — D0Ch — D8Ch — E0Ch E8Ch F0Ch F8Ch
C0Dh — C8Dh — D0Dh — D8Dh — E0Dh E8Dh F0Dh F8Dh
C0Eh — C8Eh — D0Eh — D8Eh — E0Eh E8Eh F0Eh F8Eh
C0Fh — C8Fh — D0Fh — D8Fh — E0Fh E8Fh F0Fh F8Fh
C10h — C90h — D10h — D90h — E10h E90h F10h F90h
C11h — C91h — D11h — D91h — E11h E91h F11h F91h
C12h — C92h — D12h — D92h — E12h E92h F12h F92h
C13h — C93h — D13h — D93h — E13h E93h F13h F93h
C14h — C94h — D14h — D94h — E14h E94h F14h F94h
C15h — C95h — D15h — D95h — E15h E95h F15h F95h
C16h — C96h — D16h — D96h — E16h E96h F16h F96h
C17h — C97h — D17h — D97h — E17h E97h F17h F97h
See Table 3-9 for See Table 3-9 for See Table 3-9 for See Table 3-10 for
C18h — C98h — D18h — D98h — E18h register mapping E98h register mapping F18h register mapping F98h register mapping
C19h — C99h — D19h — D99h — E19h details E99h details F19h details F99h details
C1Ah — C9Ah — D1Ah — D9Ah — E1Ah E9Ah F1Ah F9Ah
C1Bh — C9Bh — D1Bh — D9Bh — E1Bh E9Bh F1Bh F9Bh
C1Ch — C9Ch — D1Ch — D9Ch — E1Ch E9Ch F1Ch F9Ch
C1Dh — C9Dh — D1Dh — D9Dh — E1Dh E9Dh F1Dh F9Dh
C1Eh — C9Eh — D1Eh — D9Eh — E1Eh E9Eh F1Eh F9Eh
C1Fh — C9Fh — D1Fh — D9Fh — E1Fh E9Fh F1Fh F9Fh
C20h CA0h D20h DA0h E20h EA0h F20h FA0h
PIC16(L)F1717/8/9
Register Unimplemented Read as ‘0’ Read as ‘0’
80 Bytes Read as ‘0’
C6Fh CEFh D6Fh DEFh E6Fh EEFh F6Fh FEFh
C70h CF0h D70h DF0h E70h EF0h F70h FF0h
Accesses Accesses Accesses Accesses Accesses Accesses Accesses Accesses
70h – 7Fh 70h – 7Fh 70h – 7Fh 70h – 7Fh 70h – 7Fh 70h – 7Fh 70h – 7Fh 70h – 7Fh
CFFh CFFh D7Fh DFFh E7Fh EFFh F7Fh FFFh
— — —
E6Fh EEFh F6Fh
Legend: = Unimplemented data memory locations, read as ‘0’,
Note 1: Only available on PIC16(L)F1717/9 devices.
FE3h
FE4h STATUS_SHAD
FE5h WREG_SHAD
FE6h BSR_SHAD
FE7h PCLATH_SHAD
FE8h FSR0L_SHAD
FE9h FSR0H_SHAD
FEAh FSR1L_SHAD
FEBh FSR1H_SHAD
FECh —
FEDh STKPTR
FEEh TOSL
FEFh TOSH
FF0h
—
FFFh
Legend: = Unimplemented data memory locations,
read as ‘0’,
Bank 2
10Ch LATA — — LATA5 LATA4 — LATA2 LATA1 LATA0 xxxx xxxx uuuu uuuu
10Dh LATB LATB7 LATB6 LATB5 LATB4 LATB3 LATB2 LATB1 LATB0 xxxx xxxx uuuu uuuu
10Eh LATC LATC7 LATC6 LATC5 LATC4 LATC3 LATC2 LATC1 LATC0 xxxx xxxx uuuu uuuu
10Fh LATD(1) LATD7 LATD6 LATD5 LATD4 LATD3 LATD2 LATD1 LATD0 xxxx xxxx uuuu uuuu
110h LATE(1) — — — — — LATE2 LATE1 LATE0 ---- -xxx ---- -uuu
111h CM1CON0 C1ON C1OUT — C1POL C1ZLF C1SP C1HYS C1SYNC 00-0 0100 00-0 0100
112h CM1CON1 C1INTP C1INTN C1PCH<2:0> C1NCH<2:0> 0000 0000 0000 0000
113h CM2CON0 C2ON C2OUT — C2POL C2ZLF C2SP C2HYS C2SYNC 00-0 0100 00-0 0100
114h CM2CON1 C2INTP C2INTN C2PCH<2:0> C2NCH<2:0> 0000 0000 0000 0000
115h CMOUT — — — — — — MC2OUT MC1OUT ---- --00 ---- --00
116h BORCON SBOREN BORFS — — — — — BORRDY 10-- ---q uu-- ---u
117h FVRCON FVREN FVRRDY TSEN TSRNG CDAFVR<1:0> ADFVR<1:0> 0q00 0000 0q00 0000
118h DAC1CON0 DAC1EN --- DAC1OE1 DAC1OE2 DAC1PSS<1:0> --- DAC1NSS 0-00 00-0 0-00 00-0
119h DAC1CON1 DAC1R<7:0> 0000 0000 0000 0000
11Ah DAC2CON0 DAC2EN — DAC2OE1 DAC2OE2 DAC2PSS<1:0> — DAC2NSS 0-00 00-0 0-00 00-0
11Bh DAC2CON1 — — — DAC2R<4:0> ---0 0000 ---0 0000
11Ch ZCD1CON ZCD1EN — ZCD1OUT ZCD1POL — — ZCD1INTP ZCD1INTN 0-x0 --00 0-00 --00
11Dh — Unimplemented — —
11Eh — Unimplemented — —
11Fh — Unimplemented — —
Bank 3
18Ch ANSELA — — ANSA5 ANSA4 ANSA3 ANSA2 ANSA1 ANSA0 --11 1111 --11 1111
18Dh ANSELB — — ANSB5 ANSB4 ANSB3 ANSB2 ANSB1 ANSB0 --11 1111 --11 1111
18Eh ANSELC ANSC7 ANSC6 ANSC5 ANSC4 ANSC3 ANSC2 — — 1111 11-- 1111 11--
18Fh ANSELD(1) ANSD7 ANSD6 ANSD5 ANSD4 ANSD3 ANSD2 ANSD1 ANSD0 1111 1111 1111 1111
190h ANSELE(1) — — — — — ANSE2 ANSE1 ANSE0 ---- -111 ---- -111
191h PMADRL Program Memory Address Register Low Byte 0000 0000 0000 0000
192h PMADRH — Program Memory Address Register High Byte 1000 0000 1000 0000
193h PMDATL Program Memory Read Data Register Low Byte xxxx xxxx uuuu uuuu
194h PMDATH — — Program Memory Read Data Register High Byte --xx xxxx --uu uuuu
195h PMCON1 — CFGS LWLO FREE WRERR WREN WR RD -000 x000 -000 q000
196h PMCON2 Program Memory Control Register 2 0000 0000 0000 0000
197h VREGCON(2) — — — — — — VREGPM Reserved ---- --01 ---- --01
198h — Unimplemented — —
199h RC1REG USART Receive Data Register 0000 0000 0000 0000
19Ah TX1REG USART Transmit Data Register 0000 0000 0000 0000
19Bh SP1BRGL SP1BRG<7:0> 0000 0000 0000 0000
19Ch SP1BRGH SP1BRG<15:8> 0000 0000 0000 0000
19Dh RC1STA SPEN RX9 SREN CREN ADDEN FERR OERR RX9D 0000 0000 0000 0000
19Eh TX1STA CSRC TX9 TXEN SYNC SENDB BRGH TRMT TX9D 0000 0010 0000 0010
19Fh BAUD1CON ABDOVF RCIDL — SCKP BRG16 — WUE ABDEN 01-0 0-00 01-0 0-00
Legend: x = unknown, u = unchanged, q = value depends on condition, - = unimplemented, read as ‘0’, r = reserved.
Shaded locations are unimplemented, read as ‘0’.
Note 1: Unimplemented on PIC16(L)F1718.
2: Unimplemented on PIC16LF1717/8/9
Bank 4
20Ch WPUA WPUA7 WPUA6 WPUA5 WPUA4 WPUA3 WPUA2 WPUA1 WPUA0 1111 1111 1111 1111
20Dh WPUB WPUB7 WPUB6 WPUB5 WPUB4 WPUB3 WPUB2 WPUB1 WPUB0 1111 1111 1111 1111
20Eh WPUC WPUC7 WPUC6 WPUC5 WPUC4 WPUC3 WPUC2 WPUC1 WPUC0 1111 1111 1111 1111
20Fh WPUD(1) WPUD7 WPUD6 WPUD5 WPUD4 WPUD3 WPUD2 WPUD1 WPUD0 1111 1111 1111 1111
210h WPUE — — — — WPUE3 WPUE2(1) WPUE1(1) WPUE0(1) ---- 1111 ---- 1111
211h SSP1BUF Synchronous Serial Port Receive Buffer/Transmit Register XXXX XXXX uuuu uuuu
212h SSP1ADD ADD<7:0> XXXX XXXX 0000 0000
213h SSP1MSK MSK<7:0> XXXX XXXX 1111 1111
214h SSP1STAT SMP CKE D/A P S R/W UA BF 0000 0000 0000 0000
215h SSP1CON1 WCOL SSPOV SSPEN CKP SSPM<3:0> 0000 0000 0000 0000
216h SSP1CON2 GCEN ACKSTAT ACKDT ACKEN RCEN PEN RSEN SEN 0000 0000 0000 0000
217h SSP1CON3 ACKTIM PCIE SCIE BOEN SDAHT SBCDE AHEN DHEN 0000 0000 0000 0000
218h
— — Unimplemented — —
21Fh
Bank 5
28Ch ODCONA ODA7 ODA6 ODA5 ODA4 ODA3 ODA2 ODA1 ODA0 0000 0000 0000 0000
28Dh ODCONB ODB7 ODB6 ODB5 ODB4 ODB3 ODB2 ODB1 ODB0 0000 0000 0000 0000
28Eh ODCONC ODC7 ODC6 ODC5 ODC4 ODC3 ODC2 ODC1 ODC0 0000 0000 0000 0000
28Fh ODCOND(1) ODD7 ODD6 ODD5 ODD4 ODD3 ODD2 ODD1 ODD0 0000 0000 0000 0000
290h ODCONE(1) — — — — — ODE2 ODE1 ODE0 ---- -000 ---- -000
291h CCPR1L Capture/Compare/PWM Register 1 (LSB) xxxx xxxx uuuu uuuu
292h CCPR1H Capture/Compare/PWM Register 1 (MSB) xxxx xxxx uuuu uuuu
293h CCP1CON — — DC1B<1:0> CCP1M<3:0> --00 0000 --00 0000
294h
— — Unimplemented — —
297h
298h CCPR2L Capture/Compare/PWM Register 2 (LSB) xxxx xxxx uuuu uuuu
299h CCPR2H Capture/Compare/PWM Register 2 (MSB) xxxx xxxx uuuu uuuu
29Ah CCP2CON — — DC2B<1:0> CCP2M<3:0> --00 0000 --00 0000
29Bh
— — Unimplemented — —
29Dh
29Eh CCPTMRS P4TSEL<1:0> P3TSEL<1:0> C2TSEL<1:0> C1TSEL<1:0> 0000 0000 0000 0000
29Fh — Unimplemented — —
Bank 6
30Ch SLRCONA SLRA7 SLRA6 SLRA5 SLRA4 SLRA3 SLRA2 SLRA1 SLRA0 1111 1111 0000 0000
30Dh SLRCONB SLRB7 SLRB6 SLRB5 SLRB4 SLRB3 SLRB2 SLRB1 SLRB0 1111 1111 0000 0000
30Eh SLRCONC SLRC7 SLRC6 SLRC5 SLRC4 SLRC3 SLRC2 SLRC1 SLRC0 1111 1111 0000 0000
30Fh SLRCOND(1) SLRD7 SLRD6 SLRD5 SLRD4 SLRD3 SLRD2 SLRD1 SLRD0 1111 1111 0000 0000
310h SLRCONE(1) — — — — — SLRE2 SLRE1 SLRE0 ---- -111 ---- -000
311h
— — Unimplemented — —
31Fh
Legend: x = unknown, u = unchanged, q = value depends on condition, - = unimplemented, read as ‘0’, r = reserved.
Shaded locations are unimplemented, read as ‘0’.
Note 1: Unimplemented on PIC16(L)F1718.
2: Unimplemented on PIC16LF1717/8/9
Bank 7
38Ch INLVLA INLVLA7 INLVLA6 INLVLA5 INLVLA4 INLVLA3 INLVLA2 INLVLA1 INLVLA0 1111 1111 1111 1111
38Dh INLVLB INLVLB7 INLVLB6 INLVLB5 INLVLB4 INLVLB3 INLVLB2 INLVLB1 INLVLB0 1111 1111 1111 1111
38Eh INLVLC INLVLC7 INLVLC6 INLVLC5 INLVLC4 INLVLC3 INLVLC2 INLVLC1 INLVLC0 1111 1111 1111 1111
38Fh INLVLD(1) INLVLD7 INLVLD6 INLVLD5 INLVLD4 INLVLD3 INLVLD2 INLVLD1 INLVLD0 1111 1111 1111 1111
390h INLVLE INLVLE3 INLVLE2(1) INLVLE1(1) INLVLE0(1) ---- 1111 ---- 1111
391h IOCAP IOCAP7 IOCAP6 IOCAP5 IOCAP4 IOCAP3 IOCAP2 IOCAP1 IOCAP0 0000 0000 --00 0000
392h IOCAN IOCAN7 IOCAN6 IOCAN5 IOCAN4 IOCAN3 IOCAN2 IOCAN1 IOCAN0 0000 0000 --00 0000
393h IOCAF IOCAF7 IOCAF6 IOCAF5 IOCAF4 IOCAF3 IOCAF2 IOCAF1 IOCAF0 0000 0000 --00 0000
394h IOCBP IOCBP7 IOCBP6 IOCBP5 IOCBP4 IOCBP3 IOCBP2 IOCBP1 IOCBP0 0000 0000 0000 ----
395h IOCBN IOCBN7 IOCBN6 IOCBN5 IOCBN4 IOCBN3 IOCBN2 IOCBN1 IOCBN0 0000 0000 0000 ----
396h IOCBF IOCBF7 IOCBF6 IOCBF5 IOCBF4 IOCBF3 IOCBF2 IOCBF1 IOCBF0 0000 0000 0000 ----
397h IOCCP IOCCP7 IOCCP6 IOCCP5 IOCCP4 IOCCP3 IOCCP2 IOCCP1 IOCCP0 0000 0000 0000 0000
398h IOCCN IOCCN7 IOCCN6 IOCCN5 IOCCN4 IOCCN3 IOCCN2 IOCCN1 IOCCN0 0000 0000 0000 0000
399h IOCCF IOCCF7 IOCCF6 IOCCF5 IOCCF4 IOCCF3 IOCCF2 IOCCF1 IOCCF0 0000 0000 0000 0000
39Ah
— — Unimplemented — —
39Ch
39Dh IOCEP — — — — IOCEP3 — — — ---- 0--- ---- 0---
39Eh IOCEN — — — — IOCEN3 — — — ---- 0--- ---- 0---
39Fh IOCEF — — — — IOCEF3 — — — ---- 0--- ---- 0---
Bank 8
40Ch
— — Unimplemented — —
414h
415h TMR4 Holding Register for the 8-bit TMR4 Register 0000 0000 uuuu uuuu
416h PR4 Timer4 Period Register 1111 1111 uuuu uuuu
417h T4CON — T4OUTPS<3:0> TMR4ON T4CKPS<1:0> -000 0000 -000 0000
418h
— — Unimplemented — —
41Bh
41Ch TMR6 Holding Register for the 8-bit TMR6 Register 0000 0000 uuuu uuuu
41Dh PR6 Timer6 Period Register 1111 1111 uuuu uuuu
41Eh T6CON — T6OUTPS<3:0> TMR6ON T6CKPS<1:0> -000 0000 -000 0000
41Fh — Unimplemented — —
Bank 9
48Ch
to — Unimplemented — —
497h
498h NCO1ACCL NCO1ACC 0000 0000 0000 0000
499h NCO1ACCH NCO1ACC 0000 0000 0000 0000
49Ah NCO1ACCU NCO1ACC ---- 0000 ---- 0000
49Bh NCO1INCL NCO1INC 0000 0001 0000 0001
49Ch NCO1INCH NCO1INC 0000 0000 0000 0000
49Dh NCO1INCU NCO1INC ---- 0000 ---- 0000
49Eh NCO1CON N1EN — N1OUT N1POL — — — N1PFM 0-00 ---0 0-00 ---0
49Fh NCO1CLK N1PWS<2:0> — — — N1CKS<1:0> 000- --00 000- --00
Legend: x = unknown, u = unchanged, q = value depends on condition, - = unimplemented, read as ‘0’, r = reserved.
Shaded locations are unimplemented, read as ‘0’.
Note 1: Unimplemented on PIC16(L)F1718.
2: Unimplemented on PIC16LF1717/8/9
Bank 10
50Ch
— — Unimplemented — —
510h
511h OPA1CON OPA1EN OPA1SP — OPA1UG — — OPA1PCH<1:0> 00-0 --00 00-0 --00
512h
— — Unimplemented — —
514h
515h OPA2CON OPA2EN OPA2SP — OPA2UG — — OPA2PCH<1:0> 00-0 --00 00-0 --00
516h
— — Unimplemented — —
51Fh
Bank 11
58Ch
to — Unimplemented — —
59Fh
Bank 12
60Ch
to — Unimplemented — —
616h
617h PWM3DCL PWM3DC<1:0> — — — — — — xx-- ---- uu-- ----
618h PWM3DCH PWM3DCH<7:0> xxxx xxxx uuuu uuuu
619h PWM3CON PWM3EN — PWM3OUT PWM3POL — — — — 0-x0 ---- u-uu ----
61Ah PWM4DCL PWM4DCL<1:0> — — — — — — xx-- ---- uu-- ----
61Bh PWM4DCH PWM4DCH<7:0> xxxx xxxx uuuu uuuu
61Ch PWM4CON PWM4EN — PWM4OUT PWM4POL — — — — 0-x0 ---- u-uu ----
61Dh
— — Unimplemented — —
61Fh
Bank 13
68Ch
to — Unimplemented — —
690h
691h COG1PHR — — COG Rising Edge Phase Delay Count Register --xx xxxx --uu uuuu
692h COG1PHF — — COG Falling Edge Phase Delay Count Register --xx xxxx --uu uuuu
693h COG1BLKR — — COG Rising Edge Blanking Count Register --xx xxxx --uu uuuu
694h COG1BLKF — — COG Falling Edge Blanking Count Register --xx xxxx --uu uuuu
695h COG1DBR — — COG Rising Edge Dead-band Count Register --xx xxxx --uu uuuu
696h COG1DBF — — COG Falling Edge Dead-band Count Register --xx xxxx --uu uuuu
697h COG1CON0 G1EN G1LD — G1CS<1:0> G1MD<2:0> 00-0 0000 00-0 0000
698h COG1CON1 G1RDBS G1FDBS — — G1POLD G1POLC G1POLB G1POLA 00-- 0000 00-- 0000
699h COG1RIS G1RIS7 G1RIS6 G1RIS5 G1RIS4 G1RIS3 G1RIS2 G1RIS1 G1RIS0 0000 0000 -000 0000
69Ah COG1RSIM G1RSIM7 G1RSIM6 G1RSIM5 G1RSIM4 G1RSIM3 G1RSIM2 G1RSIM1 G1RSIM0 0000 0000 -000 0000
69Bh COG1FIS G1FIS7 G1FIS6 G1FIS5 G1FIS4 G1FIS3 G1FIS2 G1FIS1 G1FIS0 0000 0000 -000 0000
69Ch COG1FSIM G1FSIM7 G1FSIM6 G1FSIM5 G1FSIM4 G1FSIM3 G1FSIM2 G1FSIM1 G1FSIM0 0000 0000 -000 0000
69Dh COG1ASD0 G1ASE G1ARSEN G1ASDBD<1:0> G1ASDAC<1:0> — — 0001 01-- 0001 01--
69Eh COG1ASD1 — — — — G1AS3E G1AS2E G1AS1E G1AS0E ---- 0000 ---- 0000
69Fh COG1STR G1SDATD G1SDATC G1SDATB G1SDATA G1STRD G1STRC G1STRB G1STRA 0000 0001 0000 0001
Legend: x = unknown, u = unchanged, q = value depends on condition, - = unimplemented, read as ‘0’, r = reserved.
Shaded locations are unimplemented, read as ‘0’.
Note 1: Unimplemented on PIC16(L)F1718.
2: Unimplemented on PIC16LF1717/8/9
Bank 14-27
x0Ch/
x8Ch
— — Unimplemented — —
x1Fh/
x9Fh
Bank 28
E0Ch
— — Unimplemented — —
E0Eh
E0Fh PPSLOCK — — — — — — — PPSLOCKED ---- ---0 ---- ---0
E10h INTPPS — — — INTPPS<4:0> ---0 1000 ---u uuuu
E11h T0CKIPPS — — — T0CKIPPS<4:0> ---0 0100 ---u uuuu
E12h T1CKIPPS — — — T1CKIPPS<4:0> ---1 0000 ---u uuuu
E13h T1GPPS — — — T1GPPS<4:0> ---0 1101 ---u uuuu
E14h CCP1PPS — — — CCP1PPS<4:0> ---1 0010 ---u uuuu
E15h CCP2PPS — — — CCP2PPS<4:0> ---1 0001 ---u uuuu
E16h — Unimplemented — —
E17h COGINPPS — — — COGINPPS<4:0> ---0 1000 ---u uuuu
E18h — Unimplemented — —
E19h — Unimplemented — —
E1Ah
— Unimplemented — —
E1FH
E20h SSPCLKPPS — — — SSPCLKPPS<4:0> ---1 0011 ---u uuuu
E21h SSPDATPPS — — — SSPDATPPS<4:0> ---1 0100 ---u uuuu
E22h SSPSSPPS — — — SSPSSPPS<4:0> ---0 0101 ---u uuuu
E23h — Unimplemented — —
E24h RXPPS — — — RXPPS<4:0> ---1 0111 ---u uuuu
E25h CKPPS — — — CKPPS<4:0> ---1 0110 ---u uuuu
E26h — Unimplemented — —
E27h — Unimplemented — —
E28h CLCIN0PPS — — — CLCIN0PPS<4:0> ---0 0000 ---u uuuu
E29h CLCIN1PPS — — — CLCIN1PPS<4:0> ---0 0001 ---u uuuu
E2Ah CLCIN2PPS — — — CLCIN2PPS<4:0> ---0 1110 ---u uuuu
E2Bh CLCIN3PPS — — — CLCIN3PPS<4:0> ---0 1111 ---u uuuu
E2Ch
to — Unimplemented — —
E6Fh
Legend: x = unknown, u = unchanged, q = value depends on condition, - = unimplemented, read as ‘0’, r = reserved.
Shaded locations are unimplemented, read as ‘0’.
Note 1: Unimplemented on PIC16(L)F1718.
2: Unimplemented on PIC16LF1717/8/9
Bank 29
E8Ch
— — Unimplemented — —
E8Fh
E90h RA0PPS — — — RA0PPS<4:0> ---0 0000 ---u uuuu
E91h RA1PPS — — — RA1PPS<4:0> ---0 0000 ---u uuuu
E92h RA2PPS — — — RA2PPS<4:0> ---0 0000 ---u uuuu
E93h RA3PPS — — — RA3PPS4:0> ---0 0000 ---u uuuu
E94h RA4PPS — — — RA4PPS<4:0> ---0 0000 ---u uuuu
E95h RA5PPS — — — RA5PPS<4:0> ---0 0000 ---u uuuu
E96h RA6PPS — — — RA6PPS<4:0> ---0 0000 ---u uuuu
E97h RA7PPS — — — RA7PPS<4:0> ---0 0000 ---u uuuu
E98h RB0PPS — — — RB0PPS<4:0> ---0 0000 ---u uuuu
E99h RB1PPS — — — RB1PPS<4:0> ---0 0000 ---u uuuu
E9Ah RB2PPS — — — RB2PPS<4:0> ---0 0000 ---u uuuu
E9Bh RB3PPS — — — RB3PPS<4:0> ---0 0000 ---u uuuu
E9Ch RB4PPS — — — RB4PPS<4:0> ---0 0000 ---u uuuu
E9Dh RB5PPS — — — RB5PPS<4:0> ---0 0000 ---u uuuu
E9Eh RB6PPS — — — RB6PPS<4:0> ---0 0000 ---u uuuu
E9Fh RB7PPS — — — RB7PPS<4:0> ---0 0000 ---u uuuu
EA0h RC0PPS — — — RC0PPS<4:0> ---0 0000 ---u uuuu
EA1h RC1PPS — — — RC1PPS<4:0> ---0 0000 ---u uuuu
EA2h RC2PPS — — — RC2PPS<4:0> ---0 0000 ---u uuuu
EA3h RC3PPS — — — RC3PPS<4:0> ---0 0000 ---u uuuu
EA4h RC4PPS — — — RC4PPS<4:0> ---0 0000 ---u uuuu
EA5h RC5PPS — — — RC5PPS<4:0> ---0 0000 ---u uuuu
EA6h RC6PPS — — — RC6PPS<4:0> ---0 0000 ---u uuuu
EA7h RC7PPS — — — RC7PPS<4:0> ---0 0000 ---u uuuu
EA8h RD0PPS (1) — — — RD0PPS<4:0> ---0 0000 ---u uuuu
Bank 30
F0Ch
— — Unimplemented — —
F0Eh
F0Fh CLCDATA — — — — MLC4OUT MLC3OUT MLC2OUT MLC1OUT ---- 0000 ---- 0000
F10h CLC1CON LC1EN — LC1OUT LC1INTP LC1INTN LC1MODE<2:0> 0-x0 0000 0-00 0000
F11h CLC1POL LC1POL — — — LC1G4POL LC1G3POL LC1G2POL LC1G1POL x--- xxxx 0--- uuuu
F12h CLC1SEL0 — — — LC1D1S<4:0> ---x xxxx ---u uuuu
F13h CLC1SEL1 — — — LC1D2S<4:0> ---x xxxx ---u uuuu
F14h CLC1SEL2 — — — LC1D3S<4:0> ---x xxxx ---u uuuu
F15h CLC1SEL3 — — — LC1D4S<4:0> ---x xxxx ---u uuuu
F16h CLC1GLS0 LC1G1D4T LC1G1D4N LC1G1D3T LC1G1D3N LC1G1D2T LC1G1D2N LC1G1D1T LC1G1D1N xxxx xxxx uuuu uuuu
F17h CLC1GLS1 LC1G2D4T LC1G2D4N LC1G2D3T LC1G2D3N LC1G2D2T LC1G2D2N LC1G2D1T LC1G2D1N xxxx xxxx uuuu uuuu
F18h CLC1GLS2 LC1G3D4T LC1G3D4N LC1G3D3T LC1G3D3N LC1G3D2T LC1G3D2N LC1G3D1T LC1G3D1N xxxx xxxx uuuu uuuu
F19h CLC1GLS3 LC1G4D4T LC1G4D4N LC1G4D3T LC1G4D3N LC1G4D2T LC1G4D2N LC1G4D1T LC1G4D1N xxxx xxxx uuuu uuuu
F1Ah CLC2CON LC2EN — LC2OUT LC2INTP LC2INTN LC2MODE<2:0> 0-x0 0000 0-00 0000
F1Bh CLC2POL LC2POL — — — LC2G4POL LC2G3POL LC2G2POL LC2G1POL x--- xxxx 0--- uuuu
F1Ch CLC2SEL0 — — — LC2D1S<4:0> ---x xxxx ---u uuuu
F1Dh CLC2SEL1 — — — LC2D2S<4:0> ---x xxxx ---u uuuu
F1Eh CLC2SEL2 — — — LC2D3S<4:0> ---x xxxx ---u uuuu
F1Fh CLC2SEL3 — — — LC2D4S<4:0> ---x xxxx ---u uuuu
F20h CLC2GLS0 LC2G1D4T LC2G1D4N LC2G1D3T LC2G1D3N LC2G1D2T LC2G1D2N LC2G1D1T LC2G1D1N xxxx xxxx uuuu uuuu
F21h CLC2GLS1 LC2G2D4T LC2G2D4N LC2G2D3T LC2G2D3N LC2G2D2T LC2G2D2N LC2G2D1T LC2G2D1N xxxx xxxx uuuu uuuu
F22h CLC2GLS2 LC2G3D4T LC2G3D4N LC2G3D3T LC2G3D3N LC2G3D2T LC2G3D2N LC2G3D1T LC2G3D1N xxxx xxxx uuuu uuuu
F23h CLC2GLS3 LC2G4D4T LC2G4D4N LC2G4D3T LC2G4D3N LC2G4D2T LC2G4D2N LC2G4D1T LC2G4D1N xxxx xxxx uuuu uuuu
F24h CLC3CON LC3EN — LC3OUT LC3INTP LC3INTN LC3MODE<2:0> 0-x0 0000 0-00 0000
F25h CLC3POL LC3POL — — — LC3G4POL LC3G3POL LC3G2POL LC3G1POL x--- xxxx 0--- uuuu
F26h CLC3SEL0 — — — LC3D1S<4:0> ---x xxxx ---u uuuu
F27h CLC3SEL1 — — — LC3D2S<4:0> ---x xxxx ---u uuuu
F28h CLC3SEL2 — — — LC3D3S<4:0> ---x xxxx ---u uuuu
F29h CLC3SEL3 — — — LC3D4S<4:0> ---x xxxx ---u uuuu
F2Ah CLC3GLS0 LC3G1D4T LC3G1D4N LC3G1D3T LC3G1D3N LC3G1D2T LC3G1D2N LC3G1D1T LC3G1D1N xxxx xxxx uuuu uuuu
F2Bh CLC3GLS1 LC3G2D4T LC3G2D4N LC3G2D3T LC3G2D3N LC3G2D2T LC3G2D2N LC3G2D1T LC3G2D1N xxxx xxxx uuuu uuuu
F2Ch CLC3GLS2 LC3G3D4T LC3G3D4N LC3G3D3T LC3G3D3N LC3G3D2T LC3G3D2N LC3G3D1T LC3G3D1N xxxx xxxx uuuu uuuu
F2Dh CLC3GLS3 LC3G4D4T LC3G4D4N LC3G4D3T LC3G4D3N LC3G4D2T LC3G4D2N LC3G4D1T LC3G4D1N xxxx xxxx uuuu uuuu
F2Eh CLC4CON LC4EN — LC4OUT LC4INTP LC4INTN LC4MODE<2:0> 0-x0 0000 0-00 0000
F2Fh CLC4POL LC4POL — — — LC4G4POL LC4G3POL LC4G2POL LC4G1POL x--- xxxx 0--- uuuu
F30h CLC4SEL0 — — — LC4D1S<4:0> ---x xxxx ---u uuuu
F31h CLC4SEL1 — — — LC4D2S<4:0> ---x xxxx ---u uuuu
F32h CLC4SEL2 — — — LC4D3S<4:0> ---x xxxx ---u uuuu
F33h CLC4SEL3 — — — LC4D4S<4:0> ---x xxxx ---u uuuu
F34h CLC4GLS0 LC4G1D4T LC4G1D4N LC4G1D3T LC4G1D3N LC4G1D2T LC4G1D2N LC4G1D1T LC4G1D1N xxxx xxxx uuuu uuuu
F35h CLC4GLS1 LC4G2D4T LC4G2D4N LC4G2D3T LC4G2D3N LC4G2D2T LC4G2D2N LC4G2D1T LC4G2D1N xxxx xxxx uuuu uuuu
F36h CLC4GLS2 LC4G3D4T LC4G3D4N LC4G3D3T LC4G3D3N LC4G3D2T LC4G3D2N LC4G3D1T LC4G3D1N xxxx xxxx uuuu uuuu
F37h CLC4GLS3 LC4G4D4T LC4G4D4N LC4G4D3T LC4G4D3N LC4G4D2T LC4G4D2N LC4G4D1T LC4G4D1N xxxx xxxx uuuu uuuu
F38h
— — Unimplemented — —
F6Fh
Legend: x = unknown, u = unchanged, q = value depends on condition, - = unimplemented, read as ‘0’, r = reserved.
Shaded locations are unimplemented, read as ‘0’.
Note 1: Unimplemented on PIC16(L)F1718.
2: Unimplemented on PIC16LF1717/8/9
Bank 31
F8Ch
— — Unimplemented — —
FE3h
FE4h STATUS_SHAD — — — — — Z_SHAD DC_SHAD C_SHAD ---- -xxx ---- -uuu
FE5h WREG_SHAD WREG_SHAD xxxx xxxx uuuu uuuu
FE6h BSR_SHAD — — — BSR_SHAD ---x xxxx ---u uuuu
FE7h PCLATH_SHAD — PCLATH_SHAD -xxx xxxx -uuu uuuu
FE8h FSR0L_SHAD FSR0L_SHAD xxxx xxxx uuuu uuuu
FE9h FSR0H_SHAD FSR0H_SHAD xxxx xxxx uuuu uuuu
FEAh FSR1L_SHAD FSR1L_SHAD xxxx xxxx uuuu uuuu
FEBh FSR1H_SHAD FSR1H_SHAD xxxx xxxx uuuu uuuu
FECh — Unimplemented —
FEDh STKPTR — — — STKPTR ---1 1111 ---1 1111
FEEh TOSL TOSL xxxx xxxx uuuu uuuu
FEFh TOSH — TOSH -xxx xxxx -uuu uuuu
Legend: x = unknown, u = unchanged, q = value depends on condition, - = unimplemented, read as ‘0’, r = reserved.
Shaded locations are unimplemented, read as ‘0’.
Note 1: Unimplemented on PIC16(L)F1718.
2: Unimplemented on PIC16LF1717/8/9
14 PCH PCL 0
PC BRA
15
PC + OPCODE <8:0>
0x0C
0x0B
0x0A
Initial Stack Configuration:
0x09
After Reset, the stack is empty. The
0x08 empty stack is initialized so the Stack
Pointer is pointing at 0x1F. If the Stack
0x07
Overflow/Underflow Reset is enabled, the
0x06 TOSH/TOSL registers will return ‘0’. If
the Stack Overflow/Underflow Reset is
0x05 disabled, the TOSH/TOSL registers will
return the contents of stack address 0x0F.
0x04
0x03
0x02
0x01
0x00
Stack Reset Enabled
TOSH:TOSL 0x1F 0x0000 STKPTR = 0x1F
(STVREN = 1)
0x0F
0x0E
0x0D
0x0C
0x0B
0x0A
0x09 This figure shows the stack configuration
after the first CALL or a single interrupt.
0x08 If a RETURN instruction is executed, the
0x07 return address will be placed in the
Program Counter and the Stack Pointer
0x06 decremented to the empty state (0x1F).
0x05
0x04
0x03
0x02
0x01
TOSH:TOSL 0x00 Return Address STKPTR = 0x00
0x0F
0x0E
0x0D
0x0C
After seven CALLs or six CALLs and an
0x0B interrupt, the stack looks like the figure
on the left. A series of RETURN instructions
0x0A will repeatedly place the return addresses
into the Program Counter and pop the stack.
0x09
0x08
0x07
TOSH:TOSL 0x06 Return Address STKPTR = 0x06
0x0000 0x0000
Traditional
Data Memory
0x0FFF 0x0FFF
0x1000
Reserved
0x1FFF
0x2000
Linear
Data Memory
0x29AF
0x29B0
FSR Reserved
0x7FFF
Address
Range 0x8000 0x0000
Program
Flash Memory
0xFFFF 0x7FFF
Note: Not all memory regions are completely implemented. Consult device memory tables for memory limits.
0x7F
Bank 0 Bank 1 Bank 2 Bank 31
0xF20
Bank 30 0x7FFF
0xFFFF
0x29AF 0xF6F
Legend:
R = Readable bit P = Programmable bit U = Unimplemented bit, read as ‘1’
‘0’ = Bit is cleared ‘1’ = Bit is set -n = Value when blank or after Bulk Erase
Note 1: The entire Flash program memory will be erased when the code protection is turned off during an erase.
When a Bulk Erase Program Memory command is executed, the entire program Flash memory and
configuration memory will be erased.
Legend:
R = Readable bit P = Programmable bit U = Unimplemented bit, read as ‘1’
‘0’ = Bit is cleared ‘1’ = Bit is set -n = Value when blank or after Bulk Erase
Note 1: The LVP bit cannot be programmed to ‘0’ when Programming mode is entered via LVP.
2: The DEBUG bit in Configuration Words is managed automatically by device development tools including debuggers
and programmers. For normal device operation, this bit should be maintained as a ‘1’.
3: See VBOR parameter for specific trip point voltages.
4.5 User ID
Four memory locations (8000h-8003h) are designated
as ID locations where the user can store checksum or
other code identification numbers. These locations are
readable and writable during normal execution. See
Section 10.4 “User ID, Device ID and Configuration
Word Access” for more information on accessing
these memory locations. For more information on
checksum calculation, see the “PIC16(L)F170X
Memory Programming Specification” (DS41683).
R R R R R R R R
DEV<7:0>
bit 7 bit 0
Legend:
R = Readable bit
‘1’ = Bit is set ‘0’ = Bit is cleared
R R R R R R R R
REV<7:0>
bit 7 bit 0
Legend:
R = Readable bit
‘1’ = Bit is set ‘0’ = Bit is cleared
Stack Underflow
Stack Overlfow
MCLRE
VPP/MCLR
Sleep
WDT
Time-out Device
Reset
Power-on
Reset
VDD
BOR
Active(1)
Brown-out R
Power-up
Reset
Timer
LFINTOSC
LPBOR PWRTE
Reset
VDD
VBOR
Internal
Reset TPWRT(1)
VDD
VBOR
VDD
VBOR
Internal
Reset TPWRT(1)
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets
‘1’ = Bit is set ‘0’ = Bit is cleared q = Value depends on condition
VDD
Internal POR
TPWRT
Power-up Timer
MCLR
TMCLR
Internal RESET
Oscillator Modes
External Crystal
TOST
Oscillator Start-up Timer
Oscillator
FOSC
Internal Oscillator
Oscillator
FOSC
CLKIN
FOSC
0 0 1 1 1 0 x 1 1 Power-on Reset
0 0 1 1 1 0 x 0 x Illegal, TO is set on POR
0 0 1 1 1 0 x x 0 Illegal, PD is set on POR
0 0 u 1 1 u 0 1 1 Brown-out Reset
u u 0 u u u u 0 u WDT Reset
u u u u u u u 0 0 WDT Wake-up from Sleep
u u u u u u u 1 0 Interrupt Wake-up from Sleep
u u u 0 u u u u u MCLR Reset during normal operation
u u u 0 u u u 1 0 MCLR Reset during Sleep
u u u u 0 u u u u RESET Instruction Executed
1 u u u u u u u u Stack Overflow Reset (STVREN = 1)
u 1 u u u u u u u Stack Underflow Reset (STVREN = 1)
Legend:
HC = Bit is cleared by hardware HS = Bit is set by hardware
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
u = Bit is unchanged x = Bit is unknown -m/n = Value at POR and BOR/Value at all other Resets
‘1’ = Bit is set ‘0’ = Bit is cleared q = Value depends on condition
PLLMUX
IRCF<3:0>
INTOSC
16 MHz 1X
1111
8 MHz
Internal
Oscillator 4 MHz
Block 2 MHz SCS<1:0>
Postscaler
1 MHz
HFPLL
MUX
16 MHz 500 kHz
(HFINTOSC) 250 kHz
125 kHz
500 kHz
Source 500 kHz 62.5 kHz
(MFINTOSC) 31.25 kHz
31 kHz 31 kHz
Source 0000
Inputs Outputs
PLLEN or
SCS FOSC<2:0> IRCF PRIMUX PLLMUX
SPLLEN
0 x 1 0
=100 =1110 1 1
1
=00 ≠1110 1 0
0 x 0 0
≠100
1 x 0 1
≠00 X X X X X
OSC1/CLKIN OSC1/CLKIN
C1 To Internal C1 To Internal
Logic Logic
Quartz
RF(2) Sleep RP(3)
Crystal RF(2) Sleep
C2 OSC2/CLKOUT
RS(1) OSC2/CLKOUT
C2 Ceramic RS(1)
Resonator
Note 1: A series resistor (RS) may be required for
quartz crystals with low drive level. Note 1: A series resistor (RS) may be required for
ceramic resonators with low drive level.
2: The value of RF varies with the Oscillator mode
selected (typically between 2 M to 10 M. 2: The value of RF varies with the Oscillator mode
selected (typically between 2 M to 10 M.
3: An additional parallel feedback resistor (RP)
may be required for proper ceramic resonator
Note 1: Quartz crystal characteristics vary operation.
according to type, package and
manufacturer. The user should consult the
manufacturer data sheets for specifications 6.2.1.3 Oscillator Start-up Timer (OST)
and recommended application. If the oscillator module is configured for LP, XT or HS
2: Always verify oscillator performance over modes, the Oscillator Start-up Timer (OST) counts
the VDD and temperature range that is 1024 oscillations from OSC1. This occurs following a
expected for the application. Power-on Reset (POR) and when the Power-up Timer
3: For oscillator design assistance, reference (PWRT) has expired (if configured), or a wake-up from
the following Microchip Application Notes: Sleep. During this time, the program counter does not
increment and program execution is suspended,
• AN826, “Crystal Oscillator Basics and unless either FSCM or Two-Speed Start-Up are
Crystal Selection for rfPIC® and PIC® enabled. In this case, code will continue to execute at
Devices” (DS00826) the selected INTOSC frequency while the OST is
• AN849, “Basic PIC® Oscillator Design” counting. The OST ensures that the oscillator circuit,
(DS00849) using a quartz crystal resonator or ceramic resonator,
• AN943, “Practical PIC® Oscillator has started and is providing a stable system clock to
Analysis and Design” (DS00943) the oscillator module.
• AN949, “Making Your Oscillator Work” In order to minimize latency between external oscillator
(DS00949) start-up and code execution, the Two-Speed Clock
Start-up mode can be selected (see Section 6.4
“Two-Speed Clock Start-up Mode”).
PIC® MCU
SOSCI
C1 To Internal
Logic
32.768 kHz
Quartz
Crystal
C2 SOSCO
A fast start-up oscillator allows internal circuits to power OSCTUNE does not affect the LFINTOSC frequency.
up and stabilize before switching to HFINTOSC. Operation of features that depend on the LFINTOSC
clock source frequency, such as the Power-up Timer
The High-Frequency Internal Oscillator Ready bit (PWRT), Watchdog Timer (WDT), Fail-Safe Clock
(HFIOFR) of the OSCSTAT register indicates when the Monitor (FSCM) and peripherals, are not affected by the
HFINTOSC is running. change in frequency.
The High-Frequency Internal Oscillator Status Locked
bit (HFIOFL) of the OSCSTAT register indicates when 6.2.2.4 LFINTOSC
the HFINTOSC is running within 2% of its final value. The Low-Frequency Internal Oscillator (LFINTOSC) is
The High-Frequency Internal Oscillator Stable bit an uncalibrated 31 kHz internal clock source.
(HFIOFS) of the OSCSTAT register indicates when the The output of the LFINTOSC connects to a multiplexer
HFINTOSC is running within 0.5% of its final value. (see Figure 6-1). Select 31 kHz, via software, using the
IRCF<3:0> bits of the OSCCON register. See
6.2.2.2 MFINTOSC Section 6.2.2.7 “Internal Oscillator Clock Switch
The Medium Frequency Internal Oscillator Timing” for more information. The LFINTOSC is also
(MFINTOSC) is a factory calibrated 500 kHz internal the frequency for the Power-up Timer (PWRT),
clock source. The frequency of the MFINTOSC can be Watchdog Timer (WDT) and Fail-Safe Clock Monitor
altered via software using the OSCTUNE register (FSCM).
(Register 6-3). The LFINTOSC is enabled by selecting 31 kHz
The output of the MFINTOSC connects to a postscaler (IRCF<3:0> bits of the OSCCON register = 000) as the
and multiplexer (see Figure 6-1). One of nine system clock source (SCS bits of the OSCCON
frequencies derived from the MFINTOSC can be register = 1x), or when any of the following are
selected via software using the IRCF<3:0> bits of the enabled:
OSCCON register. See Section 6.2.2.7 “Internal • Configure the IRCF<3:0> bits of the OSCCON
Oscillator Clock Switch Timing” for more information. register for the desired LF frequency, and
The MFINTOSC is enabled by: • FOSC<2:0> = 100, or
• Configure the IRCF<3:0> bits of the OSCCON • Set the System Clock Source (SCS) bits of the
register for the desired HF frequency, and OSCCON register to ‘1x’
• FOSC<2:0> = 100, or Peripherals that use the LFINTOSC are:
• Set the System Clock Source (SCS) bits of the • Power-up Timer (PWRT)
OSCCON register to ‘1x’ • Watchdog Timer (WDT)
The Medium Frequency Internal Oscillator Ready bit • Fail-Safe Clock Monitor (FSCM)
(MFIOFR) of the OSCSTAT register indicates when the The Low-Frequency Internal Oscillator Ready bit
MFINTOSC is running. (LFIOFR) of the OSCSTAT register indicates when the
LFINTOSC is running.
LFINTOSC
System Clock
LFINTOSC
System Clock
LFINTOSC HFINTOSC/MFINTOSC
LFINTOSC turns off unless WDT or FSCM is enabled
LFINTOSC
Start-up Time 2-cycle Sync Running
HFINTOSC/
MFINTOSC
IRCF <3:0> =0 0
System Clock
INTOSC
TOST
OSC2
Program Counter PC - N PC PC + 1
System Clock
Sample Clock
System Oscillator
Clock Failure
Output
Note: The system clock is normally at a much higher frequency than the sample clock. The relative frequencies in
this example have been chosen for clarity.
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets
‘1’ = Bit is set ‘0’ = Bit is cleared
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets
‘1’ = Bit is set ‘0’ = Bit is cleared q = Conditional
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets
‘1’ = Bit is set ‘0’ = Bit is cleared
TMR0IF Wake-up
TMR0IE (If in Sleep mode)
INTF
Peripheral Interrupts INTE
(TMR1IF) PIR1<0>
IOCIF
(TMR1IE) PIE1<0> Interrupt
IOCIE to CPU
PEIE
PIRn<7>
GIE
PIEn<7>
OSC1
Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4
Interrupt
GIE
Interrupt
GIE
Interrupt
GIE
Interrupt
GIE
Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4
OSC1
CLKOUT (3)
(4)
INT pin
(1)
(1)
INTF (5) Interrupt Latency (2)
GIE
INSTRUCTION FLOW
PC PC PC + 1 PC + 1 0004h 0005h
Instruction
Fetched Inst (PC) Inst (PC + 1) — Inst (0004h) Inst (0005h)
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets
‘1’ = Bit is set ‘0’ = Bit is cleared
Note 1: The IOCIF Flag bit is read-only and cleared when all the interrupt-on-change flags in the IOCxF registers
have been cleared by software.
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets
‘1’ = Bit is set ‘0’ = Bit is cleared
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets
‘1’ = Bit is set ‘0’ = Bit is cleared
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets
‘1’ = Bit is set ‘0’ = Bit is cleared
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets
‘1’ = Bit is set ‘0’ = Bit is cleared
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets
‘1’ = Bit is set ‘0’ = Bit is cleared
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets
‘1’ = Bit is set ‘0’ = Bit is cleared
Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4
CLKIN(1)
CLKOUT(2) TOST(3)
GIE bit
(INTCON reg.) Processor in
Sleep
Instruction Flow
PC PC PC + 1 PC + 2 PC + 2 PC + 2 0004h 0005h
Instruction Inst(PC + 1) Inst(PC + 2) Inst(0004h) Inst(0005h)
Fetched Inst(PC) = Sleep
Instruction Sleep Inst(PC + 1) Forced NOP Forced NOP
Executed Inst(PC - 1) Inst(0004h)
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets
‘1’ = Bit is set ‘0’ = Bit is cleared
WDTE<1:0> = 01
SWDTEN
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
u = Bit is unchanged x = Bit is unknown -m/n = Value at POR and BOR/Value at all other Resets
‘1’ = Bit is set ‘0’ = Bit is cleared
The Flash program memory can be protected in two The PMCON2 register is a write-only register. Attempting
ways; by code protection (CP bit in Configuration Words) to read the PMCON2 register will return all ‘0’s.
and write protection (WRT<1:0> bits in Configuration To enable writes to the program memory, a specific
Words). pattern (the unlock sequence), must be written to the
Code protection (CP = 0)(1), disables access, reading PMCON2 register. The required unlock sequence
and writing, to the Flash program memory via external prevents inadvertent writes to the program memory
device programmers. Code protection does not affect write latches and Flash program memory.
the self-write and erase functionality. Code protection
can only be reset by a device programmer performing 10.2 Flash Program Memory Overview
a Bulk Erase to the device, clearing all Flash program
It is important to understand the Flash program memory
memory, Configuration bits and User IDs.
structure for erase and programming operations. Flash
Write protection prohibits self-write and erase to a program memory is arranged in rows. A row consists of
portion or all of the Flash program memory as defined a fixed number of 14-bit program memory words. A row
by the bits WRT<1:0>. Write protection does not affect is the minimum size that can be erased by user software.
a device programmers ability to read, write or erase the
After a row has been erased, the user can reprogram
device.
all or a portion of this row. Data to be written into the
Note 1: Code protection of the entire Flash program memory row is written to 14-bit wide data write
program memory array is enabled by latches. These write latches are not directly accessible
clearing the CP bit of Configuration Words. to the user, but may be loaded via sequential writes to
the PMDATH:PMDATL register pair.
Note: If the user wants to modify only a portion
of a previously programmed row, then the
contents of the entire row must be read
and saved in RAM prior to the erase.
Then, new data and retained data can be
written into the write latches to reprogram
the row of Flash program memory.
However, any unprogrammed locations
can be written without first erasing the row.
In this case, it is not necessary to save and
rewrite the other previously programmed
locations.
Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4
Flash Data INSTR (PC) INSTR (PC + 1) PMDATH,PMDATL INSTR (PC + 3) INSTR (PC + 4)
INSTR(PC + 1) INSTR(PC + 2)
INSTR(PC - 1) BSF PMCON1,RD instruction ignored instruction ignored INSTR(PC + 3) INSTR(PC + 4)
executed here executed here Forced NOP Forced NOP executed here executed here
executed here executed here
RD bit
PMDATH
PMDATL
Register
Unlock Sequence
Figure 10-3
(FIGURE x-x)
Re-enable Interrupts
(GIE = 1)
End
Erase Operation
MOVLW 0AAh ;
MOVWF PMCON2 ; Write AAh
BSF PMCON1,WR ; Set WR bit to begin erase
NOP ; NOP instructions are forced as processor starts
NOP ; row erase of program memory.
;
; The processor stalls until the erase process is complete
; after erase processor continues with 3rd instruction
PIC16(L)F1717/8/9
Rev. 10-000004A
7 6 0 7 5 4 0 7 5 0 7 0 7/30/2013
14
Write Latch #0 Write Latch #1 Write Latch #30 Write Latch #31
PMADRL<4:0> 00h 01h 1Eh 1Fh
14 14 14 14
400h 8000h - 8003h 8004h – 8005h 8006h 8007h – 8008h 8009h - 801Fh
DEVICE ID Configuration
USER ID 0 - 3 reserved reserved
CFGS = 1 Dev / Rev Words
Configuration Memory
PIC16(L)F1717/8/9
FIGURE 10-6: FLASH PROGRAM MEMORY WRITE FLOWCHART
Start
Write Operation
Unlock Sequence
Select
Last word to Yes (Figure10-3
Figure x-x)
Program or Config. Memory
(CFGS) write ?
Re-enable Interrupts
(GIE = 1)
Increment Address
(PMADRH:PMADRL++)
End
Write Operation
START_WRITE
BCF PMCON1,LWLO ; No more loading latches - Actually start Flash program
; memory write
MOVLW 0AAh ;
Required
Start
Modify Operation
Read Operation
(Figure10-1
Figure x.x)
Modify Image
The words to be modified are
changed in the RAM image
Erase Operation
(Figure10-4
Figure x.x)
Write Operation
use RAM image
(Figure10-6
Figure x.x)
End
Modify Operation
Start
Verify Operation
Read Operation
(Figure
Figure x.x)
10-1
PMDAT = No
RAM image
?
Yes Fail
Verify Operation
No Last
Word ?
Yes
End
Verify Operation
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets
‘1’ = Bit is set ‘0’ = Bit is cleared
bit 7-0 PMDAT<7:0>: Read/write value for Least Significant bits of program memory
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets
‘1’ = Bit is set ‘0’ = Bit is cleared
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets
‘1’ = Bit is set ‘0’ = Bit is cleared
bit 7-0 PMADR<7:0>: Specifies the Least Significant bits for program memory address
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets
‘1’ = Bit is set ‘0’ = Bit is cleared
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
S = Bit can only be set x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets
‘1’ = Bit is set ‘0’ = Bit is cleared HC = Bit is cleared by hardware
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
S = Bit can only be set x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets
‘1’ = Bit is set ‘0’ = Bit is cleared
PORTC
PORTD
PORTA
PORTE
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets
‘1’ = Bit is set ‘0’ = Bit is cleared
Note 1: Writes to PORTA are actually written to corresponding LATA register. Reads from PORTA register is return
of actual I/O pin values.
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets
‘1’ = Bit is set ‘0’ = Bit is cleared
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets
‘1’ = Bit is set ‘0’ = Bit is cleared
Note 1: Writes to PORTA are actually written to corresponding LATA register. Reads from PORTA register is return
of actual I/O pin values.
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets
‘1’ = Bit is set ‘0’ = Bit is cleared
Note 1: When setting a pin to an analog input, the corresponding TRIS bit must be set to Input mode in order to
allow external control of the voltage on the pin.
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets
‘1’ = Bit is set ‘0’ = Bit is cleared
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets
‘1’ = Bit is set ‘0’ = Bit is cleared
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets
‘1’ = Bit is set ‘0’ = Bit is cleared
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets
‘1’ = Bit is set ‘0’ = Bit is cleared
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets
‘1’ = Bit is set ‘0’ = Bit is cleared
Note 1: Writes to PORTB are actually written to corresponding LATB register. Reads from PORTB register is
return of actual I/O pin values.
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets
‘1’ = Bit is set ‘0’ = Bit is cleared
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets
‘1’ = Bit is set ‘0’ = Bit is cleared
Note 1: Writes to PORTB are actually written to corresponding LATB register. Reads from PORTB register is
return of actual I/O pin values.
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets
‘1’ = Bit is set ‘0’ = Bit is cleared
Note 1: When setting a pin to an analog input, the corresponding TRIS bit must be set to Input mode in order to
allow external control of the voltage on the pin.
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets
‘1’ = Bit is set ‘0’ = Bit is cleared
Note 1: Global WPUEN bit of the OPTION_REG register must be cleared for individual pull-ups to be enabled.
2: The weak pull-up device is automatically disabled if the pin is configured as an output.
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets
‘1’ = Bit is set ‘0’ = Bit is cleared
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets
‘1’ = Bit is set ‘0’ = Bit is cleared
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets
‘1’ = Bit is set ‘0’ = Bit is cleared
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets
‘1’ = Bit is set ‘0’ = Bit is cleared
Note 1: Writes to PORTC are actually written to corresponding LATC register. Reads from PORTC register is
return of actual I/O pin values.
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets
‘1’ = Bit is set ‘0’ = Bit is cleared
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets
‘1’ = Bit is set ‘0’ = Bit is cleared
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets
‘1’ = Bit is set ‘0’ = Bit is cleared
bit 7-2 ANSC<7:2>: Analog Select between Analog or Digital Function on Pins RC<7:2>, respectively(1)
0 = Digital I/O. Pin is assigned to port or digital special function.
1 = Analog input. Pin is assigned as analog input(1). Digital input buffer disabled.
bit 1-0 Unimplemented: Read as ‘0’
Note 1: When setting a pin to an analog input, the corresponding TRIS bit must be set to Input mode in order to
allow external control of the voltage on the pin.
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets
‘1’ = Bit is set ‘0’ = Bit is cleared
Note 1: Global WPUEN bit of the OPTION_REG register must be cleared for individual pull-ups to be enabled.
2: The weak pull-up device is automatically disabled if the pin is configured as an output.
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets
‘1’ = Bit is set ‘0’ = Bit is cleared
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets
‘1’ = Bit is set ‘0’ = Bit is cleared
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets
‘1’ = Bit is set ‘0’ = Bit is cleared
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets
‘1’ = Bit is set ‘0’ = Bit is cleared
Note 1: Writes to PORTD are actually written to corresponding LATD register. Reads from PORTD register is
return of actual I/O pin values.
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets
‘1’ = Bit is set ‘0’ = Bit is cleared
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets
‘1’ = Bit is set ‘0’ = Bit is cleared
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets
‘1’ = Bit is set ‘0’ = Bit is cleared
bit 7-0 ANSD<7:0>: Analog Select between Analog or Digital Function on Pins RD<7:0>, respectively(1)
0 = Digital I/O. Pin is assigned to port or digital special function.
1 = Analog input. Pin is assigned as analog input(1). Digital input buffer disabled.
Note 1: When setting a pin to an analog input, the corresponding TRIS bit must be set to Input mode in order to
allow external control of the voltage on the pin.
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets
‘1’ = Bit is set ‘0’ = Bit is cleared
Note 1: Global WPUEN bit of the OPTION_REG register must be cleared for individual pull-ups to be enabled.
2: The weak pull-up device is automatically disabled if the pin is configured as an output.
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets
‘1’ = Bit is set ‘0’ = Bit is cleared
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets
‘1’ = Bit is set ‘0’ = Bit is cleared
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets
‘1’ = Bit is set ‘0’ = Bit is cleared
ANSELD ANSD7 ANSD6 ANSD5 ANSD4 ANSD3 ANSD2 ANSD1 ANSD0 141
INLVLD INLVLD7 INLVLD6 INLVLD5 INLVLD4 INLVLD3 INLVLD2 INLVLD1 INLVLD0 142
LATD LATD7 LATD6 LATD5 LATD4 LATD3 LATD2 LATD1 LATD0 140
ODCOND ODD7 ODD6 ODD5 ODD4 ODD3 ODD2 ODD1 ODD0 142
PORTD RD7 RD6 RD5 RD4 RD3 RD2 RD1 RD0 140
SLRCOND SLRD7 SLRD6 SLRD5 SLRD4 SLRD3 SLRD2 SLRD1 SLRD0 142
TRISD TRISD7 TRISD6 TRISD5 TRISD4 TRISD3 TRISD2 TRISD1 TRISD0 140
WPUD WPUD7 WPUD6 WPUD5 WPUD4 WPUD3 WPUD2 WPUD1 WPUD0 141
Legend: x = unknown, u = unchanged, - = unimplemented locations read as ‘0’. Shaded cells are not used by
PORTD.
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets
‘1’ = Bit is set ‘0’ = Bit is cleared
Note 1: Writes to PORTE are actually written to corresponding LATE register. Reads from PORTE register is
return of actual I/O pin values.
2: PIC16(L)F1717/9 only.
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets
‘1’ = Bit is set ‘0’ = Bit is cleared
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets
‘1’ = Bit is set ‘0’ = Bit is cleared
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets
‘1’ = Bit is set ‘0’ = Bit is cleared
Note 1: When setting a pin to an analog input, the corresponding TRIS bit must be set to Input mode in order to
allow external control of the voltage on the pin.
2: PIC16(L)F1717/9 only.
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets
‘1’ = Bit is set ‘0’ = Bit is cleared
Note 1: Global WPUEN bit of the OPTION_REG register must be cleared for individual pull-ups to be enabled.
2: The weak pull-up device is automatically disabled if the pin is configured as an output.
3: PIC16(L)F1717/9 only.
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets
‘1’ = Bit is set ‘0’ = Bit is cleared
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets
‘1’ = Bit is set ‘0’ = Bit is cleared
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets
‘1’ = Bit is set ‘0’ = Bit is cleared
abcPPS RA0
RA0
Peripheral abc
RxyPPS
Rxy
Peripheral xyz
RC7 RC7PPS
xyzPPS RC7
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets
‘1’ = Bit is set ‘0’ = Bit is cleared q = value depends on peripheral
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets
‘1’ = Bit is set ‘0’ = Bit is cleared
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets
‘1’ = Bit is set ‘0’ = Bit is cleared
IOCANx D Q
R Q4Q1
edge
detect
RAx
to data bus
data bus = S
IOCAPx D Q D Q IOCAFx
0 or 1
R
write IOCAFx R
IOCIE
Q2
IOC interrupt
to CPU core
from all other
IOCnFx individual
pin detectors
FOSC
Q1 Q1 Q1
Q2 Q2 Q2
Q3 Q3 Q3
Q4 Q4 Q4
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets
‘1’ = Bit is set ‘0’ = Bit is cleared
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets
‘1’ = Bit is set ‘0’ = Bit is cleared
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets
‘1’ = Bit is set ‘0’ = Bit is cleared HS - Bit is set in hardware
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets
‘1’ = Bit is set ‘0’ = Bit is cleared
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets
‘1’ = Bit is set ‘0’ = Bit is cleared
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets
‘1’ = Bit is set ‘0’ = Bit is cleared HS - Bit is set in hardware
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets
‘1’ = Bit is set ‘0’ = Bit is cleared
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets
‘1’ = Bit is set ‘0’ = Bit is cleared
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets
‘1’ = Bit is set ‘0’ = Bit is cleared HS - Bit is set in hardware
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets
‘1’ = Bit is set ‘0’ = Bit is cleared
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets
‘1’ = Bit is set ‘0’ = Bit is cleared
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets
‘1’ = Bit is set ‘0’ = Bit is cleared HS - Bit is set in hardware
ADFVR<1:0>
2
X1
X2 FVR BUFFER1
X4 (To ADC Module)
CDAFVR<1:0> 2
X1
X2 FVR BUFFER2
X4 (To Comparators, DAC)
HFINTOSC Enable
HFINTOSC
To BOR, LDO
+
FVREN
_ FVRRDY
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets
‘1’ = Bit is set ‘0’ = Bit is cleared q = Value depends on condition
VIN+ +
Output
VIN- –
VIN-
VIN+
Output
det
CXIN0- 0 Set CxIF
CXIN1- 1
2 MUX Interrupt CxINTN
CXIN2-
(2)
det
CXIN3- 3
CXPOL
Reserved 4 CxVN
-
0 to CMXCON0 (CXOUT)
Reserved 5 D Q
Cx and CM2CON1 (MCXOUT)
FVR Buffer2 + ZLF 1
6
CxVP
Q1 EN
7
CxHYS
AGND CxZLF
CxSP
async_CxOUT
CXSYNC
TRIS bit
CXOUT
0
D Q 1
CXIN0+ 0 From Timer1
tmr1_clk sync_CxOUT
CxIN1+ 1 To Timer1
MUX
(2)
Reserved 2
Reserved 3
DAC2_Output 4
DAC1_Output 5
FVR Buffer2 6
AGND CxON
CXPCH<2:0>
3
Note 1: When CxON = 0, the comparator will produce a ‘0’ at the output.
2: When CxON = 0, all multiplexer inputs are disconnected.
CPIN ILEAKAGE(1)
VA VT 0.6V
5 pF
Vss
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets
‘1’ = Bit is set ‘0’ = Bit is cleared
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets
‘1’ = Bit is set ‘0’ = Bit is cleared
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets
‘1’ = Bit is set ‘0’ = Bit is cleared
PWMxDCH
Latched PWMxOUT
(Not visible to user)
to other peripherals: CLC and CWG
Comparator R Q 0 PWMx
S Q 1
TMR2 Module
Comparator
Clear Timer,
PR2 PWMx pin and
latch Duty Cycle
Note 1: 8-bit timer is concatenated with the two Least Significant bits of 1/FOSC adjusted by the Timer2 prescaler to
create a 10-bit time base.
Pulse Width
TMR2 = PR2
TMR2 =
PWMxDCH<7:0>:PWMxDCL<7:6>
TMR2 = 0
log 4 PR2 + 1
Resolution = ------------------------------------------ bits
log 2
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets
‘1’ = Bit is set ‘0’ = Bit is cleared
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets
‘1’ = Bit is set ‘0’ = Bit is cleared
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets
‘1’ = Bit is set ‘0’ = Bit is cleared
V+
FET QA QC FET
Driver Driver
COGxA
Load
COGxB
FET FET
Driver Driver
COGxC
QB QD
PIC16(L)F1717/8/9
V-
COGxD
DS40001740B-page 185
PIC16(L)F1717/8/9
18.1.3 HALF-BRIDGE MODE It may be necessary to guard against the possibility of
circuit faults. In this case, the active drive must be ter-
In half-bridge mode, the COG generates a two output
minated before the Fault condition causes damage.
complementary PWM waveform from rising and falling
This is referred to as auto-shutdown and is covered in
event sources. In the simplest configuration, the rising
Section 18.8 “Auto-shutdown Control”.
and falling event sources are the same signal, which is
a PWM signal with the desired period and duty cycle. The COG can be configured to operate in phase
The COG converts this single PWM input into a dual delayed conjunction with another PWM. The active
complementary PWM output. The frequency and duty drive cycle is delayed from the rising event by a phase
cycle of the dual PWM output match those of the single delay timer. Phase delay is covered in more detail in
input PWM signal. The off-to-on transition of each out- Section 18.7 “Phase Delay”.
put can be delayed from the on-to-off transition of the A typical operating waveform, with phase delay and
other output, thereby, creating a time immediately after dead band, generated from a single CCP1 input is
the PWM transition where neither output is driven. This shown in Figure 18-10.
is referred to as dead time and is covered in
Section 18.5 “Dead-Band Control”.
A typical operating waveform, with dead band, generated
from a single CCP1 input is shown in Figure 18-9.
The primary output can be steered to either or both
COGxA and COGxC. The complementary output can be
steered to either or both COGxB and COGxD.
Half-Bridge mode is selected by setting the GxMD bits
of the COGxCON0 register to ‘100’.
PIC16(L)F1717/8/9
GxASDAC<1:0>
‘1’ 11
‘0’ 10
High-Z 01
reserved 11 00
HFINTOSC 10 COG_clock 1 COGxA
FOSC 01 1
FOSC/4 00 0
GxPOLA GxSDATA 0
GxCS<1:0> Rising Input Block GxSTRA GxASDBD<1:0>
NCO1_out src7 clock
src6 ‘1’ 11
PWM3OUT
src5 Reset Dominates ‘0’ 10
CCP2
src4 High-Z 01
CCP1 rising_event S Q 00
LC1_out src3 1 COGxB
C2OUT src2 R Q 1
C1OUT src1 0
COGINPPS src0 count_en GxSDATB 0
GxPOLB
GxSTRB GxASDAC<1:0>
Falling Input Block
NCO1_out src7 ‘1’ 11
src6 clock ‘0’ 10
PWM3OUT
CCP2 src5 High-Z 01
src4 00
CCP1
LC1_out src3 falling_event 1 COGxC
C2OUT src2 1
C1OUT src1 0
COGINPPS GxSDATC 0
src0 count_en GxPOLC
GxSTRC GxASDBD<1:0>
‘1’ 11
‘0’ 10
GxEN
High-Z 01
00
2014-2015 Microchip Technology Inc.
1 COGxD
COGINPPS 1
GxAS0E 0
C1OUT GxSDATD 0
GxPOLD
GxAS1E Auto-shutdown source
GxSTRD
C2OUT
GxAS2E
LC2_out S Q GxASE
GxAS3E GxARSEN S
Write GxASE Low R D Q
Write GxASE High Set Dominates
FIGURE 18-3: SIMPLIFIED COG BLOCK DIAGRAM (SYNCHRONOUS STEERED PWM MODE, GXMD = 1)
2014-2015 Microchip Technology Inc.
GxASDAC<1:0>
‘1’ 11
‘0’ 10
High-Z 01
reserved 11 00
HFINTOSC 10 COG_clock 1 COGxA
FOSC 01 1
FOSC/4 00 0
GxPOLA GxSDATA 0
GxCS<1:0> Rising Input Block GxSTRA D Q GxASDBD<1:0>
NCO1_out src7 clock
src6 ‘1’ 11
PWM3OUT
src5 Reset Dominates ‘0’ 10
CCP2
src4 High-Z 01
CCP1 rising_event S Q 00
LC1_out src3 1 COGxB
C2OUT src2 R Q 1
C1OUT src1 0
COGINPPS src0 count_en GxSDATB 0
GxPOLB
GxSTRB D Q GxASDAC<1:0>
Falling Input Block
NCO1_out src7 ‘1’ 11
src6 clock ‘0’ 10
PWM3OUT
CCP2 src5 High-Z 01
src4 00
CCP1
LC1_out src3 falling_event 1 COGxC
C2OUT src2 1
C1OUT src1 0
COGINPPS GxSDATC 0
src0 count_en GxPOLC
D Q
PIC16(L)F1717/8/9
GxSTRC GxASDBD<1:0>
‘1’ 11
‘0’ 10
GxEN
High-Z 01
00
1 COGxD
COGINPPS 1
GxAS0E 0
C1OUT GxSDATD 0
GxPOLD
GxAS1E Auto-shutdown source
GxSTRD D Q
C2OUT
DS40001740B-page 188
GxAS2E
LC2_out S Q GxASE
GxAS3E GxARSEN S
Write GxASE Low R D Q
Write GxASE High Set Dominates
FIGURE 18-4: SIMPLIFIED COG BLOCK DIAGRAM (FULL-BRIDGE MODES, FORWARD: GXMD = 2, REVERSE: GXMD = 3)
DS40001740B-page 189
PIC16(L)F1717/8/9
GxASDAC<1:0>
‘1’ 11
‘0’ 10
High-Z 01
reserved 11 00
HFINTOSC 10 COG_clock 1 COGxA
FOSC 01
FOSC/4 0
00
Rising Dead-Band Block
GxCS<1:0> GxPOLA
Rising Input Block GxASDBD<1:0>
clock
NCO1_out src7 clock signal_out
src6 ‘1’ 11
PWM3OUT signal_in
src5 Reset Dominates ‘0’ 10
CCP2
src4 High-Z 01
CCP1 rising_event S Q 00
LC1_out src3 1 COGxB
C2OUT src2 R Q
C1OUT src1 0
COGINPPS src0 count_en
GxPOLB GxASDAC<1:0>
Falling Input Block Falling Dead-Band Block
NCO1_out src7 ‘1’ 11
clock clock ‘0’ 10
PWM3OUT src6
signal_out High-Z 01
CCP2 src5
src4 signal_in 00
CCP1
LC1_out src3 falling_event 1 COGxC
C2OUT src2
C1OUT src1 0
COGINPPS src0 count_en
GxPOLC GxASDBD<1:0>
Forward/Reverse
GxMD0 D Q ‘1’ 11
‘0’ 10
GxEN
Q High-Z 01
00
2014-2015 Microchip Technology Inc.
1
COGINPPS COGxD
GxAS0E 0
C1OUT
GxAS1E Auto-shutdown source GxPOLD
C2OUT
GxAS2E
LC2_out S Q GxASE
GxAS3E GxARSEN S
Write GxASE Low R D Q
Write GxASE High Set Dominates
FIGURE 18-5: SIMPLIFIED COG BLOCK DIAGRAM (HALF-BRIDGE MODE, GXMD = 4)
2014-2015 Microchip Technology Inc.
GxASDAC<1:0>
‘1’ 11
‘0’ 10
High-Z 01
reserved 11 00
HFINTOSC 10 COG_clock 1 COGxA
FOSC 01
FOSC/4 00 0
GxPOLB GxASDAC<1:0>
Falling Input Block Falling Dead-Band Block
NCO1_out src7 ‘1’ 11
clock clock ‘0’ 10
PWM3OUT src6
signal_out High-Z 01
CCP2 src5
src4 signal_in 00
CCP1
LC1_out src3 falling_event 1 COGxC
C2OUT src2
C1OUT src1 0
COGINPPS src0 count_en
PIC16(L)F1717/8/9
GxPOLC GxASDBD<1:0>
‘1’ 11
‘0’ 10
GxEN
High-Z 01
00
1
COGINPPS COGxD
GxAS0E 0
C1OUT
GxAS1E Auto-shutdown source
GxPOLD
C2OUT
DS40001740B-page 190
GxAS2E
LC2_out S Q GxASE
GxAS3E GxARSEN S
Write GxASE Low R D Q
Write GxASE High Set Dominates
FIGURE 18-6: SIMPLIFIED COG BLOCK DIAGRAM (PUSH-PULL MODE, GXMD = 5)
DS40001740B-page 191
PIC16(L)F1717/8/9
GxASDAC<1:0>
‘1’ 11
‘0’ 10
High-Z 01
reserved 11 00
HFINTOSC 10 COG_clock 1 COGxA
FOSC 01
FOSC/4 00 0
GxPOLB GxASDAC<1:0>
Falling Input Block
NCO1_out src7 ‘1’ 11
src6 clock ‘0’ 10
PWM3OUT
src5 High-Z 01
CCP2
src4 00
CCP1
LC1_out src3 falling_event 1 COGxC
C2OUT src2
C1OUT src1 0
COGINPPS src0 count_en
GxPOLC GxASDBD<1:0>
‘1’ 11
‘0’ 10
GxEN
High-Z 01
00
2014-2015 Microchip Technology Inc.
1
COGINPPS COGxD
GxAS0E 0
C1OUT
GxAS1E Auto-shutdown source
GxPOLD
C2OUT
GxAS2E
LC2_out S Q GxASE
GxAS3E GxARSEN S
Write GxASE Low R D Q
Write GxASE High Set Dominates
FIGURE 18-7: COG (RISING/FALLING) INPUT BLOCK
DS40001740B-page 192
PIC16(L)F1717/8/9
clock
GxPH(R/F)<3:0>
Blanking
count_en =
Cnt/Clr Phase
Delay
GxBLK(F/R)<3:0>
src7
Gx(R/F)IS7 D Q 1
(rising/falling)_event
LE 0
Gx(R/F)SIM7
src6
Gx(R/F)IS6 D Q 1
LE 0
Gx(R/F)SIM6
src5
Gx(R/F)IS5 D Q 1
LE 0
Gx(R/F)SIM5
src4
Gx(R/F)IS4 D Q 1
LE 0
Gx(R/F)SIM4
src3
Gx(R/F)IS3 D Q 1
LE 0
Gx(R/F)SIM3
src2
Gx(R/F)IS2 D Q 1
2014-2015 Microchip Technology Inc.
LE 0
Gx(R/F)SIM2
src1
Gx(R/F)IS1 D Q 1
LE 0
Gx(R/F)SIM1
src0
Gx(R/F)IS0 D Q 1
LE 0
Gx(R/F)SIM0
PIC16(L)F1717/8/9
FIGURE 18-8: COG (RISING/FALLING) DEAD-BAND BLOCK
Gx(R/F)DBTS
clock Synchronous
Delay
=
Cnt/Clr
0 0
1 GxDBR<3:0> 1
Asynchronous
Delay Chain
signal_out
signal_in
COG_clock
Source
CCP1
COGxA
Rising_event Dead-band
Falling_event Dead-band Falling_event Dead-band
COGxB
FIGURE 18-10: HALF-BRIDGE MODE COG OPERATION WITH CCP1 AND PHASE DELAY
COG_clock
Source
CCP1
COGxA
Rising_event
Dead-Band
Falling_event Dead-Band Phase Delay Falling_event
Dead-Band
COGxB
CCP1
COGxA
COGxB
CCP1
COGxA
COGxB
COGxC
COGxD
FIGURE 18-13: FULL-BRIDGE MODE COG OPERATION WITH CCP1 AND DIRECTION CHANGE
CCP1
COGxA
Falling_event Dead-Band
COGxB
COGxC
COGxD
CxMD0
18.5.6.1 Rising-to-Falling Overlap The rising event blanking time is set by the value
contained in the COGxBLKR register (Register 18-12).
In this case, the falling event occurs while the rising
event dead-band counter is still counting. When this When the COGxBLKR value is zero, rising event
happens, the primary drives are suppressed and the blanking is disabled and the blanking counter output is
dead band extends by the falling event dead-band true, thereby, allowing the event signal to pass straight
time. At the termination of the extended dead-band through to the event trigger circuit.
time, the complementary drive goes true.
18.6.3 BLANKING TIME UNCERTAINTY
18.5.6.2 Falling-to-Rising Overlap When the rising and falling sources that trigger the
In this case, the rising event occurs while the falling blanking counters are asynchronous to the
event dead-band counter is still counting. When this COG_clock, it creates uncertainty in the blanking time.
happens, the complementary drive is suppressed and The maximum uncertainty is equal to one COG_clock
the dead band extends by the rising event dead-band period. Refer to Equation 18-1 and Example 18-1 for
time. At the termination of the extended dead-band more detail.
time, the primary drive goes true.
18.7 Phase Delay
18.6 Blanking Control It is possible to delay the assertion of either or both the
Input blanking is a function, whereby, the event inputs rising event and falling events. This is accomplished
can be masked or blanked for a short period of time. by placing a non-zero value in COGxPHR or
This is to prevent electrical transients caused by the COGxPHF phase-delay count register, respectively
turn-on/off of power components from generating a (Register 18-14 and Register 18-15). Refer to
false input event. Figure 18-10 for COG operation with CCP1 and phase
delay. The delay from the input rising event signal
The COG contains two blanking counters: one trig- switching to the actual assertion of the events is calcu-
gered by the rising event and the other triggered by lated the same as the dead-band and blanking delays.
the falling event. The counters are cross coupled with Refer to Equation 18-1.
the events they are blanking. The falling event blank-
ing counter is used to blank rising input events and the When the phase-delay count value is zero, phase
rising event blanking counter is used to blank falling delay is disabled and the phase-delay counter output
input events. Once started, blanking extends for the is true, thereby, allowing the event signal to pass
time specified by the corresponding blanking counter. straight through to the complementary output driver
flop.
PIC16(L)F1717/8/9
1 2 3 4 5
CCP1
GxARSEN
GxASDAC 2b00
COGxA
COGxB
Operating State
2014-2015 Microchip Technology Inc.
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets
‘1’ = Bit is set ‘0’ = Bit is cleared q = Value depends on condition
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets
‘1’ = Bit is set ‘0’ = Bit is cleared q = Value depends on condition
bit 7 GxRDBS: COGx Rising Event Dead-band Timing Source Select bit
1 = Delay chain and COGxDBR are used for dead-band timing generation
0 = COGx_clock and COGxDBR are used for dead-band timing generation
bit 6 GxFDBS: COGx Falling Event Dead-band Timing Source select bit
1 = Delay chain and COGxDF are used for dead-band timing generation
0 = COGx_clock and COGxDBF are used for dead-band timing generation
bit 5-4 Unimplemented: Read as ‘0’.
bit 3 GxPOLD: COGxD Output Polarity Control bit
1 = Active level of COGxD output is low
0 = Active level of COGxD output is high
bit 2 GxPOLC: COGxC Output Polarity Control bit
1 = Active level of COGxC output is low
0 = Active level of COGxC output is high
bit 1 GxPOLB: COGxB Output Polarity Control bit
1 = Active level of COGxB output is low
0 = Active level of COGxB output is high
bit 0 GxPOLA: COGxA Output Polarity Control bit
1 = Active level of COGxA output is low
0 = Active level of COGxA output is high
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets
‘1’ = Bit is set ‘0’ = Bit is cleared q = Value depends on condition
REGISTER 18-4: COGxRSIM: COG RISING EVENT SOURCE INPUT MODE REGISTER
R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0
GxRSIM7 GxRSIM6 GxRSIM5 GxRSIM4 GxRSIM3 GxRSIM2 GxRSIM1 GxRSIM0
bit 7 bit 0
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets
‘1’ = Bit is set ‘0’ = Bit is cleared q = Value depends on condition
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets
‘1’ = Bit is set ‘0’ = Bit is cleared q = Value depends on condition
REGISTER 18-6: COGxFSIM: COG FALLING EVENT SOURCE INPUT MODE REGISTER
R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0
GxFSIM7 GxFSIM6 GxFSIM5 GxFSIM4 GxFSIM3 GxFSIM2 GxFSIM1 GxFSIM0
bit 7 bit 0
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets
‘1’ = Bit is set ‘0’ = Bit is cleared q = Value depends on condition
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets
‘1’ = Bit is set ‘0’ = Bit is cleared q = Value depends on condition
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets
‘1’ = Bit is set ‘0’ = Bit is cleared q = Value depends on condition
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets
‘1’ = Bit is set ‘0’ = Bit is cleared q = Value depends on condition
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets
‘1’ = Bit is set ‘0’ = Bit is cleared q = Value depends on condition
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets
‘1’ = Bit is set ‘0’ = Bit is cleared q = Value depends on condition
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets
‘1’ = Bit is set ‘0’ = Bit is cleared q = Value depends on condition
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets
‘1’ = Bit is set ‘0’ = Bit is cleared q = Value depends on condition
REGISTER 18-14: COGxPHR: COG RISING EDGE PHASE DELAY COUNT REGISTER
U-0 U-0 R/W-x/u R/W-x/u R/W-x/u R/W-x/u R/W-x/u R/W-x/u
— — GxPHR<5:0>
bit 7 bit 0
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets
‘1’ = Bit is set ‘0’ = Bit is cleared q = Value depends on condition
REGISTER 18-15: COGxPHF: COG FALLING EDGE PHASE DELAY COUNT REGISTER
U-0 U-0 R/W-x/u R/W-x/u R/W-x/u R/W-x/u R/W-x/u R/W-x/u
— — GxPHF<5:0>
bit 7 bit 0
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets
‘1’ = Bit is set ‘0’ = Bit is cleared q = Value depends on condition
LCxOUT
D Q
MLCxOUT
Q1
LCx_in[0]
LCx_in[1]
to Peripherals
LCx_in[2]
Input Data Selection Gates(1)
. lcxg1
LCxEN
. lcxg2
lcxg3
Logic
Function
(2)
lcxq LCx_out PPS
Module
CLCxOUT
. lcxg4
LCxPOL
0x55 1 AND
0x55 0 NAND
0xAA 1 NOR
0xAA 0 OR
0x00 0 Logic 0
0x00 1 Logic 1
It is possible (but not recommended) to select both the
true and negated values of an input. When this is done,
the gate output is zero, regardless of the other inputs,
but may emit logic glitches (transient-induced pulses).
If the output of the channel must be zero or one, the
recommended method is to set all gate bits to zero and
use the gate polarity bit to set the desired level.
Data gating is configured with the logic gate select
registers as follows:
• Gate 1: CLCxGLS0 (Register 19-7)
• Gate 2: CLCxGLS1 (Register 19-8)
• Gate 3: CLCxGLS2 (Register 19-9)
• Gate 4: CLCxGLS3 (Register 19-10)
Register number suffixes are different than the gate
numbers because other variations of this module have
multiple gate selections in the same register.
Data gating is indicated in the right side of Figure 19-2.
Only one gate is shown in detail. The remaining three
gates are configured identically with the exception that
the data enables correspond to the enables for that
gate.
Data Selection
LCx_in[0] 00000
Data GATE 1
lcxd1T LCxD1G1T
lcxd1N LCxD1G1N
LCx_in[31] 11111
LCxD2G1T
LCxD1S<4:0>
LCxD2G1N lcxg1
LCx_in[0] 00000
LCxD3G1T
LCxG1POL
lcxd2T
LCxD3G1N
lcxd2N
LCxD4G1T
LCx_in[31] 11111
LCxD2S<4:0> LCxD4G1N
LCx_in[0] 00000
Data GATE 2
lcxg2
lcxd3T
(Same as Data GATE 1)
lcxd3N
Data GATE 3
LCx_in[31] 11111
lcxg3
LCxD3S<4:0>
(Same as Data GATE 1)
lcxd4N
LCx_in[31] 11111
LCxD4S<4:0>
lcxg1 lcxg1
lcxg2 lcxg2
lcxq lcxq
lcxg3 lcxg3
lcxg4 lcxg4
lcxg1 lcxg1
S Q lcxq
lcxg2 lcxg2
lcxq
lcxg3 lcxg3
R
lcxg4 lcxg4
lcxg4
lcxg4
S D Q lcxq
lcxg2 D Q lcxq lcxg2
lcxg1
lcxg1 R
R
lcxg3
lcxg3
lcxg4
lcxg2 J Q lcxq
S
lcxg1 lcxg2 D Q lcxq
lcxg4 K
R
lcxg1 LE
R
lcxg3
lcxg3
LCxMODE<2:0>= 110 LCxMODE<2:0>= 111
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets
‘1’ = Bit is set ‘0’ = Bit is cleared
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets
‘1’ = Bit is set ‘0’ = Bit is cleared
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets
‘1’ = Bit is set ‘0’ = Bit is cleared
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets
‘1’ = Bit is set ‘0’ = Bit is cleared
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets
‘1’ = Bit is set ‘0’ = Bit is cleared
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets
‘1’ = Bit is set ‘0’ = Bit is cleared
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets
‘1’ = Bit is set ‘0’ = Bit is cleared
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets
‘1’ = Bit is set ‘0’ = Bit is cleared
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets
‘1’ = Bit is set ‘0’ = Bit is cleared
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets
‘1’ = Bit is set ‘0’ = Bit is cleared
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets
‘1’ = Bit is set ‘0’ = Bit is cleared
EQUATION 20-1:
NCO Clock Frequency Increment Value
F OVERFLOW = ----------------------------------------------------------------------------------------------------------------
n
2
PIC16(L)F1717/8/9
NCO xINCU NCO xINCH NCO xINCL Rev. 10-000 028B
1/10/201 4
20
(1)
INCBUFU INCBUFH INCBUFL
20
20
NCO_overflow Add er
HFINTO SC 00
20
FOSC 01 NCO x_clk
NCO xA CCU NCO xA CCH NCO xA CCL
LC3_out 10 20
reserved 11
NCO_interrup t set bit
NxCKS<1:0>
2 NCO xIF
Fixe d Duty
Cycle Mode
Circuitr y
D Q D Q 0 TRIS bit
NCO xO UT
_ 1
Q
NxP FM NxP OL
NCO x_out
To P eriphe rals
EN S Q
2014-2015 Microchip Technology Inc.
_ D Q NxO UT
Ripple
R Q
Counter
Q1
Pulse
R Freque ncy
3 Mode Circuitry
NxP WS<2:0>
Not e 1: The increment re gisters are doubl e-buffered to all ow for valu e cha nges to be ma de withou t fir st d isa bling th e NCO module. The ful l incremen t va lue is load ed into the buffe r re gisters on the
second rising edge of the NCO x_clk signal that occurs immediately after a wr ite to NCOxINCL registe r. The buffer s are not u ser-accessible an d a re shown here for reference.
PIC16(L)F1717/8/9
20.2 Fixed Duty Cycle (FDC) Mode 20.5 Interrupts
In Fixed Duty Cycle (FDC) mode, every time the When the accumulator overflows (NCO_overflow), the
accumulator overflows (NCO_overflow), the output is NCOx Interrupt Flag bit, NCOxIF, of the PIRx register is
toggled. This provides a 50% duty cycle, provided that set. To enable the interrupt event (NCO_interrupt), the
the increment value remains constant. For more following bits must be set:
information, see Figure 20-2. • NxEN bit of the NCOxCON register
The FDC mode is selected by clearing the NxPFM bit • NCOxIE bit of the PIEx register
in the NCOxCON register. • PEIE bit of the INTCON register
• GIE bit of the INTCON register
20.3 Pulse Frequency (PF) Mode The interrupt must be cleared by software by clearing
the NCOxIF bit in the Interrupt Service Routine.
In Pulse Frequency (PF) mode, every time the
accumulator overflows (NCO_overflow), the output
becomes active for one or more clock periods. Once 20.6 Effects of a Reset
the clock period expires, the output returns to an All of the NCOx registers are cleared to zero as the
inactive state. This provides a pulsed output. result of a Reset.
The output becomes active on the rising clock edge
immediately following the overflow event. For more 20.7 Operation in Sleep
information, see Figure 20-2.
The value of the active and inactive states depends on The NCO module operates independently from the
the polarity bit, NxPOL in the NCOxCON register. system clock and will continue to run during Sleep,
provided that the clock source selected remains
The PF mode is selected by setting the NxPFM bit in
active.
the NCOxCON register.
The HFINTOSC remains active during Sleep when the
20.3.1 OUTPUT PULSE WIDTH CONTROL NCO module is enabled and the HFINTOSC is
When operating in PF mode, the active state of the selected as the clock source, regardless of the system
output can vary in width by multiple clock periods. clock source selected.
Various pulse widths are selected with the
In other words, if the HFINTOSC is simultaneously
NxPWS<2:0> bits in the NCOxCLK register.
selected as the system clock and the NCO clock
When the selected pulse width is greater than the source, when the NCO is enabled, the CPU will go idle
accumulator overflow time frame, the output of the
during Sleep, but the NCO will continue to operate and
NCOx operation is indeterminate.
the HFINTOSC will remain active.
This will have a direct effect on the Sleep mode current.
20.4 Output Polarity Control
The last stage in the NCOx module is the output
polarity. The NxPOL bit in the NCOxCON register
selects the output polarity. Changing the polarity while
the interrupts are enabled will cause an interrupt for the
resulting output transition.
The NCOx output can be used internally by source
code or other peripherals. Accomplish this by reading
the NxOUT (read-only) bit of the NCOxCON register.
The NCOx output signal is available to the following
peripherals:
• CLC
• CWG
PIC16(L)F1717/8/9
Rev. 10-000029A
11/7/2013
NCOx
Clock
Source
NCOx
Increment 4000h 4000h 4000h
Value
NCOx
Accumulator 00000h 04000h 08000h FC000h 00000h 04000h 08000h FC000h 00000h 04000h 08000h
Value
NCO_overflow
NCO_interrupt
NCOx Output
2014-2015 Microchip Technology Inc.
FDC Mode
NCOx Output
PF Mode
NCOxPWS =
000
NCOx Output
PF Mode
NCOxPWS =
001
PIC16(L)F1717/8/9
20.8 Register Definitions: NCOx Control Registers
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets
‘1’ = Bit is set ‘0’ = Bit is cleared
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets
‘1’ = Bit is set ‘0’ = Bit is cleared
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets
‘1’ = Bit is set ‘0’ = Bit is cleared
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets
‘1’ = Bit is set ‘0’ = Bit is cleared
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets
‘1’ = Bit is set ‘0’ = Bit is cleared
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets
‘1’ = Bit is set ‘0’ = Bit is cleared
Note 1: Write the NCOxINCH register first, then the NCOxINCL register. See Section 20.1.4 “Increment Regis-
ters” for more information.
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets
‘1’ = Bit is set ‘0’ = Bit is cleared
Note 1: Write the NCOxINCH register first, then the NCOxINCL register. See Section 20.1.4 “Increment Regis-
ters” for more information.
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets
‘1’ = Bit is set ‘0’ = Bit is cleared
Note 1: Write the NCOxINCU register first, then the NCOxINCL register. See Section 20.1.4 “Increment Regis-
ters” for more information.
VDD
ADPREF = 00 ADPREF = 11
FVR Buffer1
VREF+ ADPREF = 10
ADNREF = 1
VREF-
GO/DONE 10
AN19 10011
0 = Left Justify
AN20(2) 10100 ADFM
1 = Right Justify
ADON 16
AN27(2) 11011
VSS ADRESH ADRESL
DAC2_output 11100
Temp Indicator 11101
DAC1_output 11110
FVR Buffer1 11111
CHS<4:0>
TABLE 21-1: ADC CLOCK PERIOD (TAD) VS. DEVICE OPERATING FREQUENCIES
ADC Clock Period
Device Frequency (FOSC)
(TAD)
ADC
Clock ADCS<2:0> 32 MHz 20 MHz 16 MHz 8 MHz 4 MHz 1 MHz
Source
FOSC/2 000 62.5ns(2) 100 ns(2) 125 ns(2) 250 ns(2) 500 ns(2) 2.0 s
FOSC/4 100 125 ns (2)
200 ns (2)
250 ns (2)
500 ns (2)
1.0 s 4.0 s
FOSC/8 001 0.5 s(2) 400 ns(2) 0.5 s(2) 1.0 s 2.0 s 8.0 s(3)
FOSC/16 101 800 ns 800 ns 1.0 s 2.0 s 4.0 s 16.0 s(3)
FOSC/32 010 1.0 s 1.6 s 2.0 s 4.0 s 8.0 s (3)
32.0 s(2)
FOSC/64 110 2.0 s 3.2 s 4.0 s 8.0 s(3) 16.0 s(2) 64.0 s(2)
FRC x11 1.0-6.0 s(1,4) 1.0-6.0 s(1,4) 1.0-6.0 s(1,4) 1.0-6.0 s(1,4) 1.0-6.0 s(1,4) 1.0-6.0 s(1,4)
Legend: Shaded cells are outside of recommended range.
Note 1: See TAD parameter for FRC source typical TAD value.
2: These values violate the required TAD time.
3: Outside the recommended TAD time.
4: The ADC clock period (TAD) and total ADC conversion time can be minimized when the ADC clock is
derived from the system clock FOSC. However, the FRC oscillator source must be used when conversions
are to be performed with the device in Sleep mode.
TAD1 TAD2 TAD3 TAD4 TAD5 TAD6 TAD7 TAD8 TAD9 TAD10 TAD11
b9 b8 b7 b6 b5 b4 b3 b2 b1 b0
THCD
Conversion Starts
TACQ On the following cycle:
Holding capacitor disconnected
from analog input (THCD).
ADRESH:ADRESL is loaded,
GO bit is cleared,
Set GO bit ADIF bit is set,
holding capacitor is reconnected to analog input.
Enable ADC (ADON bit)
and
Select channel (ACS bits)
ADRESH ADRESL
(ADFM = 0) MSB LSB
bit 7 bit 0 bit 7 bit 0
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets
‘1’ = Bit is set ‘0’ = Bit is cleared
Note 1: See Section 23.0 “8-Bit Digital-to-Analog Converter (DAC1) Module” for more information.
2: See Section 14.0 “Fixed Voltage Reference (FVR)” for more information.
3: See Section 15.0 “Temperature Indicator Module” for more information.
4: PIC16(L)F1717/9 only.
5: See Section 24.0 “5-Bit Digital-to-Analog Converter (DAC2) Module” for more information.
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets
‘1’ = Bit is set ‘0’ = Bit is cleared
Note 1: When selecting the VREF+ pin as the source of the positive reference, be aware that a minimum voltage
specification exists. See Table 34-16: ADC Conversion Requirements for details.
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets
‘1’ = Bit is set ‘0’ = Bit is cleared
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets
‘1’ = Bit is set ‘0’ = Bit is cleared
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets
‘1’ = Bit is set ‘0’ = Bit is cleared
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets
‘1’ = Bit is set ‘0’ = Bit is cleared
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets
‘1’ = Bit is set ‘0’ = Bit is cleared
T ACQ = Amplifier Settling Time + Hold Capacitor Charging Time + Temperature Coefficient
= T AMP + T C + T COFF
= 2µs + T C + Temperature - 25°C 0.05µs/°C
1
VAPPLIED 1 – ------------------------------ = VCHOLD ;[1] VCHOLD charged to within 1/2 lsb
2
n+1
– 1
– TC
----------
VAPPLIED 1 – e
RC
= VCHOLD ;[2] VCHOLD charge response to VAPPLIED
– Tc
---------
VAPPLIED 1 – e
RC 1
= VAPPLIED 1 – ------------------------------ ;combining [1] and [2]
– 1
n + 1
2
T C = – CHOLD R IC + R SS + R S ln(1/2047)
= – 10pF 1k + 7k + 10k ln(0.0004885)
= 1.37 µs
Therefore:
T ACQ = 2µs + 892ns + 50°C- 25°C 0.05µs/°C
= 4.62µs
Note 1: The reference voltage (VREF) has no effect on the equation, since it cancels itself out.
2: The charge holding capacitor (CHOLD) is not discharged after each conversion.
3: The maximum recommended impedance for analog sources is 10 k. This is required to meet the pin
leakage specification.
VDD
Analog Sampling
Input Switch
VT 0.6V
Rs pin RIC 1k SS Rss
VA CPIN I LEAKAGE(1)
VT 0.6V CHOLD = 10 pF
5 pF
Ref-
6V
5V RSS
Legend: CHOLD = Sample/Hold Capacitance VDD 4V
3V
CPIN = Input Capacitance 2V
I LEAKAGE = Leakage current at the pin due to
various junctions
5 6 7 8 9 10 11
RIC = Interconnect Resistance
Sampling Switch
RSS = Resistance of Sampling Switch (k)
SS = Sampling Switch
VT = Threshold Voltage
Full-Scale Range
3FFh
3FEh
3FDh
3FCh
ADC Output Code
3FBh
03h
02h
01h
00h
Analog Input Voltage
0.5 LSB 1.5 LSB
Ref- Zero-Scale
Transition Full-Scale
Transition Ref+
OPAxIN+ 00 OPAXEN
DAC2_output 01 OPAXSP(1)
DAC1_output 10 OPAXOUT
OPAxIN- 0 OPA
FVR Buffer 2 11
1
OPAxNCH<1:0> OPAXUG
Note 1: The OPAxSP bit must be set. Low-Power mode is not supported.
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets
‘1’ = Bit is set ‘0’ = Bit is cleared q = Value depends on condition
VSOURCE- = VSS
FVR Buffer2
VDD
VSOURCE+
DAC1R<7:0>
8
VREF+
R
R
DAC1PSS<1:0>
2
R
DAC1EN
R
32-to-1 MUX
256 DAC1_Output
Steps To Peripherals
R
R
DAC1OUT1
R
DAC1OE1
DAC1NSS
DAC1OUT2
PIC® MCU
DAC
R
Module
+
Voltage DAC1OUTX Buffered DAC Output
–
Reference
Output
Impedance
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets
‘1’ = Bit is set ‘0’ = Bit is cleared
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets
‘1’ = Bit is set ‘0’ = Bit is cleared
V OUT = V SOURCE +
V OUT = V SOURCE –
FVR BUFFER2
VDD VSOURCE+
DACR<4:0>
5
VREF+
R
R
DACPSS<1:0>
2
R
DACEN
R
32-to-1 MUX
32 DAC_Output
Steps To Peripherals
R
R DAC2OUT1
R DAC2OE1
DACNSS DAC2OUT2
DAC2OE2
VREF- VSOURCE-
VSS
PIC® MCU
DAC
R
Module
+
Voltage DACOUT Buffered DAC Output
–
Reference
Output
Impedance
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets
‘1’ = Bit is set ‘0’ = Bit is cleared
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets
‘1’ = Bit is set ‘0’ = Bit is cleared
ZCDx_output
D Q ZCDxOUT
ZCDxPOL
Q1 LE
Interrupt
det
Sets
ZCDxINTP ZCDIF flag
ZCDxINTN
Interrupt
det
R series Z cpinv
R = ------------------------------------------
pulldown V DD – Z
cpinv
V maxpeak + V minpeak
R series = ------------------------------------------------------------
–4
7 10
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets
‘1’ = Bit is set ‘0’ = Bit is cleared q = value depends on configuration bits
• 8-bit timer/counter register (TMR0) 8-Bit Counter mode using the T0CKI pin is selected by
• 8-bit prescaler (independent of Watchdog Timer) setting the TMR0CS bit in the OPTION_REG register to
• Programmable internal or external clock source ‘1’.
• Programmable external clock edge selection The rising or falling transition of the incrementing edge
• Interrupt on overflow for either input source is determined by the TMR0SE bit
• TMR0 can be used to gate Timer1 in the OPTION_REG register.
Figure 26-1 is a block diagram of the Timer0 module.
FOSC/4
Data Bus
0
8
T0CKI 1
Sync
1 2 TCY TMR0
0
TMR0SE TMR0CS Set Flag bit TMR0IF
8-bit on Overflow
Prescaler PSA
Overflow to Timer1
PS<2:0>
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets
‘1’ = Bit is set ‘0’ = Bit is cleared
000 1:2
001 1:4
010 1:8
011 1 : 16
100 1 : 32
101 1 : 64
110 1 : 128
111 1 : 256
T1G 00 T1GSPM
TABLE 27-1: TIMER1 ENABLE The following asynchronous sources may be used:
SELECTIONS • Asynchronous event on the T1G pin to Timer1
gate
Timer1
TMR1ON TMR1GE • C1 or C2 comparator input to Timer1 gate
Operation
0 0 Off 27.2.2 EXTERNAL CLOCK SOURCE
0 1 Off When the external clock source is selected, the Timer1
1 0 Always On module may work as a timer or a counter.
1 1 Count Enabled When enabled to count, Timer1 is incremented on the
rising edge of the external clock input T1CKI, which can
be synchronized to the microcontroller system clock or
can run asynchronously.
When used as a timer with a clock oscillator, an
external 32.768 kHz crystal can be used in conjunction
with the dedicated internal oscillator circuit.
Note: In Counter mode, a falling edge must be
registered by the counter prior to the first
incrementing rising edge after any one or
more of the following conditions:
• Timer1 enabled after POR
• Write to TMR1H or TMR1L
• Timer1 is disabled
• Timer1 is disabled (TMR1ON = 0)
when T1CKI is high then Timer1 is
enabled (TMR1ON=1) when T1CKI is
low.
T1CKI = 1
when TMR1
Enabled
T1CKI = 0
when TMR1
Enabled
TMR1GE
T1GPOL
t1g_in
T1CKI
T1GVAL
TMR1GE
T1GPOL
T1GTM
t1g_in
T1CKI
T1GVAL
TMR1GE
T1GPOL
T1GSPM
Cleared by hardware on
T1GGO/ Set by software falling edge of T1GVAL
DONE
Counting enabled on
rising edge of T1G
t1g_in
T1CKI
T1GVAL
Cleared by
TMR1GIF Cleared by software Set by hardware on software
falling edge of T1GVAL
TMR1GE
T1GPOL
T1GSPM
T1GTM
Cleared by hardware on
T1GGO/ Set by software falling edge of T1GVAL
DONE Counting enabled on
rising edge of T1G
t1g_in
T1CKI
T1GVAL
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets
‘1’ = Bit is set ‘0’ = Bit is cleared
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets
‘1’ = Bit is set ‘0’ = Bit is cleared HC = Bit is cleared by hardware
T2_match
Prescaler To Peripherals
TMR2 R
Fosc/4 1:1, 1:4, 1:16, 1:64
2
Postscaler set bit
T2CKPS<1:0> Comparator
1:1 to 1:16 TMR2IF
PR2 T2OUTPS<3:0>
A 4-bit counter/prescaler on the clock input allows direct Timer2 can be optionally used as the shift clock source
input, divide-by-4 and divide-by-16 prescale options. for the MSSP module operating in SPI mode.
These options are selected by the prescaler control bits, Additional information is provided in Section 30.0
T2CKPS<1:0> of the T2CON register. The value of “Master Synchronous Serial Port (MSSP) Module”.
TMR2 is compared to that of the Period register, PR2, on
each clock cycle. When the two values match, the 28.4 Timer2 Operation During Sleep
comparator generates a match signal as the timer
The Timer2 timers cannot be operated while the
output. This signal also resets the value of TMR2 to 00h
processor is in Sleep mode. The contents of the TMR2
on the next cycle and drives the output
and PR2 registers will remain unchanged while the
counter/postscaler (see Section 28.2 “Timer2
processor is in Sleep mode.
Interrupt”).
The TMR2 and PR2 registers are both directly readable
and writable. The TMR2 register is cleared on any
device Reset, whereas the PR2 register initializes to
FFh. Both the prescaler and postscaler counters are
cleared on the following events:
• A write to the TMR2 register
• A write to the T2CON register
• Power-on Reset (POR)
• Brown-out Reset (BOR)
• MCLR Reset
• Watchdog Timer (WDT) Reset
• Stack Overflow Reset
• Stack Underflow Reset
• RESET Instruction
Note: TMR2 is not cleared when T2CON is
written.
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets
‘1’ = Bit is set ‘0’ = Bit is cleared
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets
‘1’ = Bit is set ‘0’ = Bit is cleared
and Capture
Edge Detect Enable
TMR1H TMR1L
CCPxM<3:0>
System Clock (FOSC)
Pulse Width
TMR2 = PR2
TMR2 = CCPRxH:CCPxCON<5:4>
TMR2 = 0
CCPRxL:CCPxCON<5:4>
Duty Cycle Ratio = -----------------------------------------------------------------------
4 PR2 + 1
log 4 PR2 + 1
Resolution = ------------------------------------------ bits
log 2
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Reset
‘1’ = Bit is set ‘0’ = Bit is cleared
1011 = Compare mode: Auto-conversion Trigger (sets CCPxIF bit), starts ADC conversion if
TRIGSEL = CCPx (see Register 21-3)
1010 = Compare mode: generate software interrupt only
1001 = Compare mode: clear output on compare match (set CCPxIF)
1000 = Compare mode: set output on compare match (set CCPxIF)
0011 = Reserved
0010 = Compare mode: toggle output on match
0001 = Reserved
0000 = Capture/Compare/PWM off (resets CCPx module)
Data Bus
Read Write
SSP1BUF Reg
SDI
SSP1SR Reg
SDO bit 0 Shift
Clock
Edge
Select
SSPM<3:0>
4
( T2_match
2
)
SCK
Edge Prescaler TOSC
Select 4, 16, 64
Baud Rate
Generator
TRIS bit (SSP1ADD)
Internal
Data Bus
[SSPM<3:0>]
SSPDATPPS(1) Read Write
SDA
SDA In
PPS SSPxBUF Baud Rate
Generator
(SSPxADD)
Shift
RxyPPS(1) Clock
SSPSR
PPS
SCL
PPS
PPS
Note 1: SDA pin selections must be the same for input and output.
2: SCL pin selections must be the same for input and output.
Internal
Data Bus
Read Write
SDA
SSPDATPPS(1)
Match Detect Addr Match
PPS
SSPxADD Reg
PPS
Start and Set, Reset
RxyPPS(1) S, P bits
Stop bit Detect
(SSPxSTAT Reg)
Note 1: SDA pin selections must be the same for input and output.
2: SCL pin selections must be the same for input and output.
SCK SCK
SPI Master
SDO SDI SPI Slave
SDI SDO #1
General I/O SS
General I/O
General I/O SCK
SDI SPI Slave
SDO #2
SS
SCK
SDI SPI Slave
SDO #3
SS
Slave Select
General I/O SS
Processor 1 (optional) Processor 2
Write to
SSP1BUF
SCK
(CKP = 0
CKE = 0)
SCK
(CKP = 1
CKE = 0)
4 Clock
SCK Modes
(CKP = 0
CKE = 1)
SCK
(CKP = 1
CKE = 1)
Input
Sample
(SMP = 1)
SSP1IF
SSP1SR to
SSP1BUF
SCK SCK
SPI Master
SDO SDI SPI Slave
SDI SDO #1
General I/O SS
SCK
SDI SPI Slave
SDO #2
SS
SCK
SDI SPI Slave
SDO #3
SS
SS
SCK
(CKP = 0
CKE = 0)
SCK
(CKP = 1
CKE = 0)
Write to
SSP1BUF
Shift register SSP1SR
and bit count are reset
SSP1BUF to
SSP1SR
SDI bit 0
bit 7 bit 7
Input
Sample
SSP1IF
Interrupt
Flag
SSP1SR to
SSP1BUF
SS
Optional
SCK
(CKP = 0
CKE = 0)
SCK
(CKP = 1
CKE = 0)
Write to
SSP1BUF
Valid1
SDO bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0
SDI
bit 7 bit 0
Input
Sample
SSP1IF
Interrupt
Flag
SSP1SR to
SSP1BUF
Write Collision
detection active
SS
Not Optional
SCK
(CKP = 0
CKE = 1)
SCK
(CKP = 1
CKE = 1)
Write to
SSP1BUF
Valid
SDO bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0
SDI
bit 7 bit 0
Input
Sample
SSP1IF
Interrupt
Flag
SSP1SR to
SSP1BUF
Write Collision
detection active
SDA
SCL
S P
Change of Change of
Data Allowed Data Allowed
Start Stop
Condition Condition
Sr
Change of Change of
Data Allowed Data Allowed
Restart
Condition
SCL
1 2 3 4 5 6 7 8 9 1 2 3 4 5 6 7 8 9 1 2 3 4 5 6 7 8 9
S P
SSP1IF
SSP1IF set on 9th
Cleared by software Cleared by software falling edge of
SCL
BF
First byte
SSP1BUF is read of data is
available
in SSP1BUF
SSPOV
DS40001740B-page 313
PIC16(L)F1717/8/9
FIGURE 30-15:
DS40001740B-page 314
Receive Address Receive Data Receive Data ACK
SDA A7 A6 A5 A4 A3 A2 A1 R/W=0 ACK D7 D6 D5 D4 D3 D2 D1 D0 ACK D7 D6 D5 D4 D3 D2 D1 D0
SSP1IF
BF
First byte
of data is
SSP1BUF is read available
in SSP1BUF
SSPOV
SCL
S 1 2 3 4 5 6 7 8 9 1 2 3 4 5 6 7 8 9 1 2 3 4 5 6 7 8 9 P
Slave software
clears ACKDT to Slave software
ACK the received sets ACKDT to
CKP byte not ACK
When AHEN=1:
When DHEN=1: CKP set by software,
CKP is cleared by hardware
CKP is cleared by SCL is released
and SCL is stretched hardware on 8th falling
edge of SCL
ACKTIM
P
I2C SLAVE, 7-BIT ADDRESS, RECEPTION (SEN = 0, AHEN = 1, DHEN = 1)
DS40001740B-page 315
PIC16(L)F1717/8/9
Master sends
FIGURE 30-17:
Stop condition
Master releases
R/W = 0 SDA to slave for ACK sequence
DS40001740B-page 316
Receiving Address Receive Data Receive Data ACK
SDA ACK
A7 A6 A5 A4 A3 A2 A1 D7 D6 D5 D4 D3 D2 D1 D0 ACK D7 D6 D5 D4 D3 D2 D1 D0
SCL
1 2 3 4 5 6 7 8 9 1 2 3 4 5 6 7 8 9 1 2 3 4 5 6 7 8 9 P
S
SSP1IF
Cleared by software No interrupt after
PIC16(L)F1717/8/9
if not ACK
from Slave
BF
Received
address is loaded into Received data is SSP1BUF can be
SSP1BUF available on SSP1BUF read any time before
next byte is loaded
ACKDT
ACKTIM
P
I2C SLAVE, 7-BIT ADDRESS, RECEPTION (SEN = 1, AHEN = 1, DHEN = 1)
SCL
1 2 3 4 5 6 7 8 9 1 2 3 4 5 6 7 8 9 1 2 3 4 5 6 7 8 9
S P
SSP1IF
BF
BF is automatically
Received address Data to transmit is cleared after 8th falling
is read from SSP1BUF loaded into SSP1BUF edge of SCL
CKP
When R/W is set CKP is not
SCL is always held for not
held low after 9th SCL Set by software ACK
falling edge
ACKSTAT
Indicates an address
has been received
DS40001740B-page 319
PIC16(L)F1717/8/9
PIC16(L)F1717/8/9
30.5.3.3 7-Bit Transmission with Address
Hold Enabled
Setting the AHEN bit of the SSP1CON3 register
enables additional clock stretching and interrupt
generation after the eighth falling edge of a received
matching address. Once a matching address has
been clocked in, CKP is cleared and the SSP1IF
interrupt is set.
Figure 30-19 displays a standard waveform of a 7-bit
address slave transmission with AHEN enabled.
1. Bus starts Idle.
2. Master sends Start condition; the S bit of
SSP1STAT is set; SSP1IF is set if interrupt on
Start detect is enabled.
3. Master sends matching address with R/W bit
set. After the eighth falling edge of the SCL line
the CKP bit is cleared and SSP1IF interrupt is
generated.
4. Slave software clears SSP1IF.
5. Slave software reads ACKTIM bit of SSP1CON3
register, and R/W and D/A of the SSP1STAT
register to determine the source of the interrupt.
6. Slave reads the address value from the
SSP1BUF register clearing the BF bit.
7. Slave software decides from this information if it
wishes to ACK or not ACK and sets the ACKDT
bit of the SSP1CON2 register accordingly.
8. Slave sets the CKP bit releasing SCL.
9. Master clocks in the ACK value from the slave.
10. Slave hardware automatically clears the CKP bit
and sets SSP1IF after the ACK if the R/W bit is
set.
11. Slave software clears SSP1IF.
12. Slave loads value to transmit to the master into
SSP1BUF setting the BF bit.
Note: SSP1BUF cannot be loaded until after the
ACK.
13. Slave sets the CKP bit releasing the clock.
14. Master clocks out the data from the slave and
sends an ACK value on the 9th SCL pulse.
15. Slave hardware copies the ACK value into the
ACKSTAT bit of the SSP1CON2 register.
16. Steps 10-15 are repeated for each byte
transmitted to the master from the slave.
17. If the master sends a not ACK the slave
releases the bus allowing the master to send a
Stop and end the communication.
Note: Master must send a not ACK on the last
byte to ensure that the slave releases the
SCL line to receive a Stop.
SCL
S 1 2 3 4 5 6 7 8 9 1 2 3 4 5 6 7 8 9 1 2 3 4 5 6 7 8 9
P
BF BF is automatically
Received address Data to transmit is cleared after 8th falling
is read from SSP1BUF loaded into SSP1BUF edge of SCL
ACKDT
Slave clears
ACKDT to ACK
address
ACKSTAT
Master’s ACK
response is copied
to SSP1STAT
CKP
When AHEN = 1; CKP not cleared
CKP is cleared by hardware When R/W = 1; Set by software, after not ACK
after receiving matching CKP is always releases SCL
address. cleared after ACK
ACKTIM
I2C SLAVE, 7-BIT ADDRESS, TRANSMISSION (AHEN = 1)
R/W
D/A
DS40001740B-page 321
PIC16(L)F1717/8/9
PIC16(L)F1717/8/9
30.5.4 SLAVE MODE 10-BIT ADDRESS 30.5.5 10-BIT ADDRESSING WITH
RECEPTION ADDRESS OR DATA HOLD
This section describes a standard sequence of events Reception using 10-bit addressing with AHEN or
for the MSSP module configured as an I2C slave in DHEN set is the same as with 7-bit modes. The only
10-bit Addressing mode. difference is the need to update the SSP1ADD register
Figure 30-20 is used as a visual reference for this using the UA bit. All functionality, specifically when the
description. CKP bit is cleared and SCL line is held low are the
same. Figure 30-21 can be used as a reference of a
This is a step by step process of what must be done by slave in 10-bit addressing with AHEN set.
slave software to accomplish I2C communication.
Figure 30-22 shows a standard waveform for a slave
1. Bus starts Idle. transmitter in 10-bit Addressing mode.
2. Master sends Start condition; S bit of
SSP1STAT is set; SSP1IF is set if interrupt on
Start detect is enabled.
3. Master sends matching high address with R/W
bit clear; UA bit of the SSP1STAT register is set.
4. Slave sends ACK and SSP1IF is set.
5. Software clears the SSP1IF bit.
6. Software reads received address from
SSP1BUF clearing the BF flag.
7. Slave loads low address into SSP1ADD,
releasing SCL.
8. Master sends matching low address byte to the
slave; UA bit is set.
Note: Updates to the SSP1ADD register are not
allowed until after the ACK sequence.
Master sends
Stop condition
Receive First Address Byte Receive Second Address Byte Receive Data Receive Data
SDA
1 1 1 1
0 A9 A8 ACK A7 A6 A5 A4 A3 A2 A1 A0 ACK D7 D6 D5 D4 D3 D2 D1 D0 ACK D7 D6 D5 D4 D3 D2 D1 D0 ACK
SSP1IF
Set by hardware Cleared by software
on 9th falling edge
BF
If address matches Receive address is Data is read
SSP1ADD it is loaded into read from SSP1BUF from SSP1BUF
SSP1BUF
UA
When UA = 1; Software updates SSP1ADD
SCL is held low and releases SCL
CKP
DS40001740B-page 323
PIC16(L)F1717/8/9
Receive First Address Byte R/W = 0 Receive Second Address Byte Receive Data Receive Data
FIGURE 30-21:
DS40001740B-page 324
SCL S 1 2 3 4 5 6 7 8 9 UA 1 2 3 4 5 6 7 8 9 UA 1 2 3 4 5 6 7 8 9 1 2
SSP1IF
Set by hardware Cleared by software Cleared by software
on 9th falling edge
PIC16(L)F1717/8/9
BF
UA
Master sends
Master sends Stop condition
Restart event Master sends
not ACK
Receiving Address R/W = 0 Receiving Second Address Byte Receive First Address Byte Transmitting Data Byte ACK = 1
SDA 1 1 1 1 0 A9 A8 ACK A7 A6 A5 A4 A3 A2 A1 A0 ACK 1 1 1 1 0 A9 A8 ACK D7 D6 D5 D4 D3 D2 D1 D0
SSP1IF
BF
Indicates an address
has been received
I2C SLAVE, 10-BIT ADDRESS, TRANSMISSION (SEN = 0, AHEN = 0, DHEN = 0)
DS40001740B-page 325
PIC16(L)F1717/8/9
PIC16(L)F1717/8/9
30.5.6 CLOCK STRETCHING
Clock stretching occurs when a device on the bus
holds the SCL line low, effectively pausing
communication. The slave may stretch the clock to
allow more time to handle data or prepare a response
for the master device. A master device is not
concerned with stretching as anytime it is active on the
bus and not transferring data it is stretching. Any
stretching done by a slave is invisible to the master
software and handled by the hardware that generates
SCL.
The CKP bit of the SSP1CON1 register is used to
control stretching in software. Any time the CKP bit is
cleared, the module will wait for the SCL line to go low
and then hold it. Setting CKP will release SCL and
allow more communication.
Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4
SDA DX DX ‚ – 1
SCL
Master device
CKP asserts clock
Master device
releases clock
WR
SSP1CON1
SCL
1 2 3 4 5 6 7 8 9 1 2 3 4 5 6 7 8 9
S
SSP1IF
BF (SSP1STAT<0>)
Cleared by software
SSP1BUF is read
GCEN (SSP1CON2<7>)
’1’
Master mode of operation is supported by interrupt In Master Transmitter mode, serial data is output
generation on the detection of the Start and Stop through SDA, while SCL outputs the serial clock. The
conditions. The Stop (P) and Start (S) bits are cleared first byte transmitted contains the slave address of the
from a Reset or when the MSSP module is disabled. receiving device (7 bits) and the Read/Write (R/W) bit.
Control of the I 2C bus may be taken when the P bit is In this case, the R/W bit will be logic ‘0’. Serial data is
set, or the bus is Idle. transmitted eight bits at a time. After each byte is
transmitted, an Acknowledge bit is received. Start and
In Firmware Controlled Master mode, user code Stop conditions are output to indicate the beginning
conducts all I 2C bus operations based on Start and and the end of a serial transfer.
Stop bit condition detection. Start and Stop condition
detection is the only active circuitry in this mode. All In Master Receive mode, the first byte transmitted
other communication is done by the user software contains the slave address of the transmitting device
directly manipulating the SDA and SCL lines. (7 bits) and the R/W bit. In this case, the R/W bit will be
logic ‘1’. Thus, the first byte transmitted is a 7-bit slave
The following events will cause the SSP Interrupt Flag address followed by a ‘1’ to indicate the receive bit.
bit, SSP1IF, to be set (SSP interrupt, if enabled): Serial data is received via SDA, while SCL outputs the
• Start condition detected serial clock. Serial data is received eight bits at a time.
• Stop condition detected After each byte is received, an Acknowledge bit is
• Data transfer byte transmitted/received transmitted. Start and Stop conditions indicate the
• Acknowledge transmitted/received beginning and end of transmission.
• Repeated Start generated A Baud Rate Generator is used to set the clock
frequency output on SCL. See Section 30.7 “Baud
Note 1: The MSSP module, when configured in
Rate Generator” for more detail.
I2C Master mode, does not allow queuing
of events. For instance, the user is not
allowed to initiate a Start condition and
immediately write the SSP1BUF register
to initiate transmission before the Start
condition is complete. In this case, the
SSP1BUF will not be written to and the
WCOL bit will be set, indicating that a
write to the SSP1BUF did not occur
2: Master mode suspends Start/Stop
detection when sending the Start/Stop
condition by means of the SEN/PEN
control bits. The SSPxIF bit is set at the
end of the Start/Stop generation when
hardware clears the control bit.
SDA DX DX‚ – 1
BRG decrements on
Q2 and Q4 cycles
BRG
03h 02h 01h 00h (hold off) 03h 02h
Value
TBRG
SCL
S
TBRG
DS40001740B-page 334
Write SSP1CON2<0> SEN = 1 ACKSTAT in
Start condition begins SSP1CON2 = 1
From slave, clear ACKSTAT bit SSP1CON2<6>
SEN = 0
Transmitting Data or Second Half
Transmit Address to Slave R/W = 0 ACK
of 10-bit Address
SDA A7 A6 A5 A4 A3 A2 A1 ACK = 0 D7 D6 D5 D4 D3 D2 D1 D0
S P
SCL held low
while CPU
responds to SSP1IF
SSP1IF
Cleared by software service routine
Cleared by software from SSP interrupt
Cleared by software
BF (SSP1STAT<0>)
PEN
R/W
I2C MASTER MODE WAVEFORM (TRANSMISSION, 7 OR 10-BIT ADDRESS)
begin Start condition ACK from Master Set ACKEN, start Acknowledge sequence
Master configured as a receiver SDA = ACKDT = 0 SDA = ACKDT = 1
by programming SSP1CON2<3> (RCEN = 1)
DS40001740B-page 336
SEN = 0
PEN bit = 1
Write to SSP1BUF occurs here, RCEN cleared RCEN = 1, start RCEN cleared
ACK from Slave next receive automatically written here
start XMIT automatically
Transmit Address to Slave Receiving Data from Slave Receiving Data from Slave
SDA A7 A6 A5 A4 A3 A2 A1 R/W ACK D7 D6 D5 D4 D3 D2 D1 D0 ACK D7 D6 D5 D4 D3 D2 D1 D0 ACK
Bus master
ACK is not sent terminates
transfer
1 2 3 4 5 6 7 8 9 1 2 3 4 5 6 7 8 9 1 2 3 4 5 6 7 8 9
SCL S P
Data shifted in on falling edge of CLK Set SSP1IF at end
PIC16(L)F1717/8/9
Set P bit
Cleared by software Cleared by software Cleared by software Cleared by software (SSP1STAT<4>)
SDA = 0, SCL = 1 Cleared in
while CPU software and SSP1IF
responds to SSP1IF
BF
(SSP1STAT<0>) Last bit is shifted into SSP1SR and
contents are unloaded into SSP1BUF
SSPOV
ACKEN
I2C MASTER MODE WAVEFORM (RECEPTION, 7-BIT ADDRESS)
RCEN
Master configured as a receiver RCEN cleared ACK from Master RCEN cleared
by programming SSP1CON2<3> (RCEN = 1) automatically SDA = ACKDT = 0 automatically
SCL 8 9
SSP1IF
Cleared in
SSP1IF set at software
the end of receive Cleared in
software SSP1IF set at the end
of Acknowledge sequence
Note: TBRG = one Baud Rate Generator period.
SDA ACK
P
TBRG TBRG TBRG
SCL brought high after TBRG
SDA asserted low before rising edge of clock
to setup Stop condition
SDA
BCL1IF
SDA
SCL
Set SEN, enable Start SEN cleared automatically because of bus collision.
condition if SDA = 1, SCL = 1 SSP module reset into Idle state.
SEN
SDA sampled low before
Start condition. Set BCL1IF.
S bit and SSP1IF set because
BCL1IF SDA = 0, SCL = 1.
SSP1IF and BCL1IF are
cleared by software
SSP1IF
TBRG TBRG
SDA
FIGURE 30-35: BRG RESET DUE TO SDA ARBITRATION DURING START CONDITION
SDA = 0, SCL = 1
Set S Set SSP1IF
Less than TBRG
TBRG
SCL S
SCL pulled low after BRG
time-out
SEN
Set SEN, enable Start
sequence if SDA = 1, SCL = 1
BCL1IF ‘0’
SSP1IF
SDA = 0, SCL = 1, Interrupts cleared
set SSP1IF by software
SDA
SCL
RSEN
BCL1IF
Cleared by software
S ‘0’
SSP1IF ‘0’
TBRG TBRG
SDA
SCL
S ‘0’
SSP1IF
PEN
BCL1IF
P ‘0’
SSP1IF ‘0’
SDA
PEN
BCL1IF
P ‘0’
SSP1IF ‘0’
SSPM<3:0> SSP1ADD<7:0>
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets
‘1’ = Bit is set ‘0’ = Bit is cleared
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets
‘1’ = Bit is set ‘0’ = Bit is cleared HS = Bit is set by hardware C = User cleared
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets
‘1’ = Bit is set ‘0’ = Bit is cleared HC = Cleared by hardware S = User set
bit 7 GCEN: General Call Enable bit (in I2C Slave mode only)
1 = Enable interrupt when a general call address (0x00 or 00h) is received in the SSP1SR
0 = General call address disabled
bit 6 ACKSTAT: Acknowledge Status bit (in I2C mode only)
1 = Acknowledge was not received
0 = Acknowledge was received
bit 5 ACKDT: Acknowledge Data bit (in I2C mode only)
In Receive mode:
Value transmitted when the user initiates an Acknowledge sequence at the end of a receive
1 = Not Acknowledge
0 = Acknowledge
bit 4 ACKEN: Acknowledge Sequence Enable bit (in I2C Master mode only)
In Master Receive mode:
1 = Initiate Acknowledge sequence on SDA and SCL pins, and transmit ACKDT data bit.
Automatically cleared by hardware.
0 = Acknowledge sequence idle
bit 3 RCEN: Receive Enable bit (in I2C Master mode only)
1 = Enables Receive mode for I2C
0 = Receive idle
bit 2 PEN: Stop Condition Enable bit (in I2C Master mode only)
SCKMSSP Release Control:
1 = Initiate Stop condition on SDA and SCL pins. Automatically cleared by hardware.
0 = Stop condition Idle
bit 1 RSEN: Repeated Start Condition Enable bit (in I2C Master mode only)
1 = Initiate Repeated Start condition on SDA and SCL pins. Automatically cleared by hardware.
0 = Repeated Start condition Idle
bit 0 SEN: Start Condition Enable/Stretch Enable bit
In Master mode:
1 = Initiate Start condition on SDA and SCL pins. Automatically cleared by hardware.
0 = Start condition Idle
In Slave mode:
1 = Clock stretching is enabled for both slave transmit and slave receive (stretch enabled)
0 = Clock stretching is disabled
Note 1: For bits ACKEN, RCEN, PEN, RSEN, SEN: If the I2C module is not in the Idle mode, this bit may not be
set (no spooling) and the SSP1BUF may not be written (or writes to the SSP1BUF are disabled).
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets
‘1’ = Bit is set ‘0’ = Bit is cleared
Note 1: For daisy-chained SPI operation; allows the user to ignore all but the last received byte. SSPOV is still set
when a new byte is received and BF = 1, but hardware continues to write the most recent byte to
SSP1BUF.
2: This bit has no effect in Slave modes that Start and Stop condition detection is explicitly listed as enabled.
3: The ACKTIM Status bit is only active when the AHEN bit or DHEN bit is set.
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets
‘1’ = Bit is set ‘0’ = Bit is cleared
REGISTER 30-6: SSP1ADD: MSSP ADDRESS AND BAUD RATE REGISTER (I2C MODE)
R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0
ADD<7:0>
bit 7 bit 0
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets
‘1’ = Bit is set ‘0’ = Bit is cleared
Master mode:
bit 7-3 Not used: Unused for Most Significant Address Byte. Bit state of this register is a “don’t care”. Bit
pattern sent by master is fixed by I2C specification and must be equal to ‘11110’. However, those bits
are compared by hardware and are not affected by the value in this register.
bit 2-1 ADD<2:1>: Two Most Significant bits of 10-bit address
bit 0 Not used: Unused in this mode. Bit state is a “don’t care”.
10-Bit Slave mode – Least Significant Address Byte:
TXEN
TRMT
Baud Rate Generator FOSC
÷n
TX9
BRG16 n
+1 Multiplier x4 x16 x64
TX9D
SYNC 1 X 0 0 0
SP1BRGH SP1BRGL BRGH X 1 1 0 0
BRG16 X 1 0 1 0
BRG16
+1 n
Multiplier x4 x16 x64
SYNC 1 X 0 0 0
SP1BRGH SP1BRGL BRGH FIFO
X 1 1 0 0 FERR RX9D RC1REG Register
BRG16 X 1 0 1 0
8
Data Bus
RCIF Interrupt
RCIE
Write to TX1REG
Word 1
BRG Output
(Shift Clock)
TX/CK
pin Start bit bit 0 bit 1 bit 7/8 Stop bit
Word 1
TXIF bit
(Transmit Buffer 1 TCY
Reg. Empty Flag)
Write to TX1REG
Word 1 Word 2
BRG Output
(Shift Clock)
TX/CK
pin Start bit bit 0 bit 1 bit 7/8 Stop bit Start bit bit 0
TXIF bit 1 TCY Word 1 Word 2
(Transmit Buffer
Reg. Empty Flag) 1 TCY
Read Rcv
Buffer Reg.
RC1REG
RCIF
(Interrupt Flag)
OERR bit
CREN
Note: This timing diagram shows three words appearing on the RX input. The RC1REG (receive buffer) is read after the third word,
causing the OERR (overrun) bit to be set.
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets
‘1’ = Bit is set ‘0’ = Bit is cleared
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets
‘1’ = Bit is set ‘0’ = Bit is cleared
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets
‘1’ = Bit is set ‘0’ = Bit is cleared
TABLE 31-4: SUMMARY OF REGISTERS ASSOCIATED WITH THE BAUD RATE GENERATOR
Register
Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
on Page
BAUD1CON ABDOVF RCIDL — SCKP BRG16 — WUE ABDEN 362
RC1STA SPEN RX9 SREN CREN ADDEN FERR OERR RX9D 361
SP1BRGL SP1BRG<7:0> 363
SP1BRGH SP1BRG<15:8> 363
TX1STA CSRC TX9 TXEN SYNC SENDB BRGH TRMT TX9D 360
Legend: — = unimplemented location, read as ‘0’. Shaded cells are not used for the Baud Rate Generator.
* Page provides register information.
BAUD FOSC = 32.000 MHz FOSC = 20.000 MHz FOSC = 18.432 MHz FOSC = 11.0592 MHz
RATE SPBRG SPBRG SPBRG SPBRG
Actual % Actual % Actual % Actual %
value value value value
Rate Error Rate Error Rate Error Rate Error
(decimal) (decimal) (decimal) (decimal)
300 — — — — — — — — — — — —
1200 — — — — — — — — — — — —
2400 — — — — — — — — — — — —
9600 9615 0.16 207 9615 0.16 129 9600 0.00 119 9600 0.00 71
10417 10417 0.00 191 10417 0.00 119 10378 -0.37 110 10473 0.53 65
19.2k 19.23k 0.16 103 19.23k 0.16 64 19.20k 0.00 59 19.20k 0.00 35
57.6k 57.14k -0.79 34 56.82k -1.36 21 57.60k 0.00 19 57.60k 0.00 11
115.2k 117.64k 2.12 16 113.64k -1.36 10 115.2k 0.00 9 115.2k 0.00 5
BAUD FOSC = 8.000 MHz FOSC = 4.000 MHz FOSC = 3.6864 MHz FOSC = 1.000 MHz
RATE SPBRG SPBRG SPBRG SPBRG
Actual % Actual % Actual % Actual %
value value value value
Rate Error Rate Error Rate Error Rate Error
(decimal) (decimal) (decimal) (decimal)
300 — — — — — — — — — 300 0.16 207
1200 — — — 1202 0.16 207 1200 0.00 191 1202 0.16 51
2400 2404 0.16 207 2404 0.16 103 2400 0.00 95 2404 0.16 25
9600 9615 0.16 51 9615 0.16 25 9600 0.00 23 — — —
10417 10417 0.00 47 10417 0.00 23 10473 0.53 21 10417 0.00 5
19.2k 19231 0.16 25 19.23k 0.16 12 19.2k 0.00 11 — — —
57.6k 55556 -3.55 8 — — — 57.60k 0.00 3 — — —
115.2k — — — — — — 115.2k 0.00 1 — — —
BAUD FOSC = 32.000 MHz FOSC = 20.000 MHz FOSC = 18.432 MHz FOSC = 11.0592 MHz
RATE SPBRG SPBRG SPBRG SPBRG
Actual % Actual % Actual % Actual %
value value value value
Rate Error Rate Error Rate Error Rate Error
(decimal) (decimal) (decimal) (decimal)
300 300.0 0.00 6666 300.0 -0.01 4166 300.0 0.00 3839 300.0 0.00 2303
1200 1200 -0.02 3332 1200 -0.03 1041 1200 0.00 959 1200 0.00 575
2400 2401 -0.04 832 2399 -0.03 520 2400 0.00 479 2400 0.00 287
9600 9615 0.16 207 9615 0.16 129 9600 0.00 119 9600 0.00 71
10417 10417 0.00 191 10417 0.00 119 10378 -0.37 110 10473 0.53 65
19.2k 19.23k 0.16 103 19.23k 0.16 64 19.20k 0.00 59 19.20k 0.00 35
57.6k 57.14k -0.79 34 56.818 -1.36 21 57.60k 0.00 19 57.60k 0.00 11
115.2k 117.6k 2.12 16 113.636 -1.36 10 115.2k 0.00 9 115.2k 0.00 5
BAUD FOSC = 8.000 MHz FOSC = 4.000 MHz FOSC = 3.6864 MHz FOSC = 1.000 MHz
RATE SPBRG SPBRG SPBRG SPBRG
Actual % Actual % Actual % Actual %
value value value value
Rate Error Rate Error Rate Error Rate Error
(decimal) (decimal) (decimal) (decimal)
300 299.9 -0.02 1666 300.1 0.04 832 300.0 0.00 767 300.5 0.16 207
1200 1199 -0.08 416 1202 0.16 207 1200 0.00 191 1202 0.16 51
2400 2404 0.16 207 2404 0.16 103 2400 0.00 95 2404 0.16 25
9600 9615 0.16 51 9615 0.16 25 9600 0.00 23 — — —
10417 10417 0.00 47 10417 0.00 23 10473 0.53 21 10417 0.00 5
19.2k 19.23k 0.16 25 19.23k 0.16 12 19.20k 0.00 11 — — —
57.6k 55556 -3.55 8 — — — 57.60k 0.00 3 — — —
115.2k — — — — — — 115.2k 0.00 1 — — —
BAUD FOSC = 32.000 MHz FOSC = 20.000 MHz FOSC = 18.432 MHz FOSC = 11.0592 MHz
RATE SPBRG SPBRG SPBRG SPBRG
Actual % Actual % Actual % Actual %
value value value value
Rate Error Rate Error Rate Error Rate Error
(decimal) (decimal) (decimal) (decimal)
300 300.0 0.00 26666 300.0 0.00 16665 300.0 0.00 15359 300.0 0.00 9215
1200 1200 0.00 6666 1200 -0.01 4166 1200 0.00 3839 1200 0.00 2303
2400 2400 0.01 3332 2400 0.02 2082 2400 0.00 1919 2400 0.00 1151
9600 9604 0.04 832 9597 -0.03 520 9600 0.00 479 9600 0.00 287
10417 10417 0.00 767 10417 0.00 479 10425 0.08 441 10433 0.16 264
19.2k 19.18k -0.08 416 19.23k 0.16 259 19.20k 0.00 239 19.20k 0.00 143
57.6k 57.55k -0.08 138 57.47k -0.22 86 57.60k 0.00 79 57.60k 0.00 47
115.2k 115.9k 0.64 68 116.3k 0.94 42 115.2k 0.00 39 115.2k 0.00 23
BAUD FOSC = 8.000 MHz FOSC = 4.000 MHz FOSC = 3.6864 MHz FOSC = 1.000 MHz
RATE SPBRG SPBRG SPBRG SPBRG
Actual % Actual % Actual % Actual %
value value value value
Rate Error Rate Error Rate Error Rate Error
(decimal) (decimal) (decimal) (decimal)
300 300.0 0.00 6666 300.0 0.01 3332 300.0 0.00 3071 300.1 0.04 832
1200 1200 -0.02 1666 1200 0.04 832 1200 0.00 767 1202 0.16 207
2400 2401 0.04 832 2398 0.08 416 2400 0.00 383 2404 0.16 103
9600 9615 0.16 207 9615 0.16 103 9600 0.00 95 9615 0.16 25
10417 10417 0 191 10417 0.00 95 10473 0.53 87 10417 0.00 23
19.2k 19.23k 0.16 103 19.23k 0.16 51 19.20k 0.00 47 19.23k 0.16 12
57.6k 57.14k -0.79 34 58.82k 2.12 16 57.60k 0.00 15 — — —
115.2k 117.6k 2.12 16 111.1k -3.55 8 115.2k 0.00 7 — — —
BRG Clock
RCIDL
RCIF bit
(Interrupt)
Read
RC1REG
Note 1: The ABD sequence requires the EUSART module to be configured in Asynchronous mode.
RCIF
Cleared due to User Read of RC1REG
Note 1: The EUSART remains in Idle while the WUE bit is set.
Note 1: If the wake-up event requires long oscillator warm-up time, the automatic clearing of the WUE bit can occur while the stposc signal is
still active. This sequence should not depend on the presence of Q clocks.
2: The EUSART remains in Idle while the WUE bit is set.
Write to TX1REG
Dummy Write
BRG Output
(Shift Clock)
TX (pin) Start bit bit 0 bit 1 bit 11 Stop bit
Break
TXIF bit
(Transmit
Interrupt Flag)
TRMT bit
(Transmit Shift
Empty Flag)
SENDB Sampled Here Auto Cleared
SENDB
(send Break
control bit)
TX/CK pin
(SCKP = 1)
Write to
TX1REG Reg Write Word 1 Write Word 2
TXIF bit
(Interrupt Flag)
TRMT bit
‘1’ ‘1’
TXEN bit
Note: Sync Master mode, SP1BRGL = 0, continuous transmission of two 8-bit words.
TX/CK pin
Write to
TX1REG reg
TXIF bit
TRMT bit
TXEN bit
RX/DT
pin bit 0 bit 1 bit 2 bit 3 bit 4 bit 5 bit 6 bit 7
TX/CK pin
(SCKP = 0)
TX/CK pin
(SCKP = 1)
Write to
bit SREN
SREN bit
RCIF bit
(Interrupt)
Read
RC1REG
Note: Timing diagram demonstrates Sync Master mode with bit SREN = 1 and bit BRGH = 0.
Pin 1 Indicator
Pin Description*
1 1 = VPP/MCLR
2
2 = VDD Target
3
4 3 = VSS (ground)
5
6 4 = ICSPDAT
5 = ICSPCLK
6 = No Connect
External
Programming VDD Device to be
Signals Programmed
VDD VDD
VPP MCLR/VPP
VSS VSS
Data ICSPDAT
Clock ICSPCLK
* * *
To Normal Connections
OPCODE only
13 0
OPCODE
INHERENT OPERATIONS
CLRWDT – Clear Watchdog Timer 1 00 0000 0110 0100 TO, PD
NOP – No Operation 1 00 0000 0000 0000
OPTION – Load OPTION_REG register with W 1 00 0000 0110 0010
RESET – Software device Reset 1 00 0000 0000 0001
SLEEP – Go into Standby mode 1 00 0000 0110 0011 TO, PD
TRIS f Load TRIS register with W 1 00 0000 0110 0fff
C-COMPILER OPTIMIZED
ADDFSR n, k Add Literal k to FSRn 1 11 0001 0nkk kkkk
MOVIW n mm Move Indirect FSRn to W with pre/post inc/dec 1 00 0000 0001 0nmm Z 2, 3
modifier, mm
k[n] Move INDFn to W, Indexed Indirect. 1 11 1111 0nkk kkkk Z 2
MOVWI n mm Move W to Indirect FSRn with pre/post inc/dec 1 00 0000 0001 1nmm 2, 3
modifier, mm
k[n] Move W to INDFn, Indexed Indirect. 1 11 1111 1nkk kkkk 2
Note 1: If the Program Counter (PC) is modified, or a conditional test is true, the instruction requires two cycles. The second
cycle is executed as a NOP.
2: If this instruction addresses an INDF register and the MSb of the corresponding FSR is set, this instruction will require
one additional instruction cycle.
Description: Bit ‘b’ in register ‘f’ is cleared. Description: If bit ‘b’ in register ‘f’ is ‘1’, the next
instruction is executed.
If bit ‘b’, in register ‘f’, is ‘0’, the next
instruction is discarded, and a NOP is
executed instead, making this a
2-cycle instruction.
C register f 0 Words: 1
Cycles: 1
Example: MOVF FSR, 0
After Instruction
W = value in FSR register
Z = 1
0 register f C
Before Instruction
W = 0x07
After Instruction
W = value of k8
Note 1: Maximum current rating requires even load distribution across I/O pins. Maximum current rating may be
limited by the device package power dissipation characterizations, see Table 34-6 to calculate device
specifications.
2: Power dissipation is calculated as follows:
Pdis = VDD* {Idd- ΣIoh} + Σ{VDD-Voh)*Ioh} + Σ(Vol*IoI).
† NOTICE: Stresses above those listed under “Absolute Maximum Ratings” may cause permanent damage to the
device. This is a stress rating only and functional operation of the device at those or any other conditions above those
indicated in the operation listings of this specification is not implied. Exposure above maximum rating conditions for
extended periods may affect device reliability.
5.5
VDD (V)
2.5
2.3
0 4 10 16 32
Frequency (MHz)
Note 1: The shaded region indicates the permissible combinations of voltage and frequency.
2: Refer to Table 34-7 for each Oscillator mode’s supported frequencies.
3.6
2.5
1.8
0 4 10 16 32
Frequency (MHz)
Note 1: The shaded region indicates the permissible combinations of voltage and frequency.
2: Refer to Table 34-7 for each Oscillator mode’s supported frequencies.
PIC16F1717/8/9
Param.
Sym. Characteristic Min. Typ.† Max. Units Conditions
No.
D001 VDD Supply Voltage
VDDMIN VDDMAx
1.8 — 3.6 V FOSC 16 MHz
2.5 — 3.6 V FOSC 32 MHz (Note 2)
D001 2.3 — 5.5 V FOSC 16 MHz
2.5 — 5.5 V FOSC 32 MHz (Note 2)
D002* VDR RAM Data Retention Voltage(1)
1.5 — — V Device in Sleep mode
D002* 1.7 — — V Device in Sleep mode
D002A* VPOR Power-on Reset Release Voltage(3)
— 1.6 — V
D002A* — 1.6 — V
D002B* VPORR* Power-on Reset Rearm Voltage(3)
— 0.8 — V
D002B* — 1.5 — V
D003 VFVR Fixed Voltage Reference Voltage -4 — +4 % 1x Gain, 1.024, VDD 2.5V,
-40°C to 85°C
-4 — +4 % 2x Gain, 2.048, VDD 2.5V,
-40°C to 85°C
-5 — +5 % 4x Gain, 4.096, VDD 4.75V,
-40°C to 85°C
D004* SVDD VDD Rise Rate(2) 0.05 — — V/ms Ensures that the Power-on
Reset signal is released
properly.
*
These parameters are characterized but not tested.
†
Data in “Typ” column is at 3.0V, 25°C unless otherwise stated. These parameters are for design guidance only
and are not tested.
Note 1: This is the limit to which VDD can be lowered in Sleep mode without losing RAM data.
2: PLL required for 32 MHz operation.
3: See Figure 34-3: POR and POR Rearm with Slow Rising VDD.
VDD
VPOR
VPORR
SVDD
VSS
NPOR(1)
POR REARM
VSS
TVLOW(2) TPOR(3)
PIC16F1717/8/9
PIC16F1717/8/9
Param.
Sym. Characteristic Min. Typ.† Max. Units Conditions
No.
VIL Input Low Voltage
I/O PORT:
D034 with TTL buffer — — 0.8 V 4.5V VDD 5.5V
D034A — — 0.15 VDD V 1.8V VDD 4.5V
D035 with Schmitt Trigger buffer — — 0.2 VDD V 2.0V VDD 5.5V
with I2C levels — — 0.3 VDD V
with SMBus levels — — 0.8 V 2.7V VDD 5.5V
D036 MCLR, OSC1 (EXTRC mode) — — 0.2 VDD V (Note 1)
D036A OSC1 (HS mode) — — 0.3 VDD V
VIH Input High Voltage
I/O ports:
D040 with TTL buffer 2.0 — — V 4.5V VDD 5.5V
D040A 0.25 VDD + 0.8 — — V 1.8V VDD 4.5V
D041 with Schmitt Trigger buffer 0.8 VDD — — V 2.0V VDD 5.5V
with I2C levels 0.7 VDD — — V
with SMBus levels 2.1 — — V 2.7V VDD 5.5V
D042 MCLR 0.8 VDD — — V
D043A OSC1 (HS mode) 0.7 VDD — — V
D043B OSC1 (EXTRC oscillator) 0.9 VDD — — V VDD 2.0V(Note 1)
IIL Input Leakage Current(2)
D060 I/O Ports — ±5 ± 125 nA VSS VPIN VDD,
Pin at high-impedance,
85°C
— ±5 ± 1000 nA VSS VPIN VDD,
Pin at high-impedance,
125°C
D061 MCLR(3) — ±5 ± 200 nA VSS VPIN VDD,
Pin at high-impedance,
85°C
* These parameters are characterized but not tested.
† Data in “Typ” column is at 3.0V, 25°C unless otherwise stated. These parameters are for design guidance
only and are not tested.
Note 1: In EXTRC oscillator configuration, the OSC1/CLKIN pin is a Schmitt Trigger input. It is not recommended to
use an external clock in EXTRC mode.
2: Negative current is defined as current sourced by the pin.
3: The leakage current on the MCLR pin is strongly dependent on the applied voltage level. The specified
levels represent normal operating conditions. Higher leakage current may be measured at different input
voltages.
4: Including OSC2 in CLKOUT mode.
Param.
Sym. Characteristic Min. Typ.† Max. Units Conditions
No.
IPUR Weak Pull-up Current
D070* 25 100 200 A VDD = 3.3V, VPIN = Vss
25 140 300 A VDD = 5.0V, VPIN = Vss
VOL Output Low Voltage(4)
D080 I/O ports — — 0.6 V IOL = 8mA, VDD = 5V
IOL = 6mA, VDD = 3.3V
IOL = 1.8mA, VDD = 1.8V
VOH Output High Voltage(4)
D090 I/O ports VDD - 0.7 — — V IOH = 3.5mA, VDD = 5V
IOH = 3mA, VDD = 3.3V
IOH = 1mA, VDD = 1.8V
Capacitive Loading Specs on Output Pins
D101* COSC2 OSC2 pin — — 15 pF In XT, HS and LP modes
when external clock is
used to drive OSC1
D101A* CIO All I/O pins — — 50 pF —
* These parameters are characterized but not tested.
† Data in “Typ” column is at 3.0V, 25°C unless otherwise stated. These parameters are for design guidance
only and are not tested.
Note 1: In EXTRC oscillator configuration, the OSC1/CLKIN pin is a Schmitt Trigger input. It is not recommended to
use an external clock in EXTRC mode.
2: Negative current is defined as current sourced by the pin.
3: The leakage current on the MCLR pin is strongly dependent on the applied voltage level. The specified
levels represent normal operating conditions. Higher leakage current may be measured at different input
voltages.
4: Including OSC2 in CLKOUT mode.
Param.
Sym. Characteristic Min. Typ.† Max. Units Conditions
No.
Program Memory Programming Specifications
D110 VIHH Voltage on MCLR/VPP pin 8.0 — 9.0 V (Note 2)
D111 IDDP Supply Current during Programming — — 10 mA
D112 VBE VDD for Bulk Erase 2.7 — VDDMAX V
D113 VPEW VDD for Write or Row Erase VDDMIN — VDDMAX V
D114 IPPGM Current on MCLR/VPP during — 1.0 — mA
Erase/Write
D115 IDDPGM Current on VDD during Erase/Write — 5.0 — mA
Program Flash Memory
D121 EP Cell Endurance 10K — — E/W -40C TA +85C
(Note 1)
D122 VPRW VDD for Read/Write VDDMIN — VDDMAX V
D123 TIW Self-timed Write Cycle Time — 2 2.5 ms
D124 TRETD Characteristic Retention — 40 — Year Provided no other
specifications are
violated
D125 EHEFC High-Endurance Flash Cell 100K — — E/W -0C TA +60°C,
Lower byte last 128
addresses
† Data in “Typ” column is at 3.0V, 25°C unless otherwise stated. These parameters are for design guidance
only and are not tested.
Note 1: Self-write and Block Erase.
2: Required only if single-supply programming is disabled.
Param.
Sym. Characteristic Typ. Units Conditions
No.
TH01 JA Thermal Resistance Junction to 60.0 C/W 28-pin SPDIP package
Ambient 80.3 C/W 28-pin SOIC package
90.0 C/W 28-pin SSOP package
36.0 C/W 28-pin QFN 6x6 mm package
48.0 C/W 28-pin UQFN 4x4 mm package
47.2 C/W 40-pin PDIP package
46.0 C/W 44-pin TQFP
41.0 C/W 40-pin UQFN 5x5 mm package
TH02 JC Thermal Resistance Junction to 31.4 C/W 28-pin SPDIP package
Case 24.0 C/W 28-pin SOIC package
24.0 C/W 28-pin SSOP package
6.0 C/W 28-pin QFN 6x6 mm package
12.0 C/W 28-pin UQFN 4x4 mm package
24.7 C/W 40-pin PDIP package
14.5 C/W 44-pin TQFP
50.5 C/W 40-pin UQFN 5x5 mm package
TH03 TJMAX Maximum Junction Temperature 150 C —
TH04 PD Power Dissipation — W PD = PINTERNAL + PI/O
TH05 PINTERNAL Internal Power Dissipation — W PINTERNAL = IDD x VDD(1)
TH06 PI/O I/O Power Dissipation — W PI/O = (IOL * VOL) + (IOH * (VDD - VOH))
TH07 PDER Derated Power — W PDER = PDMAX (TJ - TA)/JA(2)
Note 1: IDD is current to run the chip alone without driving any load on the output pins.
2: TA = Ambient Temperature, TJ = Junction Temperature
Pin CL
VSS
Q4 Q1 Q2 Q3 Q4 Q1
CLKIN
OS02 OS12 OS11
OS03
CLKOUT
(CLKOUT Mode)
Param.
Sym. Characteristic Min. Typ.† Max. Units Conditions
No.
OS01 FOSC External CLKIN Frequency(1) DC — 0.5 MHz External Clock (ECL)
DC — 4 MHz External Clock (ECM)
DC — 20 MHz External Clock (ECH)
(1)
Oscillator Frequency — 32.768 — kHz LP Oscillator
0.1 — 4 MHz XT Oscillator
1 — 4 MHz HS Oscillator
1 — 20 MHz HS Oscillator, VDD > 2.7V
DC — 4 MHz EXTRC, VDD > 2.0V
OS02 TOSC External CLKIN Period(1) 27 — s LP Oscillator
250 — ns XT Oscillator
50 — ns HS Oscillator
50 — ns External Clock (EC)
Oscillator Period(1) — 30.5 — s LP Oscillator
250 — 10,000 ns XT Oscillator
50 — 1,000 ns HS Oscillator
250 — — ns EXTRC
OS03 TCY Instruction Cycle Time(1) 125 TCY DC ns TCY = 4/FOSC
OS04* TOSH, External CLKIN High, 2 — — s LP Oscillator
TOSL External CLKIN Low 100 — — ns XT Oscillator
20 — — ns HS Oscillator
OS05* TOSR, External CLKIN Rise, 0 — ns LP Oscillator
TOSF External CLKIN Fall 0 — ns XT Oscillator
0 — ns HS Oscillator
* These parameters are characterized but not tested.
† Data in “Typ” column is at 3.0V, 25°C unless otherwise stated. These parameters are for design guidance
only and are not tested.
Note 1: Instruction cycle period (TCY) equals four times the input oscillator time base period. All specified values are
based on characterization data for that particular oscillator type under standard operating conditions with the
device executing code. Exceeding these specified limits may result in an unstable oscillator operation and/or
higher than expected current consumption. All devices are tested to operate at “min” values with an external
clock applied to OSC1 pin. When an external clock input is used, the “max” cycle time limit is “DC” (no clock)
for all devices.
Param. Freq.
Sym. Characteristic Min. Typ.† Max. Units Conditions
No. Tolerance
OS08 HFOSC Internal Calibrated HFINTOSC ±2% — 16.0 — MHz VDD = 3.0V, TA = 25°C,
Frequency(1) (Note 2)
OS08A MFOSC Internal Calibrated MFINTOSC ±2% — 500 — kHz VDD = 3.0V, TA = 25°C,
Frequency(1) (Note 2)
OS09 LFOSC Internal LFINTOSC Frequency — — 31 — kHz -40°C TA +125°C,
(Note 3)
OS10* TWARM HFINTOSC — — 3.2 8 s
Wake-up from Sleep Start-up Time
MFINTOSC — — 24 35 s
Wake-up from Sleep Start-up Time
LFINTOSC — — 0.5 — ms
Wake-up from Sleep Start-up Time
*
These parameters are characterized but not tested.
†
Data in “Typ” column is at 3.0V, 25°C unless otherwise stated. These parameters are for design guidance only
and are not tested.
Note 1: To ensure these oscillator frequency tolerances, VDD and VSS must be capacitively decoupled as close to the
device as possible. 0.1 F and 0.01 F values in parallel are recommended.
2: See Figure 34-6.
3: See Figure 35-57: LFINTOSC Frequency, PIC16LF1717/8/9 Only., and
Figure 35-58: LFINTOSC Frequency, PIC16F1717/8/9 Only..
FIGURE 34-6: HFINTOSC FREQUENCY ACCURACY OVER DEVICE VDD AND TEMPERATURE
125
± 5%
85
± 3%
Temperature (°C)
60
± 2%
25
0
-20
± 5%
-40
1.8 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5
VDD (V)
Param.
Sym. Characteristic Min. Typ.† Max. Units Conditions
No.
F10 FOSC Oscillator Frequency Range 4 — 8 MHz
F11 FSYS On-Chip VCO System Frequency 16 — 32 MHz
F12 TRC PLL Start-up Time (Lock Time) — — 2 ms
F13* CLK CLKOUT Stability (Jitter) -0.25% — +0.25% %
* These parameters are characterized but not tested.
† Data in “Typ” column is at 5V, 25C unless otherwise stated. These parameters are for design guidance
only and are not tested.
Param.
Sym. Characteristic Min. Typ.† Max. Units Conditions
No.
OS11 TOSH2CKL FOSC to CLKOUT (1) — — 70 ns 3.3V VDD 5.0V
OS12 TOSH2CKH FOSC to CLKOUT (1) — — 72 ns 3.3V VDD 5.0V
OS13 TCKL2IOV CLKOUT to Port out valid(1) — — 20 ns
OS14 TIOV2CKH Port input valid before CLKOUT(1) TOSC + 200 ns — — ns
OS15 TOSH2IOV FOSC (Q1 cycle) to Port out valid — 50 70* ns 3.3V VDD 5.0V
OS16 TOSH2IOI FOSC (Q2 cycle) to Port input invalid 50 — — ns 3.3V VDD 5.0V
(I/O in hold time)
OS17 TIOV2OSH Port input valid to FOSC(Q2 cycle) 20 — — ns
(I/O in setup time)
OS18* TIOR Port output rise time(2) — 40 72 ns VDD = 1.8V
— 15 32 3.3V VDD 5.0V
OS19* TIOF Port output fall time(2) — 28 55 ns VDD = 1.8V
— 15 30 3.3V VDD 5.0V
OS20* TINP INT pin input high or low time 25 — — ns
OS21* TIOC Interrupt-on-Change new input level 25 — — ns
time
* These parameters are characterized but not tested.
† Data in “Typ” column is at 3.0V, 25C unless otherwise stated.
Note 1: Measurements are taken in EXTRC mode where CLKOUT output is 4 x TOSC.
2: Slew rate limited.
VDD
MCLR
30
Internal
POR
33
PWRT
Time-out 32
OSC
Start-up Time
Internal Reset(1)
Watchdog Timer
Reset(1)
31
34
34
I/O pins
TABLE 34-11: RESET, WATCHDOG TIMER, OSCILLATOR START-UP TIMER, POWER-UP TIMER
AND BROWN-OUT RESET PARAMETERS
Standard Operating Conditions (unless otherwise stated)(2)
Param.
Sym. Characteristic Min. Typ† Max. Units Conditions
No.
T0CKI
40 41
42
T1CKI
45 46
47 49
TMR0 or
TMR1
VDD
VBOR and VHYST
VBOR
37
Reset
33(1)
(due to BOR)
Note 1: 64 ms delay only if PWRTE bit in the Configuration Word register is programmed to ‘0’.
2 ms delay if PWRTE = 0.
Param.
Sym. Characteristic Min. Typ.† Max. Units Conditions
No.
40* TT0H T0CKI High Pulse Width No Prescaler 0.5 TCY + 20 — — ns
With Prescaler 10 — — ns
41* TT0L T0CKI Low Pulse Width No Prescaler 0.5 TCY + 20 — — ns
With Prescaler 10 — — ns
42* TT0P T0CKI Period Greater of: — — ns N = prescale value
20 or TCY + 40
N
45* TT1H T1CKI High Synchronous, No Prescaler 0.5 TCY + 20 — — ns
Time Synchronous, with Prescaler 15 — — ns
Asynchronous 30 — — ns
46* TT1L T1CKI Low Synchronous, No Prescaler 0.5 TCY + 20 — — ns
Time Synchronous, with Prescaler 15 — — ns
Asynchronous 30 — — ns
47* TT1P T1CKI Input Synchronous Greater of: — — ns N = prescale value
Period 30 or TCY + 40
N
Asynchronous 60 — — ns
48 FT1 Secondary Oscillator Input Frequency Range 32.4 32.76 33.1 kHz
(oscillator enabled by setting bit T1OSCEN) 8
49* TCKEZTMR1 Delay from External Clock Edge to Timer 2 TOSC — 7 TOSC — Timers in Sync
Increment mode
* These parameters are characterized but not tested.
† Data in “Typ” column is at 3.0V, 25°C unless otherwise stated. These parameters are for design guidance only and are not
tested.
CC01 CC02
CC03
Param.
Sym. Characteristic Min. Typ.† Max. Units Conditions
No.
CC01* TCCL CCPx Input Low Time No Prescaler 0.5TCY + 20 — — ns
With Prescaler 20 — — ns
CC02* TCCH CCPx Input High Time No Prescaler 0.5TCY + 20 — — ns
With Prescaler 20 — — ns
CC03* TCCP CCPx Input Period 3TCY + 40 — — ns N = prescale value
N
* These parameters are characterized but not tested.
† Data in “Typ” column is at 3.0V, 25°C unless otherwise stated. These parameters are for design guidance only and are not
tested.
Note 1: See Figure 19-1: CLCx Simplified Block Diagram to identify specific CLC signals.
Param.
Sym. Characteristic Min. Typ† Max. Units Conditions
No.
CLC01* TCLCIN CLC input time — 7 OS17 ns (Note 1)
CLC02* TCLC CLC module input to output progagation time — 24 — ns VDD = 1.8V
— 12 — ns VDD > 3.6V
CLC03* TCLCOUT CLC output time Rise Time — OS18 — — (Note 1)
Fall Time — OS19 — — (Note 1)
CLC04* FCLCMAX CLC maximum switching frequency — 45 — MHz
* These parameters are characterized but not tested.
† Data in “Typ” column is at 3.0V, 25°C unless otherwise stated. These parameters are for design guidance
only and are not tested.
Note 1: See Table 34-10 for OS17, OS18 and OS19 rise and fall times.
Param.
Sym. Characteristic Min. Typ.† Max. Units Conditions
No.
AD01 NR Resolution — — 10 bit
AD02 EIL Integral Error — — ±1.7 LSb VREF = 3.0V
AD03 EDL Differential Error — — ±1 LSb No missing codes, VREF = 3.0V
AD04 EOFF Offset Error — — ±2.5 LSb VREF = 3.0V
AD05 EGN Gain Error — — ±2.0 LSb VREF = 3.0V
AD06 VREF Reference Voltage 1.8 — VDD V VREF = (VREF+ minus VREF-)
AD07 VAIN Full-Scale Range VSS — VREF V
AD08 ZAIN Recommended Impedance of — — 10 k Can go higher if external 0.01F capacitor
Analog Voltage Source is present on input pin.
* These parameters are characterized but not tested.
† Data in “Typ” column is at 3.0V, 25°C unless otherwise stated. These parameters are for design guidance only and
are not tested.
Note 1: Total Absolute Error includes integral, differential, offset and gain errors.
2: The ADC conversion result never decreases with an increase in the input voltage and has no missing codes.
3: ADC VREF is from external VREF+ pin, VDD pin or FVR, whichever is selected as reference input.
4: See Section 35.0 “DC and AC Characteristics Graphs and Charts” for operating characterization.
Param.
Sym. Characteristic Min. Typ.† Max. Units Conditions
No.
AD130* TAD ADC Clock Period (TADC) 1.0 — 9.0 s FOSC-based
ADC Internal FRC Oscillator 1.0 2 6.0 s ADCS<1:0> = 11 (ADC FRC
Period (TFRC) mode)
AD131 TCNV Conversion Time (not including — 11 — TAD Set GO/DONE bit to conversion
Acquisition Time)(1) complete
AD132* TACQ Acquisition Time — 5.0 — s
AD133* THCD Holding Capacitor Disconnect — 1/2 TAD — ADCS<2:0> x11 (FOSC-based)
Time — 1/2 TAD + 1TCY — ADCS<2:0> = x11 (FRC-based)
*These parameters are characterized but not tested.
†Data in “Typ” column is at 3.0V, 25°C unless otherwise stated. These parameters are for design guidance only and
are not tested.
Note 1: The ADRES register may be read on the following TCY cycle.
BSF ADCON0, GO
1 TCY
AD133
AD131
Q4
AD130
ADC_clk
ADC Data 9 8 7 6 3 2 1 0
ADIF 1 TCY
GO DONE
Sampling Stopped
Sample AD132
BSF ADCON0, GO
AD133 1 TCY
AD131
Q4
AD130
ADC_clk
ADC Data 9 8 7 6 3 2 1 0
ADIF 1 TCY
GO DONE
Note 1: If the ADC clock source is selected as FRC, a time of TCY is added before the ADC clock starts. This allows the
SLEEP instruction to be executed.
Param.
Symbol Characteristics Min. Typ. Max. Units Conditions
No.
OPA01* GBWP Gain Bandwidth Product — 2 — MHz
OPA02* TON Turn on Time — 10 — s
OPA03* PM Phase Margin — 40 — degrees
OPA04* SR Slew Rate — 3 — V/s
OPA05 OFF Offset — ±3 ±9 mV
OPA06 CMRR Common Mode Rejection Ratio 55 70 — dB
OPA07* AOL Open Loop Gain — 90 — dB
OPA08 VICM Input Common Mode Voltage 0 — VDD V VDD > 2.5V
OPA09* PSRR Power Supply Rejection Ratio — 80 — dB
* These parameters are characterized but not tested.
Param.
Sym. Characteristics Min. Typ. Max. Units Comments
No.
CM01 VIOFF Input Offset Voltage — ±2.5 ±5 mV CxSP = 1,
VICM = VDD/2
CM02 VICM Input Common Mode Voltage 0 — VDD V
CM03 CMRR Common Mode Rejection Ratio 40 50 — dB
CM04A TRESP(1) Response Time Rising Edge — 60 85 ns CxSP = 1
CM04B Response Time Falling Edge — 60 90 ns CxSP = 1
CM04C Response Time Rising Edge — 85 — ns CxSP = 0
CM04D Response Time Falling Edge — 85 — ns CxSP = 0
CM05* TMC2OV Comparator Mode Change to — — 10 s
Output Valid*
CM06 CHYSTER Comparator Hysteresis 20 45 75 mV CxHYS = 1,
CxSP = 1
* These parameters are characterized but not tested.
Note 1: Response time measured with one comparator input at VDD/2, while the other input transitions from VSS to
VDD.
Param.
Sym. Characteristics Min. Typ. Max. Units Comments
No.
DAC01* CLSB Step Size — VDD/256 — V
DAC02* CACC Absolute Accuracy — — 1.5 LSb
DAC03* CR Unit Resistor Value (R) — 600 —
DAC04* CST Settling Time (1)
— — 10 s
* These parameters are characterized but not tested.
Note 1: Settling time measured while DACR<7:0> transitions from ‘0x00’ to ‘0xFF’.
Param.
Sym. Characteristics Min. Typ. Max. Units Comments
No.
DAC05* CLSB Step Size — VDD/32 — V
DAC06* CACC Absolute Accuracy — — 0.5 LSb
DAC07* CR Unit Resistor Value (R) — 6000 —
DAC08* CST Settling Time(1) — — 10 s
* These parameters are characterized but not tested.
Note 1: Settling time measured while DACR<7:0> transitions from ‘0x00’ to ‘0xFF’.
CK
US121 US121
DT
US120 US122
Param.
Symbol Characteristic Min. Max. Units Conditions
No.
US120 TCKH2DTV SYNC XMIT (Master and Slave) — 80 ns 3.0V VDD 5.5V
Clock high to data-out valid — 100 ns 1.8V VDD 5.5V
US121 TCKRF Clock out rise time and fall time — 45 ns 3.0V VDD 5.5V
(Master mode) — 50 ns 1.8V VDD 5.5V
US122 TDTRF Data-out rise time and fall time — 45 ns 3.0V VDD 5.5V
— 50 ns 1.8V VDD 5.5V
CK
US125
DT
US126
Param.
Symbol Characteristic Min. Max. Units Conditions
No.
US125 TDTV2CKL SYNC RCV (Master and Slave)
Data-setup before CK (DT hold time) 10 — ns
US126 TCKL2DTL Data-hold after CK (DT hold time) 15 — ns
SS
SP81
SCK
(CKP = 0)
SP71 SP72
SP78 SP79
SCK
(CKP = 1)
SP79 SP78
SP80
SP75, SP76
SP74
SP73
SS
SP81
SCK
(CKP = 0)
SP71 SP72
SP79
SP73
SCK
(CKP = 1)
SP80
SP78
SP75, SP76
SP74
SS
SP70
SCK SP83
(CKP = 0)
SP71 SP72
SP78 SP79
SCK
(CKP = 1)
SP79 SP78
SP80
SP74
SP73
SP82
SS
SP70
SCK SP83
(CKP = 0)
SP71 SP72
SCK
(CKP = 1)
SP80
SP77
SP75, SP76
SDI
MSb In bit 6 - - - -1 LSb In
SP74
Param.
Symbol Characteristic Min. Typ.† Max. Units Conditions
No.
SCL
SP91 SP93
SP90 SP92
SDA
Start Stop
Condition Condition
Param.
Symbol Characteristic Min. Typ. Max. Units Conditions
No.
SP90* TSU:STA Start condition 100 kHz mode 4700 — — ns Only relevant for Repeated
Setup time 400 kHz mode 600 — — Start condition
SP91* THD:STA Start condition 100 kHz mode 4000 — — ns After this period, the first
Hold time 400 kHz mode 600 — — clock pulse is generated
SP92* TSU:STO Stop condition 100 kHz mode 4700 — — ns
Setup time 400 kHz mode 600 — —
SP93 THD:STO Stop condition 100 kHz mode 4000 — — ns
Hold time 400 kHz mode 600 — —
* These parameters are characterized but not tested.
SCL
SP90
SP106
SP107
SP91 SP92
SDA
In
SP110
SP109
SP109
SDA
Out
Param.
Symbol Characteristic Min. Max. Units Conditions
No.
SP100* THIGH Clock high time 100 kHz mode 4.0 — s Device must operate at a
minimum of 1.5 MHz
400 kHz mode 0.6 — s Device must operate at a
minimum of 10 MHz
SSP module 1.5TCY —
SP101* TLOW Clock low time 100 kHz mode 4.7 — s Device must operate at a
minimum of 1.5 MHz
400 kHz mode 1.3 — s Device must operate at a
minimum of 10 MHz
SSP module 1.5TCY —
SP102* TR SDA and SCL rise 100 kHz mode — 1000 ns
time 400 kHz mode 20 + 0.1CB 300 ns CB is specified to be from
10-400 pF
SP103* TF SDA and SCL fall 100 kHz mode — 250 ns
time 400 kHz mode 20 + 0.1CB 250 ns CB is specified to be from
10-400 pF
SP106* THD:DAT Data input hold time 100 kHz mode 0 — ns
400 kHz mode 0 0.9 s
SP107* TSU:DAT Data input setup 100 kHz mode 250 — ns (Note 2)
time 400 kHz mode 100 — ns
SP109* TAA Output valid from 100 kHz mode — 3500 ns (Note 1)
clock 400 kHz mode — — ns
SP110* TBUF Bus free time 100 kHz mode 4.7 — s Time the bus must be free
400 kHz mode 1.3 — s before a new transmission
can start
SP111 CB Bus capacitive loading — 400 pF
* These parameters are characterized but not tested.
Note 1: As a transmitter, the device must provide this internal minimum delay time to bridge the undefined region
(min. 300 ns) of the falling edge of SCL to avoid unintended generation of Start or Stop conditions.
2: A Fast mode (400 kHz) I2C bus device can be used in a Standard mode (100 kHz) I2C bus system, but the
requirement TSU:DAT 250 ns must then be met. This will automatically be the case if the device does not
stretch the low period of the SCL signal. If such a device does stretch the low period of the SCL signal, it
must output the next data bit to the SDA line TR max. + TSU:DAT = 1000 + 250 = 1250 ns (according to the
Standard mode I2C bus specification), before the SCL line is released.
10 400
8 Max. 300
7 Typical
250
IDD (µA)
IDD (µA)
6 200
5 150 1 MHz XT
4 100
3 50
2 0
1.6 1.8 2.0 2.2 2.4 2.6 2.8 3.0 3.2 3.4 3.6 3.8 1.6 1.8 2.0 2.2 2.4 2.6 2.8 3.0 3.2 3.4 3.6 3.8
FIGURE 35-1: IDD, LP Oscillator Mode, FIGURE 35-4: IDD Maximum, XT and
Fosc = 32 kHz, PIC16LF1717/8/9 Only. EXTRC Oscillator, PIC16LF1717/8/9 Only.
28 450
4 MHz XT
Max: 85°C + 3ı Max.
26 400 Typical: 25°C
Typical: 25°C
24 350
Typical
22 300
IDD (µA)
20 250
IDD (µA)
1 MHz XT
18 200
16 150
14 100
12 50
10 0
2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0
FIGURE 35-2: IDD, LP Oscillator Mode, FIGURE 35-5: IDD Typical, XT and EXTRC
Fosc = 32 kHz, PIC16F1717/8/9 Only. Oscillator, PIC16F1717/8/9 Only.
400 500
4 MHz XT
450 Max: 85°C + 3ı
350 Typical: 25°C
400
4 MHz XT
300
350
250 300
IDD (µA)
IDD (µA)
200
150
1 MHz XT 150
100
100
50
50
0 0
1.6 1.8 2.0 2.2 2.4 2.6 2.8 3.0 3.2 3.4 3.6 3.8 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0
FIGURE 35-3: IDD Typical, XT and EXTRC FIGURE 35-6: IDD Maximum, XT and
Oscillator, PIC16LF1717/8/9 Only. EXTRC Oscillator, PIC16F1717/8/9 Only.
12 60
Max: 85°C + 3ı Max. Max.
Typical: 25°C 55 Max: 85°C + 3ı
10 Typical: 25°C
50
Typical
8
45
IDD (µA)
IDD (µA)
Typical
6 40
35
4
30
2
25
0 20
1.6 1.8 2.0 2.2 2.4 2.6 2.8 3.0 3.2 3.4 3.6 3.8 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0
FIGURE 35-7: IDD, EC Oscillator LP Mode, FIGURE 35-10: IDD, EC Oscillator LP Mode,
Fosc = 32 kHz, PIC16LF1717/8/9 Only. Fosc = 500 kHz, PIC16F1717/8/9 Only.
24 350
20 250
Typical
IDD (µA)
18 200
IDD (µA)
16 150
14 100 1 MHz
12 50
10 0
2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0 1.6 1.8 2.0 2.2 2.4 2.6 2.8 3.0 3.2 3.4 3.6 3.8
FIGURE 35-8: IDD, EC Oscillator LP Mode, FIGURE 35-11: IDD Typical, EC Oscillator
Fosc = 32 kHz, PIC16F1717/8/9 Only. MP Mode, PIC16LF1717/8/9 Only.
50 350
35
IDD (µA)
200
IDD (µA)
Typical
30
150
25
1 MHz
100
20
15 50
10 0
1.6 1.8 2.0 2.2 2.4 2.6 2.8 3.0 3.2 3.4 3.6 3.8 1.6 1.8 2.0 2.2 2.4 2.6 2.8 3.0 3.2 3.4 3.6 3.8
FIGURE 35-9: IDD, EC Oscillator LP Mode, FIGURE 35-12: IDD Maximum, EC Oscillator
Fosc = 500 kHz, PIC16LF1717/8/9 Only. MP Mode, PIC16LF1717/8/9 Only.
400 3.0
2.0
250
IDD (µA)
IDD (mA)
200 1.5
1 MHz
150 16 MHz
1.0
100
8 MHz
0.5
50
0 0.0
2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0 1.6 1.8 2.0 2.2 2.4 2.6 2.8 3.0 3.2 3.4 3.6 3.8
FIGURE 35-13: IDD Typical, EC Oscillator FIGURE 35-16: IDD Maximum, EC Oscillator
MP Mode, PIC16F1717/8/9 Only. HP Mode, PIC16LF1717/8/9 Only.
450 2.5
32 MHz
400 Max: 85°C + 3ı Typical: 25°C
2.0
350 4 MHz
300
1.5
IDD (µA)
IDD (mA)
250
16 MHz
200
1 MHz 1.0
150 8 MHz
100 0.5
50
0 0.0
2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0
FIGURE 35-14: IDD Maximum, EC Oscillator FIGURE 35-17: IDD Typical, EC Oscillator
MP Mode, PIC16F1717/8/9 Only. HP Mode, PIC16F1717/8/9 Only.
2.5 2.5
2.0 2.0
1.5 1.5
IDD (mA)
IDD (mA)
16 MHz
16 MHz
1.0 1.0
8 MHz
8 MHz 0.5
0.5
0.0 0.0
1.6 1.8 2.0 2.2 2.4 2.6 2.8 3.0 3.2 3.4 3.6 3.8 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0
FIGURE 35-15: IDD Typical, EC Oscillator FIGURE 35-18: IDD Maximum, EC Oscillator
HP Mode, PIC16LF1717/8/9 Only. HP Mode, PIC16F1717/8/9 Only.
9 260
Max.
Max.
8 Max: 85°C + 3ı Max: 85°C + 3ı
240
Typical: 25°C Typical: 25°C
7 Typical
220
6 Typical
200
IDD (µA)
IDD (µA)
5
180
4
160
3
2 140
1 120
0 100
1.6 1.8 2.0 2.2 2.4 2.6 2.8 3.0 3.2 3.4 3.6 3.8 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0
FIGURE 35-19: IDD, LFINTOSC Mode, FIGURE 35-22: IDD, MFINTOSC Mode,
Fosc = 31 kHz, PIC16LF1717/8/9 Only. Fosc = 500 kHz, PIC16F1717/8/9 Only.
24 1.6
Max. 16 MHz
22 1.4 Typical: 25°C
20 Typical 1.2
IDD (µA)
IDD (mA)
18 1.0
8 MHz
16 0.8
4 MHz
14 0.6
2 MHz
12 0.4
Max: 85°C + 3ı
Typical: 25°C 1 MHz
0.2
10
1.6 1.8 2.0 2.2 2.4 2.6 2.8 3.0 3.2 3.4 3.6 3.8
2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0
VDD (V)
VDD (V)
FIGURE 35-20: IDD, LFINTOSC Mode, FIGURE 35-23: IDD Typical, HFINTOSC
Fosc = 31 kHz, PIC16F1717/8/9 Only. Mode, PIC16LF1717/8/9 Only.
180 1.6
16 MHz
170 Max: 85°C + 3ı
Typical: 25°C 1.4 Max: 85°C + 3ı
160 Max.
1.2
150
IDD (mA)
8 MHz
IDD (µA)
1.0
Typical
140
0.8
130 4 MHz
0.6 2 MHz
120
100 0.2
1.6 1.8 2.0 2.2 2.4 2.6 2.8 3.0 3.2 3.4 3.6 3.8 1.6 1.8 2.0 2.2 2.4 2.6 2.8 3.0 3.2 3.4 3.6 3.8
FIGURE 35-21: IDD, MFINTOSC Mode, FIGURE 35-24: IDD Maximum, HFINTOSC
Fosc = 500 kHz, PIC16LF1717/8/9 Only. Mode, PIC16LF1717/8/9 Only.
1.6 2.0
1.2 1.4
16 MHz
1.2
1.0 8 MHz
IDD (mA)
IDD (mA)
1.0
0.8
4 MHz 0.8
0.6 8 MHz
0.6 2 MHz
0.4
0.4 1 MHz 4 MHz
0.2
0.2 0.0
2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0 2.4 2.6 2.8 3.0 3.2 3.4 3.6 3.8
FIGURE 35-25: IDD Typical, HFINTOSC FIGURE 35-28: IDD Maximum, HS Oscillator,
Mode, PIC16F1717/8/9 Only. PIC16LF1717/8/9 Only.
1.6 2.0
16 MHz
1.8 Typical: 25°C 20 MHz
1.4 Max: 85°C + 3ı
1.6
16 MHz
1.2
1.4
8 MHz 1.2
1.0
IDD (mA)
IDD (mA)
1.0
0.8 4 MHz
0.8 8 MHz
0.2 0.0
2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0
FIGURE 35-26: IDD Maximum, HFINTOSC FIGURE 35-29: IDD Typical, HS Oscillator,
Mode, PIC16F1717/8/9 Only. 25°C, PIC16F1717/8/9 Only.
2.0 2.2
Max: 85°C + 3ı
1.8 Typical: 25°C 2.0
20 MHz
1.6 1.8
20 MHz
1.4 1.6
16 MHz
1.2 16 MHz 1.4
IDD (mA)
IDD (mA)
1.0 1.2
0.8 1.0
0.4 0.6
4 MHz
0.2 0.4 4 MHz
0.0 0.2
2.4 2.6 2.8 3.0 3.2 3.4 3.6 3.8 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0
FIGURE 35-27: IDD Typical, HS Oscillator, FIGURE 35-30: IDD Maximum, HS Oscillator,
25°C, PIC16LF1717/8/9 Only. PIC16F1717/8/9 Only.
3.0 1.2
Max.
Max. 1.0
2.5
0.8
Typical
2.0
IPD (µA)
Max: 85°C + 3ı
IDD (mA)
0.6 T i l 25°C
Typical:
1.5
0.4
Typical
1.0
0.2
Typical: 25°C
Max: 85°C + 3ı
0.5 0.0
2.4 2.6 2.8 3.0 3.2 3.4 3.6 3.8 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0
FIGURE 35-31: IDD, HS Oscillator, 32 MHz FIGURE 35-34: IPD Base, LP Sleep Mode
(8 MHz + 4x PLL), PIC16LF1717/8/9 Only. (VREGPM = 1), PIC16F1717/8/9 Only.
3.5 3.0
Max: 85°C + 3ı
Typical: 25°C
2.5
3.0
Max.
Max.
2.0
2.5 Typical
µA)
IPD (µA)
IDD (mA)
1.5
15
2.0
1.0
Typical
1.5 0.5
Typical: 25°C
Max: 85°C + 3ı
0.0
1.0 1.6 1.8 2.0 2.2 2.4 2.6 2.8 3.0 3.2 3.4 3.6 3.8
2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0
FIGURE 35-32: IDD, HS Oscillator, 32 MHz FIGURE 35-35: IPD, Watchdog Timer (WDT),
(8 MHz + 4x PLL), PIC16F1717/8/9 Only. PIC16LF1717/8/9 Only.
450 2.5
300
1.5
IPD (µA)
IDD (nA)
250
100
00
0.5
50 Typical
0
1.6 1.8 2.0 2.2 2.4 2.6 2.8 3.0 3.2 3.4 3.6 3.8 0.0
1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0
FIGURE 35-33: IPD Base, LP Sleep Mode, FIGURE 35-36: IPD, Watchdog Timer (WDT),
PIC16LF1717/8/9 Only. PIC16F1717/8/9 Only.
35 13
Max: 85°C + 3
M 3ı Max: 85°C + 3ı
Typical: 25°C 12 Typical: 25°C
30 Max.
11
Max.
25 10
IDD (nA)
IDD (nA)
nA)
Typical
20
8
Typical
7
15
10
5
4
5 2.8 3.0 3.2 3.4 3.6 3.8 4.0 4.2 4.4 4.6 4.8 5.0 5.2 5.4 5.6
1.6 1.8 2.0 2.2 2.4 2.6 2.8 3.0 3.2 3.4 3.6
VDD (V) VDD (V)
FIGURE 35-37: IPD, Fixed Voltage Reference FIGURE 35-40: IPD, Brown-out Reset
(FVR), PIC16LF1717/8/9 Only. (BOR), BORV = 1, PIC16F1717/8/9 Only.
35 1.8
1.6 Max.
30 Max.
1.4
1.2
25 Max: 85°C + 3ı
IDD (nA)
IDD (nA)
Typical 0.8
20
0.6
Typical
0.4
15 Max: 85°C + 3ı
Typical: 25°C
0.2
10 0.0
1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0 2.9 3.0 3.1 3.2 3.3 3.4 3.5 3.6 3.7
FIGURE 35-38: IPD, Fixed Voltage Reference FIGURE 35-41: IPD, LP Brown-out Reset
(FVR), PIC16F1717/8/9 Only. (LPBOR = 0), PIC16LF1717/8/9 Only.
11 1.8
Max: 85°C + 3
M 3ı Max: 85°C + 3ı
Typical: 25°C 1.6 Typical: 25°C
10 Max. Max.
1.4
9
1.2
IDD (nA)
IDD (µA)
8 Typical 1.0
7 0.8
0.6
6
0.4 Typical
5
02
0.2
4 0.0
2.9 3.0 3.1 3.2 3.3 3.4 3.5 3.6 3.7 2.8 3.0 3.2 3.4 3.6 3.8 4.0 4.2 4.4 4.6 4.8 5.0 5.2 5.4 5.6
FIGURE 35-39: IPD, Brown-out Reset FIGURE 35-42: IPD, LP Brown-out Reset
(BOR), BORV = 1, PIC16LF1717/8/9 Only. (LPBOR = 0), PIC16F1717/8/9 Only.
7 900
Max: 8
M 85°C
°C + 3
3ı
Max: 85°C + 3ı 800 Typical: 25°C
6 Typical: 25°C Max.
Max.
700
5
600
IDD (µA)
IDD (µA)
4 500
Typical
3 400
Typical 300
2
200
1
100
0 0
1.6 1.8 2.0 2.2 2.4 2.6 2.8 3.0 3.2 3.4 3.6 3.8 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0
FIGURE 35-43: IPD, Timer1 Oscillator, FIGURE 35-46: IPD, Op Amp, High GBWP
FOSC = 32 kHz, PIC16LF1717/8/9 Only. Mode (OPAxSP = 1), PIC16F1717/8/9 Only.
12 500
Max: 85°C + 3
M 3ı Max: 85°C + 3ı
450 Typical: 25°C
Typical: 25°C
10 Max.
400
350
8 Max.
µA)
IDD (µA) 300
µA)
IDD (µA)
6 250
Typical
200
4
150
100
2
50 Typical
0 0
1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0 1.6 1.8 2.0 2.2 2.4 2.6 2.8 3.0 3.2 3.4 3.6 3.8
FIGURE 35-44: IPD, Timer1 Oscillator, FIGURE 35-47: IPD, ADC Non-Converting,
FOSC = 32 kHz, PIC16F1717/8/9 Only. PIC16LF1717/8/9 Only.
700 1.4
400 0.8
µA)
IDD (µA)
µA)
IDD (µA)
Typical
300 0.6
200 0.4
Typical
100 0.2
0 0.0
1.6 1.8 2.0 2.2 2.4 2.6 2.8 3.0 3.2 3.4 3.6 3.8 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0
FIGURE 35-45: IPD, Op Amp, High GBWP FIGURE 35-48: IPD, ADC Non-Converting,
Mode (OPAxSP = 1), PIC16LF1717/8/9 Only. PIC16F1717/8/9 Only.
800 5
600
Typical 3
D (µA)
VOL (V)
500 -40°C
IDD
2 Typical
400
125°C
300 1
200
0
1.6 1.8 2.0 2.2 2.4 2.6 2.8 3.0 3.2 3.4 3.6 3.8
0 10 20 30 40 50 60 70 80
IOL (mA)
VDD (V)
FIGURE 35-49: IPD, Comparator, NP Mode FIGURE 35-52: VOL vs. IOL Over
(CxSP = 1), PIC16LF1717/8/9 Only. Temperature, VDD = 5.0V, PIC16F1717/8/9 Only.
800 3.5
Max: -40°C + 3ı
Typical: 25°C Max. Graph represents 3ı Limits
700 3.0
2.5
600
Typical 2.0
VOH (V)
IDD (µA)
500
1.5
125°C
400 Typical
1.0
300 -40°C
0.5
200 0.0
2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0 -14 -12 -10 -8 -6 -4 -2 0
FIGURE 35-50: IPD, Comparator, NP Mode FIGURE 35-53: VOH vs. IOH Over
(CxSP = 1), PIC16F1717/8/9 Only. Temperature, VDD = 3.0V.
6 3.0
5 2.5
4 2.0
VOL (V)
VOH (V)
-40°C -40°C
3 1.5 Typical
125°C
125°C
2 1.0
Typical
1 0.5
0 0.0
-30 -25 -20 -15 -10 -5 0 0 5 10 15 20 25 30
FIGURE 35-51: VOH vs. IOH Over FIGURE 35-54: VOL vs. IOL Over
Temperature, VDD = 5.0V, PIC16F1717/8/9 Only. Temperature, VDD = 3.0V.
2.0 40,000
Graph represents 3ı Limits
1.8 38,000
1.6 Max.
36,000
1.4 34,000
Typical
1.2
Frequency (Hz)
32,000
VOH (V)
0.4 24,000
Max: Typical + 3ı (-40°C to +125°C)
22,000 Typical; statistical mean @ 25°C
0.2 Min: Typical - 3ı (-40°C to +125°C)
0.0 20,000
-4.0 -3.5 -3.0 -2.5 -2.0 -1.5 -1.0 -0.5 0.0 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0
FIGURE 35-55: VOH vs. IOH Over FIGURE 35-58: LFINTOSC Frequency,
Temperature, VDD = 1.8V, PIC16LF1717/8/9 PIC16F1717/8/9 Only.
Only.
40,000
1.8 38,000
Graph represents 3ı Limits Max.
1.6 36,000
34,000
1.4
Typical
Frequency (Hz) 32,000
1.2
30,000
Vol (V)
1.0 Min.
28,000
125°C Typical
0.8
-40°C 26,000
0.6 24,000
Max: Typical + 3ı (-40°C to +125°C)
0.4 22,000 Typical; statistical mean @ 25°C
Min: Typical - 3ı (-40°C to +125°C)
0.2 20,000
2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0
0.0
0 1 2 3 4 5 6 7 8 9 10 VDD (V)
22
40,000 Max.
38,000 20
Max.
36,000
Time (ms)
18
34,000 Typical
Typical
16
Frequency (Hz)
32,000
Min.
30,000
14
Min.
28,000 Max: Typical + 3ı (-40°C to +125°C)
12 Typical; statistical mean @ 25°C
26,000 Min: Typical - 3ı (-40°C to +125°C)
24,000 10
Max: Typical + 3ı (-40°C to +125°C)
Typical; statistical mean @ 25°C 1.6 1.8 2.0 2.2 2.4 2.6 2.8 3.0 3.2 3.4 3.6 3.8
22,000 Min: Typical - 3ı (-40°C to +125°C) VDD (V)
20,000
1.6 1.8 2.0 2.2 2.4 2.6 2.8 3.0 3.2 3.4 3.6 3.8 FIGURE 35-60: WDT Time-Out Period,
VDD (V) PIC16LF1717/8/9 Only.
FIGURE 35-57: LFINTOSC Frequency,
PIC16LF1717/8/9 Only.
2.00 70.0
Max: Typical + 3ı
Typical: statistical mean
Max. 60.0 Min: Typical - 3ı
Max.
1.95
50.0
Typical
Voltage (mV)
Voltage (V)
40.0
1.90 Typical
30.0
Min.
20.0
1.85
Max: Typical + 3ı Min.
Typical: statistical mean 10.0
Min: Typical - 3ı
1.80 0.0
-60 -40 -20 0 20 40 60 80 100 120 140 -60 -40 -20 0 20 40 60 80 100 120 140
Temperature (°C)
( C) Temperature (°C)
FIGURE 35-61: Brown-out Reset Voltage, FIGURE 35-64: Brown-out Reset Hysteresis,
Low Trip Point (BORV = 1), PIC16LF1717/8/9 Low Trip Point (BORV = 1), PIC16F1717/8/9 Only.
Only.
2.85
70 Max: Typical + 3ı
Typical: statistical mean
Max: Typical + 3ı 2.80 Min: Typical - 3ı
60 Typical: statistical mean
Min: Typical - 3ı Max.
Voltage (V)
50 Max. 2.75
Typical
Voltage (mV)
40
2.70 Min.
30
Typical
2.65
20
Min.
10
2.60
-60 -40 -20 0 20 40 60 80 100 120 140
0
-60 -40 -20 0 20 40 60 80 100 120 140 Temperature (°C)
2.55 50
Voltage (mV)
Max.
Typical Typical
40
2.50
Voltage (V)
30
Min.
2.45
20
Min.
2.40 10
Max: Typical + 3ı
Typical: statistical mean 0
2.35 Min: Typical - 3ı -60 -40 -20 0 20 40 60 80 100 120 140
Temperature (°C)
( C)
2.30
-60 -40 -20 0 20 40 60 80 100 120 140 FIGURE 35-66: Brown-out Reset Hysteresis,
Temperature (°C) High Trip Point (BORV = 0).
FIGURE 35-63: Brown-out Reset Voltage,
Low Trip Point (BORV = 1), PIC16F1717/8/9
Only.
2.7 100
Max: Typical + 3ı Max: Typical + 3ı (-40°C to +125°C)
2.6 Typical: statistical mean
Typical; statistical mean @ 25°C
Min: Typical - 3ı (-40°C to +125°C)
Min: Typical - 3ı Max. 90
2.5
Max.
2.4
80
Voltage (V)
Time (ms)
2.3
Typical
2.2 70
Typical
2.1
60
2.0 Min.
1.9
Min. 50
1.8
1.7 40
-60 -40 -20 0 20 40 60 80 100 120 140 1.6 1.8 2 2.2 2.4 2.6 2.8 3 3.2 3.4 3.6 3.8
50 1.70
35 1.64
Voltage (V) Typical
1.62
Voltage (mV)
30
25 1.60
Min.
20 1.58
Typical
15 1.56
0 1.50
-60 -40 -20 0 20 40 60 80 100 120 140 -50 -25 0 25 50 75 100 125 150
FIGURE 35-68: LPBOR Reset Hysteresis. FIGURE 35-71: POR Release Voltage.
100 1.58
1.58
Max: Typical + 3ı (-40°C to +125°C) Max: Typical + 3ı
Typical; statistical mean @ 25°C Typical: 25°C
Min: Typical - 3ı (-40°C to +125°C)
1.56
90 1.56 Min: Typical - 3ı
Max. Max.
1.54
1.54
(V) (V)
80
Typical
Voltage
Time (ms)
1.52
Typical 1.52
Voltage
70
1.5
1.50
Min.
60 1.48 Min.
1.48
1.46
50 Max: Typical + 3ı 0
1.46 -40 Typical:-20
statistical mean
20 40 60 80 100 120
1.4 40
Max: Typical + 3ı
1.3 Typical: statistical mean @ 25°C
Max. 35
1.2
Max.
30
1.1
Voltage (V)
Time (µs)
Typical
1.0 25 Typical
0.9
Min. 20
0.8
Note:
Max: Typical + 3ı 15
0.7 The FVR Stabiliztion Period applies when coming out of RESET
Typical: statistical mean or exiting sleep mode.
Min: Typical - 3ı
0.6 10
-50 -25 0 25 50 75 100 125 150 1.6 1.8 2.0 2.2 2.4 2.6 2.8 3.0 3.2 3.4 3.6 3.8
FIGURE 35-73: POR Rearm Voltage, FIGURE 35-76: FVR Stabilization Period,
NP Mode, PIC16LF1717/8/9 Only. PIC16LF1717/8/9 Only.
12
Max: Typical + 3ı (-40°C to +125°C)
Typical; statistical mean @ 25°C 1.0
10 Min: Typical - 3ı (-40°C to +125°C)
8
0.5
Time (µs)
Max.
DNL(LSb)
6
Typical
0.0
4
2
Ͳ0.5
0
1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0
Ͳ1.0
VDD (V)
0 128 256 384 512 640 768 896 1024
45 1.0
40
Max.
35
0.5
Time (µs)
30
Typical
DNL(LSb)
25
20 0.0
15
0
1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0
Ͳ1.0
VDD (V) 0 128 256 384 512 640 768 896 1024
1.5
1.0
MaxͲ40°C
1.0
Max25°C
0.5
Max125°C
0.5
INL(LSb)
INL(LSb)
0.0 0.0
Min25°C
Min125°C
Ͳ0.5 MinͲ40°C
Ͳ0.5
Ͳ1.0
Ͳ1.0 Ͳ1.5
0 128 256 384 512 640 768 896 1024 5.00EͲ07 1.00EͲ06 2.00EͲ06 4.00EͲ06 8.00EͲ06
OutputCode TADs
FIGURE 35-79: ADC 10-bit Mode, FIGURE 35-82: ADC 10-bit Mode,
Single-Ended INL, VDD = 3.0V, TAD = 1 S, 25°C. Single-Ended INL, VDD = 3.0V, VREF = 3.0V.
2.0
1.0 1.5
1.5
1.0
1.0
0.5
0.5
DNL(LSb)
MaxͲ40°C
0.5
0.0 Max25°C
INL(LSb)
Max125°C
DNL(LSb)
Ͳ0.5
0.0 0.0
Ͳ1.0
Ͳ0.5
Ͳ2.0 Min25°C
0 512 1024 1536 2048 2560 3072 3584 4096
MinͲ40°C
Ͳ1.0
OutputCode
Ͳ1.0
Ͳ1.5
0 128 256 384 512 640 768 896 1024
1.8 2.3 3
OutputCode VREF
FIGURE 35-80: ADC 10-bit Mode, FIGURE 35-83: ADC 10-bit Mode,
Single-Ended INL, VDD = 3.0V, TAD = 4 S, 25°C. Single-Ended DNL, VDD = 3.0V, TAD = 1 S.
1.5 1.5
MinͲ40°C MaxͲ40°C
1.0
1.0
Min25°C
0.5 Max25°C
INL(LSb)
0.0
Min125°C
0.0
Ͳ0.5 Min25°C
Min125°C
MinͲ40°C
MinͲ40°C
Ͳ0.5
Ͳ1.0 Min25°C
Ͳ1.5 Ͳ1.0
5.00EͲ07 1.00EͲ06 2.00EͲ06 4.00EͲ06 8.00EͲ06 1.8 2.3 3
TADs VREF
FIGURE 35-81: ADC 10-bit Mode, FIGURE 35-84: ADC 10-bit Mode,
Single-Ended DNL, VDD = 3.0V, VREF = 3.0V. Single-Ended INL, VDD = 3.0V, TAD = 1 S.
800 150
ADC VREF+ SET TO VDD ADC VREF+ SET TO VDD Max.
ADC VREF- SET TO GND 125 ADC VREF- SET TO GND Typical
700
Max.
100
600
Typical Min.
75
500
Min.
50
400
25
300
0
200
-25
Max: Typical + 3ı
100 Max: Typical + 3ı
Typical; statistical mean
Typical; statistical mean
Min: Typical - 3ı -50
Min: Typical - 3ı
0
2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0 -75
-50 -25 0 25 50 75 100 125 150
VDD (V) Temperature (°C)
( C)
FIGURE 35-85: Temp. Indicator Initial Offset, FIGURE 35-88: Temp. Indicator Slope
High Range, Temp. = 20°C, PIC16F1717/8/9 Only. Normalized to 20°C, High Range, VDD = 5.5V,
PIC16F1717/8/9 Only.
900
ADC VREF+ SET TO VDD
ADC VREF- SET TO GND Max.
250
800 Typical
ADC VREF+ SET TO VDD
Max.
Min. ADC VREF- SET TO GND
200
Typical
700
150 Min.
ADC Output Codes
600 100
ADC Output Codes
50
500
0
Max: Typical + 3ı
400 Typical; statistical mean
Min: Typical - 3ı -50
Low Range, Temp. = 20°C, PIC16F1717/8/9 Only. FIGURE 35-89: Temp. Indicator Slope
Normalized to 20°C, High Range, VDD = 3.0V,
800
ADC VREF+ SET TO VDD
PIC16F1717/8/9 Only.
ADC VREF- SET TO GND
700 Max.
Typical 150
600 Max.
Min. ADC VREF+ SET TO VDD
125 ADC VREF- SET TO GND
ADC Output Codes
Typical
500
100
Min.
400 75
ADC Output Codes
50
300
25
200 Max: Typical + 3ı
Typical; statistical mean
Min: Typical - 3ı 0
100
-25
1.5 1.8 2.1 2.4 2.7 3.0 3.3 3.6 3.9
Max: Typical + 3ı
-50 Typical; statistical mean
VDD (V) Min: Typical - 3ı
250
80
ADC VREF+ SET TO VDD Max.
ADC VREF- SET TO GND
200 Typical 75
Max.
150
Min. 70
CMRR (dB)
100
ADC Output Codes
65
Typical
50
60
0
55 Min.
-50
50
Max: Typical + 3ı Max: Typical + 3ı
-100 Typical; statistical mean
Typical; statistical mean 45
Min: Typical - 3ı Min: Typical - 3ı
-150
-50 -25 0 25 50 75 100 125 150 40
-50 -25 0 25 50 75 100 125 150
Temperature (°C)
( C) Temperature (°C)
FIGURE 35-91: Temp. Indicator Slope FIGURE 35-94: Op Amp, Common Mode
Normalized to 20°C, Low Range, VDD = 1.8V, Rejection Ratio (CMRR), VDD = 3.0V.
PIC16LF1717/8/9 Only.
35%
50
15%
0
10%
-50 5%
Max: Typical + 3ı
Typical; statistical mean
Min: Typical - 3ı
0%
-100 -7 -5 -4 -3 -2 -1 0 1 2 3 4 5 6 7
-50 -25 0 25 50 75 100 125 150
Offset Voltage (mV)
Temperature (°C)
( C)
FIGURE 35-95: Op Amp, Output Voltage
FIGURE 35-92: Temp. Indicator Slope Histogram, VDD = 3.0V, VCM = VDD/2.
Normalized to 20°C, Low Range, VDD = 3.0V,
PIC16LF1717/8/9 Only.
8
Max.
6
250
ADC VREF+ SET TO VDD Max.
ADC VREF- SET TO GND 4
200
Offset Voltage (V)
Typical Typical
2
150
Min.
0
100
ADC Output Codes
Min.
-2
50
-4
0 Max: Typical + 3ı
Typical; statistical mean
-6 Min: Typical - 3ı
-50
Max: Typical + 3ı -8
-100 Typical; statistical mean -0.3 0.0 0.3 0.6 0.9 1.2 1.5 1.8 2.1 2.4 2.7 3.0 3.3
Min: Typical - 3ı
Common Mode Voltage (V)
-150
-50 -25 0 25 50 75 100 125 150
FIGURE 35-96: Op Amp, Offset Over
Temperature (°C)
Common Mode Voltage, VDD = 3.0V,
FIGURE 35-93: Temp. Indicator Slope Temp. = 25°C.
Normalized to 20°C, High Range, VDD = 3.6V,
PIC16LF1717/8/9 Only.
8 45
Max.
6 43
-40°C
41
4
39
Offset Voltage (V)
Typical
Hysteresis (mV)
25°C
2
37 85°C
0 35
125°C
-2 33
31
-4
Min.
Max: Typical + 3ı 29
-6 Typical; statistical mean
Min: Typical - 3ı 27
-8 25
-0.5 0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5
3.8
30
VDD = 3.6V
3.7 25
20
3.6
Max.
VDD = 5.5V
Slew Rate (V/µs)
15
3.3 0
Min.
VDD = 3V
-5
3.2
-10
3.1
-15
3.0
-20
-60 -40 -20 0 20 40 60 80 100 120 140
0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5
Temperature (°C)
Common Mode Voltage (V)
FIGURE 35-98: Op Amp, Output Slew Rate, FIGURE 35-101: Comparator Offset, NP Mode
Rising Edge, PIC16F1717/8/9 Only. (CxSP = 1), VDD = 3.0V, Typical Measured Values
at 25°C.
5.4
5.2
4.8
25
Max.
4.6 20
4.4 15
VDD = 3.6V
Offset Voltage (mV)
4.0 5
0
3.8 VDD = 3V Min.
-5
3.6
-60 -40 -20 0 20 40 60 80 100 120 140 -10
140
50
Max: Typical + 3ı (-40°C to +125°C)
120 Typical; statistical mean @ 25°C
Min: Typical - 3ı (-40°C to +125°C)
45
-40°C
100
Hysteresis (mV)
40
25°C
Time (ns)
80
85°C
35 125°C
60
Max.
30
40 Typical
Min.
25
20
20 0
0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0 1.5 2.0 2.5 3.0 3.5 4.0
90
30
Max: Typical + 3ı (-40°C to +125°C)
25 80 Typical; statistical mean @ 25°C
Min: Typical - 3ı (-40°C to +125°C)
20 Max. 70
15
60
Hysteresis (mV)
Time (ns)
10
50
5 Max.
40
0 Typical
Min.
30
-5 Min.
-10 20
-15 10
-20 0
0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0
Common Mode Voltage (V) VDD (V)
FIGURE 35-104: Comparator Offset, NP Mode FIGURE 35-107: Comparator Response Time
(CxSP = 1), VDD = 5.0V, Typical Measured Values Over Voltage, NP Mode (CxSP = 1), Typical
at 25°C, PIC16F1717/8/9 Only. Measured Values, PIC16F1717/8/9 Only.
1,400
40
Max: Typical + 3ı (-40°C to +125°C)
1,200 Typical; statistical mean @ 25°C
Min: Typical - 3ı (-40°C to +125°C)
30
Max.
1,000
Offset Voltage (mV)
20
Time (ns)
800
10
600
0
400
Min. Max.
-20 0
0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 1.5 2.0 2.5 3.0 3.5 4.0
VDD (V)
Common Mode Voltage (V)
FIGURE 35-105: Comparator Offset, NP Mode FIGURE 35-108: Comparator Output Filter
(CxSP = 1), VDD = 5.5V, Typical Measured Values Delay Time Over Temp., NP Mode (CxSP = 1),
From -40°C to 125°C, PIC16F1717/8/9 Only. Typical Measured Values, PIC16LF1717/8/9
Only.
500
Time (ns)
DNL (LSb)
0.005
400
0.000
300
Max. -0.005
200
Typical
100 -0.010
Min.
0
-0.015
2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0
0 16 32 48 64 80 96 112 128 144 160 176 192 208 224 240
VDD (V) Output Code
FIGURE 35-109: Comparator Output Filter FIGURE 35-112: Typical DAC INL Error,
Delay Time Over Temp., NP Mode (CxSP = 1), VDD = 5.0V, VREF = External 5V,
Typical Measured Values, PIC16F1717/8/9 Only. PIC16F1717/8/9 Only.
0.025 0.00
-40°C
0.020 -0.05
25°C
85°C
0.015 -0.10
125°C
0.010 -0.15
DNL (LSb)
0.000 -0.25
-0.005 -0.30
-40°C
-0.010 -0.35
25°C
-0.015 -0.40 85°C
125°C
-0.020 -0.45
0 16 32 48 64 80 96 112 128 144 160 176 192 208 224 240 0 16 32 48 64 80 96 112 128 144 160 176 192 208 224 240
Output Code Output Code
FIGURE 35-110: Typical DAC DNL Error, FIGURE 35-113: Typical DAC INL Error,
VDD = 3.0V, VREF = External 3V. VDD = 5.0V, VREF = External 5V,
PIC16F1717/8/9 Only.
0.00
,
-0.05
24
-0.10
22 Max.
-0.15
20
INL (LSb)
-0.20
DNL (LSb)
-0.25 18
Typical
-0.30
16
-40°C
-0.35 25°C
14
85°C
-0.40 Min.
125°C
12 Max: Typical + 3ı (-40°C to +125°C)
-0.45 Typical; statistical mean @ 25°C
Min: Typical - 3ı (-40°C to +125°C)
0 16 32 48 64 80 96 112 128 144 160 176 192 208 224 240
Output Code 10
1.6 1.8 2 2.2 2.4 2.6 2.8 3 3.2 3.4 3.6 3.8
FIGURE 35-111: Typical DAC INL Error, Output Code
VDD = 3.0V, VREF = External 3V. FIGURE 35-114: DAC INL Error,
VDD = 3.0V, PIC16LF1717/8/9 Only.
0.85
1.00
0.90
0.80
-40°C 0.80
ZCD Pin Voltage (V)
0.70
0.75
0.60
Time (µs)
25°C
0.50
0.70
85°C 0.40
FIGURE 35-115: ZCD Pin Voltage, Typical FIGURE 35-118: ZCD Pin Response Time
Measured Values Over Current, Typical Measured Values From
-40°C to 125°C.
1.4
Fall-2.3V
0.28
1.2
Fall-3.0V
Fall-5.5V
0.26
1.0
0.24
0.8
Time (µs)
Time (µs)
0.22
0.6
0.20
0.4
Rise-2.3V
Rise-3.0V 0.18
0.2 Rise-5.5V 125°C
85°C
0.16 25°C
0.0 -40°C
-50 -25 0 25 50 75 100 125 150
Temperature (°C) 0.14
1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0
VDD (V)
FIGURE 35-116: ZCD Response Time Over
Voltage, Typical Measured Values. FIGURE 35-119: COG Dead-Band Delay,
Title TYPICAL MEASURED VALUES FROM 40 C to 125 C DBR/DBF = 32, Typical Measured Values
8.0
5.5V
9.0
3.0V
ZCD Source/Sink Current (mA)
6.0
8.5
2.3V 8.0
4.0
7.5
Time (ns)
2.0 1.8V
7.0
6.5
0.0
6.0
-2.0
5.5 125°C
85°C
5.0 25°C
-4.0
-40°C
-0.20 0.00 0.20 0.40 0.60 0.80 1.00 1.20 1.40 1.60 1.80 2.00 2.20
4.5
ZCD Pin Voltage (V) 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0
VDD (V)
FIGURE 35-117: ZCD Pin Current Over ZCD
Pin Voltage, Typical Measured Values From -40°C FIGURE 35-120: COG Dead-Band DBR/DBF
to 125°C. Delay Per Step, Typical Measured Values.
0.30
Min.
0.25
Time (µs)
0.20
0.15
0.10
0.05
0.00
0 10 20 30 40 50 60 70
DBR/DBF Value
Max.
Max: Typical + 3ı
0.06
Typical; statistical mean
Min: Typical - 3ı Typical
0.05
Min.
0.04
Time (µs)
0.03
0.02
0.01
0.00
0 1 2 3 4 5 6 7 8 9 10 11
DBR/DBF Value
PIC16F1718
-I/SP e3
1401017
XXXXXXXXXXXXXXXXXXXX PIC16F1718
XXXXXXXXXXXXXXXXXXXX -I/SO e3
XXXXXXXXXXXXXXXXXXXX
YYWWNNN 1401017
PIC16F1718
-E/SS e3
1401017
Note: In the event the full Microchip part number cannot be marked on one line, it will
be carried over to the next line, thus limiting the number of available
characters for customer-specific information.
PIN 1 PIN 1
XXXXXXXX 16LF1718
XXXXXXXX -I/MM
YYWWNNN 1401017
XXXXXXXXXXXXXXXXXX PIC16LF1717
XXXXXXXXXXXXXXXXXX -I/P e3
XXXXXXXXXXXXXXXXXX
YYWWNNN 1401017
Note: In the event the full Microchip part number cannot be marked on one line, it will
be carried over to the next line, thus limiting the number of available
characters for customer-specific information.
PIN 1 PIN 1
PIC16
F1719
-I/MV e3
1401017
XXXXXXXXXX PIC16F1719
XXXXXXXXXX -E/PT e3
XXXXXXXXXX 1401017
YYWWNNN
Note: In the event the full Microchip part number cannot be marked on one line, it will
be carried over to the next line, thus limiting the number of available
characters for customer-specific information.
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Note: For the most current package drawings, please see the Microchip Packaging Specification located at
http://www.microchip.com/packaging
Note: For the most current package drawings, please see the Microchip Packaging Specification located at
http://www.microchip.com/packaging
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http://www.microchip.com/packaging
Note: For the most current package drawings, please see the Microchip Packaging Specification located at
http://www.microchip.com/packaging
Note: For the most current package drawings, please see the Microchip Packaging Specification located at
http://www.microchip.com/packaging
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Note: For the most current package drawings, please see the Microchip Packaging Specification located at
http://www.microchip.com/packaging
Note: For the most current package drawings, please see the Microchip Packaging Specification located at
http://www.microchip.com/packaging
Note: For the most current package drawings, please see the Microchip Packaging Specification located at
http://www.microchip.com/packaging
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http://www.microchip.com/packaging
Revision A (02/2014)
Initial release of the document.
Revision B (12/2015)
Chapter 18.0 COG rewritten.
Added High-endurance Flash Data Memory informa-
tion to cover pages and Memory chapter. Added Sec-
tion 11.3.1 heading. Added Section 6.3.5: Clock
Switching Before Sleep.
Deleted Section 24.4: Low-Power Voltage State.
Updated the Family Types Table and the Product Iden-
tification System page.
Updated Examples 3-2 and 21-; Figures 16-2, 18-2,
18-3, 18-4, 18-5, 18-6, 21-1, 22-1, 23-1, 24-1, 27-1,
29-2 and 29-4; Registers 11-8, 11-16, 11-24, 11-32,
11-40, 21-2, 22-1, 23-1, 23-2 and 30-4; Sections 3.3.2,
8.2.2, 11.9.1, 11.9.2, 18.1.1, 18.1.2,18.1.3, 18-1-4,
18-1.6, 18.2, 18.3.2, 18.3.3, 18.5, 18.5.4, 18.5.5,
18.8.3, 18.10, 20.0, 21.1.3, 22.0, 22.1, 22.1.1, 23.5,
24.0, 24.1, 24.3, 24.4, 24.5, 25.2, 25.8, 30.6, 31.6.2
and 34-1; Tables 3-10, 3-12, 6-1, 12-1, 16-3, 17-3,
21-3, 24-1, 34-1, 34-2, 34-3, 34-4, 34-5, 34-8, 34-11
and 34-24.
Minor typos corrected.
Package:(2) MV = UQFN, 28-lead 4x4x0.5mm Note 1: Tape and Reel identifier only appears in
MV = UQFN, 40-lead 5x5x0.5mm the catalog part number description. This
MM = QFN-S, 28-lead 6x6x0.9mm identifier is used for ordering purposes and
P = PDIP, 40-lead is not printed on the device package.
PT = TQFP, 44-lead 10x10x1mm Check with your Microchip Sales Office
SO = SOIC, 28-lead for package availability with the Tape and
SP = SPDIP, 28-lead Reel option.
SS = SSOP, 28-lead
2: Small form-factor packaging options may
be available. Please check
Pattern: QTP, SQTP, Code or Special Requirements www.microchip.com/packaging for
(blank otherwise) small-form factor package availability, or
contact your local Sales Office.
• Microchip believes that its family of products is one of the most secure families of its kind on the market today, when used in the
intended manner and under normal conditions.
• There are dishonest and possibly illegal methods used to breach the code protection feature. All of these methods, to our
knowledge, require using the Microchip products in a manner outside the operating specifications contained in Microchip’s Data
Sheets. Most likely, the person doing so is engaged in theft of intellectual property.
• Microchip is willing to work with the customer who is concerned about the integrity of their code.
• Neither Microchip nor any other semiconductor manufacturer can guarantee the security of their code. Code protection does not
mean that we are guaranteeing the product as “unbreakable.”
Code protection is constantly evolving. We at Microchip are committed to continuously improving the code protection features of our
products. Attempts to break Microchip’s code protection feature may be a violation of the Digital Millennium Copyright Act. If such acts
allow unauthorized access to your software or other copyrighted work, you may have a right to sue for relief under that Act.
QUALITY MANAGEMENT SYSTEM Microchip received ISO/TS-16949:2009 certification for its worldwide
headquarters, design and wafer fabrication facilities in Chandler and
CERTIFIED BY DNV Tempe, Arizona; Gresham, Oregon and design centers in California
and India. The Company’s quality system processes and procedures
== ISO/TS 16949 ==
are for its PIC® MCUs and dsPIC® DSCs, KEELOQ® code hopping
devices, Serial EEPROMs, microperipherals, nonvolatile memory and
analog products. In addition, Microchip’s quality system for the design
and manufacture of development systems is ISO 9001:2000 certified.