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Asic Notes PDF
Asic Notes PDF
Asic Notes PDF
SYSTEM REQUIREMENTS
SPECIFICATION
SPECIFICATION
LOGIC DESIGN
MODELLING
LOGIC DESIGN
SYNTHESIS
VERIFICATION
TEST GENERATION
/ Configuration data
PROTOTYPE
SYSTEM
PROTO TESTING
VERIFICATION
SYSTEM TESTING
• The goal is to specify the functional requirements for the design and
define the external interfaces to the related designs.
SYSTEM REQUIREMENTS
SPECIFICATION
System Req. Specification
System Func. Specification
ASIC Project Plan
Tools
Re qu i r e me n
tS p e c i f i c a t
i
e . g. Wo r d
REQ. SPEC
REVI EW
Re qu i r e me n t
Spe c i f i c at i
Da t a
Sp e c ti f i c a t
Sh
i
e . g. Wor d
DATA SHEET
REVI EW Da t a S he e t
l 1
• Architecture design
• Model validation ok
-> Logic design
• Reusing
• Synchronous design !!
• Use the same name or similar names for ports and signals,
throughout the hierarchy, that are connected. (for example, a => a;
or a => a_int;)
• Use the name enab for an enable signal. If there is more than one
enable in the design, use enab as the prefix for all enable signals.
• Testbench is named 'name_of_the_block'_TB.
FF FF
clk
• partition the design so that all the logic in a single module uses a
single clock and a single reset.
• Isolating clock and reset generation logic in a separate module allows
the other modules to use the standard timing analysis and scan
insertion techniques. It also makes it easier to develop specific test
strategies for the clock/reset generation logic.
clk1
submodule
master clock
1
Clock clk2
submodule
Generation 2
clk3
submodule
3
FF FF
clk
data
enable
master
clock
reset
A C
clk FF A COMB
clk FF C Better
A&B&C
A C
COMB
clk FF A
A&B&C clk FF C Best
P RTL
titi
Bl k
VHDL
RTL Bl o c k Sch.,DFD
D i
Ar c hi t e c t u r e
Pl
A a n/
hi De s c r i p t M
i d l
Sy nt he s i z a b l e
Te x t RTL Bl oc k VHDL
di D i
RTL VHDL
Target
technology
Tar ge t Syn t h e s i s
h dal t a Ch k Schematics
b De s i g n
C il S c h e mat i c
i
VHDL TB
RTL Bl o c k simulation
VHDL Te s t Be n c h F ti results
Me n t o r V ifi ti S t i mu l
VSS iRe s po ns e
Si l
RTL VHDL,DFD
Doc
Bl ume
k nt a t i o
Add e d c o mme n t s
Te x t
di
Bl o c k
RTL Block
Re v i e w
Re l e a s e d RTL
bl k
RTL Mod e l
I nt e g r a t i
LOGIC DESIGN
SYNTHESIS VHDL
VHDL
e . g. S e pa
Pr t h r a ti i Sch.,DFD
Te x t
di RTL VHDL Mode l
opt i mi z e d f or
h i
Generic Mo dul e
technology Schematics
Syn t he s i
Ge n e r i c
h dat l a Sc h e mat i c
b bas e d on ge i ne r i c
De s i gn h l
Compi l e r
Te s t Comp i l e r
M
Lia pb pi ng Schematics
Sc h e mat i c
bas e d on ti ar ge t
h l
ASI C t e s t
Target s yn t he s i s , Schematics
technology
t t bi l i t
Tar ge t Sc h e mat i c
h datl a add e d t e s ti s t r u c t ur e
b
M d i mi
Opt l zat i Schematics
Sc h e mat i c
opt i mi z e d i f or t ar ge t
h l
Ti mi ng
A l i
Ti mi ng
R
VERIFICATION
CHIP VERIFICATION
Sy nops y s De s i gn or
FPGA
Static timing analysis
Qui c k c he c k
Formal
Ti mi ng
orc ompi
e quil ve al
l
r e nt
Netlist creator Ne t l i s
verification
Sy nt he s i s
Li br ar
and
ASI C/ FPGA
gat e
Li b
St i mul i
static timing
Te s t be nc h, Functional simulation
be h. mode l
Fl oor pl anni n
Floorplanning i nf or mat i
ASI C/ FPGA
Ce l l Static timing analysis
Li b
Ti mi ng
CHIP VERIFICATION
Chip gate level schematic
with test structures
TEST GENERATION Test
Pr e l i m. t e s t Patterns
pa t t e r n
ti ASCI I
(ASIC only) Pr e l i mi na r y
Ma nu a l t e s t Test
pa t t e r n Pattern
ti
ASCI I
Man ua l : RAM . .
Test Compiler
Plus Au t o ma t i c Test
p Pattern
t at t er n
i
ASCI I
Aut omat i c
Te s t Test pattern
Si
t i mull a t i o n responses
ASCI I
Te s t da t a : s t i mu l i +
VeriFault Fa u l t
G di
Ve r i f i e d Ch i p
h i
Layout
TEST
GENERATI ON
Schema
Lay o ut Netlist
De s i gn , t e s t d a t a
(ASIC)
simulation
Pr e l a yo ut results
Ve n d or s De s i gn i l ti S t i mul
Ki iRe s p on s e
Pl a c e & Rou t e
Design
Target
technology
GDS I I
Tar ge t
h datl a
b simulation
Po s t l a y ou t results
i l ti S t i mul
iRe s p on s e
Ba c k a nn ot a t e t o Back annotation
S St a t i c Ti mi ng
A l i Ti mi ng f i l e t o
d i
De s i gn
DRC,
i f i LVS
ti Re p o r t
Ve n d or fil
l fil
Si g n o f f
Man u f a c t . a g r e e me nt
MANUFACTURI NG
PROTO TESTI NG
• Advantages:
VHDL is tested with real clock speed, in real environment
Prototyping environment offers "early ASIC" for other projects
More secure to sign off
• Disadvantages
Requires a lot of time and resources
Expensive